TWI251272B

TWI251272B - Method of forming self-aligned metal silicide

Info

Publication number: TWI251272B
Application number: TW90118555A
Authority: TW
Inventors: Erh-Kun Lai; Shou-Wei Hwang; Tung-Cheng Kuo; Yu-Ping Huang
Original assignee: Macronix Int Co Ltd
Priority date: 2001-07-31
Filing date: 2001-07-31
Publication date: 2006-03-11

Abstract

This invention relates to a method of forming self-aligned metal silicide (silicide) and, more especially, to a method of forming self-aligned metal silicide in partial region. The invention uses the silicon layer as a mask layer to form a local self-aligned metal silicide on the logic circuit. A metal silicide is formed on a gate in cell array region while no metal silicide is formed in a diffusion region. The gate and diffusion regions can be formed with metal silicide in periphery circuit regions. The method of this invention is able to obtain lower resistance for the semiconductor device, and the drawback of leakage current is not likely to occur.

Description

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5 - 1發明領域：曰修正本發明係為一種形成自對準金屬矽化物之方法，特別疋有關於一種在部分區域形成自對準金屬矽化物之方法，乂順利在周邊電路區域與晶胞陣列區域上的閘極區域及周邊電路區域上之擴散區域形成金屬矽化物，以使半導體元件獲得較低之電阻，且較不會產生漏電流之缺陷。5 - 1 FIELD OF THE INVENTION: 曰 MODIFICATION The present invention is a method of forming a self-aligned metal telluride, and more particularly to a method of forming a self-aligned metal telluride in a partial region, 乂 smoothly in the peripheral circuit region and the unit cell The gate region on the array region and the diffusion region on the peripheral circuit region form a metal germanide so that the semiconductor device obtains a lower resistance and is less likely to cause a leakage current.

5-2發明背景 ▲元件的積集度（integrity)增加，使金氧半電晶體元件的源極/汲極（source/drain)的電阻，逐漸的上升到與金氧半電晶體元件通道（channe丨）的電阻相當時，為了调降源極/>及極的片電阻（sheet resistance)，並確保金屬與金氧半電晶體間的r淺接合（shai i〇w junct i〇n)」之完整’一種稱為「自行對準金屬矽化物（self_aHgned si 1 icide)」製程的應用，便漸漸地走入〇· 5微米（micr〇n; #m)以下的超大型積體電路（very iarge scaie 一秦 integration; VLSI)製程。這個製程又因此而簡稱為自對丨準金屬矽化物（salicide)製程。一般最常用之金屬矽化物當首推鈦矽化物。鈦矽化物之形成，一般皆採用兩階段快速加熱製程（rap i d thermalprocess; RTP )方式。首先，參照第一圖所示，5-2 BACKGROUND OF THE INVENTION ▲The degree of integration of the component increases, so that the source/drain resistance of the MOS transistor gradually rises to the channel of the MOS transistor. When the resistance of channe丨 is equivalent, in order to reduce the source/> and the sheet resistance of the pole, and to ensure the shallow junction between the metal and the MOS transistor (shai i〇w junct i〇n) The application of a complete process called "self_aHgned si 1 pesticide" has gradually entered the ultra-large integrated circuit below 5 micrometers (micr〇n; #m) Very iarge scaie a Qin integration; VLSI) process. This process is therefore referred to as the self-aligned metal salicide process. The most commonly used metal halides are the first to promote titanium halides. The formation of titanium telluride generally adopts a two-stage rapid heating process (RTP). First, referring to the first figure,

1251272 — 案號 90118555 年月_日修正五、發明說明（2) 提供一石夕底材10，在底材1〇上已經形成金氧半電晶體及淺渠溝隔離層3 0。此金氧半電晶體具有源極/汲極區域丨2、閘極以及在閘極的側壁形成間隙壁（spacer)18，且此閘極至少包含閘極氧化物層1 4與多晶矽層1 6，然後以化學氣相沉積法（ chemical vapor deposition; CMP)或是磁控直流電濺鍍法（direct current magnetron sputtering)沉積一層鈦金屬層20於底材1〇上，此鈦金屬層2〇的厚度大約為“ο埃。接下來，進行第一快速加熱製程，使鈦金屬與接觸處之矽層反應，以形成鈦矽化物，其厚度大約在6 〇〇至7 〇〇埃之間。此時的鈦矽化物的結構主要是電阻值較高之c_49相的結構。參照第二圖所示，利用RCA清洗的方式來去除未參與反應或反應後所殘留的鈦金屬，而將鈦矽化合物層留在金氧半電晶體的最表面上。此未參與反應或反 :的：金屬不見得-定是以鈦的形式留下來。最後再執行第二快速加熱製程，將C-49相之鈦矽化物結構轉換值較低的C - 5 4相之結構。、在深次微米元件的製程中，為了避免源極/ ::::阻引起之電晶體驅動電流衰退’對源極/汲極加以化處理乃為一重要且廣為應用的製程技術。純之源極/汲極矽化處理，或由自行對秸田^ 來達成。自行料金心化物製程可屬/化物製程與閑極之石夕化處理。了门成源極/及極1251272 — Case No. 90118555 Year Month_Day Revision V. INSTRUCTIONS (2) A stone substrate 10 is provided, and a gold oxide semi-transistor and a shallow trench isolation layer 30 have been formed on the substrate. The MOS transistor has a source/drain region 丨2, a gate, and a spacer 18 formed on a sidewall of the gate, and the gate includes at least a gate oxide layer 14 and a polysilicon layer 16 Then, a layer of titanium metal 20 is deposited on the substrate 1 by chemical vapor deposition (CMP) or direct current magnetron sputtering. The thickness of the titanium layer 2 About ο 埃. Next, a first rapid heating process is performed to react the titanium metal with the ruthenium layer at the contact to form a titanium ruthenium having a thickness of between about 6 7 and 7 〇〇. The structure of the titanium telluride is mainly the structure of the c_49 phase with a relatively high resistance value. Referring to the second figure, the RCA cleaning method is used to remove the titanium metal remaining after the reaction or the reaction, and the titanium germanium compound layer is removed. Leaving on the outermost surface of the gold-oxygen semi-transistor. This is not involved in the reaction or the reverse: the metal is not visible - it will be left in the form of titanium. Finally, the second rapid heating process is performed, and the C-49 phase is titanium. Lower telluride structure conversion value The structure of the C-5 phase is important. In the process of deep submicron components, it is important to treat the source/drain in order to avoid the decay of the transistor drive current caused by the source / :::: resistance. And the widely used process technology. Pure source / bungee deuteration treatment, or by self-satisfaction of the straw field ^. The self-feeding metallization process can be a chemical process and the idle process of the stone. Source/pole

1251272 曰 -----SS__90118555_ 五、發明說明（3) 以降低配合在形成金而傳統金屬石夕區域上，傳統須運用在目前之邏輯電路上，傳導層之t阻並增加丨導/需要使用金屬石夕化物邏輯電路的運作，在雷疋件之品質。但是為了屬矽化物，以防卜主道麯電路上有部分之區域不能的自對準金屬矽化物梦r疋，發生漏電流之缺陷。化物，則必須經過相當‘雜部分材料上形成形成金屬矽化物。在:秦：能在所需之較為耗時的步驟已無法配= 製程中本發明之方法，以加速製程運;體-程，必 _ 5 - 3發明目的及概述：於上述的發明背寻中，在玀鈕ΦL ’、 j用傳、、、先的方法無法快速地在邏輯電路上局部形成金屬矽化物，本發明主利用一石夕層戶斤作為的遮罩層 P ' 陣列F Η p…？ t 周邊電路區域與晶胞 :=域上的閑極及周邊電路區域上之擴散區域形成金屬1251272 曰-----SS__90118555_ V. Description of invention (3) In order to reduce the coordination in the formation of gold and the traditional metal stone area, the traditional must be applied to the current logic circuit, the t-resistance of the conduction layer and increase the guidance / need The use of metal lithium logic circuits operates in the quality of Thunder pieces. However, in order to be a telluride, in order to prevent the self-aligned metal telluride in a part of the circuit of the main circuit, the leakage current is defective. The compound must form a metal telluride through a relatively 'different part of the material. In: Qin: The method of the present invention can be used in the more time-consuming steps required to speed up the process of the invention to accelerate the process; the body-process, must be _ 5 - 3 invention purpose and summary: Looking forward to the above invention In the above method, the metal bismuth compound cannot be formed locally on the logic circuit by the method of transmitting the button ΦL ', j, and the first method of the present invention utilizes a mask layer P ' array F Η p ...? t peripheral circuit area and cell: : the idle pole on the domain and the diffusion region on the peripheral circuit region form a metal

物，以降低晶胞陣列區域籍周邊電路區 w〇rd line)的電阻。 -予兀琛C 本發明的第二個目的為利用一矽層所作為的遮罩声，順利在周邊電路區域與晶胞陣列區域上的閘極及周邊^路區域上之擴散區域形成金屬矽化物，以避免晶胞陣列區上之擴散區域發生漏電流之缺陷。一Object to reduce the resistance of the cell array region to the peripheral circuit region w〇rd line). - 兀琛C The second object of the present invention is to form a metal smear in the diffusion region of the gate region and the peripheral region on the peripheral circuit region and the cell array region by using the mask sound as a layer of the layer. To avoid the leakage current leakage in the diffusion region on the cell array region. One

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本發明的第三個目沾盔；丨田_ μ院丨暗利产田息心办目的為利用一石夕層所作為的遮罩層，區域=域與晶胞陣列區域上的閘極及周邊電路域形成金屬…’以減少周邊電路區域石夕層所作為的遮罩層，域上的閘極及周邊電路，以提高半導體元件之本發明的第四個目的為利用一 ^利在周邊電路區域與晶胞陣列區區域上之擴散區域形成金屬矽化物品質0 今、％ % I丹一個目的為利用一矽層所 =在周邊電路區域與晶胞陣列區域上的 &域上之擴散區域形成金屬矽化物，周邊電路製程運作效率。 # N +導體元件之根據以上所述之目的，本發明提供了一一矽層所作為的遮罩層，順利在周邊電路區试法，利用區域上的閘極及周邊電路區域上之擴散區^=晶胞陣列物，以降低晶胞陣列區域及周邊電路區域之二或金屬石夕化並避免晶胞陣列區域上之擴散區域發生漏☆元線的電阻發明之方法也可減少周邊電路區域上之電阻，L之缺陷。本法更可提高半導體元件之品質並提高半導]t發明之方作效率。、暇疋件之製程運 5 一 4發明詳細說明：The third object of the present invention is a helmet; the 丨田_μ院丨密利产田心心目 aims to use a layer of the layer as a mask layer, the area = domain and the cell gate array area and the periphery The fourth domain of the present invention is to reduce the thickness of the peripheral circuit region by using a barrier layer, a gate layer on the domain, and a peripheral circuit to improve the semiconductor device. The region and the diffusion region on the region of the cell array region form a metal telluride quality. Now, %% I Dan is intended to utilize a layer of germanium = a diffusion region on the & field in the peripheral circuit region and the cell array region. The formation of metal telluride, peripheral circuit process efficiency. # N + Conductor Element According to the above purpose, the present invention provides a mask layer as a layer of germanium, which is successfully tested in the peripheral circuit region, utilizing the gate on the region and the diffusion region on the peripheral circuit region. ^=cell array to reduce the cell array region and the peripheral circuit region or the metallization and avoid the leakage of the diffusion region on the cell array region. The method of the invention can also reduce the peripheral circuit region. The resistance on the upper side, the defect of L. This method can improve the quality of semiconductor components and improve the efficiency of semiconductors. , the process of the piece of equipment 5 4 invention details:

1251272 本發明的一些實施例會詳細描述如下。然而細描述外二本發明還可以廣泛地在其他的實施例本發明的範圍不受限定，其以之後的專利範圍為邏輯電路主要是藉由字元線（w〇rd 11〇6)與 bit line)來連接邏輯電路上之半導體元件。字的為定義訊號之位置，而位元線之目的則為判定型，因此字元線連接至半導體元件之閘極，而位至半導體元件上之源極/汲極。對於字元線而言有較高之傳輸速度傳輸資料，因此必須利用本發在字元線及半導體元件之閘極上形成一金屬矽化低字元線之電阻，提高字元線之傳輸速度。，除了詳施行，且準。位元線（元線的目訊號之類兀線連接，其需要 _ 明之方法物，以降邏輯胞陣列區的功能為的儲存元資料，藉器等元件由周邊電須個別獨邊電路區度。所以極與擴散電路上主域另一儲存資料件之内。由周邊電，對所需路傳導致立以防止域之元件必須運用區域上形要區分為區域則為，將資料而周邊電路區域内處理之資其他區域因短路的則必須相本發明之成金屬石夕兩大區周邊電以電荷路區域之元件料進行。因此缺陷所互連結方式，化物，域，其路區域的模式之功能，像是處理，晶胞陣造成資，以加在周邊同時在中之一。晶胞儲存在則為傳加法器處理完列區域料的流快資料電路區晶胞陣區域為晶陣列區域晶胞陣列導及運算或是減法之後並藉彳的元件必失。而周之處理速域上之閘列區域上1251272 Some embodiments of the invention are described in detail below. However, the invention may be broadly defined in other embodiments without limitation. In the following patent scope, the logic circuit is mainly by word line (w〇rd 11〇6) and bit. Line) to connect the semiconductor components on the logic circuit. The word is defined as the position of the signal, and the purpose of the bit line is the decision type, so the word line is connected to the gate of the semiconductor element and to the source/drain on the semiconductor element. For the word line, there is a higher transmission speed transmission data. Therefore, it is necessary to form a metal-deuterated low-word line resistor on the word line and the gate of the semiconductor element to improve the transmission speed of the word line. Except for detailed implementation, and accurate. The bit line (the line of the source line or the like is connected, which requires the method of the method to store the metadata of the function of the logic cell array area, and the components such as the device must be individually unilaterally circuitized by the peripheral power. Therefore, the pole and the diffused circuit are in the other stored data piece of the main domain. By the surrounding power, the required path is led to prevent the components of the domain from being used, and the area must be divided into regions, and the data and peripheral circuit regions are In other areas of the internal processing, the short circuit must be carried out in the vicinity of the metal regions of the present invention. The electrical components of the two regions are carried out by the component materials of the charge path region. Therefore, the mode of interconnection, the compound, the domain, and the mode of the road region are , such as processing, the cell array is used to add one to the periphery at the same time. The unit cell is stored in the flow fast data circuit area of the crystal region for the transfer device to be the crystal array region crystal After the cell array is guided or operated, or after subtraction, the components that are borrowed must be lost.

1251272 案號901185昍五、發明說明（6) 之閘極形成金屬矽列區域上的擴散區力與資料運算能力象而導致資料的流化物，並避免金屬域，以加快周邊電，並防止晶胞陣列失0 矽化物形成於晶胞陣路區域之資料傳輸能區域發生漏電流之現參照第三圖所示，首先提供一包含底材1〇〇之晶圓並在底材100上形成一第一氧化物層12〇，接下來在此第一氧化物層120上形成一氮化物層140，最後在此氮化物層i4f 上形成一第二氧化物層1 60。通常此第一氧化物層丨2"〇之厚度約為70至90埃，氮化物層140之厚度約為6〇至8〇埃，而第二氧化物層160之厚度大約為60至80埃。在目前的製程中通常採用第一氧化物層120的厚度為8〇埃，氮化物層140的厚度為70埃’而第二氧化物層160的厚度則為埃。但是隨著製程寬度曰漸縮小，第一氧化物層丨2〇、氮化、物層1 4 0與第二氧化物層1 6 〇之厚度也必須隨著縮小，以符合製程上之需求。參照第四圖所示，接下來在晶圓上定義晶胞陣列區域 104與周邊電路區域1〇2後，藉由一微影 (photolithography)及姓刻（etching)之方式移除周邊電路區域102上之第一氧化物層120、氮化物層140與第二氧化物層160，使周邊電路區域1〇2露出底材。參照第五圖所示，在周邊電路區域102之底材上形成一第三氧化物層 200，此第三氧化物層20 0之厚度約為40至60埃，在目前之製程中，第三氧化物層200之厚度通常為50埃。但是隨著1251272 Case No. 901185昍5, invention description (6) The formation of the diffusion region force on the metal-parallel region of the gate and the data computing capability of the gate cause the data to flow, and avoid the metal domain to accelerate the peripheral electricity and prevent the crystal The cell array is lost. The leakage current is formed in the data transmission energy region of the cell array region. Referring to the third figure, a wafer containing the substrate 1 is first provided and a substrate 100 is formed. A first oxide layer 12 is formed, a nitride layer 140 is formed on the first oxide layer 120, and a second oxide layer 160 is formed on the nitride layer i4f. Typically, the first oxide layer 丨 2 " 〇 has a thickness of about 70 to 90 angstroms, the nitride layer 140 has a thickness of about 6 〇 to 8 Å, and the second oxide layer 160 has a thickness of about 60 to 80 angstroms. . In the current process, the thickness of the first oxide layer 120 is generally 8 Å, the thickness of the nitride layer 140 is 70 Å, and the thickness of the second oxide layer 160 is Å. However, as the width of the process is gradually reduced, the thicknesses of the first oxide layer, the nitride layer, the layer 110 and the second oxide layer 16 must also be reduced to meet the processing requirements. Referring to the fourth figure, after the cell array region 104 and the peripheral circuit region 1〇2 are defined on the wafer, the peripheral circuit region 102 is removed by a photolithography and an etching method. The first oxide layer 120, the nitride layer 140 and the second oxide layer 160 are disposed to expose the peripheral circuit region 1〇2 to the substrate. Referring to the fifth figure, a third oxide layer 200 is formed on the substrate of the peripheral circuit region 102. The thickness of the third oxide layer 20 is about 40 to 60 angstroms. In the current process, the third The thickness of the oxide layer 200 is typically 50 angstroms. But with

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__案號 90118^ 五、發明說明（7) 製程寬度曰漸縮小’第三氧化物層2〇〇之厚度也必須隨― 縮小’以符合製程上之需求。通常第—氧化物層丨2〇 & ^ 一氧化物層160及苐三氧化物層200之材料為二氧化秒（ silicon dioxide)，而氮化物層140的材料通常為氮化石夕 silicon nitride) 〇在本實施例中’晶圓上的晶胞陣列區域與周邊電路區域在底材上採用不同形式之介電層。在晶胞陣列區域上& 用氧化物/氮化物/氧化物的三明治型態作為介電層，而在周邊電路區域則採用單一一層氧化物作為介電層。隨著製程需求之不同，在晶胞陣列區域與周邊電路區域在底材上也可採用相同形式之介電層以發揮半導體元件之效能。此介電層可為一氧化物層。__ Case No. 90118^ V. Description of the invention (7) The width of the process is gradually reduced. The thickness of the third oxide layer 2 must also be reduced to meet the requirements of the process. Usually, the material of the first oxide layer 丨2〇& ^ oxide layer 160 and the tantalum oxide layer 200 is silicon dioxide, and the material of the nitride layer 140 is usually silicon nitride. In the present embodiment, the cell array region on the wafer and the peripheral circuit region employ different dielectric layers on the substrate. A sandwich type of oxide/nitride/oxide is used as the dielectric layer on the cell array region, and a single layer of oxide is used as the dielectric layer in the peripheral circuit region. Depending on the process requirements, the same form of dielectric layer can be used on the substrate in the cell array region and the peripheral circuit region to achieve the performance of the semiconductor device. The dielectric layer can be an oxide layer.

#參照第六圖所示，形成一矽層3〇〇於第二氧化物層16〇與第二氧化物層2 〇〇之上，此矽層3 〇〇為一閘極層。參照第七圖=示，接下來在周邊電路區域1〇2上定義閘極之位置，並藉由一微影及蝕刻的製程移除周邊電路區域1〇2上的部分矽層，以在周邊電路區域1〇2上形成多數個第一閘極 400與多數個第-擴散區45〇，此多數個第一擴散區45〇位於夕數個第一閘極4 〇〇的兩側。接下來進行輕摻雜汲極（ lightly doped drain; LDD )之製程，以在多數個第一擴月欠區4 5 0内形成一輕度摻雜之汲極區域3 2 〇。此製程的目的為用以降低熱載子效應（h〇t carrier effects)所造成之缺陷。# Referring to the sixth figure, a germanium layer 3 is formed over the second oxide layer 16? and the second oxide layer 2?, and the germanium layer 3 is a gate layer. Referring to the seventh figure, the position of the gate is defined on the peripheral circuit area 1〇2, and a part of the germanium layer on the peripheral circuit area 1〇2 is removed by a lithography and etching process to be around. A plurality of first gates 400 and a plurality of first diffusion regions 45A are formed on the circuit region 〇2, and the plurality of first diffusion regions 45 〇 are located on both sides of the first plurality of first gates 4 夕. Next, a lightly doped drain (LDD) process is performed to form a lightly doped drain region 3 2 在 in the majority of the first expanded region 450. The purpose of this process is to reduce the defects caused by the h〇t carrier effects.

第10頁 1251272 ____案號90118555_年月日修正五、發明說明（8) 參照第八圖所示，在進行輕摻雜汲極之製程後，在第二氧化物層1 6 0、晶胞陣列區域1 0 4上之矽層3 0 0、多數個第一閘極400與多數個第一擴散區4 50上形成一間隙壁層，並藉由一微影及蝕刻的製程以在晶胞陣列區域1 04上之石夕層3 0 0與多數個第一閘極40 0的側壁上形成間隙壁5 0 0。參照第九圖所示，定義周邊電路區域1 〇 2上之閘極/汲極之位置後，植入製程上所需之離子，以在多數個第一擴散區4 5 0内形成源極/沒極5 5 0。參照第十圖所示，形成一金屬層600於晶胞陣列區域1〇4上之矽層300、多數個第一閘極40 0與多數個第一擴散區450上，在沉積金屬層前，首先先使用濕式清潔法清除矽層3 0 0與基板上的氧化物，使得金屬石夕化物較易形成。大部分使用化學氣相沉積法或是Page 10 1251272 ____ Case No. 90118555_ Year Month Day Correction V. Invention Description (8) Referring to the eighth figure, after the process of lightly doping the drain, in the second oxide layer 160, crystal a spacer layer 300 is formed on the cell array region 110, a plurality of first gates 400 and a plurality of first diffusion regions 420 are formed on the cell array region by a lithography and etching process. A spacer 500 is formed on the sidewall of the plurality of first gates 40 0 on the cell array region 104. Referring to the ninth figure, after defining the position of the gate/drain on the peripheral circuit region 1 〇 2, the ions required for the process are implanted to form a source in a plurality of first diffusion regions 450 / Nothing 5 5 0. Referring to FIG. 10, a metal layer 600 is formed on the germanium layer 300 on the cell array region 1〇4, the plurality of first gates 40 0 and the plurality of first diffusion regions 450, before depositing the metal layer. First, the wet layer cleaning method is used to remove the oxide layer on the substrate and the oxide on the substrate, so that the metallization is easier to form. Most use chemical vapor deposition or

磁控直流電錢鍍法來沉積此金屬層6 〇〇。接下來，將晶圓送入反應，室中進行第一快速加熱製程，使金屬層6 〇〇與接觸處之石夕反應’以形成金屬石夕化物（metal siiicide) 第快物圖層金屬矽化照或在多數個第一第十反應後所晶胞陣列，將C - 4 9才目之結構。第速的所殘擴之加熱製程的溫度大約為500至7〇〇 t。此時的結構主要是電阻值較高之c — 49相的結構。參示，利用RCA清洗的方式來去除未參與反應留的金屬層600，而將金屬矽化合物層62〇留域104上之矽層3〇〇、多數個第一閘極與散區450上。最後再執行第二快速加熱製程金屬矽化物結構轉換成電阻值較低的c 5 4相 f夬速加熱製程的溫度大約為7 5Magnetron DC plating is used to deposit this metal layer 6 〇〇. Next, the wafer is sent to the reaction, and the first rapid heating process is performed in the chamber, so that the metal layer 6 反应 reacts with the stone in the contact portion to form a metal siiicide. Or in the array of unit cells after the majority of the first tenth reaction, the structure of C-49 is the only one. The temperature of the first speed of the reheating process is approximately 500 to 7 Torr. The structure at this time is mainly a structure of a c-49 phase having a high resistance value. Referring to the RCA cleaning method, the metal layer 600 not participating in the reaction is removed, and the metal germanium compound layer 62 is disposed on the germanium layer 3 of the germanium region 104, and the plurality of first gates and the bulk region 450. Finally, the second rapid heating process is performed. The metal halide structure is converted into a c 5 4 phase with a low resistance value. The temperature of the idle heating process is about 7 5 .

第11頁 ^^90118555 1251272Page 11 ^^90118555 1251272

五、發明說明（9) 金屬層600的材質可為鈦金屬層60 0的材皙人^ 專通常使用鈦為此灯貝。為了配合製程的需唳，属600層之前，會移除多數個第-擴散區上^在f積金層20。，以提高半導體元件之品質：1之第二氧化物鈦是現在自對準金屬矽化物製程中最料。在適當的溫度下，欽極易與金的方-材 =(It夕因交互擴散而形成匕口物Ultanium silicide; TiSi2)。 y di:金屬石夕化物的製程中，9曰曰包陣列區域上之石夕 Γ6Λ失Λ，可避免金屬矽化物形成於第二氧化物層製程後/定義Λ二鱼圖所示，在完成自對準金屬石夕化物之衣耘後疋義日日胞陣列區域1 04上之閘極位置，並經由一微影及蝕刻之製程移除部分晶胞陣列上之矽層3〇〇了以在第二氧化物層160上形成多數個第二閘極7〇〇與多數個第二擴散區域75 0。此多數個第二擴散區75〇位於多數個第一閘極7 0 〇的兩侧。在移除部分晶胞陣列上之矽層的蝕刻製程時，餘刻製程可停止於第二氧化物層丨6〇、氮化物層丨4〇或是第一氧化物層1 2 0。根據以上所述之實施例，本發明提供了一項方法，利用一矽層所作為的遮罩層，順利在周邊電路區域與晶胞陣列區域上的閘極及周邊電路區域上之擴散區形成金屬矽化物，以降低晶胞陣列區域之字元線的電阻並避免晶胞陣列V. Description of the Invention (9) The material of the metal layer 600 may be a material of the titanium metal layer 60 0. The titanium is usually used for this purpose. In order to meet the needs of the process, before the 600 layer, most of the first-diffusion regions are removed. To improve the quality of semiconductor components: 1 of the second oxide Titanium is now the best in the self-aligned metal telluride process. At the appropriate temperature, Qin is easy to form with gold - (It is formed by the interdiffusion of Ultanium silicide; TiSi2). y di: In the process of metal lithium, the Γ Γ 6Γ on the array of 9 曰曰 Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Self-aligning the metallization of the metallurgical layer, and then removing the gate layer on the array of cell arrays by a lithography and etching process. A plurality of second gates 7A and a plurality of second diffusion regions 75 0 are formed on the second oxide layer 160. The plurality of second diffusion regions 75 are located on either side of the plurality of first gates 70 〇. When the etching process of the germanium layer on the partial cell array is removed, the residual process may stop at the second oxide layer 〇6〇, the nitride layer 丨4〇 or the first oxide layer 120. According to the embodiments described above, the present invention provides a method for smoothly forming a diffusion region on a gate region and a peripheral circuit region on a peripheral circuit region and a cell array region by using a mask layer as a mask layer. Metal telluride to reduce the resistance of the word line of the cell array region and avoid cell arrays

第12頁 1251272 案號90118555 年月曰修正五、發明說明（10) 區域上之擴散區域發生漏電流之缺陷。本發明也可減少周邊電路區域上之電阻。本發明更可提高半導體元件之品質並提高半導體元件之製程運作效率，不僅具有實用功效外，並且為前所未見之設計，具有功效性與進步性之增進，故已符合專利法之要件，爰依法具文申請之。為此，謹貴審查委員詳予審查，並祈早曰賜准專利，至感德便。以上所述僅為本發明之較佳實施例而已，此實施例僅係用來說明而非用以限定本發明之申請專利範圍。在不脫離本發明之實質内容的範疇内仍可予以便化而加以實施，此等變化應仍屬本發明之範圍。因此，本發明之範疇係由以下之申請專利範圍所界定。Page 12 1251272 Case No. 90118555 Month 修正 Amendment V. Invention Description (10) Defects in leakage current in the diffusion region of the area. The present invention also reduces the resistance on the peripheral circuit area. The invention can improve the quality of the semiconductor component and improve the process operation efficiency of the semiconductor component, and has the practical effect, and is unprecedented in design, has the improvement of efficacy and progress, and thus has met the requirements of the patent law. Apply in accordance with the law. To this end, I would like to ask the review committee for detailed review, and pray for granting patents as soon as possible. The above is only the preferred embodiment of the present invention, and this embodiment is for illustrative purposes only and is not intended to limit the scope of the invention. It is still possible to carry out the invention without departing from the spirit and scope of the invention, and such variations are still within the scope of the invention. Accordingly, the scope of the invention is defined by the scope of the following claims.

第13頁 SS.^90118555 !251272Page 13 SS.^90118555 !251272

i 月日_itJL 圖式簡單說明屬層=示，^運用傳統技術在金氧半電晶體上沉積一鈦金上π ί二圖為運用傳統技術在閘極區域與源極/汲極區域上形成鈦矽化物之示意圖；與第第底材上形成第一氧化物層、氮化物層意圖；層與====區域之第-氧化物層、氮化物卜> 第ίΞ為形成一第三氧化物層於周邊電路區域之底材上ι不思圖；上之工為形成-矽層於第二氧化物層與第三氧化物層形成輕摻雜汲極個第第：在周邊電路區域形成多數個第-閘極與多數個弟一擴散區，並在多數個第一擴散區内之不意圖；的側…層與多數個第一閘極第14頁 1251272 案號 90118555 年月曰修正圖式簡單說明第九圖為在多數個第一擴散區内形成源極/汲極之示意圖，第十圖為形成一金屬層於晶胞陣列區域上之矽層、多數個第一閘極與多數個第一擴散區上之示意圖；第十一圖為在晶胞陣列區域上之矽層、多數個第一閘極與多數個第一擴散區上形成金屬矽化合物層之示意圖；及第十二圖為在第二氧化物層上形成多數個第二閘極與多數個第二擴散區域之示意圖。主要部份之代表符號： 10 底材 Φ 12 源極/汲極區域 14 閘極氧化物層 16 多晶矽層 18 間隙壁 2 0 鈦金屬層 22 鈦矽化合物層 30 淺渠溝隔離層 1 0 0 底材 102 周邊電路區域 1 0 4 晶胞陣列區域i month _itJL diagram simply shows the genus layer = show, ^ using traditional techniques to deposit a titanium on the gold-oxygen semi-transistor π ί two maps using conventional techniques in the gate region and the source / drain region A schematic diagram of forming a titanium telluride; forming a first oxide layer and a nitride layer on the first substrate; a first oxide layer of the layer and the ==== region, a nitride buck; The triple oxide layer is on the substrate of the peripheral circuit region; the upper layer is formed to form a germanium layer on the second oxide layer and the third oxide layer to form a lightly doped drain electrode: in the peripheral circuit The region forms a majority of the first-gate and most of the brother-diffusion zones, and is not intended in the majority of the first diffusion zone; the side layer and the majority of the first gates page 14 1251272 case number 90118555 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 9 is a schematic diagram showing the formation of a source/drain in a plurality of first diffusion regions, and the tenth is a layer in which a metal layer is formed on a cell array region, and a plurality of first gates are formed. Schematic diagram with a plurality of first diffusion regions; eleventh image is at the unit cell A schematic diagram of forming a metal germanium compound layer on the germanium layer, a plurality of first gates, and a plurality of first diffusion regions on the column region; and a twelfth pattern forming a plurality of second gates on the second oxide layer A schematic representation of a plurality of second diffusion regions. Representative symbols for the main parts: 10 Substrate Φ 12 Source/drain region 14 Gate oxide layer 16 Polysilicon layer 18 Gap 2 0 Titanium layer 22 Titanium bismuth compound layer 30 Shallow trench isolation layer 1 0 0 Material 102 Peripheral Circuit Area 1 0 4 Cell Array Area

第15頁 1251272 案號 90118555 修正圖式簡單說明 120 140 160 200 300 320 400 450 500 550 600 620 700 750 第一氧化物層氮化物層第二氧化物層第三氧化物層矽層輕度摻雜之汲極區域多數個第一閘極多數個第一擴散區域間隙壁在多數個第一擴散區内所形成之源極/汲極金屬層金屬石夕化合物層多數個第二閘極多數個第二擴散區域 ΦPage 15 1251272 Case No. 90118555 Corrective Description of Modification 120 140 160 200 300 320 400 450 500 550 600 620 700 750 First oxide layer nitride layer second oxide layer third oxide layer 轻 layer lightly doped a plurality of first gates, a plurality of first diffusion regions, a plurality of first diffusion regions, a source/drain metal layer formed in a plurality of first diffusion regions, and a plurality of second gates Two diffusion region Φ

第16頁Page 16

Claims

1251272 案號 90118555 六、申請專利範圍修正種在一局部區域形成一自對準金屬矽化物的方法，其中至少包含：提供形成一第形成一氮形成一第移除部分層以在該晶圓形成一第形成一石夕移除部分一閘極與一多位於該多數個晶圓，該晶一氧化物層於該圓至少包含一底材；化物層於該第一二氧化物層於該之該第二氧化物之一第一區域露層於該二氧化以在該擴散區三氧化物層於該第之該矽層數個第一第一閘極之一側底材上；氧化物層上；氮化物層；層、氮化物層與第一氧化物出該底材；第一區域之該底材上；物層與該第三氧化物層上；第一區域上形成一多數個第域’该多數個第一擴散區域側壁形成一間隙壁於該多數個第一閘極與該矽層之植入一離子以在該多數個第一擴散區域内形極/汲極區域； ^一金屬該多*個第1極、該多數擴欢&域與該矽層上；個莖！一快速加熱製程以在該多數個第-間極、該多數弟一擴散區域與該矽層上形成一金屬矽化物屛；移除該金屬層；及曰之一：除rt該石夕層與部分之該金屬石夕化物層以在該晶圓第一區域上形成一多數個第二閘極與—多數個第二擴1251272 Ref. No. 90118555. The method for modifying a seed to form a self-aligned metal telluride in a partial region, comprising at least: providing a formation of a first formation of a nitrogen to form a removed portion of the layer to form on the wafer Forming a stone to remove a portion of the gate and a plurality of the plurality of wafers, the crystalline oxide layer comprising at least one substrate in the circle; the layer of the compound on the first dioxide layer a first region of the second oxide is exposed on the oxide layer in the diffusion region, and the first oxide layer is on the first substrate of the first first gate; a nitride layer; a layer, a nitride layer and a first oxide exiting the substrate; a substrate on the first region; a layer on the third oxide layer; and a plurality of layers on the first region a plurality of sidewalls of the plurality of first diffusion regions form a spacer to implant an ion between the plurality of first gates and the germanium layer to form a pole/drain region in the plurality of first diffusion regions; More than * metal An electrode, the most spread joy & domains on the silicon layer; a stem! a rapid heating process to form a metal telluride layer on the plurality of first-interpoles, the majority-diffusion region and the germanium layer; removing the metal layer; and one of the germanium layers: in addition to the rt Part of the metallization layer to form a plurality of second gates on the first region of the wafer and - a plurality of second extensions

1251272 案號90118555 年月曰修正六、申請專利範圍散區域。 2.如申請專利範圍第1項的方法，其中上述之金屬層之一材料為鈦。 3.如申請專利範圍第1項的方法，其中上述之金屬層之一材料為始。 4.如申請專利範圍第1項的方法，其中上述之金屬層之一材料為白金。 5. 如申請專利範圍第1項的方法，其中上述之第一區域為一周邊電路區域。 6. 如申請專利範圍第1項的方法，其中上述之第二區域為一晶胞陣列區域。 7. —種在一局部區域形成一自對準金屬石夕化物的方法，其中至少包含：提供一晶圓，該晶圓至少包含一底材；形成一第一氧化物層於該底材上；形成一氮化物層於該第一氧化物層上；形成一第二氧化物層於該氮化物層；移除部分之該第二氧化物層、氮化物層與第一氧化物1251272 Case No. 90118555 Month 修正 Amendment VI. Patent Application Scope. 2. The method of claim 1, wherein one of the metal layers is titanium. 3. The method of claim 1, wherein the material of one of the metal layers is the beginning. 4. The method of claim 1, wherein one of the metal layers is platinum. 5. The method of claim 1, wherein the first region is a peripheral circuit region. 6. The method of claim 1, wherein the second region is a cell array region. 7. A method of forming a self-aligned metal lithium in a localized region, comprising at least: providing a wafer comprising at least one substrate; forming a first oxide layer on the substrate Forming a nitride layer on the first oxide layer; forming a second oxide layer on the nitride layer; removing a portion of the second oxide layer, the nitride layer and the first oxide

第18頁 1251272 案號 90118555 曰修正六、申請專利範圍層以在該晶圓之一第一區域露出該底材；形成一第三氧化物層於該第一區域之該底材上；形成一矽層於該第二氧化物層與該第三氧化物層上；移除部分之該矽層以在該第一區域上形成一多數個第一閘極與一多數個第一擴散區域，該多數個第一擴散區域位於該多數個第一閘極之一側；形成一輕摻雜汲極於該多數個第一擴散區内；形成一間隙壁於該多數個第一閘極與該石夕層之一側壁植入一離子以在該多數個第一擴散區域内形成一源極/汲極區域；形成一金屬層於該多數個第一閘極、該多數個第一擴散區域與該矽層上；進行一第一快速加熱製程以在該多數個第一閘極、該多數個第一擴散區域與該矽層上形成一金屬矽化物層；移除該金屬層並進行一第二快速加熱製程；及移除部分該矽層與部分之該金屬矽化物層以在該晶圓之一第二區域上形成一多數個第二閘極與一多數個第二擴散區域。 8. 如申請專利範圍第7項的方法，其中上述之金屬層之一材料為鈦。 9. 如申請專利範圍第7項的方法，其中上述之金屬層之一Page 18 1251272 Case No. 90118555 曰 Amendment 6. Applying a patent range layer to expose the substrate in a first region of the wafer; forming a third oxide layer on the substrate of the first region; forming a a layer of germanium on the second oxide layer and the third oxide layer; removing a portion of the germanium layer to form a plurality of first gates and a plurality of first diffusion regions on the first region a plurality of first diffusion regions are located on one side of the plurality of first gates; forming a lightly doped drain in the plurality of first diffusion regions; forming a spacer on the plurality of first gates One side of the layer is implanted with an ion to form a source/drain region in the plurality of first diffusion regions; a metal layer is formed on the plurality of first gates, and the plurality of first diffusion regions And performing a first rapid heating process to form a metal telluride layer on the plurality of first gates, the plurality of first diffusion regions and the germanium layer; removing the metal layer and performing a Second rapid heating process; and removing part of the Layer and the metal silicide layer to form a portion of the plurality of second gate and a plurality of second diffusion region of the second region on one wafer. 8. The method of claim 7, wherein one of the metal layers is titanium. 9. The method of claim 7, wherein one of the above metal layers

第19頁 1251272 ΛΜ 90118555 六、申請專利範圍材料為鈷。月曰修正 1 〇 ·如申請專利範圍第7 材料為白金。員的方法，其中上述之金屬層之一 11 ·如申請專利範圍第7 一周邊電路區域。項的方法，其中上述之第一區域為局部區域形成一自對準金㈣物的方法，底材，該底材至少包提供一晶圓，該晶圓至少包含一含一第一區域與一第二區域；形成一氧化物層於該底材上；形成一矽層於該氧化物層上；移除部分之該矽層以在該第一區域上形成一多一閘極與一多數個第一擴散區域，該多數個第一擴 7第位於該多數個第一閘極之一侧； κ敢區域側壁形成一間隙壁於5亥多數個第一^閘極與該碎層之源植入一離子以在該多數個第一擴散區域内形成極/汲極區域；Page 19 1251272 ΛΜ 90118555 VI. Scope of Application The material is cobalt. Month 修正 Correction 1 〇 · If the patent application area is 7th, the material is platinum. The method of the member, wherein one of the above metal layers is 11 · as in the patent application range 7 a peripheral circuit area. The method of the present invention, wherein the first region is a partial region forming a self-aligned gold (four) material, the substrate, the substrate is provided with at least one wafer, and the wafer comprises at least one first region and one a second region; forming an oxide layer on the substrate; forming a germanium layer on the oxide layer; removing a portion of the germanium layer to form a plurality of gates and a majority on the first region a first diffusion region, the plurality of first extensions 7 are located on one side of the plurality of first gates; the sidewall of the κ dare region forms a gap wall at a plurality of first gates and a source of the layer Implanting an ion to form a pole/drain region in the plurality of first diffusion regions;

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1251272 修正1251272 amendment

-- 案號901彳郎[^ 六、申請專利範圍 =成金屬層於該多數個第一閘極、該多數個第一擴散區域與該矽層上； ^擴個楚，仃一快速加熱製程以在該多數個第一閘極、該多數擴散區域與該矽層上形成一金屬矽化物層；移除該金屬層；及之一 ^刀該矽層與部分之該金屬矽化物層以在該晶圓散ΐ Ϊ ,區域上形成一多數個第二閘極與一多數個第二擴述之金屬層之 14·如申請專利範圍第13項的方法，其中上一材料為鈦。〃 t5·#如，申請專利範圍第13項的方法，其甲上述之金屬層之材料為銘·。 =·如申請專利範圍第13項的方法，其中上述之金屬層之 —材料為白金。如申請專利範圍第13項的方法，其中上述之第一區域為一周邊電路區域。如申請專利範圍第1 3項的方法，其中上述之第二區域為一晶胞陣列區域。-- Case No. 901 彳 Lang [^ Sixth, the scope of application for the patent = metal layer on the majority of the first gate, the majority of the first diffusion region and the layer of 矽; ^ expansion Chu, 仃 a rapid heating process Forming a metal telluride layer on the plurality of first gates, the plurality of diffusion regions and the germanium layer; removing the metal layer; and etching the germanium layer and a portion of the metal germanide layer to The wafer is formed by a plurality of second gates and a plurality of second expanded metal layers. The method of claim 13 wherein the upper material is titanium. 〃 t5·# For example, in the method of claim 13, the material of the above metal layer is Ming·. = The method of claim 13, wherein the material of the above metal layer is platinum. The method of claim 13, wherein the first region is a peripheral circuit region. The method of claim 13, wherein the second region is a unit cell array region.

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