1250827 案號：093107646 玖、發明說明： 【發明所屬之技術領域】 本發明提供一種經由多層電路板上之凸塊焊墊（bumpe;f pad)來 設置（route)複數個訊號繞線（Signai trace)的方法，尤指一種於 多層電路板上設置複數個訊號繞線及複數個屏蔽繞線（shielding trace)的區塊式佈線方法。 【先前技術】 於具有南度發展之電腦技術的現代社會中，包含有複數個積體電 路的電腦系統已經廣泛地運用在各個不同領域裡。舉例來說，具有自 動控制系統的家用設備、行動通訊裝置以及個人電腦都是利用積體電 路來實現某些特定功能。積體電路的主體是由習知半導體製程所生產 的晶粒（die)構成，該晶粒的製程始於製造晶圓（wafer)，然後，每 一個晶圓再被分成複數個區塊，因此，便可藉由習知半導體製程於每 個區塊中形成複數個電路，最後，晶圓上每個加工過的區塊便進一步 地被切割賴數個晶粒。當麟所需的晶減，仍需使麟殊方式將 該晶粒電連接於-電路，例如―_電路板（pHntedeireuitb〇ard， PCB)上。因此，該晶粒便能夠從印刷電路板上獲得所需的操作電壓以 執行-預定操作。舉例來說，假設—晶粒的功能對應於—編碼電路， 所以’當該編碼電路接收到適當的操作電壓後，該晶粒就能對印刷電 路板所輸人的f料進行編碼處理，並將完成編碼後的資料回傳至印刷 電路板。 某些積體電路之晶粒，例如習知之引線接合晶粒（wire—b〇nd IC )係於其日日粒周圍5又置金屬連接墊（肥拉1 pa(J)，用來 1為Hx連接H粒與外部訊號，例如控制訊號，電源端以及接地 端。-般而言，引線接合晶粒係設置於一塑膠或陶竟封裝體（阳冰哪） 1250827 案號：〇93107646 裝體上的接斤以晶粒周圍的金屬連接墊與封 然而’上述的封裝方式有其一 =:::一特定大小的晶粒而言’其所=== 納的邏輯閘‘量：:::此外’然而隨著科技的進展’晶粒中所容 地端的τ…更需摘外佈線以將減（_是電源端與接 用曰 晶粒内部的邏輯電路；第三，在引線接合晶粒中， /晶粒與封裝體上接腳的金屬線會產生額外的組抗值 resistance)與電感值（inductance)而惡化晶粒的效能。 1為了改。上述問題’覆晶封裝（fHp—cj^p卿㈣恤）已成為今 日較佳的雖对。覆晶封裝技術使得封裝翻整體尺寸可更緊密， 且=車乂於引線接合晶粒’該晶粒與外部電子零件連結的連接所產生的 阻抗值與電紐更小。另外，因為該晶粒與賴端與接地端的連線距 離縮短，所以能獲得較高品f的電源供應。然而，即使是應用覆晶封 裝技術’晶粒的實際大小仍無可避免地m粒上分佈之凸塊焊塾的 大小與數量所影響。由於市場激烈競爭，因此不斷刺齡業來研發與 生產尺寸更小的，更有效的，以及高效能的產品，因此如何縮小產品 尺寸以符合生產成本考量已成為一重要課題。 為了達到節省空間的優點，電子系統中也應用多層基板（例如一 電路板）的技術。現今多層基板可應用不同的製造方式來生產，例如 多層基板可以是薄片堆®基板（laminated substrate)或積沉基板 (build-up substrate)，而於上述不同的製造方式所生成的多層基板 中’由於積沉基板上之訊號線路的線寬可細至3〇，所以積沉基板係 最適合應用於多接腳數需求的裝置以擴展習知電路板的電路密度。請 1250827 案號：0931〇7646 參閱圖一與圖二，圖一為習知於六層增層式基板12上配置一晶粒10 的示意圖，而圖二為圖一所示之六層增層式基板12的示意圖。六層增 層式基板12包含四個内層12A、12B、12E、12F，用於配置複數個訊號 繞線，其中每個内層可提供線寬/線距為25/zm/25//m的接線以及徑 長110//m的導通孔12G。另外的二層12C、12D各自提供線寬/線距為 100 // m/100 // m的接線及440 // m的導通孔12H。基於上述六層增層式 基板12的結構，當應用六層增層式基板12時，只有四個内層12A，12B， 12E，及12F可用來佈置訊號繞線，因為剩下的兩層12C，12D之間可 提供較大的導通孔(440 // m) 12H來提供電源與接地，所以上述兩層12C， 12D則不宜讓訊號繞線經過。 請參閱圖三，圖三為圖一所示之框示區域14的放大示意圖。圖三 所示之實施例顯示複數個訊號繞線18自晶粒1〇電連接至圖二所示之 六層增層式基板12。圖三之實施例顯示所有的訊號繞線都被設計成電 連接至内層12A，12B，所以，複數個訊號繞線18可根據位於内層12A 或12B而分為位於第一層的訊號繞線18(1)與第二層的訊號繞線 18(2)。睛參閱圖四，圖四係為設置於圖一、三所述之晶粒1〇上之凸 塊焊墊20的示意圖。複數個凸塊焊墊20係用來作為晶粒1〇之輸入/ 輸出的端點。圖一或圖三所示之訊號繞線18可被連接至相對應的凸塊 焊塾20，其中凸塊焊墊20可能位於晶粒邊緣區域（die periphery) 22或是晶粒中心區域24。 請回頭參閱圖一與圖二，當訊號繞線18自晶粒1〇的凸塊焊墊2〇 處開始設置時，圖一所示之虛線區域16並不足以容納如此大孔徑的導 通孔12H。因此僅有少數的訊號繞線18可直接向下設置至内層EE， 12F。這也解釋了為何訊號繞線18幾乎都分布於圖三所示之上曰兩層的 内層12A、12B。如圖四所示，當使用覆晶封裝技術（flip_chip packaging)時，一個標準的晶粒1〇包含數以百計的凸塊焊墊2〇，如 何將上百條讯號繞線18佈線至晶粒1〇上的適當位置是一件相當複雜 1250827 案號：093107646 的工作。除此之外，大量的凸塊焊墊20必須緊密排置以使得基板 上的繞線空間可被有效地利用，同時，這也表示六層積沉基板12必須 於一區域中提供更加緊密的佈線以及更佳的彈性於設置所要的訊號繞 線18。無可避免地，高密度的訊號繞線分布及較小的晶粒尺寸都使得 訊號繞線18之間的間隔極小，亦即惡化訊號繞線π之間具有的串音 效應（cross-talk effect)，其中大部分是電容性的串音效應 (capacitive cross-talk)，所以上述串音效應便會進一步地降低訊 號品質。 【發明内容】 因此’本發明的主要目的在於提供一種利用區塊式佈線方法以於 多層電路板上設置複數個訊號繞線與屏蔽繞線，以解決上述問題。 本發明提出一種在多層基板（電路板）上設置對應複數個凸塊焊墊 (bumper pad)之複數個訊號繞線（signai trace)的方法。本發明 方法係根據一特殊排列方法來將複數個凸塊焊墊組成複數個凸塊焊墊 區塊，此外，複數個訊號繞線僅佈線至多層基板的第一層與第二層， 而第三層則用於電源端與接地端之電連接。除此之外，複數個屏蔽繞 線係穿插第一層與第二層上複數個訊號繞線之間，用來提供屏蔽效 果。此外，本發明方法可應用於覆晶封裝技術，引線接合技術，捲帶 式自動接合（tape automatic bonding)技術，以及其他封裝技術。 本發明中，凸塊焊墊於凸塊焊墊區塊中係對應一特定排列。複數個 第一層繞線係設計成一直線的走向，而第二層繞線則轉換方向以避免 與位於第一層的繞路於垂直面上互相平行，因此，此一簡單且好用的 排列方式輕易地從各個凸塊焊墊分配至相對應的訊號繞線。 本發明係揭露一種在一多層電路板（multi—layercircuitboard) 1250827 案號：093107646 上没置對應複數個凸塊焊墊（bumperpad)之複數個訊號繞線（以四以 · trace)的佈線方法，該多層電路板包含有至少有_第一層與一第二 層σ亥佈線方法包含有·依據複數個二角單元（triangle unit)來排 列該複數個凸塊焊墊；在該第一層上設置對應複數個凸塊焊墊之複數 個訊號繞線；在該第二層上設置對應複數個凸塊焊墊之複數個訊號繞 線，該第二層之該複數個訊號繞線未於垂直面與該第一層之複數個訊 號繞線平行；以及在該第一與第二層之複數個訊號繞線之間設置複數 個屏蔽繞線（shielding trace)。 再者，本發明另揭露一種區塊式佈線方法，用來在一多層電路板 (multi-layer circuit board)上設置對應複數個凸塊焊墊（bumper ® pad)之複數個訊號繞線（signal trace)的佈線方法，該多層電路板 包含有至少有一第一層與一第二層。該區塊式佈線方式包含有：依據 一特殊排列方式將該複數個凸塊焊墊規劃成一凸塊焊墊區塊；指定對 應該凸塊焊墊區塊中複數個凸塊焊墊之複數個訊號繞線為設置於該第 一層上之複數個第一層繞線；指定對應該凸塊焊墊區塊中複數個凸塊 焊墊之複數個訊號繞線為設置於該第二層上之複數個第二層繞線；以 直線方式來没置該複數個第一層繞線；以一轉折方式設置該複數個 第二層繞線以使該複數個第二層繞線未垂直地平行於該複數個第一層 繞線；以及屏蔽該複數個第一層繞線與該複數個第二層繞線。 φ 此外’本發明又揭露一種設置對應複數個凸塊焊墊之複數個訊號 繞線之方法’其係應用於一多層電路板（jjJUlfi —layercircuitb〇ar(J) 上之一晶粒（die)。該方法包含有：使用設置於該晶粒之晶粒邊緣區 域（periphery area)之複數個凸塊焊墊；使用設置於該晶粒之晶粒 中心區域（center area)之複數個電源端/接地端凸塊焊墊；指定對 應複數個凸塊焊墊之複數個訊號繞線為設置於該第一層上之複數個第 一層繞線；指定對應複數個凸塊焊墊之複數個訊號繞線為設置於該第 一層上之衩數個弟一層繞線，其中該第二層係垂直地位於該第一層之 1250827 案號：093107646 下方，以一直線方式來設置該複數個第一層繞線；以一轉折方式來設 - 置=複數個第二層繞線以使該複數個第二層繞線未垂直地位於該複數 個第一層繞線之下方；以及經由自該複數個電源端/接地端凸塊焊墊 設置複數瓣蔽麟來屏_複數辩—層舰赫複數個第二層繞 線。 曰、凡 【實施方式】 ^請參閱圖五，圖五為部分凸塊焊墊31〜38與複數個訊號繞線39〜仙 的第一種擺設示意圖。此凸塊焊墊的擺設與多接腳數晶粒的晶粒尺寸 有高度相關，對於覆晶封裝而言，晶粒尺寸（圖—與圖四所示之晶粒_ 10)受兩項要素影響，亦即凸塊焊墊的數量以及相對應訊號線繞所需 佔用的面積。如圖五所示，凸塊焊墊31〜38配置於多層基板82上，該 多層基板82包含至少一第一層82A與一第二層82B (第二層82B位於 第一層82A的正下方）。多層基板82可為圖2所示之六層增層式基板 12(第一層82A可對應到内層12A，以及第二層82B可對應到内層12B) 或者疋任何多層電路板（multi-layer circuit board)。依現行製程 技術，兩凸塊焊墊之間的距離（稱為凸塊焊墊間距）所對應的最小值 為227/zm，而任一凸塊焊墊之徑長（width)則為110/zm。於多層基 板82上的第一層82A上，複數個訊號繞線39〜42係分別自複數個凸塊 焊塾31、32、35、36向外設置，而訊號繞線的最小線寬為25//m 以及相鄰兩繞線之最小線距亦為25//m。經過簡單的計算後，凸塊焊 墊31與凸塊焊墊35之間尚留有112/zm (227-115 = 112)的距離，亦 即上述間隙僅能容許單一訊號繞線穿越，因此對應到凸塊焊墊33、34、 37、39的訊號繞線43〜46(圖中虛線標示的線路)便只能設置於第二層 82B 上。 請特別注意凸塊焊墊31或凸塊焊墊35不可規劃為電源連接墊或 是接地連接墊，若此二凸塊焊墊規劃為接地連接墊或是電源連接墊的 11 1250827 案號：093107646 功能，則將失去兩條相對應的訊號繞線，因此便需要規書彳、 谭墊及更大範圍的晶粒邊緣區域（圖四中所示晶粒邊緣區域^凸， 合凸塊焊墊數的需要，因此上述方法並非一節劣成本的方法。美二付 述之考量，因此-種更有效之凸塊焊墊的剩便用來達_少1 = 寸的目的，請參閱圖四，圖四為排列於圖一所示之晶粒1〇上之 凸塊焊塾20的示意Η。晶粒邊輕域22設置有職晶粒1()之^ ^ 入/輸出訊號繞線的凸塊焊墊，也就是說，所有對應輸人/輸出訊於: 訊號繞線涵蓋了整個晶粒10的周圍，亦即晶粒邊緣區域㈡，=粒 10的中心區域24則包含對應電源端/接地端的凸塊焊墊。 根據圖五所示之複數個凸塊焊墊31〜38的擺置方式，所有的訊號 繞線39〜46都可在晶粒邊緣區域22緊密擺置以避免任何可用空間的浪ϋ 費。在高密度的佈線狀況下，以及在繞線散佈開來之前，兩相鄰繞^ 的間距非常小（如先前所述，最小線距為25/zm)，因此繞線之間相互 的電磁干擾便成為影響傳輸訊號品質的重要因素。請參閱圖五，訊號 繞線39〜46的佈線不是平行地位於同一層就是平行地位於不同層，如 此來’ 5孔號繞線間的干擾不只來自同一層的鄰近訊號繞線，也會來 自不同層上的讯號繞線。以第一層82Α為例，訊號繞線39〜42必定會 因為距離太近與缺乏屏蔽保護而嚴重地受到鄰近繞線的干擾。將兩層 (第一層82Α與第二層82Β)納入考慮，因為空間不足，所以已經沒有 任何空間可放置屏蔽線路以維護訊號品質。 請參閱圖六，圖六係為圖五所示之多層基板82中一部分的立體示 意圖。訊號繞線39〜41係位於多層基板82的第一層82Α，而另三條訊 號繞線43〜45則位於多層基板82的第二層82β，此外，第一層與 第二層82Β之間另有一層47作為一絕緣層。當訊號繞線39、41、44 同時運作時’顯而易見地，訊號繞線4〇會受到水平及垂直方向之三條 相鄰訊號繞線39、41、44的嚴重干擾，因為圖二所示的增層式基板12 中’第一層82Α與第二層82Β僅相距30所以上述訊號繞線造成的 12 1250827 案號：093107646 干擾在圖二所示的增層式基板12中將會更為顯著，因此，在降低或至 少不大幅增加晶粒尺寸的前提下，便需要一種全新的凸塊焊墊與佈線 的配置方式來提昇訊號品質。 基於上述提到有關現行製程技術所具有的線寬與線距限制，本發 明闡述如何適當的擺置凸塊焊墊，電源端/接地端的凸塊焊墊，以及 多層基板82上凸塊焊墊所設置之訊號繞線的佈線。請回顧圖五，如同 先前所述’兩相鄰凸塊焊墊之間距容許範圍内（227//m)只有一條訊號 繞線付以通過。為了清楚地說明新的凸塊焊墊配置與上述圖五中凸塊 焊墊配置之間的不同，因此使用與定義一種凸塊焊墊區塊 (bumper-tile block)。請參閱圖七，圖七係為凸塊焊墊η〜別之第 二種配置與圖五所示之凸塊焊墊31〜38之第一種配置的示意圖。八個 凸塊焊墊31〜38被視為對應第一種排列方式的第一凸塊焊墊區塊84， 而另外八個凸塊焊墊51〜58則是對應第二種侧方式的第三凸塊焊塾 區塊86，每一個凸塊焊墊區塊，不論是第一凸塊焊墊區塊以或第二凸 塊焊墊區塊86都包含八個凸塊焊墊，用來連接八條分布在多層基板犯 /例如圖二所示之六層增層式基板12)中第_層82A與第二層的 訊號繞線增層式。請注意，賴八個凸塊焊墊51〜58之新的第二種配 置方式係為本發_於凸塊焊墊51〜58之設置的—種實施例，而對第 二凸塊焊墊區塊86的微小更動亦屬本發日·嘴，下舰述將會詳细說 明從第-凸塊焊無塊84進步至第二凸塊區塊邪的過程。… 首先 母個凸塊:塊可減為由複數個不啦彡狀之單元所植 成。請參麵七，原本的第-凸塊㈣區塊84可視為由複數個方形單 兀84a組成，而第-種配置方式的特性已於圖五所示之實施例中說明。 根據本發明之技術’新的凸塊焊墊區塊改由複數個三角單元伽（ =所示）所組成，而這些三角單元86a的每—邊對應相同的長度^ 焊塾區塊86帽有凸塊焊塾間距皆與原先凸塊焊墊區塊84 中的凸塊焊·距相同，然而，因為每—組成單元的形狀改變，因此 13 1250827 案號：093107646 凸塊焊墊區塊所佔據面積（其決定了晶粒尺寸）也有所改變。第一凸 塊焊墊區塊的寬度為342//m (最小凸塊焊墊間距+凸塊焊墊寬度，亦即 227 + 115 = 342(//m)) ’長度為796/zm (最小凸塊焊墊間距+凸塊焊 墊寬，亦即681 + 115二796(//m));在新的配置中，凸塊焊墊區塊86 的寬度為455· 5/zm(l· 5*最小凸塊焊墊間距+凸塊焊墊寬，亦即340. 5 + 115 = 455· 5(/zm))，長度為 700//m (1. 5 * /3 * 最小凸塊焊塾寬 +凸塊焊塾寬，亦即590 +115 = 700(μm))。經由上述簡易計算可見 第二凸塊烊墊區塊86的配置造成寬度增加，但是長度卻縮短，所以該 新配置方式並不會額外大幅地增加晶粒的尺寸，但卻能充分利用本發 明的特點。1250827 Case No.: 093107646 玖, Invention Description: [Technical Field] The present invention provides a route (signal trace) through a bump pad (f pad) on a multi-layer circuit board The method, in particular, is a block wiring method in which a plurality of signal windings and a plurality of shielding traces are disposed on a multi-layer circuit board. [Prior Art] In a modern society with computer technology developed in the south, a computer system including a plurality of integrated circuits has been widely used in various fields. For example, home devices, mobile communication devices, and personal computers with automatic control systems use integrated circuits to perform certain functions. The main body of the integrated circuit is composed of a die produced by a conventional semiconductor process, and the process of the die starts from manufacturing a wafer, and then each wafer is further divided into a plurality of blocks, so A plurality of circuits can be formed in each block by a conventional semiconductor process. Finally, each processed block on the wafer is further diced by a plurality of dies. When the crystal required for the lining is reduced, it is still necessary to electrically connect the die to the circuit, such as a __ circuit board (pH ed ire ire 。 。 。 。). Therefore, the die can obtain a desired operating voltage from the printed circuit board to perform a predetermined operation. For example, suppose that the function of the die corresponds to the encoding circuit, so 'when the encoding circuit receives the appropriate operating voltage, the die can encode the input material of the printed circuit board, and The encoded data is returned to the printed circuit board. The die of some integrated circuits, such as the conventional wire-bonded die (wire-b〇nd IC), is placed around the day-to-day grain and has a metal connection pad (fat 1 pa(J) for 1 Hx connects H particles with external signals, such as control signals, power terminals and ground terminals. In general, the wire bonding die is set in a plastic or ceramic package (Yangbing) 1250827 Case No.: 〇93107646 The upper connection is made of a metal connection pad around the die and the package is provided. The above package has one of the following =::: a specific size of the die 'its === nano logic gate' quantity::: : In addition, 'but with the advancement of technology', the τ at the ground end of the die... more need to pick up the external wiring to reduce (_ is the power supply terminal and the logic circuit inside the 曰 die; third, in the wire bonding crystal In the grain, / the metal wire of the die and the pin on the package will generate additional resistance and inductance to deteriorate the performance of the die. 1 In order to change the above problem 'clip chip package (fHp- Cj^pqing (four) shirts have become the better today. The flip chip packaging technology makes the package turn over the overall size. Tight, and = rut in the wire bonding die 'The connection between the die and the external electronic component produces a smaller impedance value and a smaller power. In addition, because the connection distance between the die and the ground is shortened, Therefore, it is possible to obtain a power supply of a higher product f. However, even the application of flip chip packaging technology 'the actual size of the die is inevitably affected by the size and number of bump solders distributed on the m grain. Due to the intense market Competition, so we continue to develop and produce smaller, more efficient, and more efficient products, so how to reduce product size to meet production cost considerations has become an important issue. In order to achieve space-saving advantages, electronics Multi-layer substrates (such as a circuit board) are also used in the system. Today's multi-layer substrates can be produced by different manufacturing methods, for example, the multilayer substrate can be a laminated substrate or a build-up substrate. In the multilayer substrate produced by the above different manufacturing methods, the line width of the signal line on the substrate can be as small as 3〇. Therefore, the sinking substrate is most suitable for the device with multiple pin count requirements to extend the circuit density of the conventional circuit board. Please note 1250827 Case No.: 0931〇7646 Refer to Figure 1 and Figure 2, Figure 1 is a conventional six-layer increase. A schematic diagram of a die 10 is disposed on the layer substrate 12, and FIG. 2 is a schematic view of the six-layer build-up substrate 12 shown in FIG. 1. The six-layer build-up substrate 12 includes four inner layers 12A, 12B, 12E, and 12F. It is used to configure a plurality of signal windings, wherein each inner layer can provide a line width/line spacing of 25/zm/25//m and a via hole 12G with a diameter of 110//m. The other two layers 12C, Each of the 12Ds provides a wire width/line spacing of 100 // m/100 // m and a 440 // m via 12H. Based on the structure of the above six-layer build-up substrate 12, when six layers of the build-up substrate 12 are applied, only four inner layers 12A, 12B, 12E, and 12F can be used to arrange the signal winding because the remaining two layers 12C, A large via (440 // m) 12H can be provided between the 12D to provide power and ground, so the above two layers 12C, 12D should not allow the signal to pass. Please refer to FIG. 3 , which is an enlarged schematic view of the framed area 14 shown in FIG. 1 . The embodiment shown in Figure 3 shows that a plurality of signal windings 18 are electrically connected from the die 1 to the six-layer build-up substrate 12 shown in Figure 2. The embodiment of Figure 3 shows that all of the signal windings are designed to be electrically connected to the inner layers 12A, 12B. Therefore, the plurality of signal windings 18 can be divided into signal windings 18 located on the first layer according to the inner layer 12A or 12B. (1) With the second layer of signal winding 18 (2). Referring to Figure 4, Figure 4 is a schematic view of the bump pads 20 disposed on the die 1 of Figures 1 and 3. A plurality of bump pads 20 are used as the end points of the input/output of the die 1〇. The signal winding 18 shown in FIG. 1 or FIG. 3 can be connected to the corresponding bump pad 20, wherein the bump pad 20 may be located in the die periphery 22 or the die center region 24. Referring back to FIG. 1 and FIG. 2, when the signal winding 18 is disposed from the bump pad 2〇 of the die 1,, the dotted line region 16 shown in FIG. 1 is not enough to accommodate the via hole 12H having such a large aperture. . Therefore, only a few signal windings 18 can be directly down to the inner layers EE, 12F. This also explains why the signal windings 18 are almost always distributed over the inner layers 12A, 12B of the two layers shown in Figure 3. As shown in Figure 4, when using flip chip packaging technology, a standard die 1〇 contains hundreds of bump pads 2, how to route hundreds of signal wires 18 to The proper position on the die 1 is a fairly complicated work in the 1250827 case number: 093107646. In addition, a large number of bump pads 20 must be closely packed so that the winding space on the substrate can be effectively utilized, and this also means that the six-layered substrate 12 must be provided more tightly in an area. Wiring and better flexibility are used to set the desired signal winding 18. Inevitably, the high-density signal winding distribution and the small grain size make the spacing between the signal windings 18 extremely small, that is, the cross-talk effect between the signal windings π is deteriorated (cross-talk effect). ), most of which is capacitive cross-talk, so the above crosstalk effect will further reduce the signal quality. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a method of using a block wiring method to provide a plurality of signal windings and shield windings on a multilayer circuit board to solve the above problems. The present invention provides a method of providing a plurality of signal-aiden traces corresponding to a plurality of bumper pads on a multilayer substrate (circuit board). The method of the present invention comprises a plurality of bump pads forming a plurality of bump pad blocks according to a special arrangement method, and further, the plurality of signal windings are only wired to the first layer and the second layer of the multilayer substrate, and The third layer is used for electrical connection between the power supply terminal and the ground terminal. In addition, a plurality of shield windings are interspersed between the plurality of signal windings on the first layer and the second layer to provide a shielding effect. In addition, the method of the present invention can be applied to flip chip packaging techniques, wire bonding techniques, tape automatic bonding techniques, and other packaging techniques. In the present invention, the bump pads are corresponding to a particular arrangement in the bump pad block. The plurality of first-layer windings are designed to run in a straight line, and the second-layer windings are switched in direction to avoid paralleling with the windings on the first layer in a vertical plane. Therefore, this simple and easy-to-use arrangement The method is easily distributed from each bump pad to the corresponding signal winding. The present invention discloses a wiring method for a plurality of signal windings (four traces) without a plurality of bump pads on a multi-layer circuit board 1250827 case number: 093107646. The multi-layer circuit board includes at least a first layer and a second layer, and the plurality of bump pads are arranged according to a plurality of triangular elements; the first layer is arranged a plurality of signal windings corresponding to the plurality of bump pads are disposed on the second layer; a plurality of signal windings corresponding to the plurality of bump pads are disposed on the second layer, and the plurality of signal windings of the second layer are not The vertical plane is parallel to the plurality of signal windings of the first layer; and a plurality of shielding traces are disposed between the plurality of signal windings of the first and second layers. Furthermore, the present invention further discloses a block wiring method for providing a plurality of signal windings corresponding to a plurality of bumper pads on a multi-layer circuit board ( The signal trace method of the multilayer circuit board includes at least one first layer and one second layer. The block type wiring method comprises: planning the plurality of bump pads into a bump pad block according to a special arrangement manner; specifying a plurality of bump pads corresponding to the plurality of bump pads in the bump pad block The signal winding is a plurality of first layer windings disposed on the first layer; and the plurality of signal windings corresponding to the plurality of bump pads in the bump pad block are disposed on the second layer a plurality of second layer windings; the plurality of first layer windings are not disposed in a straight line manner; the plurality of second layer windings are disposed in a turning manner such that the plurality of second layer windings are not vertically Parallel to the plurality of first layer windings; and shielding the plurality of first layer windings and the plurality of second layer windings. φ In addition, the present invention also discloses a method for setting a plurality of signal windings corresponding to a plurality of bump pads, which is applied to a multilayer circuit board (jjJUlfi-layercircuitb〇ar(J). The method includes: using a plurality of bump pads disposed in a peripheral region of the die; using a plurality of power terminals disposed in a center area of the die / grounding bump pad; specifying a plurality of signal windings corresponding to the plurality of bump pads is a plurality of first layer windings disposed on the first layer; specifying a plurality of corresponding plurality of bump pads The signal winding is a winding of a plurality of layers disposed on the first layer, wherein the second layer is vertically located below the first layer of 1250827 case number: 093107646, and the plurality of lines are set in a line manner a layer of winding; set in a turning manner - set = a plurality of second layer windings such that the plurality of second layer windings are not vertically located below the plurality of first layer windings; Multiple power/ground bump pads Set a number of petals to cover the screen _ complex number of layers - layer ship Hehe multiple second layer winding. 曰, 凡 [Implementation] ^ Please refer to Figure 5, Figure 5 is a partial bump pads 31 ~ 38 and a number of signals The first type of schematic diagram of the winding 39~xian. The arrangement of the bump pad is highly correlated with the grain size of the multi-pin number die. For the flip chip package, the grain size (Fig. 4 and Figure 4) The die _ 10) shown is affected by two elements, that is, the number of bump pads and the area required for the corresponding signal wire winding. As shown in FIG. 5, the bump pads 31 to 38 are disposed in multiple layers. On the substrate 82, the multilayer substrate 82 includes at least a first layer 82A and a second layer 82B (the second layer 82B is located directly below the first layer 82A). The multilayer substrate 82 can be a six-layer buildup as shown in FIG. The substrate 12 (the first layer 82A may correspond to the inner layer 12A, and the second layer 82B may correspond to the inner layer 12B) or any multi-layer circuit board. According to the current process technology, the two bump pads The minimum distance (called the bump pad pitch) corresponds to a minimum of 227/zm, and any bump pad The width is 110/zm. On the first layer 82A of the multilayer substrate 82, a plurality of signal windings 39 to 42 are respectively disposed outward from the plurality of bump pads 31, 32, 35, and 36. The minimum line width of the signal winding is 25//m and the minimum line spacing of the adjacent two windings is also 25/m. After a simple calculation, between the bump pad 31 and the bump pad 35 There is still a distance of 112/zm (227-115 = 112), that is, the gap can only allow a single signal to traverse, so the signal windings 43 to 46 corresponding to the bump pads 33, 34, 37, 39 (The line indicated by the dotted line in the figure) can only be placed on the second layer 82B. Please pay special attention to the bump pad 31 or the bump pad 35 which cannot be planned as a power connection pad or a ground connection pad. If the two bump pads are planned as a ground connection pad or a power connection pad, 11 1250827 Case No.: 093107646 The function will lose two corresponding signal windings, so it is necessary to specify the 彳, 谭 pads and a wider range of grain edge regions (the grain edge regions shown in Figure 4 are convex, bump bumps) The need for the number, so the above method is not a method of inferior cost. The United States is more concerned about the considerations, so the more effective bump pads are used to achieve _ less 1 = inch, please refer to Figure 4, 4 is a schematic diagram of the bump pad 20 arranged on the die 1 shown in FIG. 1. The die edge light region 22 is provided with a bump of the input die of the die 1 () The solder pads, that is, all corresponding input/output signals: The signal winding covers the entire periphery of the die 10, that is, the edge region of the die (2), and the central region 24 of the grain 10 includes the corresponding power terminal/ground. a bump pad of the end. According to the arrangement of the plurality of bump pads 31 to 38 shown in FIG. 5, All of the signal windings 39-46 can be placed tightly in the die edge region 22 to avoid any wasted space. In high-density wiring conditions, and before the windings are spread, two adjacent windings The spacing between ^ is very small (as mentioned earlier, the minimum line spacing is 25/zm), so the mutual electromagnetic interference between the windings becomes an important factor affecting the quality of the transmitted signal. Please refer to Figure 5, signal winding 39~46 The wiring is not in the same layer in parallel or in different layers in parallel, so the interference between the '5-hole windings is not only from the adjacent signal windings of the same layer, but also from the signal windings on different layers. In the case of a layer 82Α, the signal windings 39~42 must be seriously disturbed by adjacent windings due to too close distance and lack of shielding protection. The two layers (the first layer 82Α and the second layer 82Β) are taken into account because There is not enough space, so there is no space for the shielded circuit to maintain the signal quality. Please refer to Figure 6, Figure 6 is a perspective view of a part of the multi-layer substrate 82 shown in Figure 5. The signal windings 39~41 are located in multiple The first layer 82 of the substrate 82 is turned on, and the other three signal windings 43 to 45 are located on the second layer 82β of the multilayer substrate 82. Further, a layer 47 is provided between the first layer and the second layer 82 as an insulating layer. When the signal windings 39, 41, 44 are operating simultaneously, 'obviously, the signal winding 4〇 will be seriously disturbed by the three adjacent signal windings 39, 41, 44 in the horizontal and vertical directions, because the layering shown in Figure 2 In the substrate 12, the first layer 82 is only 30 apart from the second layer 82, so the 121250827 case number: 093107646 caused by the above signal winding will be more prominent in the build-up substrate 12 shown in FIG. Under the premise of reducing or at least not significantly increasing the grain size, a new bump pad and wiring configuration is needed to improve the signal quality. Based on the above mentioned line width and line spacing limitations of current process technology, the present invention describes how to properly place the bump pads, the bump pads on the power/ground terminals, and the bump pads on the multilayer substrate 82. The wiring of the set signal winding. Referring back to Figure 5, as previously described, only one signal winding was passed within the allowable range (227//m) between two adjacent bump pads. In order to clearly illustrate the difference between the new bump pad configuration and the bump pad configuration of Figure 5 above, a bumper-tile block is used and defined. Referring to FIG. 7, FIG. 7 is a schematic diagram showing the first configuration of the bump pads η~ and the second configuration and the bump pads 31-38 shown in FIG. The eight bump pads 31 to 38 are regarded as corresponding to the first bump pad block 84 of the first arrangement, and the other eight bump pads 51 to 58 are corresponding to the second side mode. a three-bump solder pad block 86, each bump pad block, whether the first bump pad block or the second bump pad block 86, comprises eight bump pads for Eight signal-wound-layered layers of the first layer 82A and the second layer in the multi-layer substrate/such as the six-layer build-up substrate 12 shown in FIG. 2 are connected. Please note that the new second configuration of the eight bump pads 51-58 is an embodiment of the present invention, and the second bump pads are provided. The minor change of block 86 is also the date of the present day. The next ship description will detail the process from the advancement of the bump-free block 84 to the second bump block. ... First, the parent bump: the block can be reduced to a number of cells that are not shaped. Referring to Figure 7, the original block-bump (four) block 84 can be considered to be composed of a plurality of square cells 84a, and the characteristics of the first mode are described in the embodiment shown in FIG. According to the technique of the present invention, the new bump pad block is composed of a plurality of triangular unit gamma (shown by =), and each side of the triangular unit 86a corresponds to the same length ^ the solder bump block 86 has The bump solder pitch is the same as the bump soldering distance in the original bump pad block 84. However, since the shape of each constituent unit is changed, 13 1250827 case number: 093107646 is occupied by the bump pad block. The area (which determines the grain size) has also changed. The width of the first bump pad block is 342 / / m (minimum bump pad pitch + bump pad width, that is, 227 + 115 = 342 (/ / m)) 'length is 796 / zm (minimum The bump pad pitch + bump pad width, which is 681 + 115 2796 (/ / m)); in the new configuration, the bump pad block 86 has a width of 455 · 5 / zm (l · 5* minimum bump pad pitch + bump pad width, ie 340. 5 + 115 = 455· 5(/zm)), length 700//m (1. 5 * /3 * minimum bump soldering塾 width + bump width, ie 590 +115 = 700 (μm)). It can be seen from the above simple calculation that the configuration of the second bump pad block 86 increases the width, but the length is shortened, so the new configuration does not additionally greatly increase the size of the die, but can fully utilize the present invention. Features.
根據上述第二凸塊焊墊區塊86的配置，一種佈線方法係揭露以自 多層基板82上複數個（8個）凸塊焊墊連接相對應之複數個（8個） 訊號繞線。如前所述，訊號繞線係分布於多層基板82的第一層82A及 第二層82B ’請參閱圖八，圖八為本發明應用於圖七所示之凸塊焊墊區 塊86之佈線方法的流程圖，其操作步驟如下： 步驟100 ·在複數個三角單元上配置複數個凸塊焊塾； 步驟101 :在第一層上，從複數個凸塊焊墊配置相對應之複數 個訊號繞線； 步驟102 :在第二層上，從複數個凸塊焊墊配置相對應之複數個訊號繞 線，但是該複數個訊號繞線不可位於該第一層中現有訊號 繞線的正下方；以及 步驟103:分別在該第一與第二層之複數個訊號繞線之間配置 複數個屏蔽繞線。 注意依據每-個單S的形狀並不限定為正三角形，而不同形狀 ^ t亦可用來⑤計本發日种每—個單元，除此之外，凸塊焊墊區 A 、凸塊焊細1量並不受限於八個，而可按照實際f求來加以調 14 1250827 案號：093107646 玉明茶閱圖九’圖九為圖七所示之凸塊桿墊區塊抓盘 號繞線與屏蔽繞線的示意圖。如圖九所示，多層基板82、=1=塾 s5；:™:r ^ ：4 ^ 5： ' -立楚一一曰82B而弟一層上的線路則佈滿斜線來表 ^ 67^70(|.^)f ^ 59^62 之間以ki、苐-層82A上相鄰兩訊號繞線的干擾屏蔽功能。同理，第 二層82B上四條屏蔽繞線71〜74 (細線且填滿斜線）穿插於四條訊號繞 線63〜66之間以提供第二層82B上相鄰兩訊號線的干擾屏蔽功能。 、圖九所示之佈線方式可從圖五所示之實施例一步一步地改良而 成。凊參關十，圖十為從圖五所示之實施例改良至圖九所示之實施 例的示意圖。圖十包含五個實施例A〜E，其中涵蓋圖五及圖九所示的實 施例’而圖E係為與圖九完全相同的實施例。實施例a係由圖五之實 施例修改而來，而源自凸塊焊墊33、34、37、38的訊號繞線43〜46於 離開凸塊焊墊33、34、37、38後便立即轉向以避免位於第一層之訊號 繞線39〜42的正下方。然後，於實施例b中，凸塊焊塾區塊經由調整 而對應圖七與圖九所示之第二凸塊焊墊區塊86，同時建立一佈線規則 來設置所有的訊號繞線18 :第一層82A中的所有的訊號繞線18全部改 走直線，而弟一層82B的訊號繞線於離開相對應凸塊焊塾時便轉向。 因此，所有的訊號繞線互相錯開以避免不同層的繞線位於同一垂直面 上’至此只解決掉垂直干擾的問題。然而，同一層訊號繞線之間的水 平干擾需要更進一步的方法來解決，也就是加入屏蔽繞線。請參閱實 施例C，其顯示第一層（上層）上訊號繞線59〜62與穿插其間之屏蔽繞 線67〜70的設置。同理，請參閱實施例D，其顯示第二層82B (下層） 上訊號繞線63〜66與牙插其間之屏蔽繞線71〜74的設置。於組合實施 例C與實施例D的裝置特性後即產生最終所需的實施例E。 基於圖十所示之實施例E與上述佈線規則，本發明揭露另一種佈 15 1250827 案號：093107646 線方法的詳細實施例以於多層基板82上第二凸塊焊墊區塊86設置複 數個（8個）凸塊焊墊與複數個（8個）訊號繞線。請參閱圖十一， 圖十一為本發明方法應用於圖十所示之實施例E的流程圖，其操作步 驟如下： 步驟200 :按照一特殊方式將複數個凸塊焊墊規劃為一凸塊焊 墊區塊，且該複數個凸塊焊墊構成複數個三角單元； 步驟201:配置對應該凸塊焊墊區塊中之複數個凸塊焊墊的複數 個訊號繞線，用來作為佈線於第一層上的第一層繞 線’而依據圖十所示之實施例E，第一層繞線即為訊 號繞線為59〜62 ; 步驟202:配置對應該凸塊焊墊區塊中之複數個凸塊焊墊的複數個訊號 繞線，用來作為佈線於第二層上的第二層繞線，而依據圖十 所示之實施例E，第二層繞線即為訊號繞線為63〜66 ; 步驟203 :以一直線走向來設置複數個第一層繞線； 步驟204 :設置中複數個第二層繞線具有一轉折以使其不位在第一層 繞線的正下方； 步驟205 :在第一層上，每兩相鄰之第一層繞線間加入一第一層屏蔽 繞線，如圖十所示之實施例E，第一層屏蔽繞線即為屏蔽繞 線67〜70 ;以及 步驟206 :在第二層上，每兩相鄰之第二層繞線間加入一第二層屏蔽 繞線，如®十所示之實補E，第二層屏蔽麟即為屏蔽繞 線71〜74 。 此一簡易且有效的佈線規則，亦即第一層82A上的訊號繞線走直 線，以及第二層82B上的訊號繞線於離開相對應凸塊焊墊而轉向，提 供-方法來解決如何設置訊號繞線於一具有大量凸塊焊墊的晶粒 (晶粒80係對應圖一所示之晶，粒1〇)上的問題。為強調本發明此一於 構，另有十二來加以。針二係相十所示之實_ E的:; 16 1250827 案藏· 093107646 «^9 6〇 ^ 疋義），而成號繞線63、64係為位於多層基板82 二=Γΐΐ 、線72所屏蔽，因此，除了幾條邊緣的According to the configuration of the second bump pad block 86 described above, a wiring method discloses a plurality of (8) signal windings connected by a plurality of (8) bump pads from the multilayer substrate 82. As described above, the signal winding is distributed on the first layer 82A and the second layer 82B of the multilayer substrate 82. Referring to FIG. 8, FIG. 8 is applied to the bump pad block 86 shown in FIG. A flow chart of the wiring method, the operation steps are as follows: Step 100: Configuring a plurality of bump soldering pads on a plurality of triangular cells; Step 101: Configuring a plurality of corresponding bump pads from the plurality of bump pads on the first layer Signal winding; Step 102: On the second layer, a plurality of corresponding signal windings are arranged from the plurality of bump pads, but the plurality of signal windings may not be located in the first layer of the existing signal windings. And a step 103: respectively arranging a plurality of shield windings between the plurality of signal windings of the first and second layers. Note that the shape of each single S is not limited to an equilateral triangle, and different shapes can also be used for 5 units of the current day, in addition to the bump pad area A and bump welding. The fine 1 quantity is not limited to eight, but can be adjusted according to the actual f. 14 1250827 Case number: 093107646 Yuming tea reading picture nine 'Figure 9 is the bump block pad block number shown in Figure 7. Schematic diagram of winding and shielding winding. As shown in FIG. 9, the multilayer substrate 82, =1=塾s5;:TM:r ^ :4 ^ 5: ' - Li Chuyiyi 82B and the line on the first layer is covered with a diagonal line to form ^ 67^70 (|.^)f ^ 59^62 The interference shielding function of the adjacent two signal windings on the ki, 苐-layer 82A. Similarly, the four shield windings 71-74 (thin lines and filled with diagonal lines) on the second layer 82B are interspersed between the four signal windings 63-66 to provide interference shielding function for the adjacent two signal lines on the second layer 82B. The wiring pattern shown in Fig. 9 can be improved step by step from the embodiment shown in Fig. 5. Fig. 10 is a schematic view showing an improvement from the embodiment shown in Fig. 5 to the embodiment shown in Fig. 9. Fig. 10 includes five embodiments A to E, which incorporate the embodiment shown in Figs. 5 and 9, and Fig. E is an embodiment identical to that of Fig. 9. The embodiment a is modified from the embodiment of FIG. 5, and the signal windings 43 to 46 derived from the bump pads 33, 34, 37, 38 are separated from the bump pads 33, 34, 37, 38. Immediately turn to avoid directly below the signal windings 39-42 of the first layer. Then, in the embodiment b, the bump solder bump block is adjusted to correspond to the second bump pad block 86 shown in FIG. 7 and FIG. 9 , and a wiring rule is established to set all the signal windings 18 : All of the signal windings 18 in the first layer 82A are all changed to a straight line, and the signal of the second layer 82B is turned around when it exits the corresponding bump soldering. Therefore, all of the signal windings are staggered from each other to prevent the windings of the different layers from being on the same vertical plane. This only solves the problem of vertical interference. However, horizontal interference between the same layer of signal windings requires a further method of solution, that is, adding shielded windings. Referring to Example C, the arrangement of the signal windings 59-62 on the first layer (upper layer) and the shield windings 67-70 interposed therebetween are shown. For the same reason, please refer to the embodiment D, which shows the arrangement of the signal windings 63-66 on the second layer 82B (lower layer) and the shield windings 71-74 between the teeth. The final desired Example E was produced after combining the device characteristics of Example C with Example D. Based on the embodiment E shown in FIG. 10 and the above-mentioned wiring rule, the present invention discloses another embodiment of the cloth 15 1250827 case number: 093107646 line method to set a plurality of second bump pad blocks 86 on the multilayer substrate 82. (8) bump pads and a plurality of (8) signal windings. Referring to FIG. 11 , FIG. 11 is a flowchart of applying the method of the present invention to Embodiment E shown in FIG. 10 . The operation steps are as follows: Step 200 : Plan a plurality of bump pads as a convex according to a special manner. a block pad block, and the plurality of bump pads constitute a plurality of triangular cells; Step 201: arranging a plurality of signal windings corresponding to the plurality of bump pads in the bump pad block, The first layer winding is wired on the first layer. According to the embodiment E shown in FIG. 10, the first layer winding is the signal winding 59~62; Step 202: Configuring the corresponding bump pad area a plurality of signal windings of the plurality of bump pads in the block are used as a second layer winding on the second layer, and according to the embodiment E shown in FIG. 10, the second layer winding is The signal winding is 63~66; Step 203: setting a plurality of first layer windings in a straight line direction; Step 204: setting a plurality of second layer windings to have a turning point so as not to be in the first layer winding Directly below; Step 205: On the first layer, a first layer is added between each two adjacent first layer windings Shielding the winding, as in the embodiment E shown in FIG. 10, the first layer of the shielding winding is the shielding winding 67~70; and the step 206: on the second layer, between the two adjacent second layer of the winding Add a second layer of shield winding, such as the real complement E shown in the ten, the second layer of shield is the shield winding 71~74. This simple and effective wiring rule, that is, the signal winding on the first layer 82A is straight, and the signal winding on the second layer 82B is turned away from the corresponding bump pad, providing a method to solve how The set signal is wound on a die having a large number of bump pads (the die 80 corresponds to the crystal shown in Figure 1, the grain 1). To emphasize this aspect of the invention, twelve others are added. The needle II is the same as the ten shown in the phase _ E:: 16 1250827 Case · 093107646 «^9 6〇^ 疋义), the number of windings 63, 64 is located on the multilayer substrate 82 == Γΐΐ, line 72 Shielded, therefore, except for a few edges
Hit 9)外，第一層82Α中每一條訊號繞線都被 二條屏蔽繞線所包圍’其中兩條與該訊號繞線在水平方向平行，而另 一條在垂直方向與之平行。_，第二層訊魏線亦具有囉的特性， 以訊號繞線63為例，其兩旁分別受到兩條屏蔽繞線7卜72所保護， 除此之外，第-層還有屏蔽繞線67位於其正上方，而其正下方則是第 二層82C。因此，第二層82BJi的任-條訊號繞線不只受到三條屏蔽繞 線所保護，還有位於其正下方的接地平面（第三層82〇。依據本發明 佈線方法，所有的訊號繞線皆可受到完整的保護，而電容性干擾 (capacitive interference)也可被有效地降低。 最後，與訊號繞線相連的所有凸塊焊塾組成一晶粒邊緣區域92。 請參閱圖十三，圖十三係為本發明於一晶粒8〇設置複數個凸塊焊墊9〇 與相對應第一層繞線88的示意圖。晶粒8〇包含一中心區域94以及一 晶粒邊緣區域92。圖十三所示之實施例與圖四所示之實施例相似，其 係適用上述本發明之實施例的特點。所有的訊號繞線（包含第一層繞 路88)都均勻地分布，且與屏蔽繞線（接地端）交錯，而圖十三中只 以虛線來表示第一層屏蔽繞線89。對於晶粒80的每一邊緣來說，每 一弟一層繞路88都與屏蔽繞線89平行並向前直走，直到到達其相對 應導通孔，因此第一層繞路88便可連接至相對應焊錫球（soldering ball);再者，所有訊號繞線（包含第一層繞線88)都自晶粒邊緣區域 92上相對應凸塊焊墊90起開始向外設置，而其餘對應電源端或接地端 的凸塊焊墊則放置在晶粒80的中心區域24。 17 1250827 案號·· 093107646 本發明提出一種新的佈線方法，可用於覆晶封裝技術使得多層基 板中複數個凸塊焊墊可被連接至複數個訊號繞線，該複數個凸塊焊墊 聚集形成複數個凸塊焊墊區塊，且依據複數個三角單元之方式來排 列。當本發明方法實施時，複數個訊號繞線係分佈在多層基板的第 一及第二層，而多層基板的第三層則用於連接電源端或是接地端， 除此之外，在第一層與第二層中，複數個屏蔽繞線則在不需使用額 外工間的清形下配置於複數個訊$虎繞線之間以提供干擾屏蔽功能。 以上所述僅為本發明之較佳實施例，凡本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖式簡單說明】 圖式之簡單說明 圖一係為習知於六層增層式基板上配置一晶粒的示意圖。 圖二係為圖一所示之六層增層式基板的示意圖。 增層式增層式圖三係為圖一所示之區域的放大示意圖。 圖四係為設置於圖一、三所述之晶粒上之凸塊焊墊的示意圖。 圖五係為複數個凸塊焊墊與複數個相對應訊號繞線的第一種配置示意 圖。 圖六係為圖五所示之多層基板中一部分的立體示意圖。 圖七係為複數個凸塊焊墊之第二種配置與圖五所示之凸塊焊墊之第一 種配置的示意圖。 圖八係為本發明應用於圖七所示之凸塊焊墊區塊之佈線方法的流程 圖。 圖九係為圖七所就凸麟倾塊與其婦應之峨齡與屏蔽繞線 的示意圖。 圖十係為從圖五所示之實施例改良至圖九所示之實施例的示意圖。 18 1250827 案號：093107646 圖十一係為本發明方法應用於圖十所示之實施例E的流程圖。 圖十二係為圖十所示之實施例E的剖面圖。 圖十三係為本發明於一晶粒設置複數個凸塊焊墊與相對應第一層繞線 的示意圖。In addition to Hit 9), each of the signal windings of the first layer 82 is surrounded by two shield windings. Two of them are parallel to the signal winding in the horizontal direction, and the other is parallel to the vertical direction. _, the second layer of the Wei line also has the characteristics of 啰, taking the signal winding 63 as an example, the two sides are protected by two shield windings 7 and 72, in addition, the first layer has a shield winding 67 is located directly above it, and just below it is the second layer 82C. Therefore, any of the signal windings of the second layer 82BJi is protected not only by the three shield windings, but also by the ground plane directly below it (the third layer 82〇. According to the wiring method of the present invention, all the signal windings are It can be fully protected, and capacitive interference can be effectively reduced. Finally, all bump pads connected to the signal winding form a grain edge region 92. See Figure 13 and Figure 10. The three series are schematic diagrams of a plurality of bump pads 9 〇 and a corresponding first layer winding 88 disposed on a die 8 。. The die 8 〇 includes a central region 94 and a die edge region 92. The embodiment shown in the thirteenth embodiment is similar to the embodiment shown in Fig. 4, and is applicable to the features of the embodiment of the invention described above. All signal windings (including the first layer of the bypass path 88) are evenly distributed, and The shield windings (grounding ends) are staggered, and the first layer of shielding windings 89 is indicated by dashed lines in Fig. 13. For each edge of the die 80, each of the layers of the windings 88 is shielded and wound. 89 parallel and go straight ahead until you reach it Corresponding to the vias, the first layer of the routing 88 can be connected to the corresponding soldering ball; further, all of the signal windings (including the first layer of windings 88) correspond to the edge regions 92 of the die. The bump pads 90 are initially disposed outwardly, and the remaining bump pads corresponding to the power or ground terminals are placed in the central region 24 of the die 80. 17 1250827 Case No. 093107646 The present invention proposes a new wiring method. The utility model can be used for flip chip packaging technology, wherein a plurality of bump pads in the multilayer substrate can be connected to a plurality of signal windings, the plurality of bump pads are gathered to form a plurality of bump pad blocks, and according to the plurality of triangle units In the manner of the present invention, a plurality of signal windings are distributed on the first and second layers of the multilayer substrate, and the third layer of the multilayer substrate is used to connect the power supply terminal or the ground terminal. In addition, in the first layer and the second layer, a plurality of shield windings are disposed between the plurality of signals to provide interference shielding function without clearing the additional work space. Only for the present invention The preferred embodiments of the present invention are to be construed as being within the scope of the present invention. The simple description of the drawings is a conventional six-layer layering. FIG. 2 is a schematic diagram of a six-layer build-up substrate shown in FIG. 1. The build-up layered three-layer is an enlarged view of the area shown in FIG. It is a schematic diagram of the bump pads disposed on the die of Figures 1 and 3. Figure 5 is a schematic diagram of the first configuration of a plurality of bump pads and a plurality of corresponding signal windings. 5 is a perspective view of a portion of the multilayer substrate shown in FIG. 5. FIG. 7 is a schematic view showing a second configuration of a plurality of bump pads and a first configuration of the bump pads shown in FIG. Fig. 8 is a flow chart showing the wiring method of the bump pad block shown in Fig. 7 of the present invention. Figure IX is a schematic diagram of the ageing and shielding winding of the bulging block and its yoke in Figure 7. Figure 10 is a schematic view of an embodiment modified from the embodiment shown in Figure 5 to the embodiment shown in Figure 9. 18 1250827 Case No. 093107646 FIG. 11 is a flow chart showing the application of the method of the present invention to Embodiment E shown in FIG. Figure 12 is a cross-sectional view of Embodiment E shown in Figure 10. Figure 13 is a schematic view showing the arrangement of a plurality of bump pads and a corresponding first layer winding in a die.
圖式之符號說明 10 晶粒 12 六層增層式基板 22、92 晶粒邊緣區域 24、94 晶粒中心區域 12A、12B、12C、12D、 内層 12H、12G 導通孔 12E、12F、82A82B、 82C 18(1)、18(2)、39〜 訊號線路 20、31 〜38、51 凸塊焊墊 46、59〜66、88、89 〜58、90 67 〜74 屏蔽線路 82 多層基板 84、86 凸塊焊墊區塊DESCRIPTION OF SYMBOLS 10 Grain 12 Six-layer build-up substrate 22, 92 Grain edge regions 24, 94 Grain center regions 12A, 12B, 12C, 12D, Inner layers 12H, 12G Via holes 12E, 12F, 82A82B, 82C 18(1), 18(2), 39~ signal lines 20, 31~38, 51 bump pads 46, 59~66, 88, 89~58, 9067~74 shielded lines 82 multilayer substrates 84, 86 convex Block pad block
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