1250528 12570twf.doc/y 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種記憶體元件，且特別是有關於一 種記憶體元件程式化與抹除的方法。 【先前技術】 、在今日，關於非揮發性資訊儲存的記憶體元件被廣泛 地運用。其中，部份非揮發性記憶體元件係以電荷陷入 (charge trapping)為基礎。而屬於這些電荷陷入元件的例子 有矽-氧化物-氮化物-氧化物_半導體1250528 12570twf.doc/y IX. Description of the Invention: [Technical Field] The present invention relates to memory elements, and in particular to a method of programming and erasing a memory element. [Prior Art] Today, memory components for non-volatile information storage are widely used. Among them, some non-volatile memory components are based on charge trapping. Examples of these charge trapping elements are germanium-oxide-nitride-oxide-semiconductors.
oxide-semiconductor，SONOS)以及氮化矽唯讀記憶體 (nitride read memory，Nr0M)等。一般來說，電荷陷入^件 ^有夾在兩氧化層之間的-電荷陷人層，電荷係儲存於電 荷陷入層中，且藉由儲存的電荷來記錄資料。然而，電荷 陷入元件進行抹除的方法較浮置閘極困難許多，因為電子 陷入於非常深的位置，而使得解除陷入(de_trapping)的 非常緩慢。 'X 圖1係繪示一矽-氧化物-氮化物__氧化物_半導體結 構。圖1中包括基底10、源極12及汲極14。而在矽_氧^ 物-氮化物-氧化物-半導體結構在基底10與閘極之間更 包括一氧化物-氮化物-氧化物層，其所對應的標號分別為 氧化層16、氮化層18及氧化層20。其中，氮化物層18 係用以使電荷陷入，意即電荷從氮化物層18進行注入戋是 一般來說’石夕-氧化物-氮化物-氧化物_半導體結構係藉 125052§2570twf,oc/y 由電子直接穿遂來進行程式化與抹除。關於電子穿遂係為 一種置子力學的過程(quantum mechanical process)，電荷载 子需要充足的能量來穿遂通過氧化層而陷入於氮化物層。 然而，習知的矽-氧化物-氮化物_氧化物_半導體元件係使用 厚度約20埃的薄穿遂氧化層，以增進抹除速度。在此種型 態的結構中，直接穿遂的電洞是用以抹除的主要機制。例 如在矽-氧化物-氮化物-氧化物_半導體抹除狀態中，啟始電 壓值VT為負數而導致電洞直接進行穿遂。但是，使用薄 穿遂閘氧化層由於易產生電荷洩漏，將面臨資料保存能力 較差的問題。 為了防止電荷洩漏使用一種氮化矽唯讀記憶體，而每 氮化石夕唯項記憶體的記憶胞位元係藉由通道熱電子注入 來進行程式化。其中，通道熱電子注入需要在源極與汲極 上施加高電壓，以使得電子通過通道區而進入電荷陷入層 T。然而，當電子深埋於電荷陷入層中，電子無法從電荷 入層中移除。因此，在進行抹除過程中，需要熱電洞注 入亚穿過底氧化層。而電洞係藉由能帶間穿遂(band t〇 tunneling)而產生，再經由橫向電場加速，接著注入並 牙過底氧化層以和電子進行復合(c〇mpensati〇n)。然而，熱 龟同/主入系要很大的界面偏壓，而此界面偏壓會破壞底氧 化層疋眾所皆知的。對於底氧化層的破壞很可能導致可靠 度^問題，如高啟始電壓VT的電荷損失、低啟始電壓的 電荷獲得及對於讀取的干擾等。 由上述可知，電荷陷入記憶體元件需要一種可靠且具 12 5 Ο 5 2 §257〇twf.doc/y 結構性的程式化及抹除的方法。 【發明内容】 廣泛地說，本發明能夠在電荷陷入記憶體元件中進行 程式化及抹除。在此，本發明所提出之方法及結構增進了 電荷陷入記憶體元件的電荷保存能力及可靠度。 依照本發明的一種觀點，提出一種電荷陷入記憶體元 件的程式化及抹除方法。首先，在閘極上施加第一負電壓 以得到刷新樣本(fresh sampie)，這個過程稱為元件的「重 置(RESET)」，而重置使閘極注入與解除陷入的電子間達 到動悲的平衡。接著，在閘極上施加正電壓，以使來自通 道區f外的電子注入陷入層。在抹除的操作中，在閘極上 施加第二負電壓以使記憶體元件恢復到重置/抹除的狀態。 依照本發明的另一種觀點，提出一種電荷陷入記憶體 兀件，包括一底氧化層、一陷入層及一頂氧化層。此外， 形成閘極的材質較佳的是多晶矽，以減少閘極注入。另外， 一高工作函數(high_Work负加如…金屬閘極也能用以減少 閘極注入的現象。 本$明具有許多優點，第一，本發明的記憶體元件是 具有可罪度的。第二，能量的消耗相當低。第三，本發明 的記憶體元件可以縮小至很小的尺寸。第四，抹除機制係 自我收斂，因此沒有過度抹除的問題存在。第五，本發明 的S己憶體70件可以解決電漿充電效應⑼ effect)。 為讓本發明之上述和其他目的、特徵和優點能更明顯 125052§2570tw£doc/y 易懂’下文特舉較佳實施例，並配合所關式，作詳 ^如下^並不用以_本發明，本發明 ^ 後附之申請專利範圍所界定者為準。 圍田現 【實施方式】 本發明舉出詳盡的實施例作為參考資料。在本發明 相關的實施舰行贿時，試圖包含在不脫離本發明申j 專，範圍所定義之精神和範_，所有替代、修飾及等= =貫施方式。更進-步地，在本發明下列詳盡的描述中， 提出許多明確的細節部分，使能更清楚了解本發明。然而， 熟悉此技_域者可以清楚的知道，本剌在沒有這些明 確的細節也可以進行操作。因此，在其它的例子、眾㈣ 知的方法、製程、元件及電路未詳錢露的情況下，本發Oxide-semiconductor, SONOS) and nitride read read memory (Nr0M). Generally, the charge trapping member has a charge trapping layer sandwiched between the two oxide layers, and the charge is stored in the charge trapping layer, and the stored charge is used to record the data. However, the method of erasing the charge trapping component is much more difficult than the floating gate because the electrons are trapped in a very deep position, and the de_trapping is very slow. 'X Figure 1 shows a germanium-oxide-nitride__oxide_semiconductor structure. The substrate 10, the source 12 and the drain 14 are included in FIG. In the 矽_Oxygen-nitride-oxide-semiconductor structure, an oxide-nitride-oxide layer is further included between the substrate 10 and the gate, and the corresponding reference numerals are oxide layer 16, nitriding, respectively. Layer 18 and oxide layer 20. Wherein, the nitride layer 18 is used to trap the charge, that is, the charge is injected from the nitride layer 18. Generally, the '石夕-oxide-nitride-oxide-semiconductor structure is borrowed 125052§2570twf,oc /y is programmed and erased by direct electronic transmission. With regard to the electron tunneling system as a quantum mechanical process, the charge carriers need sufficient energy to penetrate through the oxide layer and get trapped in the nitride layer. However, conventional germanium-oxide-nitride-oxide-semiconductor devices use a thin tantalum oxide layer having a thickness of about 20 angstroms to enhance the erase speed. In this type of structure, the hole that is directly pierced is the main mechanism for erasing. For example, in the yttrium-oxide-nitride-oxide-semiconductor erasing state, the starting voltage value VT is a negative number, causing the hole to directly pass through. However, the use of a thin pass gate oxide layer is subject to poor data retention due to charge leakage. In order to prevent charge leakage, a tantalum nitride read-only memory is used, and the memory cell level of each nitride-only memory is programmed by channel hot electron injection. Among them, the channel hot electron injection needs to apply a high voltage on the source and the drain so that electrons enter the charge trapping layer T through the channel region. However, when electrons are deeply buried in the charge trapping layer, electrons cannot be removed from the charge inlayer. Therefore, in the erasing process, a thermoelectric hole is required to be injected sub-pass through the bottom oxide layer. The holes are generated by band t〇 tunneling, accelerated by a transverse electric field, and then injected into the bottom of the oxidized layer to recombine with electrons (c〇mpensati〇n). However, the hot turtle/main system has a large interface bias, which is well known to the underlying oxide layer. Destruction of the bottom oxide layer is likely to cause reliability problems such as charge loss of the high start voltage VT, charge acquisition of the low start voltage, and interference with reading. From the above, it can be seen that the charge trapping into the memory device requires a reliable stylization and erasing method with a structure of 12 5 Ο 5 2 § 257 〇 twf. doc / y. SUMMARY OF THE INVENTION Broadly speaking, the present invention is capable of being programmed and erased in charge trapping memory elements. Here, the method and structure proposed by the present invention enhance the charge retention capability and reliability of the charge trapped in the memory element. In accordance with one aspect of the present invention, a stylized and erased method of charge trapping memory elements is presented. First, a first negative voltage is applied to the gate to obtain a refresh sampie. This process is called a "RESET" of the component, and a reset causes the gate to be injected and the electrons that are trapped into a sorrowful balance. Next, a positive voltage is applied to the gate so that electrons from outside the channel region f are injected into the trap layer. In the erase operation, a second negative voltage is applied across the gate to return the memory element to the reset/erase state. According to another aspect of the present invention, a charge trapping memory device is provided, comprising a bottom oxide layer, a trap layer, and a top oxide layer. In addition, the material forming the gate is preferably polysilicon to reduce gate implantation. In addition, a high work function (high_Work negative plus metal gate can also be used to reduce the phenomenon of gate injection. This $ has many advantages, first, the memory component of the present invention is guilty. Second, the energy consumption is quite low. Third, the memory element of the present invention can be reduced to a small size. Fourth, the erasing mechanism self-converges, so there is no problem of excessive erasure. Fifth, the present invention 70 pieces of S memory can solve the plasma charging effect (9) effect). The above and other objects, features, and advantages of the present invention will become more apparent by reference to the preferred embodiments of the <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The invention is defined by the scope of the appended claims. FIELD OF THE INVENTION [Embodiment] The present invention is described in detail as a reference. In the practice of the invention relating to the bribery of the invention, it is intended to include all alternatives, modifications and equivalents of the spirit and scope defined by the scope of the invention. Further, in the following detailed description of the invention, numerous specific details are set forth to provide a However, those skilled in the art will be well aware that Benedict can operate without these specific details. Therefore, in the case of other examples, methods, processes, components, and circuits that are not known to the public,
明仍可被清楚的了解。 X 本發明提出一種電荷陷入記憶體元件的程式化及抹 除方法，且此記憶體元件具有一氧化物_氮化物_氧化物結 構。圖2A〜圖2C係繪示本發明一較佳實施例。圖2A係繪 示電荷陷入記憶體元件的剖面圖。在圖2A具有一 p型矽 基底200，此矽基底200具有兩個摻雜界面202及204。另 外’乳化物-氮化物-氧化物(oxide-nitride-oxide，ΟΝΟ)結構 207配置於石夕基底200上。其中，此氧化物-氮化物_氧化物 結構207由下而上具有底氧化層206及頂氧化層210，且 具有一氮化層208配置於底氧化層206及頂氧化層210之 間。此外，有一閘極(未繪示）定義在頂氧化層210上方。 在圖2Α中’記憶體元件係透過如箭頭212之福勒諾罕 12570twf.doc/y 1250528 mrNordheim，姻)間極注入以進行第一次重置，而福 /干閘極/主入係藉由在閘極上施加負電壓來完成的。此 ί加在開極上的負電壓使記㈣元件處於重置/抹除的狀 二此重置/抹除的狀係為閘極注入與解除陷入的機制達到 I、的平衡。其中，所施加的貞電壓其電壓範關如是在 •15伏特到-23伏特之間。 办士^著明參照圖犯’可藉由在閘極上施力口正電壓以 元、私式化其中，所施加的正電壓範圍約在加伏特，以 使記憶體元· Ν型反轉料2G5(n_in_iQn eh_ei)注 ίΓΐΐ陷入層208，如箭頭214所示。然後，在閘極上 二2壓^以使記憶體元件由程式化狀態恢復到重置/ 2 在一實施例中’在此所施加的負電壓與圖2Α 二置日i所施加的負電壓相同。上述抹除過程係繪示 注入的電子將會如同圖2C中箭頭= 在抹除循環中被驅離至陷入層外。 =明一較佳實施例中，形成閘極的材質例如是具 有很问的有效阻障高度的材料，以降低閘極注入。並 ，極的材質較少使用N+型多晶石夕閘極，較佳的是.多 晶石夕閘極歧具有高卫作函數的金屬閘極， 重置狀態的啟始電壓(Vt)。更進—步來說，使用夕曰 料的情況下，福勒諾罕抹除是可能達成的。^ 閘極材料有效地減州極注人，顿得間極可 在非吊鬲的負閘極電壓VG下進行操作。在一實施例中， I25052^2570twfdoc/y 曰石夕ίϊ 成方法，例如先沉積—層非摻雜的多 = 是氟化卿F2)植人多妙膜層中所形 另-方面’非常高的負電壓會使得電子解除陷入 使用非常編_壓Vg，將會 雷一Ui層。其中，使用厚的穿遂氧化層可避免 電何搞的現象’而且使記㈣元件具有更高的可靠度。 在一實施例中，穿遂氧化層的厚度範圍係在3n 之間。 雖然小量的閘極注入仍會發生，但是抹除操作可使得 在閘極注人與電子m於動態平衡的狀態。如圖 2C所繪示’在抹除操作期間施加一負電壓將驅離額外的電 子’並使記髓元件恢制平衡雜態。上述的抹除操作 係為自我收敛(self-converging)。 口圖t〜圖3c係繪示本發明一較佳實施例中記憶體元件 操作之實驗結果的曲線圖。圖中所繪示氮化矽唯讀記憶體 技術在0.25娜設計法則下所製造之記憶體元件的實驗結 果。其中，此閘極係為摻雜硼的P+型多晶矽閘極，以減^ 閘極注入。而底氧化層、氮化矽陷入層及頂氡化層的厚度 分別為5.5nm、6nm及9nm。圖3a係繪示本發明一較佳實 ^例之5己丨思體元件的重置狀態。在圖3a中，y轴係用以表 不啟始電壓VT，X軸係用以表示時間，且時間的單位為秒。 為了重置§己憶體元件，施加一約為-21伏特的閘極電壓及 約為1伏特的讀取電壓。關於重置操作的進行方式如前述。 在進行重置之後，記憶體元件可被程式化。圖3b係 I250528_ twf.doc/y 繪示本發明一較佳實施例之記憶體元件的程式化狀態。在 圖3b中’y軸係用以表示啟始電壓ντ，χ軸係用以表示時 間，且時間的單位為秒。其中，每一條線係以不同的圖案 表不’用以呈現出不圖的閘極電壓。此閘極電壓的範圍約 在17伏特到20伏特之間。 ，3c係繪示本發明一較佳實施例之記憶體元件的抹 除狀態。如同圖3a及圖3b，y軸係用以表示啟始電壓ντ， X轴係用=表示時間，且時間的單位為秒。為了抹除記憶 體兀，、’施加與重置操作中相同的負電壓，以使記憶體元 件恢復為原來的重置/抹除狀態。原因是當閘極電壓約為 21伏特時，會產生動態平衡狀態。在此閘極電壓下，可 使啟始電壓VT維持敎，以使得閘極注人與電子解除陷 入之間互相維持平衡。以此方法，藉由正電壓所造成之額 外注入的電子會被㈣到氮化層之外。而且，此抹除操作 係為自我收斂。就其本身而論，本發明可轉決過度抹除 (over-erase)的問題。 圖4係緣示本發明一較佳實施例中記憶體元件之持久 特性的曲線圖。其中’y軸制以表示啟始電壓vT，x軸 示循環的次數。如上述的程式化操作中，係藉由 :二、伏特的電歷來完成。如上述對圖3C的描述中， =操作，藉由施加約_21伏特的電壓來完成。可以清楚 且有^雷，明由於使用厚的底氧化層，使得記憶體元件 何ί存能力。而且’此一厚的底氧化層可避免 …、電 更可進一步將電荷保留。圖5係緣示本發明 11 1250528· twf.doc/y 一較佳實施例中在高溫烘烤環境中經過1〇〇〇個程式化/抹 除循環之電荷保存能力的曲線圖。其中，y軸係用以表示 啟始電壓VT的損失，X軸係用以表示時間，且時間的單位 為年。即使在此情況下，電荷的損失量依舊很少。 睛參照圖6,係為本發明一較佳實施例中閘極注入所 需阻障南度600的示意圖。一般來說，阻障高度都相當高 以減少閘極注入及啟始重置電壓(reset thresh〇】d v〇ltage)。 在實鉍例中，阻P早尚度高於氧化物及矽導帶的偏移量 (offset)，例如是3.1eV。在一種重摻雜p+型多晶矽閘極的 實例中，阻障冑度應該接近於氧化物及#之價帶 band)f^^^#t , 4.2eV〇 ft的福勒諾罕穿遂可顯著的減少，且可以降低重置/抹除 狀悲的啟始電壓VT。 圖7係繪示本發明—較佳實施例中電荷陷人記憶體元 、^面圖。其中，此記憶體元件具有基底7GG、汲極702 观。此半導體元件更具有頂氧化層爪及底氧化 :n :陷入層7〇8配置於底氧化層及頂氧化層71〇 “。712係配置於頂氧化層710上。在閘極712上 時’底氧化層706下方形成一通道區7Η， 、、區4係配置於汲極702與源極704之間。 的電卜情^間極712施加一負電壓能重置圖7中所描述 元件。。在二2。其中，負電壓能有效的重置此記憶體 式化及抹實關中’福勒諾罕穿遂係用以程 匕體疋件。而福勒諾罕穿遂係藉由施加一強 12 twf.doc/y 125052^2570, 大的電場？過氧化層來完成，以使電子穿過氧化層。 在圖7的電荷陷入記憶體元件中，閘極可為p+型多晶 石夕閘極丄如此-來能有效減少閘極注人。此外，閘極的二 質可為高卫作函數的金屬，例如是翻。為了增進電子解除 陷入及抹除的速度，可對底氧化層的厚度進行調整。同樣 的’氧化石夕_氮化石夕-氧化石夕(0N0)堆疊結構中的每_膜層之 特性參數皆可進行調整。舉例來說，將f知的氮化物^入 層可用高介電常數(恤dielectric constant(k))的材料進行 替換’例如是氧化鋁(八丨2〇3)或Hf〇2，以使得解除電荷的速鲁 度改變。如此-來，當氮化層中陷入狀態的能量光譜不同 時’本發明與習知之電荷陷入記憶體元件的抹除特性將會 不同。此一特性也有助於改變抹除的速度。 曰 同介電常數(high k)穿遂氧化層很可能減少電荷陷入 及穿遂所需的阻障高度。因此，電荷陷入及抹除的速度可 、^力同樣的，南介電常數材料的底氧化層也很可能減 少頂氧化層的電場，而可能導致閘極注入減少。在一實施 例中，用以代替頂氧化層的高介電常數材料其介電常數較 佳的疋9 ’以及閘極注入的阻障高度約大於3eV，以減少 閘極注入。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 13 7570twf.doc/y 圖i係繪示一典型矽_氧化物-氮化物-氧化物-半導體 元件。 圖2A係繪示本發明一較佳實施例中藉由在閘極上施 加一負電壓以重置記憶體元件的剖面圖。 圖2B係綠示本發明一較佳實施例中藉由在閘極上施 加一正電壓以程式化記憶體元件的剖面圖。 圖2C係繪示本發明一較佳實施例中藉由在閘極上施 加一負電壓以抹除記憶體元件的剖面圖。 圖3A係繪示本發明一較佳實施例中記憶體元件之重 置狀態特性的曲線圖。 圖3B係繪不本發明一較佳實施例中記憶體元件之程 式化狀態特性的曲線圖。 圖3C係繪示本發明一較佳實施例中記憶體元件之抹 除狀態特性的曲線圖。 圖4係繪不本發明一較佳實施例中記憶體元件之持久 特性的曲線圖。 圖5係繪示本發明一較佳實施例中在高溫烘烤環境中 經過1000個程式化/抹除循環之電荷保存能力的曲線圖。 圖6係繪示本發明一較佳實施例中閘極注入所需阻 高度的示意圖。 圖7係繪示本發明一較佳實施例中電荷陷入記憶體元 件的剖面圖。 【主要元件符號說明】 10、200、700 :基底 >twf.doc/y 12、704 :源極 14、702 :汲極 16、20 :底氧化層 18 :氮化層 22、712 :閘極 202、204 :摻雜界面 205 : N型反轉通道 206、706 :底氧化層 207 :氧化物-氮化物-氧化物結構 208、708 :陷入層 210、710 :頂氧化層 212、214 ·•箭頭 600 :阻障高度 714 :通道區Ming can still be clearly understood. X The present invention provides a stylization and erasing method for charge trapping memory elements, and the memory element has an oxide-nitride-oxide structure. 2A to 2C illustrate a preferred embodiment of the present invention. Figure 2A is a cross-sectional view showing the charge trapping memory element. In Fig. 2A there is a p-type germanium substrate 200 having two doped interfaces 202 and 204. Further, an oxide-nitride-oxide structure 207 is disposed on the Shixia substrate 200. The oxide-nitride-oxide structure 207 has a bottom oxide layer 206 and a top oxide layer 210 from bottom to top, and has a nitride layer 208 disposed between the bottom oxide layer 206 and the top oxide layer 210. In addition, a gate (not shown) is defined above the top oxide layer 210. In Fig. 2Α, the 'memory component is injected through the pole of the Fowlernohan 12570twf.doc/y 1250528 mrNordheim, as shown by arrow 212, for the first reset, and the Fu/dry gate/primary system is borrowed. This is done by applying a negative voltage on the gate. The negative voltage applied to the open electrode causes the (4) component to be reset/erased. The reset/erase mode is the balance between the gate injection and the release mechanism. Among them, the applied voltage of the 贞 voltage is between 15 volts and -23 volts. The manager can make a positive reference voltage by applying a positive voltage to the gate. The positive voltage applied is about volts, so that the memory element is reversed. 2G5(n_in_iQn eh_ei) is immersed in layer 208 as indicated by arrow 214. Then, two or two voltages are applied to the gate to restore the memory element from the stylized state to the reset / 2. In one embodiment, the negative voltage applied here is the same as the negative voltage applied by Figure 2 . The above erase process shows that the injected electrons will be driven out of the trapped layer as in the arrow = Figure 2C arrow = in the erase cycle. In the preferred embodiment, the material forming the gate is, for example, a material having a high effective barrier height to reduce gate injection. Moreover, the material of the pole is less used with the N+ type polycrystalline stone gate, and it is preferable that the polycrystalline stone gate has a high gate function metal gate, the starting voltage (Vt) of the reset state. Further, step by step, in the case of the use of eve, the Fleurnoham eradication is possible. ^ The gate material effectively reduces the state's extreme injection, and the inter-electrode can operate under the non-concealed negative gate voltage VG. In one embodiment, the method of I25052^2570twfdoc/y ,石夕 ϊ ϊ , , , , , , , , , , , = = = 是 是 是 是 是 是 是 是 是 是 是 是 是 是 是 是 是 是 是The negative voltage will cause the electrons to be released into the use of very programmed _pressure Vg, which will be a Ui layer. Among them, the use of a thick pass-through oxide layer can avoid the phenomenon of electricity, and the component (4) has higher reliability. In one embodiment, the thickness of the tantalum oxide layer is between 3 n. Although a small amount of gate injection still occurs, the erase operation allows the gate to be in a state of dynamic equilibrium with the electron m. As shown in Figure 2C, 'applying a negative voltage during the erase operation will drive away the extra electrons' and restore the core elements to equilibrium. The above erase operation is self-converging. Port diagrams t to 3c are graphs showing experimental results of memory element operation in a preferred embodiment of the present invention. The experimental results of the memory device fabricated by the 5% semiconductor design rule under the 0.25 Na design rule are shown in the figure. Among them, the gate is a boron-doped P+ type polysilicon gate, which is injected with a reduced gate. The thickness of the bottom oxide layer, the tantalum nitride trap layer, and the top germanium layer were 5.5 nm, 6 nm, and 9 nm, respectively. Fig. 3a is a diagram showing the reset state of a body element of a preferred embodiment of the present invention. In Figure 3a, the y-axis is used to indicate the start voltage VT, the X-axis is used to represent time, and the time is in seconds. To reset the § memory element, a gate voltage of approximately -21 volts and a read voltage of approximately 1 volt are applied. The manner in which the reset operation is performed is as described above. After the reset, the memory components can be programmed. Figure 3b is a diagram showing the stylized state of a memory component in accordance with a preferred embodiment of the present invention. In Figure 3b, the 'y-axis is used to indicate the starting voltage ντ, and the x-axis is used to represent time, and the time is in seconds. Each of the lines is represented by a different pattern to present a gate voltage that is not shown. This gate voltage ranges from approximately 17 volts to 20 volts. 3c illustrates the erased state of the memory device in accordance with a preferred embodiment of the present invention. As with Figures 3a and 3b, the y-axis is used to indicate the starting voltage ντ, the X-axis is used to represent time, and the time is in seconds. To erase the memory port, 'apply the same negative voltage as in the reset operation to return the memory element to its original reset/erase state. The reason is that when the gate voltage is about 21 volts, a dynamic equilibrium state occurs. At this gate voltage, the starting voltage VT can be maintained at a level such that the gate is in balance with the electrons being trapped. In this way, the extra electrons injected by the positive voltage are (4) outside the nitride layer. Moreover, this erase operation is self-converging. As such, the present invention can turn over the problem of over-erase. Figure 4 is a graph showing the persistent characteristics of a memory device in accordance with a preferred embodiment of the present invention. The 'y-axis system is used to indicate the starting voltage vT, and the x-axis shows the number of cycles. As in the above stylized operation, it is completed by the electric history of volts. As described above with respect to Figure 3C, the = operation is accomplished by applying a voltage of approximately _21 volts. It can be clear and there is a thunder, which makes the memory components more capable due to the use of a thick underlying oxide layer. Moreover, this thick underlying oxide layer can avoid ... and the electricity can further retain the charge. Figure 5 is a graph showing the charge retention ability of one of the stylized/erased cycles in a high temperature baking environment in accordance with a preferred embodiment of the invention 11 1250528 twf.doc/y. Among them, the y-axis is used to indicate the loss of the starting voltage VT, the X-axis is used to represent the time, and the unit of time is the year. Even in this case, the amount of charge loss is still small. Referring to Figure 6, there is shown a schematic diagram of a barrier 600 required for gate injection in accordance with a preferred embodiment of the present invention. In general, the barrier height is quite high to reduce gate injection and start reset voltage (reset thresh〇) d v〇ltage). In the actual example, the resistance P is earlier than the offset of the oxide and the antimony conduction band, for example, 3.1 eV. In an example of a heavily doped p+-type polysilicon gate, the barrier mobility should be close to the oxide and the valence band of the #f^^^#t, and the Fore-Nornon perforation of 4.2eV〇ft can be significant. The reduction is reduced and the reset voltage VT of resetting/erasing can be reduced. Figure 7 is a cross-sectional view showing the charge trapped memory element in the preferred embodiment of the present invention. Wherein, the memory element has a base 7GG and a drain 702 view. The semiconductor device further has a top oxide layer and a bottom oxide: n: the trapped layer 7〇8 is disposed on the bottom oxide layer and the top oxide layer 71〇. The .712 is disposed on the top oxide layer 710. When on the gate 712 A channel region 7 is formed under the bottom oxide layer 706, and the region 4 is disposed between the drain 702 and the source 704. A negative voltage is applied to the device 712 to reset the component described in FIG. In 2: 2. The negative voltage can effectively reset this memory and smear the 'Follerham wears the 遂 system for the 匕 疋 。. And the Fleurnohan wears the 藉 by applying a strong 12 Twf.doc/y 125052^2570, a large electric field is completed by a peroxide layer to pass electrons through the oxide layer. In the charge trapping memory device of Figure 7, the gate can be a p+ type polycrystalline slab gate丄 - 来 来 来 - - - - - - - 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。. Make adjustments. The same 'oxidized stone _ _ 氮化 夕 - 氧化 氧化 氧化 氧化 氧化 0 0 (0N0) stacked structure The characteristic parameters can be adjusted. For example, the nitride layer can be replaced by a material with a high dielectric constant (k) (for example, alumina (eight 丨 2 〇 3) or Hf 〇 2, so that the speed of the charge is changed. Thus, when the energy spectrum of the state of the trapped layer in the nitride layer is different, the erase characteristic of the present invention and the conventional charge trapped memory element will be different. A characteristic also helps to change the speed of erasing. The same dielectric constant (high k) through the oxide layer is likely to reduce the barrier height required for charge trapping and piercing. Therefore, the rate of charge trapping and erasing can be Similarly, the bottom oxide layer of the south dielectric constant material is also likely to reduce the electric field of the top oxide layer, which may result in a decrease in gate implant. In one embodiment, the high dielectric constant material used to replace the top oxide layer The 疋9' with a better dielectric constant and the barrier height of the gate implant are greater than about 3 eV to reduce gate implant. Although the invention has been disclosed in the preferred embodiments above, it is not intended to limit the invention, any Familiar with this artist The scope of protection of the present invention is defined by the scope of the appended claims. The description of the drawings is based on the description of the appended claims. 13 7570twf. Doc/y Figure i shows a typical germanium oxide-nitride-oxide-semiconductor device. Figure 2A illustrates a memory of a preferred embodiment of the present invention by applying a negative voltage across the gate to reset the memory. Figure 2B is a cross-sectional view of a preferred embodiment of the present invention in which a positive voltage is applied to a gate to program a memory device. Figure 2C illustrates a preferred embodiment of the present invention. A cross-sectional view of the memory device is erased by applying a negative voltage across the gate. Fig. 3A is a graph showing the state of the reset state of a memory element in a preferred embodiment of the present invention. Fig. 3B is a graph showing the state of the process state of the memory device in a preferred embodiment of the present invention. Figure 3C is a graph showing the erased state characteristics of a memory device in accordance with a preferred embodiment of the present invention. Figure 4 is a graph depicting the persistent characteristics of a memory component in a preferred embodiment of the present invention. Figure 5 is a graph showing the charge retention capability of 1000 staging/erasing cycles in a high temperature baking environment in accordance with a preferred embodiment of the present invention. Fig. 6 is a schematic view showing the required resistance height of gate implantation in a preferred embodiment of the present invention. Figure 7 is a cross-sectional view showing a charge trapped memory device in accordance with a preferred embodiment of the present invention. [Description of main component symbols] 10, 200, 700: substrate > gtf.doc/y 12, 704: source 14, 702: drain 16, 20: bottom oxide layer 18: nitride layer 22, 712: gate 202, 204: doping interface 205: N-type inversion channel 206, 706: bottom oxide layer 207: oxide-nitride-oxide structure 208, 708: trapping layer 210, 710: top oxide layer 212, 214 · Arrow 600: barrier height 714: channel area
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