TWI249230B - Method for producing multi-dice stacked package and structure of the same - Google Patents

Method for producing multi-dice stacked package and structure of the same Download PDF

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Publication number
TWI249230B
TWI249230B TW094116937A TW94116937A TWI249230B TW I249230 B TWI249230 B TW I249230B TW 094116937 A TW094116937 A TW 094116937A TW 94116937 A TW94116937 A TW 94116937A TW I249230 B TWI249230 B TW I249230B
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Taiwan
Prior art keywords
wafer
carrier
electromagnetic shielding
package
shielding layer
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Application number
TW094116937A
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Chinese (zh)
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TW200642057A (en
Inventor
Johnny Chen
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Advanced Semiconductor Eng
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Priority to TW094116937A priority Critical patent/TWI249230B/en
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Publication of TWI249230B publication Critical patent/TWI249230B/en
Publication of TW200642057A publication Critical patent/TW200642057A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Laminated Bodies (AREA)

Abstract

A method for producing multi-dice stacked package and structure of the same is provided, and particularly, a method for disposing a plurality of dice together in a stacked manner is provided with an electromagnetic shielding layer. A first die, a first molding compound, an electromagnetic shielding layer, a second die and a second molding compound are stacked on a substrate sequentially. The first molding compound encloses the first die. The electromagnetic shielding layer is covered over the first molding compound for insulation purposes between the first and second dice. The second die is disposed on the electromagnetic shielding layer. The second molding compound encloses the second die, the electromagnetic shielding layer and the first molding compound simultaneously.

Description

1249230 九、發明說明.· 【發明所屬之技術領域】 本發明係關於一種厂多晶片雄嚴' 置」’特別是指一種將複數個晶片二：f方吻 並於其，-晶片的封膠體上形成 封裝方法及裝置者。 '兹屏敝層的 【先前技術】 由於電子產業的蓬勃發屏， 不斷地朝小型化和古、穿I : 人邛为的電子產品均 電子產品必須使用射頻（RF)曰 ^其中更有不少 數位Ic、射頻曰片^ )日日片，例如將射頻晶片與1249230 IX. Description of the invention. [Technical field of the invention] The present invention relates to a factory multi-chip majestic 'setting', in particular to a plurality of wafers: f-square kiss, and - the chip sealant The method and device for forming the package are formed. [Previous technology] Because of the booming screen of the electronics industry, the electronic products that are constantly becoming smaller and older, and wearing I: people must use radio frequency (RF) 曰 ^ which is more A few bits of Ic, RF chips ^) Japanese films, such as RF chips and

Signal Process〇r)、或射 p，DlgitalSignal Process〇r), or shoot p, Dlgital

Base 化的目標，惟由於該射頻：片：屬他 行電磁屏蔽（shielding)處理。 口八因此必須進 第一n ::弟-種封裝技術係先將-高頻的 乐/片（例如射頻晶片）與—第二晶片分 士， 接者再表面黏著(SMT)於一板上。惟 、衣 的習知第二、三種封裝技術。㈣功效不如後述 Μ Η Γ知弟一種係為多晶片模組（MCM，Multi-Chip M:ule)封裝技術’其主要係將— 處理哭曰（例如數位1C、數位訊號 :圖二ί 置於同—封襄之内，如第 处：干：H if4習知乐二種的多晶片模組封裝的 f不思圖，其係將該些電性且機械性連接於-載板 1249230 1上的第一晶片n盥 — ，體13内一 ~弟—日日片12,予以封裝於同一封 ”13内，料夺合小型化和高速化的要求，惟該習 且封裝技術的缺點即是姆 、^二片上進行電磁屏蔽（shieldmg)處理。 =二種係為系統整合封裝（SiP，System in 且機械性連接於—载’其係將該些電性 一曰 戟板2上的咼頻的第一晶片21與第 ::片22,封裝於各別的封膠體2H、221内，藉以 付曰於整合的要求，惟一 術雖能夠在該第—晶片21白上\弟：；種糸統整合封裝技 處理，卻會有封膠體川尸；；二電的磁屏蔽（shlelding) 合小型化的要求。'偏大的缺點’反而不符 【發明内容】 晶片矛 本發明「多晶片堆疊之封裝彳法及裝 在於以-種多晶片堆疊的封裝方式來封裝第_ 第二晶片’藉以縮小整體封裝的封膠體尺寸 小型化和高速化要求。 :本發明「多晶片堆疊之封裝方法及裝置」，另一. 面遢能同時在該第-晶片的封膠體上進行電磁屏蔽. =處理’藉以使該高頻的第-晶片具有電磁屏； [發明特徵] 為解決上述諸問題，本發明係在 之封裝方法，其包括： 種夕曰曰片心 提供-載板，其具有一上表面及—下表面； 1249230 將一第一晶片配置於該載板之上表面，且與該載板電 性連接； 以一第一封膠體包覆該第一晶片及該載板上表面； 於該第一封膠體上形成一電磁屏蔽層； 將一第二晶片配置於該電磁屏蔽層上，且與該載板電 性連接；及 以一第二封膠體包覆該弟二晶片、該電磁屏献層、該 第一封膠體及該載板上表面。 本發明另提供一種多晶片堆疊之封裝裝置，其包 括·· 一載板，該載板具有一上表面及一下表面； 一第一.晶片’其設置於該載板之上表面； 一第一封膠體，其包覆該第一晶片和該載板上表面； 一電磁屏蔽層，其設於該第一封膠體上; 一第二晶片，其設置於該電磁屏蔽層上；及 一第二封膠體，其包覆該第二晶片、該電磁屏蔽層、 該第一封膠體和該載板上表面。 【實施方式】 為能更進一步瞭解本發明之特徵與技術内容，請 參閱以下有關本發明之詳細說明與所附圖式。 請參閱第三〜七圖所示，本發明係提供一種多晶 片堆疊之封裝方法及裝置，其主要在於將多個晶片以 堆疊方式封裝在一起，並於其中之第一晶片的封膠體 1249230 =形成-電磁疆層，藉以兼具小型化與電磁屏蔽效 封事〜七圖所示，為本發明多晶片堆疊之 其具有_卜本二00』 ^ 代卜、载板3， . σ：；^Φ 33^^Α«„ 就考jf守一弟一晶片4配置於古玄恭士 32 n a u /、，， 載板3之上表面The target of the base, but because of the radio: film: belongs to other electromagnetic shielding (shielding) processing. Mouth 8 must therefore enter the first n:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- . However, the second and third packaging techniques of the clothing. (4) The effect is not as follows Μ Γ Γ 弟 Brother is a multi-chip module (MCM, Multi-Chip M: ule) packaging technology 'the main system will be - processing crying (such as digital 1C, digital signal: Figure 2 置于 placed In the same - in the seal, as in the first: dry: H if4 I know the two kinds of multi-chip module package, do not think about it, which is electrically and mechanically connected to the carrier plate 1249230 1 The first wafer n盥-, the body 13-di-day-day film 12, is packaged in the same "13", which is expected to meet the requirements of miniaturization and high-speed, but the shortcoming of the package technology is Electromagnetic shielding (shieldmg) processing on the two pieces of the film. = Two systems are system integrated packages (SiP, System in and mechanically connected to the 'loading' of the electrical frequency on the board 2 The first wafer 21 and the :: sheet 22 are encapsulated in the respective encapsulants 2H, 221, so as to pay for the integration requirements, the only technique can be on the first wafer 21 white: The integration of packaging technology, but there will be sealant body corpse;; the second magnetic shielding (shlelding) and miniaturization requirements. 'large Disadvantages of the present invention [Disclosed] The invention relates to a "multi-chip stack package method and a package in which a second wafer is packaged in a multi-wafer stack package form" to reduce the size of the package body of the entire package. And high-speed requirements: The present invention "package method and apparatus for multi-wafer stacking", another. The surface can simultaneously perform electromagnetic shielding on the sealing body of the first wafer. = Processing 'by the high frequency - The wafer has an electromagnetic screen; [Inventive Features] In order to solve the above problems, the present invention is a packaging method comprising: a seeding core providing-carrier having an upper surface and a lower surface; 1249230 The first wafer is disposed on the upper surface of the carrier and electrically connected to the carrier; the first wafer and the surface of the carrier are covered by a first sealing body; and an electromagnetic is formed on the first sealing body a shielding layer; a second wafer is disposed on the electromagnetic shielding layer and electrically connected to the carrier; and the second sealing body is coated with the second sealing body, the electromagnetic shielding layer, and the first sealing body And the carrier The present invention further provides a multi-wafer stack packaging device comprising: a carrier plate having an upper surface and a lower surface; a first wafer 'which is disposed on the upper surface of the carrier plate; a first colloid covering the first wafer and the surface of the carrier; an electromagnetic shielding layer disposed on the first encapsulant; a second wafer disposed on the electromagnetic shielding layer; a second encapsulant covering the second wafer, the electromagnetic shielding layer, the first encapsulant and the surface of the carrier. [Embodiment] In order to further understand the features and technical contents of the present invention, please refer to the following The detailed description of the present invention and the accompanying drawings. Referring to the third to seventh embodiments, the present invention provides a multi-wafer stack packaging method and apparatus, which mainly comprises packaging a plurality of wafers in a stacked manner. And the first wafer of the first wafer 1249230 = formed - electromagnetic layer, thereby having both miniaturization and electromagnetic shielding effect sealing ~ seven figures, which is the multi-wafer stack of the present invention has _ 卜本二00 ^ Dibu, The plate 3, σ:; ^ Φ 33 ^^ Α «" jf keep a brother to test a wafer arranged in the ancient mysterious CHRISTINE 4 Disabled 32 n a u / ,,, 3 on the surface of the carrier plate

圖斯與該載板3電性連接，如第三B Z:不者，該第一晶片4係藉由複數條第—導電忑 二，板3電性連接，或亦可如第七圖所示，使: 曰曰片4藉由複數個凸塊43與該載板接： 發明對此並未限定；進者，再以一 ^生逆接本 該第~晶>| 4 @ 1 4 q A 十膠體41包覆 4與該^ : ^ -係些弟一導電線42或一 磁屏圖而所由示二ΐ第一封膠體41上係形成-電 晶片4及封膠體41係'包覆於該第一 乃亦包一 It32㈣ 『“二 曰片4及該载板3的上表面32,藉 、’)確貫的電磁屏蔽效果。其申，該 的成型係可有複數種不同 :开敝k ^rmpfQl 的方式，例如可利用金屬喷 ί " 如第五A、五β圖所示 ^亦=用金屬電鑛（metaipiatin 方"亥弟—封膠體4Γ上，本㈣對此並未限定。 士口楚 X Λ f _ 斗兩、 叫厂々不，將一第二晶片5配罟 呑亥％磁屏蔽層6上，兮楚 "" 5亥弟二晶片5並與該載板3電, 1249230 晶片5、該電磁屏蔽層 第二封膠體51包覆該第 该第一封膠體41及号τq + 曰 及4載板3的上表面32，如第五Β 圖所示，該第二晶# q #。 ; 曰曰月b舁该載板3之間的該些第二導 電線52，係亦被包覆住。 /如弟六圖所不，該载板3之下表面33還能進一步 =有複數個錫球31 ’藉以電性連、其它電子產品 或其它電子裝置。 其中，該第一晶片4係為—高頻的晶#，例如是 一射頻晶片（RF device)，而哕筮一曰y g曰r &二 h 而3罘一日日片5則為其它晶 一，歹丨日口疋一數位iC、一數位訊號處理器（DSP)、或 基頻日日片（Base Band)。本發明該實施例乃適用於所 有的整合產品，例如：射頻曰u扣垂^ J 射頻晶片與數位1C的整合、射 頻晶片與數位訊號處理器⑽，Dlgltal Slgnal ，的整合、或射頻晶片與基頻晶 Band)白勺 m # ' 請參閱第八圖所示，係為本發明多晶片堆疊之封 方法的流程圖，其包括提供一載板（s〇i)，將一曰 片配置於该載板（S02)，以„篦一射映雕 u ,οπολ Μ弟封恥體包覆該第一晶 片⑽）’於該第一封膠體上形成—電磁屏蔽層 (S04) ’將一弟二晶片配置於該電磁屏蔽層上（s〇 以及以一第二封膠體包霜呤笙—曰 是5亥弟一日日片、該電磁屏蔽層 及該弟一封膠體（S06h 閱弟六圖或第+同沉_ — u 乂弟七圖所不，係為本發明多晶片 1249230 堆疊之封裝裝置的一實施例示意圖，其包括有一載板 3，該載板3係具有一上表面32及_下表面33 ; 一第 一晶片4，係設置於該載板3之上表面犯；一第一封 膠體4卜係包覆該第-晶片4和該载板3的上表面 32 ; —電磁屏蔽層6，係設於該第—封膠體41上；一 第二晶片5，係設置於該電磁屏蔽層6上；以及一第 二封膠體51，係包覆該第二晶片5、該電磁屏蔽層6、 該第一封膠體41和該載板上表面32〇 【發明特點及優點】 一、藉由本發明該多晶片堆疊的封裝The figure is electrically connected to the carrier 3, such as the third BZ: no, the first wafer 4 is electrically connected by a plurality of first-conducting electrodes 2, or as shown in the seventh figure. So that: the cymbal 4 is connected to the carrier by a plurality of bumps 43: the invention is not limited thereto; in addition, the slab is reversed by the first crystallization >| 4 @ 1 4 q A The ten colloid 41 is coated with 4 and the ^: ^ - is a conductive wire 42 or a magnetic screen, and is formed by the second sealing body 41. The electric wafer 4 and the sealing body 41 are coated. The first is also included in the It32 (4) ""2" 4 and the upper surface 32 of the carrier 3, borrowed, ') the effective electromagnetic shielding effect. It is claimed that the molding system can have a plurality of different types:敝k ^rmpfQl way, for example, can use metal spray ί " as shown in the fifth A, five beta diagram ^ also = use metal ore (metaipiatin side " Haidi - sealant 4 Γ, this (four) Unrestricted. Shikou Chu X Λ f _ Dou two, called the factory 々 No, will a second wafer 5 with 罟呑 % % % % % % % % % % & & & & & 亥 亥 亥 亥 亥 亥 亥 亥 亥Carrier 3 power, 1249230 wafer 5, the electromagnetic The second sealing body 51 of the shielding layer covers the first surface 32 of the first sealing body 41 and the number τq + 曰 and the fourth carrier 3, as shown in the fifth figure, the second crystal #q#. The second conductive wires 52 between the carrier plates 3 are also covered. / If the figure is not shown, the lower surface 33 of the carrier 3 can further have a plurality of tins. The ball 31' is electrically connected to other electronic products or other electronic devices. The first wafer 4 is a high frequency crystal, for example, an RF device, and the yg曰r &2h and 3罘1, the day 5 is another crystal, the next day is a digital iC, a digital signal processor (DSP), or a baseband solar band (Base Band). The examples are applicable to all integrated products, such as: RF 曰 扣 ^ ^ J RF chip and digital 1C integration, RF chip and digital signal processor (10), Dlgltal Slgnal, integration, or RF chip and baseband crystal Band ) m # ' See the eighth figure, which is a flow chart of the method for sealing a multi-wafer stack of the present invention, which includes providing a carrier board (s 〇i), a slab is disposed on the carrier (S02), and the first wafer (10) is formed on the first encapsulant by 篦 射 映 , u, οπολ 封 封 封 耻 包覆 — Electromagnetic shielding layer (S04) 'distributing a second chip to the electromagnetic shielding layer (s〇 and a second encapsulating body 呤笙 曰 曰 5 5 5 5 5 、 、 、 、 、 、 、 、 、 、 、 、 、 A colloid (S06h, 6th, or 6th), which is a schematic diagram of an embodiment of a multi-wafer 1249230 stacking device of the present invention, comprising a carrier 3, The carrier 3 has an upper surface 32 and a lower surface 33; a first wafer 4 is disposed on the upper surface of the carrier 3; a first encapsulant 4 covers the first wafer 4 and the The upper surface 32 of the carrier 3; the electromagnetic shielding layer 6 is disposed on the first sealing body 41; a second wafer 5 is disposed on the electromagnetic shielding layer 6; and a second sealing body 51 Wrap the second wafer 5, the electromagnetic shielding layer 6, the first encapsulant 41 and the surface of the carrier board 32 [invention features and advantages] The stacked multi-chip package

Stacked CSP)，該第一曰片 4p 工 ^ ^ ^ s 、该弟—封膠體41 4¾¾屏敝層6、該第二晶片5以 日 ;二=體 且封裝後將更適合於通訊=和-Stacked CSP), the first die 4p ^ ^ ^ s, the brother - sealant 41 43⁄43⁄4 screen layer 6, the second wafer 5 in days; two = body and after packaging will be more suitable for communication = and -

Stacfed ctn Ϊ f " ! ^ # ^ ^ 11 ^ ^ (SCSP 萨以竹古頻的-利於成型該電磁屏蔽層6, 褚以4邊同頻的弟—晶片4 尸 晶片 而能避免干擾到該第-q "磁屏蔽效果 法及;ΐ所:可種多晶片堆疊之封 -電磁屏蔽層的缺失，實::::型二、無法有效. 發明產品，並具功“。具“度產業利她 10 1249230 惟以上所述者，僅係本發明之一較佳可行的實施例而 已，非因此即局限本發明之權利範圍，舉凡運用本發明說 明書及圖式内容所為之等效變化，均理同包含於本發明之 權利範圍内，合予陳明。 【圖式簡單說明】 第一圖為習知多晶片模組封裝的結構示意圖。 第二圖為習知系統整合封裝的結構示意圖。 第二A、二B圖為本發明多晶片堆豐封裝的弟"一晶片封 裝示意圖。 第四圖為本發明多晶片堆疊封裝的電磁屏蔽層成型示意 圖。 第五A、五B圖為本發明多晶片堆豐封装的弟二晶片封 裝示意圖。 第六圖為本發明多晶片堆疊封裝的錫球設置示意圖。 第七圖為本發明多晶片堆疊封裝的另一實施例示意圖。 第八圖為本發明多晶片堆疊封裝方法的流程圖。 【主要元件符號說明】 [習知] 1載板 11第一晶片 12第二晶片 13封膠體 2載板 21第一晶片 211封膠體 1249230 22第二晶片 221封膠體 [本發明] 3載板 31錫球 32上表面 33下表面 4第一晶片 41第一封膠體 42第一導電線 43凸塊 5第二晶片 51第二封膠體 52第二導電線 6電磁屏敝層Stacfed ctn Ϊ f " ! ^ # ^ ^ 11 ^ ^ (SCSP Saizhu Zhugu frequency - to shape the electromagnetic shielding layer 6, 褚 with 4 sides of the same frequency of the brother - wafer 4 corpse wafer can avoid interference The first -q "magnetic shielding effect method and; ΐ所: can be multi-wafer stacked seal - the absence of electromagnetic shielding layer, real:::: type two, can not be effective. Invented products, and has a merit". The above is only one of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and equivalent variations of the present specification and drawings are used. The same is included in the scope of the present invention and is given to Chen Ming. [Simple Description of the Drawing] The first figure is a schematic structural view of a conventional multi-chip module package. The second figure is a schematic structural view of a conventional system integrated package. 2A and 2B are schematic diagrams of a wafer package of the multi-wafer stack package of the present invention. The fourth figure is a schematic diagram of the electromagnetic shield layer formation of the multi-wafer stack package of the present invention. Invented the multi-chip stack package The sixth figure is a schematic diagram of the solder ball arrangement of the multi-wafer stack package of the present invention. The seventh figure is a schematic diagram of another embodiment of the multi-wafer stack package of the present invention. The eighth figure is a flow chart of the multi-wafer stack packaging method of the present invention. [Main component symbol description] [Generally known] 1 carrier 11 first wafer 12 second wafer 13 encapsulant 2 carrier 21 first wafer 211 encapsulant 1249230 22 second wafer 221 encapsulant [invention] 3 carrier 31 Tin ball 32 upper surface 33 lower surface 4 first wafer 41 first encapsulant 42 first conductive line 43 bump 5 second wafer 51 second encapsulant 52 second conductive line 6 electromagnetic screen layer

1212

Claims (1)

1249230 申請專利範圍： 、一種多晶片堆疊之封裝方法，包括： 提供-載板，該載板具有一上表面及一下表面. Ίΐ片配置於該载板之上表面，且與該载 板電性連接；^ 以一第 面； 封膠 包覆該第一晶片及該載板上表 於該第-封膠體上形成一電磁屏蔽層； 將一第二晶片配置於該電屏厗 板電性連接；及屏蚊層上，且與該] 以一第二封膠體包覆曰千 H皆+ 罘—曰日门、该電磁屏肖 層该弟—封膠體及該載板上表面。 請ί:範圍第1項所述之多晶片堆疊之則 ’tt 電磁屏蔽層係利用金屬噴濺(raeta sputtenng)技術來成型。 参 4 ‘如申請專利範圍第丄項所述之 方法，其中該電磁屏蔽芦 日日 宜之士| Plating)技術來成型。 "^屬-鍍(㈣a 2”:範圍第1項所述之多晶片堆疊之封, 方其中該第-晶片係為-射頻晶片 如申請專㈣圍第：項所述之 方法’其中該第二晶片係為一*二隹-之封各 號處理器(DSP)、或—Λ:曰H」C、-數位訊 ^由咬車工 基頻晶片（Base Band)。 申㈣專利範圍第1項所述之多晶片堆疊之封裝 13 1249230 方係藉& 與該載板電性連接。 久數 <木弟一導電線 7、 如申請專利範圍第1項所述之多晶片堆聂之… 方法，其中該第一晶片係夢门且之封衣 板電性連接。 猎由魏個凸塊與該载 8、 如申請專利範圍第丄項所述 a 方法，其中該第—曰 夕日日片堆®之封裝 與該載板電4;㈣由複數條第二導電線 9專·圍第w所述之多晶片堆疊之封 方：:更形成複數個锡球於該載板之下表面: 1 0、一種夕晶片堆疊之封裝裝置，包括·· -載板’其具有一上表面及―下表面； 一第一晶片，其設置於該载板之上表面. 面;一第一封膠體，其包覆該第-晶片和該载板上表 一電磁屏蔽層，其設於該第一封膠體上； 一第二晶片，其設置於該電磁屏蔽層上；及 一第二封膠體，其包覆該第_曰 μ 、气隻, 弗—日日片、该電磁屏蔽 層3亥弟一封膠體和該載板上表面。 1 1請專利範圍第1 0項所述之多晶片堆疊之 封裝裝置，更包含複數個錫球形成於該载板: 表面。 Γ L 2、如申請專利範圍第1Q項所述之多晶片堆 封叙裝置’其中該第一晶片係藉由複數條第—導 14 仫49230 電線與該载板電性連接。 3、 如申請專利範圍第丄〇 夕 封裝裝置，其中該第—B =之夕晶片堆疊之 該载板電性連接。日日片係藉由複數個凸塊與 4、 如申請專利範圍第1 n 、 封裝裝置，其中兮第一、所述之多晶片堆疊之 電線與該载板電;日片係藉_^ 封裝裝置，其中該第―晶片係為'_曰门。 封ΐ!:專利範圍第10項所述之多晶片堆疊之 仅衣i，其中該第二晶片係為一數位1C、一數 位訊號處理器（DSP)、或一基頻晶片（Base Band)。 :::專=!f10項所述之多晶片堆疊之 射頻晶片1249230 Patent application scope: A multi-wafer stack packaging method, comprising: providing a carrier board having an upper surface and a lower surface. The cymbal sheet is disposed on the upper surface of the carrier board and electrically connected to the carrier board Connecting the first wafer and the carrier to form an electromagnetic shielding layer on the first sealing body; and electrically connecting a second wafer to the electric screen And the screen mosquito layer, and with the second cover body covered with a second seal body 曰 thousand H are + 罘 曰 曰 门, the electromagnetic screen Xiao layer of the brother - sealant and the surface of the carrier. Please ί: The multi-wafer stack described in the first item of the range 'tt electromagnetic shielding layer is formed by metal sputtening technology. 4 4 ‘As described in the scope of the patent application, in which the electromagnetic shielding is made by the Japanese | Plating technology. "^属-plating ((4)a 2": the package of the multi-wafer stack described in the above paragraph 1, wherein the first wafer is a radio-frequency wafer, as described in the application (4) The second chip is a *2隹-series processor (DSP), or -Λ:曰H"C,-digit information is used by the bite driver baseband chip (Base Band). The multi-wafer stack package 13 1249230 is electrically connected to the carrier board. The number of times < the younger brother's conductive line 7, as described in claim 1, the multi-chip stack The method, wherein the first wafer is a dream door and the enclosure is electrically connected. The hunting is performed by a bump and the carrier 8, as described in the third aspect of the patent application, wherein the first day The package of the wafer stack® and the carrier plate 4; (4) the sealing of the multi-wafer stack described by the plurality of second conductive wires 9: a plurality of solder balls are formed under the carrier plate Surface: 10, a package device for stacking a wafer, comprising: - a carrier plate having an upper surface and a lower surface; a first wafer, a first sealing body covering the first wafer and an electromagnetic shielding layer on the carrier plate, which is disposed on the first sealing body; a second wafer, And disposed on the electromagnetic shielding layer; and a second encapsulant covering the first _μμ, the gas only, the Fu-Japanese film, the electromagnetic shielding layer 3, a gel and the surface of the carrier 1 1 Please package the multi-wafer stacking device described in claim 10, further comprising a plurality of solder balls formed on the carrier: surface. Γ L 2. Multi-wafer as described in claim 1Q The stacking device is wherein the first wafer is electrically connected to the carrier by a plurality of wires - 43152. 3, as in the patent application, the package device, wherein the first B = The carrier of the wafer stack is electrically connected. The solar wafer is composed of a plurality of bumps and 4, as in the patent application scope 1 n , a packaging device, wherein the first and the plurality of wafers are stacked with the wire and the The carrier is powered by a _^ package device, wherein the first chip is a '_曰门The sealing of the multi-wafer stack described in claim 10, wherein the second chip is a digital 1C, a digital signal processor (DSP), or a baseband chip (Base Band). :::Special =! Multi-wafer stacked RF chip as described in item f10 1515
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