TWI248176B - Windowing lead-frame semiconductor package structure and fabrication process thereof - Google Patents

Windowing lead-frame semiconductor package structure and fabrication process thereof Download PDF

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Publication number
TWI248176B
TWI248176B TW090110815A TW90110815A TWI248176B TW I248176 B TWI248176 B TW I248176B TW 090110815 A TW090110815 A TW 090110815A TW 90110815 A TW90110815 A TW 90110815A TW I248176 B TWI248176 B TW I248176B
Authority
TW
Taiwan
Prior art keywords
window
lead frame
opening
type
semiconductor
Prior art date
Application number
TW090110815A
Other languages
Chinese (zh)
Inventor
Tsang-Ling Chiou
Shiu-Di Chen
Tzung-Da He
Original Assignee
Siliconware Precision Industries Co Ltd
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Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW090110815A priority Critical patent/TWI248176B/en
Application granted granted Critical
Publication of TWI248176B publication Critical patent/TWI248176B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present invention relates to a windowing lead-frame semiconductor package structure and fabrication process thereof, which employs a windowing lead-frame as a chip carrier and is characterized by placing a windowing pad between a die pad and a semiconductor die, thereby making the lead-frame having the same specification suitable for packaging dies with all types of sizes. Such characteristic enables the application of the windowing lead-frame semiconductor packaging technique in the present invention to be more cost-effective than conventional techniques. Besides, the windowing pad can also extrinsically increase the heat dissipation performance of the packaged semiconductor chip.

Description

1248176 員 Α7 Β7 五、發明說明（1 ) 【發明領域] 本發明係有關於一種半導體封裝技術，特別是有關 於一種開窗型導線架式半導體封裝結構及製程，其係採用 開齒型導線架來作為晶片載具，且其特點在於將一開窗型 墊片安置於晶片座與半導體晶片之間，藉此而使得同一規 袼的導線架可適用於封裝各種大小尺寸之晶片，並可附帶 地增加所封裝之半導體晶片的散熱效能。 [發明背景】 導線架式半導體封裝技術為一種利用導線架 (leadframe)作為晶片載具（ehip carrier)的封裝技術，其所 採用之導線架一般係包括一位於中央的晶片座（.㈣和 複數支位於周邊的導腳（leads);其中晶片座即用以安置半 導體晶片，而導腳則作為該半導體晶片的外部電性連接 點。 開窗型導線架為一種特殊型式的導線架，其特點在 於其晶片座上形成有-空洞之開窗部，可藉此而防止其上 所黏貼之半導體晶片產生脫層現象（delaminati〇n)。以下 即配合所附圖式之第！八至10圖，以圖解方式簡述一習 知之開窗型導線架式半導體封裝技術。 第1A圖顯示該習知技術所採用之開窗型導線架1〇〇 的上視圖，而第1B圖則顯示該開窗型導線架ι〇〇沿 線切開的剖面圖。如圖所示，此開窗型導線架ι〇〇 —般係 為銅製，其結構包括複數支位於周邊的導腳11〇和—位於 中央的晶片座12〇，且該晶片座12〇 、 , 开负貫體之環狀部 本尺度適(CNS)A4規格⑵G χ 297公爱） 1 16258 •裝--------訂---------^9— 2清先閱讀背面之注音？事項再填寫本頁} 1248176 五 A7 發明說明（ 121和一空洞之開窗部（wind〇w)122。 此開窗型導線架1〇〇係用以安置一 ,,w % 千導體晶片14〇〇 此處須注思的一點是，該半導體 “ 千导體曰曰片140的寬度％須為 大於日日片座120之開窗部122的寬度 ，、、、 ^ ^。，否則其將盔法 被安置於晶片座120上。 长 請接著參閲第丨匸圖，下一個步驟為進行一置晶程 藉以將該半導體晶片140安置於晶片座120上，^方’ 將半導體晶uo藉由一導熱性黏膠層141，例如為銀膠為 而黏貼至晶片座120的環狀部121上。 請接著參閱第m圖，下一個步驟為進行一鲜線程序 (Wlre-b〇ndingP_ss)，藉以利用複數條銲線15〇，例如 為金線，將半導體晶片140電性藕接至導線架100的導卿 no。完成之後接著即進行一封裝膠體製程’藉此而形成 一封裝膠體（encapsulation body)16〇，用以包覆半導體晶 片140。此即完成一個封裝單元的製作。 於上述之製程中，將導線架100之晶片座12〇設計 成具有開窗部122的目的在於其可防止半導體晶片14〇產 生脫層現象，亦即可防止半導體晶片14〇從晶片座12〇上 脫落。若是晶片座120不具有此開窗部122，則由於鋼製 之晶片座120的熱膨脹係數（c〇efficient 〇f Thermal1248176 员Α7 Β7 V. INSTRUCTION DESCRIPTION (1) Field of the Invention The present invention relates to a semiconductor package technology, and more particularly to a window-opening lead frame type semiconductor package structure and process, which uses an open-toothed lead frame As a wafer carrier, and characterized in that a window-opening spacer is disposed between the wafer holder and the semiconductor wafer, thereby making the same gauge lead frame suitable for packaging wafers of various sizes and can be attached The heat dissipation performance of the packaged semiconductor wafer is increased. [Background of the Invention] The lead frame type semiconductor package technology is a package technology using a lead frame as an ehip carrier, and the lead frame used generally includes a centrally located wafer holder (.(4) and plural Leading the periphery of the lead; wherein the wafer holder is used to place the semiconductor wafer, and the lead is used as the external electrical connection point of the semiconductor wafer. The window type lead frame is a special type of lead frame, and its characteristics A window opening portion is formed in the wafer holder, thereby preventing delamination of the semiconductor wafer adhered thereon. The following is the drawing of the figure 8 to 10 A schematic view of a conventional windowed lead frame type semiconductor package technology is schematically illustrated. Fig. 1A shows a top view of the windowed lead frame 1〇〇 used in the prior art, and Fig. 1B shows the open A cross-sectional view of the window type lead frame cut along the line. As shown in the figure, the window type lead frame is generally made of copper, and the structure includes a plurality of guide pins 11 〇 and located at the periphery. The wafer holder of the center is 12〇, and the wafer holder is 12〇, and the annular portion of the opening and closing body is of the appropriate size (CNS) A4 specification (2) G χ 297 gong) 1 16258 • Loading-------- ---------^9— 2 Read the phonetic on the back first? Matters refill this page} 1248176 Five A7 Description of the invention (121 and a hollow window (wind〇w) 122. This window-type lead frame 1 is used to place a, w% thousand conductor wafer 14〇 One point to note here is that the semiconductor "the width % of the one-piece conductor piece 140 must be greater than the width of the window opening portion 122 of the day seat 120, ^, ^ ^. The method is disposed on the wafer holder 120. Please refer to the second drawing for the length. The next step is to perform a crystallizing process to place the semiconductor wafer 140 on the wafer holder 120. A thermally conductive adhesive layer 141, for example, a silver paste, is adhered to the annular portion 121 of the wafer holder 120. Please refer to the mth diagram, and the next step is to perform a fresh line program (Wlre-b〇ndingP_ss). The semiconductor wafer 140 is electrically connected to the guide no of the lead frame 100 by using a plurality of bonding wires 15 , for example, a gold wire. After completion, an encapsulation process is performed to form an encapsulation (encapsulation). Body) 16〇, used to cover the semiconductor wafer 140. This completes a The fabrication of the package unit. In the above process, the wafer holder 12 of the lead frame 100 is designed to have the window opening portion 122 for the purpose of preventing delamination of the semiconductor wafer 14 and preventing the semiconductor wafer 14 from being defective. The wafer holder 12 is detached from the wafer holder 12. If the wafer holder 120 does not have the window opening portion 122, the thermal expansion coefficient of the wafer holder 120 made of steel (c〇efficient 〇f Thermal

Expansion, CTE)大致為 16卯111/。(：：至2〇1)1)111/。(：：之間，而 半導體晶片140的熱膨脹係數則大致為3ppm/〇c至 4ppm/°C之間，因此二者之間的熱膨脹係數差異將易於導 致半導體晶片140於後續之高溫製程中，因熱膨脹程度不 本紙張尺度適財國國家鮮（CNS)A4規格（210 X挪公爱）— —φ. Μ-------It------- (請先閱讀背面之注音？事項再填寫本頁) 16258 1248176 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（3 ) 同而產生脫層現象。 然而，於實際應用上，前述之開窗型導線架式半導 體封裝技術卻有以下之二項缺點。 第一項缺點為其中所採用之導線架100的設計規格 僅適用於封裝大尺寸的晶片，亦即半導體晶片140的寬度 %須大於晶片座120之開窗部122的寬度％，否則其將 無法被安置於晶片座120上。因此若有較小尺寸的晶片需 要封裝，則便須另外設計新規格的導線架。但此作法將使 得整體之製造成本更為增加。半導體業界因此需求一種新 的開窗型導線架式半導體封裝技術，其可使得同一規格的 導線架適用於封裝各種大小尺寸之晶片。 第二項缺點為晶片座120形成開窗部122會減小半 導體晶片140與晶片座120之間的接觸面積，因此將大為 減低半導體晶片140的散熱效能。 相關之專利技術例如包括有美國專利第5，140,404號 "SEMICONDUCTOR DEVICE MANUFACTURED BY A METHOD FOR ATTACHING A SEMICONDUCTOR DIE TO A LEADFRAME USING A THERMOPLASTIC COVERED CARRIER TAPE”。此美國專利揭露了一種進步性的導線 架式半導體封裝技術。然而此美國專利並未對前述之二項 問題提供適當的解決方法。 [發明概述1 鑒於以上所述習知技術之缺點，本發明之主要目的 便是在於提供一種新的開窗型導線架式半導體封裝技術， - - * -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 3 16258 1248176 B7 五、發明說明（4 ) 其可使得同一規格的導線架適用於封裝各種大小尺寸之半 導體晶片。 本發月之另目的在於提供一種新的開 式半導體封裝結構，1可姆* % &壯 架 稱其了增加所封裝之半導體晶片的散埶 效能。 μ 根據以上所述之目的，本發明即提供了一種新的開 窗型導線架式半導體封裝技術。 發月之開自型導線架式半導體封裝技術於製程上 以下步驟.（1)預製—導線架，其包括複數支導腳和一 晶片座’·該晶片座具有一實體之環狀部和一空洞之開窗 部’且該開窗部具有—狀尺寸；⑺安置—開窗型塾片 於該導線架的晶片座上；該開窗型塾片具有一實體之環狀 朴空洞之開窗部，且該開窗型塾片的開窗部係大致對 齊至該導線架之晶片座的開窗部；（3)安置-半導體晶片 於該開窗型塾片上；⑷進行—銲線程序，藉此而將該半 導體晶片電性藕接至該導線架的導腳；以及(5)進行一封 裝膠體製程’藉此而形成一封裝膠體，用以包覆該半導體 晶片。 本發明之開窗型導線架式半導體封裝技術於結構上 包δ以下構件：（a)一導線架，其包括複數支導腳和一晶片 座，》玄晶片座具有一實體之環狀部和一空洞之開窗部，且 該開窗部具有一預定尺寸；（b)一㈣型塾片其係安置 於該導線架的晶片座上；該開窗型墊片具有一實體之環狀 部和一空洞之開窗部，且該開窗型墊片的開窗部係大致對 16258 t 訂 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ四7公釐） 1248176 A7 五、發明說明（5 ) (請先閱讀背面之注意事項再填寫本頁) 齊至該導線架之晶片座的開窗部；（C)一半導體晶片，其 係安置於該開窗型墊片的環狀部上；（幻一銲線組，其用 以將該半導體晶片電性藕接至該導線架的導腳；以及（e) 一封裴膠體，其用以包覆該半導體晶片。 本發明之開窗型導線架式半導體封裝技術的特點在 於將一開窗型墊片安置於晶片座與半導體晶片之間，藉此 而使得同一規格的導線架可適用於封裝各種大小尺寸之晶 片。此特點使得本發明於應用上較習知技術更具有成本效 益。此外，此開窗型墊片亦可附帶地增加所封裝之半導體 晶片的散熱效能。 【圈式簡述1 本發明之實質技術内容及其實施例已用圖解方式詳 細揭露繪製於本說明書所附之圖式之中。此些圖式之内容 簡述如下： 第1A至1D圖（習知技術）為結構示意圖，其中顯示 一習知之開窗型導線架式半導體封裝技術於製程上的各個 主要步驟； 經濟部智慧財產局員工消費合作社印製 第2A至2D圖為結構示意圖，其中顯示本發明之開 窗型導線架式半導體封裝技術於製程上的各個主要步驟。 [圈式標號說明] 100 開窗型導線架 110 導腳 120 晶片座 121 晶片座120之環狀部 16258 1248176 A? 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 122 晶片座120之開窗部 140 半導體晶片 141 導熱性黏膠層 150 銲線 160 封裝膠體 200 開窗型導線架 210 導腳 220 晶片座 221 晶片座220之環狀部 222 晶片座220之開窗部 230 開窗型墊片 231 開窗型墊片230 ^ 232 開窗型塾片230之μ 1 233 導熱性黏膠層 240 半導體晶片 241 導熱性黏膠層 250 銲線 260 封裝膠體 [發明實施例I 部 以下即配合所附圖式之第2 a至2〇 -----------•裝------ (請先閱讀背面之注意事項再填寫本頁) tr---------s'. 明本發明之開窗型導線架式半導體莊圖，詳細揭露說 、裝技術之一實施例 請首先參閱第2A圖，本發明之4知乃之開窗型導線架式半驾 體封裝技術於製程上的第一個步驟為首先預製一開窗型’ 線架200和一開窗型墊片230，用以封裝一半導體晶片 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） !6258 1248176 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（7 240 〇 開窗型導線架200包括複數支位於周邊之導腳21〇 和一位於中央之晶片座220，且該晶片座220具有一實體 之環狀部221和一空洞之開窗部222，其中該開窗部222 具有一預定之寬度％。 開窗型墊片230亦具有一實體之環狀部231和一空 洞之開窗部232。此開窗型墊片230的整體寬度％須大 於晶片座220之開窗部222的寬度％，而其中之開窗部 232的寬度％則須小於半導體晶片mo的寬度％。此外， 此開窗型墊片230的環狀部231的寬度％須至少等於或 大於〇.25mm，以能提供良妤的支撐效果。再者，此開窗 型塾片230的熱膨脹係數須介於開窗型導線架2〇〇的熱膨 脹係數與半導體晶片24〇的熱膨脹係數之間。 半導體晶片240的寬度％可為大於或小於晶片座22〇 之開窗部222的寬度。於此實施例中，假設半導體晶 片240的寬度R係小於晶片座220之開窗部222的寬度 %(本發明的一項優點即在於第1Α至1D圖所示之習知技 術並無法用來封裝此種較小尺寸的晶片）。 請接著參閱第2Β圖，下一個步驟為將開窗型塾片23〇 安置於導線架200的晶片座220上，其方式為利用_導熱 性黏膠層233，例如為銀膠，將開窗型墊片230的環狀部 231黏貼至晶片座220的環狀部221，並使得開窗型塾片 230的開窗部232對齊至晶片座220的開窗部222。 請接著參閱第2C圖，下一個步驟為進行一置晶程序， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 裝--------訂----- (請先閱讀背面之注音？事項再填寫本頁) s'. 1248176 A7 ----^---- 五、發明說明（8 ) 藉以將半導體晶片240安置於晶片座22〇上的開窗型墊片 23〇上，其方式為將半導體晶24〇藉由一導熱性黏膠層 (請先閱讀背面之注意事項再填寫本頁) 241，例如為銀膠，而黏貼至開窗型墊片23〇的環狀部 上。 請接著參閱第2D圖，下一個步驟為進行一銲線程序， 藉以利用複數條銲線250,例如為金線，將半導體晶片24〇 電性藕接至導線架200的導腳210。完成之後接著及即進 行一封裝膠體製程，藉此而形成一封裝膠體26〇，用以包 覆半導體晶片240。此即完成本發明之開窗型導線架式半 導體封裝製程，其所製成之封裝單元即如第21)圖所示。 經濟部智慧財產局員工消費合作社印製 綜而言之，本發明提供了一種新穎之開窗型導線架 式半導體封裝技術，其係採用開窗型導線架來作為晶片載 具，且其特點在於將一開窗型墊片安置於晶片座與半導體 晶片之間，藉此而使得同一規格的導線架可適用於封裝各 種大小尺寸之晶片。此特點使得本發明於應用上較習知技 術更具有成本效益。此外，此開窗型墊片亦可附帶地增加 所封裝之半導體晶片的散熱效能。本發明因此較習知技術 具有更佳之進步性及實用性。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之實質技術内容的範圍。本發明之實質技術内 容係廣義地定義於下述之申請專利範圍中。任何他人所完i 成之技術實體或方法，若是與下述之申請專利範圍所定義 者為完全相同、或是為一種等效之變更，均將被視為涵蓋 於此專利範圍之中。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 8 16258Expansion, CTE) is roughly 16卯111/. (:: to 2〇1) 1) 111/. (::, and the thermal expansion coefficient of the semiconductor wafer 140 is approximately between 3 ppm/〇c and 4 ppm/°C, so the difference in thermal expansion coefficient between the two will easily cause the semiconductor wafer 140 to be in a subsequent high temperature process. Due to the degree of thermal expansion, the paper size is suitable for the country's national fresh (CNS) A4 specification (210 X Ngonggong love) - φ. Μ-------It------- (please read the back Note: Please fill out this page again. 16258 1248176 Ministry of Economic Affairs, Intellectual Property Office, Staff Consumer Cooperative, Printed A7 B7 V. Invention Description (3) At the same time, delamination occurs. However, in practical applications, the aforementioned window-type lead frame The semiconductor package technology has the following two disadvantages. The first disadvantage is that the design of the lead frame 100 used therein is only suitable for packaging large-sized wafers, that is, the width % of the semiconductor wafer 140 must be larger than that of the wafer holder 120. The width of the window portion 122 is %, otherwise it will not be placed on the wafer holder 120. Therefore, if a smaller size wafer needs to be packaged, a new specification of the lead frame must be additionally designed. However, this method will make the overall manufacturing. More cost The semiconductor industry therefore requires a new window-opening leadframe semiconductor package technology that allows the same size of leadframe to be used to package wafers of various sizes. The second drawback is that the wafer holder 120 forms the window opening 122. The contact area between the semiconductor wafer 140 and the wafer holder 120 is reduced, and thus the heat dissipation performance of the semiconductor wafer 140 is greatly reduced. Related patent technologies include, for example, U.S. Patent No. 5,140,404 "SEMICONDUCTOR DEVICE MANUFACTURED BY A METHOD FOR ATTACHING A SEMICONDUCTOR DIE TO A LEADFRAME USING A THERMOPLASTIC COVERED CARRIER TAPE". This U.S. patent discloses a progressive leadframe semiconductor package technology. However, this U.S. patent does not provide an appropriate solution to the aforementioned two problems. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the main object of the present invention is to provide a new window-opening type lead frame type semiconductor packaging technology, - - * - - - --------Book --------- (Please read the note on the back and fill out this page) This paper size is applicable National Standard (CNS) A4 Specification (210 X 297 mm) 3 16258 1248176 B7 V. Invention Description (4) It can make the lead frame of the same specification suitable for packaging semiconductor chips of various sizes. The other purpose of this month is A new open semiconductor package structure is provided, which is said to increase the divergence performance of the packaged semiconductor wafer. μ According to the above, the present invention provides a new window-opening type lead frame type semiconductor package technology. The opening of the self-type lead-frame semiconductor package technology in the process of the following steps. (1) prefabricated - lead frame, comprising a plurality of legs and a wafer holder '. The wafer holder has a solid annular portion and a a window opening portion of the hollow portion, and the window opening portion has a shape-like size; (7) a window-shaped slat is disposed on the wafer holder of the lead frame; the window-opening cymbal has a solid window opening And the window opening portion of the window opening type is substantially aligned to the window opening portion of the wafer holder of the lead frame; (3) the semiconductor wafer is disposed on the window opening type; (4) the wire bonding process is performed. Thereby, the semiconductor wafer is electrically connected to the lead of the lead frame; and (5) performing an encapsulation process to form an encapsulant for coating the semiconductor wafer. The window-opening type semiconductor package technology of the present invention comprises the following components: δ: a lead frame comprising a plurality of lead legs and a wafer holder, wherein the hollow wafer holder has a solid annular portion and a hollow window opening portion, wherein the window opening portion has a predetermined size; (b) a (four) type blade is disposed on the wafer holder of the lead frame; the window opening type gasket has a solid annular portion And a hollow window opening portion, and the window opening portion of the window opening type gasket is substantially applicable to the Chinese National Standard (CNS) A4 specification (21〇χ4 7 mm) for the 16258 t staple paper size. 1248176 A7 (5) (Please read the note on the back side and then fill in the page) to the window opening of the wafer holder of the lead frame; (C) a semiconductor wafer, which is placed in the ring of the window-type spacer On the top; (a magic wire group for electrically connecting the semiconductor wafer to the lead of the lead frame; and (e) a silicone body for coating the semiconductor wafer. The window-opening lead frame type semiconductor packaging technology is characterized by placing a window-opening gasket Between the wafer holder and the semiconductor wafer, thereby making the lead frame of the same specification suitable for packaging wafers of various sizes. This feature makes the invention more cost-effective to apply to the prior art. Moreover, the window is opened. The type of spacer can also additionally increase the heat dissipation performance of the packaged semiconductor wafer. [Circle Brief Description 1 The technical contents of the present invention and its embodiments have been disclosed in detail in the drawings attached to the present specification. The contents of these drawings are briefly described as follows: FIGS. 1A to 1D (preferred technology) are schematic structural diagrams showing various main steps of a conventional window-opening lead frame type semiconductor packaging technology in a process; 2A to 2D are printed as a structural diagram showing the main steps of the window-opening type semiconductor package technology of the present invention in the manufacturing process. [Circle label description] 100 window type lead frame 110 lead 120 wafer holder 121 wafer holder 120 ring portion 16258 1248176 A? Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing five, issued Description (122 wafer opening 120 of the wafer holder 120 semiconductor wafer 141 thermal conductive adhesive layer 150 bonding wire 160 encapsulant 200 window type lead frame 210 lead 220 wafer holder 221 wafer holder 220 annular portion 222 wafer holder 220 Windowing part 230 window type spacer 231 window type spacer 230 ^ 232 window type diaphragm 230 μ 1 233 thermal conductive adhesive layer 240 semiconductor wafer 241 thermal conductive adhesive layer 250 bonding wire 260 encapsulant colloid The first part of the following is the 2nd to 2nd 〇-----------• ------ (Please read the note on the back and fill out this page) Tr---------s'. The window-opening type semiconductor frame of the invention is disclosed in detail. For an embodiment of the invention, please refer to FIG. 2A firstly. The first step of the window-type lead frame type semi-riding package technology in the process is to first prefabricate an open window type 'wire frame 200 and a window opening type spacer 230 for packaging a semiconductor wafer. China National Standard (CNS) A4 Specification (210 X 297 mm) !6258 1248176 Ministry of Economic Affairs Intellectual Property Office staff Consumer Cooperatives Print A7 V. Invention Description (7 240 〇 window type lead frame 200 includes a plurality of lead legs 21 周边 at the periphery and a wafer holder 220 at the center, and the wafer holder 220 has a solid annular portion 221 and a hollow window opening 222, wherein the window opening portion 222 has a predetermined width %. The fenestration spacer 230 also has a solid annular portion 231 and a hollow window opening portion 232. The overall width % of the fenestration spacer 230 must be greater than the width % of the fenestration portion 222 of the wafer holder 220, and the width % of the fenestration portion 232 must be less than the width % of the semiconductor wafer mo. Further, the width % of the annular portion 231 of the fenestration type gasket 230 must be at least equal to or greater than 〇25 mm to provide a good supporting effect. Further, the coefficient of thermal expansion of the fenestration type sheet 230 must be between the coefficient of thermal expansion of the fenestration type lead frame 2 与 and the coefficient of thermal expansion of the semiconductor wafer 24 。. The width % of the semiconductor wafer 240 may be greater or smaller than the width of the window portion 222 of the wafer holder 22A. In this embodiment, it is assumed that the width R of the semiconductor wafer 240 is smaller than the width % of the window opening portion 222 of the wafer holder 220 (an advantage of the present invention is that the prior art shown in Figures 1 to 1D cannot be used. Packaging such smaller sized wafers). Please refer to FIG. 2, the next step is to place the window-opening cymbal 23 〇 on the wafer holder 220 of the lead frame 200 by using a thermal conductive adhesive layer 233, such as silver glue, to open the window. The annular portion 231 of the spacer 230 is adhered to the annular portion 221 of the wafer holder 220, and the window opening portion 232 of the window-opening tab 230 is aligned to the window opening portion 222 of the wafer holder 220. Please refer to Figure 2C. The next step is to perform a crystal setting procedure. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm).----- - (Please read the phonetic on the back first? Then fill out this page) s'. 1248176 A7 ----^---- V. Invention Description (8) The semiconductor wafer 240 is placed on the wafer holder 22 The window spacer 23 is formed by laminating the semiconductor crystal 24 by a thermal conductive adhesive layer (please read this page on the back side of the page) 241, for example, silver paste, and sticking to the window type. The gasket 23 is on the annular portion. Please refer to FIG. 2D. The next step is to perform a wire bonding process for electrically splicing the semiconductor wafer 24 to the lead pin 210 of the lead frame 200 by using a plurality of bonding wires 250, such as gold wires. After completion, an encapsulation process is performed, thereby forming an encapsulant 26 〇 for coating the semiconductor wafer 240. Thus, the window-opening type lead frame type semiconductor package process of the present invention is completed, and the package unit formed is as shown in Fig. 21). In summary, the present invention provides a novel window-opening lead frame type semiconductor package technology, which uses a window-opening type lead frame as a wafer carrier, and is characterized in that A window-opening spacer is disposed between the wafer holder and the semiconductor wafer, thereby making the lead frame of the same specification suitable for packaging wafers of various sizes. This feature makes the invention more cost effective to use than conventional techniques. In addition, the fenestration type gasket can additionally increase the heat dissipation performance of the packaged semiconductor wafer. The present invention therefore has better advancement and utility than conventional techniques. The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the technical scope of the present invention. The technical content of the present invention is broadly defined in the scope of the following claims. Any technical entity or method that is completed by another person is deemed to be identical or equivalent to the scope of the patent application described below, and is considered to be within the scope of this patent. This paper scale applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 8 16258

Claims (1)

12481761248176 六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 1- 一種開窗型導線架式半導體封裝製程，其至少包含以 下步驟： (1) 預製一導線架，其包括複數支導腳和一晶片 座；該晶片座具有一實體之環狀部和一空洞之開窗部， 且該開窗部具有一預定尺寸； (2) 安置一開窗型墊片於該導線架的晶片座上；該 開窗型墊片具有一實體之環狀部和一空洞之開窗部， 且該開窗型墊片的開窗部係大致對齊至該導線架之晶 片座的開窗部； (3) 女置一半導體晶片於該開窗型墊片上； (4) 進行一銲線程序，藉此而將該半導體晶片電性 藕接至該導線架的導腳；以及 (5) 進行一封裝膠體製程，藉此而形成一封裝膠 體，用以包覆該半導體晶片。 2 ·如申請專利範圍第1項所述之開窗型導線架式半導體 封裝製程，其中步驟（1)中所述之導線架係為銅製。 3.如申請專利範圍第1項所述之開窗型導線架式半導體 封裝製程，其中步驟（2)中所述之開窗型墊片的熱膨脹 係數係介於該開窗型導線架的熱膨脹係數與該半導體 晶片的熱膨脹係數之間。 4·如申請專利範圍第1項所述之開窗型導線架式半導體 封裝製程，其中步驟（2)中所述之開窗型墊片係藉由一 導熱性黏膠層而黏貼至該導線架之晶片座的環狀部。 5·如申請專利範圍第4項所述之開窗型導線架式半導體 k張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） "'" ----- 9 16258 (請先閲讀背面之注意事項再填寫本頁) -1¾ 訂---------線秦Sixth, the scope of application for patents Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 1 - a window-type lead frame type semiconductor packaging process, which at least comprises the following steps: (1) Prefabricated a lead frame, which includes a plurality of lead legs and a a wafer holder; the wafer holder has a solid annular portion and a hollow window opening portion, and the window opening portion has a predetermined size; (2) a window opening type gasket is disposed on the wafer holder of the lead frame; The fenestration type gasket has a solid annular portion and a hollow window opening portion, and the window opening portion of the window opening type gasket is substantially aligned to the window opening portion of the wafer holder of the lead frame; a semiconductor wafer is placed on the fenestration pad; (4) performing a wire bonding process to electrically splicing the semiconductor wafer to the lead leg of the lead frame; and (5) performing an encapsulation colloid The process thereby forms an encapsulant for coating the semiconductor wafer. 2. The window-opening lead frame type semiconductor package process of claim 1, wherein the lead frame described in the step (1) is made of copper. 3. The window-opening lead frame type semiconductor packaging process according to claim 1, wherein the thermal expansion coefficient of the window-opening spacer described in the step (2) is between the thermal expansion of the window-opening lead frame. The coefficient is between the coefficient of thermal expansion of the semiconductor wafer. 4. The window-opening type lead frame type semiconductor packaging process according to claim 1, wherein the window-opening type gasket described in the step (2) is adhered to the wire by a thermal conductive adhesive layer. The annular portion of the wafer holder. 5. The window-type lead frame type semiconductor k-scale according to item 4 of the patent application scope applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) "'" ----- 9 16258 (Please read the notes on the back and fill out this page) -13⁄4 Order---------Line Qin 申請專利範圍 1248176 封裝製程，其中該導熱性黏膠層係為銀膠。 6.如申請專利範圍第丨項所述之開窗型導線架式半導體 封裝製程，其中步驟（3)中所述之半導體晶片係藉由— 導熱性黏膠層而黏貼至該開窗型墊片的環狀部。 7·如申請專利範圍第6項所述之開窗型導線架式半導體 封裝製程，其中該導熱性黏膠層係為銀膠。 8·如申請專利範圍第丨項所述之開窗型導線架式半導體 封裝製程，其中步驟（5)中所述之銲線係為金製銲線。 9· 一種開窗型導線架式半導體封裝結構，其至少包含以 下構件： (a) —導線架，其包括複數支導腳和一晶片座，·該 晶片座具有一實體之環狀部和一空洞之開窗部，且該Λ 開窗部具有一預定尺寸； (b) -開窗型墊片，其係安置於該導線架的晶片座 上；該開窗型墊片具有一實體之環狀部和一空洞之開 窗部，且該開窗型墊片的開窗部係大致對齊至該導= 架之晶片座的開窗部； (c) -半導體晶片，其係安置於該開窗型墊片的環 狀部上； (d) -銲線組’其用以將該半導體晶片電性藕接至 該導線架的導腳；以及 (e) —封裝膠體，其用以包覆該半導體晶片。 10·如申請專利範圍第9項所述之開窗型導線架式半導體 封裝結構’其中該導線架係為鋼製。 木紙張尺度適用中國國家標準（CNS)A4規袼（2】Qx297^7 10 16258 * > * --------^------— (請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 1248176 A8 B8 C8 D8Patent application 1248176 packaging process, wherein the thermal adhesive layer is silver glue. 6. The window-opening type lead frame type semiconductor packaging process according to the invention of claim 2, wherein the semiconductor wafer described in the step (3) is adhered to the window opening pad by a thermal conductive adhesive layer. The annular portion of the piece. 7. The window-opening lead frame type semiconductor packaging process of claim 6, wherein the thermally conductive adhesive layer is silver paste. 8. The window-opening lead frame type semiconductor packaging process according to the invention of claim 2, wherein the bonding wire described in the step (5) is a gold bonding wire. 9. A window-opening lead frame type semiconductor package structure comprising at least the following members: (a) a lead frame comprising a plurality of lead legs and a wafer holder, the wafer holder having a solid annular portion and a a window opening portion of the cavity, and the window opening portion has a predetermined size; (b) a window opening type gasket disposed on the wafer holder of the lead frame; the window opening type gasket has a physical ring a window portion and a hollow window opening portion, and the window opening portion of the window opening type gasket is substantially aligned to the window opening portion of the wafer holder of the guide frame; (c) a semiconductor wafer disposed on the opening (d) a wire bond group for electrically connecting the semiconductor wafer to the lead leg of the lead frame; and (e) an encapsulant for coating The semiconductor wafer. 10. The window-opening type lead frame type semiconductor package structure according to claim 9, wherein the lead frame is made of steel. Wood paper scale applies to China National Standard (CNS) A4 regulations (2) Qx297^7 10 16258 * > * --------^------— (Please read the notes on the back first Fill in the page} Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 1248176 A8 B8 C8 D8 、申請專利範圍 11 ·如申請專利範 封裝結構，其 開窗型導線架 係數之間。 12 ·如申請專利範 封袭結構，其 而黏貼至該導 13 ·如申請專利範 封裝結構，其 14·如申請專利範 封裝結構，其 而黏貼至該開 15·如申請專利範 封裝結構，其 16·如申請專利範 封裝結構，其 圍第9項所述之開窗型導線架式半導體 中該開窗型墊片的熱膨脹係數係介於該 的熱膨脹係數與該半導體晶片的熱膨脹 圍第9項所述之開窗Μ導線架式半導體 中該開窗型墊片係藉由一導熱性黏膠層 線架之晶片座的環狀部。 圍第12項所述之開窗型導線架式半導體 中該導熱性黏膠層係為銀膠。 圍第9項所述之開窗型導線架式半導體 中該半導體晶片係藉由-導熱性黏膠層 窗型墊片的環狀部。 圍第14項所述之開窗型導線架式半導體 中該導熱性黏膠層係為銀膠。 圍第9項所述之開窗型導線架式半導體 中該銲線係為金製銲線。 I - — III — — — ^ « — — — — — — I— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製Patent application scope 11 · If the patent application package structure is applied, the window-type lead frame coefficient is between. 12 · If you apply for a patent-enclosed structure, it is attached to the guide 13 · If you apply for a patent package structure, 14 · If you apply for a patent package structure, and paste it to the open 15 · If you apply for a patent package structure, The thermal expansion coefficient of the fenestration type gasket in the fenestration type lead frame type semiconductor according to Item 9 is between the thermal expansion coefficient and the thermal expansion of the semiconductor wafer. In the fenestration lead frame semiconductor of the above-mentioned item 9, the fenestration type gasket is formed by an annular portion of a wafer holder of a thermally conductive adhesive layer. The thermally conductive adhesive layer of the window-opening lead frame type semiconductor according to Item 12 is a silver paste. In the fenestration type lead frame type semiconductor according to Item 9, the semiconductor wafer is formed by an annular portion of a heat conductive adhesive layer window spacer. The thermally conductive adhesive layer of the window-opening lead frame type semiconductor according to item 14 is a silver paste. In the fenestration type lead frame type semiconductor according to Item 9, the wire is a gold bonding wire. I - — III — — — ^ « — — — — — — I — (Please read the notes on the back and fill out this page) Printed by the Intellectual Property Office of the Ministry of Economic Affairs 11 1625811 16258
TW090110815A 2001-05-07 2001-05-07 Windowing lead-frame semiconductor package structure and fabrication process thereof TWI248176B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI496267B (en) * 2007-07-24 2015-08-11 Micron Technology Inc Semiconductor dies with recesses, associated leadframes, and associated systems and methods

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI496267B (en) * 2007-07-24 2015-08-11 Micron Technology Inc Semiconductor dies with recesses, associated leadframes, and associated systems and methods
US10074599B2 (en) 2007-07-24 2018-09-11 Micron Technology, Inc. Semiconductor dies with recesses, associated leadframes, and associated systems and methods

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