TWI247549B - Code tracking loop with automatic power normalization - Google Patents
Code tracking loop with automatic power normalization Download PDFInfo
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- TWI247549B TWI247549B TW091108597A TW91108597A TWI247549B TW I247549 B TWI247549 B TW I247549B TW 091108597 A TW091108597 A TW 091108597A TW 91108597 A TW91108597 A TW 91108597A TW I247549 B TWI247549 B TW I247549B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7085—Synchronisation aspects using a code tracking loop, e.g. a delay-locked loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/709—Correlator structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
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Description
1247549 五、發明說明(1) 碑多一種數碼追蹤系統,其係應用於-分 ==上1信系統之一接收裝置。特別是,本 ϋ 二階數碼追縱系、統,藉卩更有效率地移 除傳輸數碼及接收數碼間之時序差異。 同步在任何類型電信中均是一^ 门此a曰女 複數種等級,諸如:載子、頻;、;:工:號=;= 等級中’同步係可以區分為兩個階段, 亦即.取侍(啟始同步)及追蹤(精細同步)階段。 個i:i:ϊ i通信系統係由一基地台傳送下行鏈路至- 備(ue)、並由使用者設備⑽)傳送 收f置#刹 。、在此使用者設備(ue)内部之一接 路^ 乃,用板關,或解擴(despread),此接收下行鏈 已知數碼序列,藉以進行其工作。此序列必須 屮士垃^ 序列’#以由此相關裝置得到最大輸 商庫:?;裝置應該能夠在不中止操作的情況下,輕易ϊ =了 ^ #…線電線路改變之環境中之一變化。為達此目 蔣广节雜收褒置係盡可能收集較多之傳輸信號能量’藉以 r; :;:rR)最大化。然而,在多重路徑衰落通 定時間數量内路f及散射,此信號能量係在-特 之一決定性卫作i^、dtespread)。因此,本接收裝置 係具有與通道輪廊=通^改善其效能e° 接收裝置 法隨即係指派ϋ個之貞祝,則收集信號能篁之一種方 建設性地級合裝置分支於不同之回音路徑、並 口八勒出,亦即··已知^]^接收裝置之一結 12475491247549 V. INSTRUCTIONS (1) There is a digital tracking system, which is applied to the receiving device of the -1 = 1 upper system. In particular, the second-order digital tracking system and the system are used to more efficiently remove the timing differences between the transmission digital and the receiving digital. Synchronization in any type of telecommunications is a multi-level, such as: carrier, frequency;,;: work: number =; = level in the 'synchronization system can be divided into two stages, that is. Take the wait (start sync) and track (fine sync) stages. The i:i:ϊ i communication system is transmitted by a base station to the downlink (ue) and transmitted by the user equipment (10). One of the internal devices (ue) is connected, or despread, to receive a downlink known digital sequence for its operation. This sequence must have a gentleman's sequence '# to get the largest library of the relevant devices:? The device should be able to easily change one of the environments in which the line circuit changes without interrupting the operation. In order to achieve this goal, Jiang Guangjie's miscellaneous collection system collects as much as possible of the transmitted signal energy 'by r; :;:rR). However, in the case of multiple paths fading for a certain amount of time, the path f and the scatter, this signal energy is in the deterministic guardian i^, dtespread). Therefore, the receiving device has the same function as the channel corridor=improving the performance e° receiving device method, and then collecting the signal capable of constructing the cascading device to branch to different echoes. The path and the parallel port are eight, which is known as ^^^ one of the receiving devices 1247549
此RAKE接收裝置係具有複數個手指,每— 於每-個回音路徑,並且,在每一個手指::指對應 參考延遲(諸如:一直接或最早接收路徑)之此政於邙为 必,在整體傳輸中加以估算及追蹤。路徑啟始位J控延, 估算係可以利用-多重路徑搜尋演算法以得到 == 徑搜尋演算法係經由相關裝置以進行一延伸,二 用一晶片精確度設置此等路徑。待找到這些啟始位^ = 1 此等追蹤單元係利用早期延遲時序誤差偵測裝置之手^, 藉以產生複數個多重路徑元件之延遲之精確估算、並^用 這些不,延遲之估算,藉以平移此等數碼之相位。此^型 之追縱單元係已知為一早期延遲閘門同步裝置。一延遲鎖 定迴路(DLL )係經常用以實施此早期延遲閘門同步裝 置。在第一圖中所介紹的係此延遲鎖定迴路(DLL )之一 方塊圖。此數碼追縱迴路(C T L )之頻寬係決定此同步裝 置之雜訊慮波能力。若頻寬愈窄,則此同步裝置對於雜訊 變形之耐用性愈高、且對於微小信號變化之靈敏度愈低。 此迴路之頻寬係取決於此迴路濾波裝置之參數(a、b )、 整體迴路增益(KT)、以及輸入信號功率位準(Pin)。 此迴路之阻尼比亦取決於相同參數。此迴路之阻尼比係決 定此迴路之穩定性。雖然此迴路之參數係可以固定,但想 要固定輪入信號位準卻是非常困難的。 大部分不連續接收裝置係於其物理層中應用部分形式 之自動增益控制(AGC )。雖然自動增益控制(AGC )會限The RAKE receiving device has a plurality of fingers, each for each echo path, and each finger:: refers to a corresponding reference delay (such as: a direct or earliest receiving path). Estimate and track the overall transmission. The path start bit J is controlled, and the estimation system can use the multi-path search algorithm to obtain the == track search algorithm via the associated device for an extension, and the path is set with a wafer precision. To find these start bits ^ = 1 These tracking units use the hand of the early delay timing error detection device to generate an accurate estimate of the delay of the complex multipath components and use these estimates of delays. Pan the phase of these digits. This type of tracking unit is known as an early delay gate synchronization device. A delay locked loop (DLL) is often used to implement this early delay gate synchronization device. The block diagram of this delay locked loop (DLL) is described in the first figure. The bandwidth of this digital tracking circuit (C T L ) determines the noise filtering capability of this synchronous device. The narrower the bandwidth, the higher the durability of the synchronizing device for noise distortion and the lower the sensitivity to small signal changes. The bandwidth of this loop depends on the parameters of the loop filter (a, b), the overall loop gain (KT), and the input signal power level (Pin). The damping ratio of this loop also depends on the same parameters. The damping ratio of this loop determines the stability of this loop. Although the parameters of this loop can be fixed, it is very difficult to fix the rounded signal level. Most discontinuous receiving devices are part of the automatic gain control (AGC) in their physical layer. Although automatic gain control (AGC) limits
第7頁 1247549 五、發明說明(3) 制輸入信號位準,但此信號位準之動態位準仍然是寬廣 的。這是由於自動增益控制(AGC )係實際設計以避免類 比不連續轉換裝置(ADC )進入飽和狀態之事實。 由於此輸入信號位準之動態範圍並未有效率地限制, 因此此數碼追蹤迴路之頻寬及阻尼比會隨著輸入信號功率 而改變。這將導致此數碼追蹤迴路之效能退化。 因此,對一數碼追蹤迴路而言,將會存有一需求以維 持此迴路之頻寬及阻尼比’不論輸入信號功率位準如何蠻 化0 本發明之 實施例後,變 本發明係 裝置,其包括 (CDMA )通信 基地台。此使 信、並經由此 通信信號係利 相關,其係估 迴路係包括: 信號;以及一 生時序信號版 蹤迴路中,係 碼參考信號。 一自動功率正 其他目的及優點係可以在讀完本發明之較佳 得更加明瞭。 一分碼多重存取(CDMA )通信系統之一接收 於一使用者設備(UE )中,此分碼多重存取 系統係包括:此使用者設備(UE )及複數個 用者設備(UE )係與此等基地台之一進行通 接收裝置而自此基地台接收一通信信號。此 用一延遲鎖定數碼追蹤迴路而以此接收裝置 算及追縱此通信信號之一通道延遲。此追蹤 一參考數碼產生裝置,藉以產生一參考數碼 内插裝罝,藉以因應此通信信號之接收而產 本。一時序信號相關裝置,其亦包括於此追 用以相關至少兩個此等時序信號版本及此數 此相關步驟之結果係用以產生一誤差信號。 規化迴路(APN),其因應於此内插裝置,Page 7 1247549 V. INSTRUCTIONS (3) The input signal level is determined, but the dynamic level of this signal level is still broad. This is due to the fact that Automatic Gain Control (AGC) is actually designed to avoid the fact that the analog discontinuous converter (ADC) is saturated. Since the dynamic range of this input signal level is not effectively limited, the bandwidth and damping ratio of this digital tracking loop will vary with the input signal power. This will result in degradation of the performance of this digital tracking loop. Therefore, for a digital tracking loop, there will be a need to maintain the bandwidth and damping ratio of the loop, regardless of the input signal power level. Includes (CDMA) communication base stations. The signal is and is related to the communication signal, and the evaluation loop includes: a signal; and a code reference signal in the lifetime timing signal trace loop. An automatic power source and other objects and advantages will be more apparent from the reading of the present invention. One of the code division multiple access (CDMA) communication systems is received in a user equipment (UE), the code division multiple access system includes: the user equipment (UE) and a plurality of user equipments (UE) And receiving a communication signal from one of the base stations and receiving a communication signal from the base station. This delays the digital tracking loop with a delay and the receiving device counts and tracks the channel delay of the communication signal. This tracking is a reference digital generating device for generating a reference digital interpolation device for the purpose of receiving the communication signal. A timing signal correlation apparatus is further included herein for tracking the at least two versions of the timing signals and the result of the correlation step for generating an error signal. Normalized loop (APN), which is adapted to this interpolation device,
第8頁 !247549 五、發明說明(4) 係產♦ — JL + '^ 王一功率誤差信號,藉以 差信號正規化。 、、一正規化電路而將此誤 【圖式之簡單說明】 ^二係一習知延遲鎖定追蹤迴路之—方塊圖 h弟一圖係根據本發明具有 方塊圖。 疋數碼追蹤迴路之一方塊圖。 力率正規化之一延遲鎖 =三圖係本發明延遲鎖定數 々第四圖係包括於本發明延遲雜〜路之—流程圖。 旄例迴路濾波裝置之一方塊圖。、疋數碼追蹤迴路中之一 【較佳實施例之詳細說明】 梦你t車父佳實施例係參考圖式而加以說明,文Φ… 儿係用以表示類似元件。 中’類似編 ^第二圖中所介紹的係根據本發明較佳 數碼追蹤迴路(DCTL )1〇之一方换园、包例之延遲鎖定 蹤迴路UCTL”。係包括:一=:署5延遲鎖定數瑪追 尼裝置12a、12b,兩個平方裝置"二13:,:個整合及阻 14、-迴路濾波裝置15、一數碼產生裝 f規化裝置 17、-限制裝置18、一量化裝置19、二b電:累加裝置 一自動功率正規化迴路(APN ) 2〇。 曰里電路9、以及 (DCTL) 10##^ 1 此延遲鎖定數碼追蹤 、峪係接收一輸入信號χ(ΐ — 此接收信號中之時序誤差。由於此時 ’ /、中,T係 至Tc,其中,Tc係利用多重路徑搜尋演算法期Τ, 平移此進入信號之唯一方法係利用數 3 " 内插裝置η,其搞合至此等整合裝^子2内插9法。因此,此 哥玄。展置I2a、12b、此數碼產Page 8 !247549 V. Invention Description (4) System ♦ — JL + '^ Wang Yi power error signal, whereby the difference signal is normalized. , a normalized circuit and this error [simple description of the schema] ^ two systems a conventional delay lock tracking loop - block diagram h brother a map according to the invention has a block diagram.方块 A block diagram of the digital tracking loop. One of the delay ratios of the force rate normalization = three graphs is the delay lock number of the present invention. The fourth graph is included in the flow chart of the delay heterocycle of the present invention. A block diagram of a loop filter device. One of the digital tracking circuits. [Detailed Description of the Preferred Embodiments] The dream embodiment is described with reference to the drawings, which are used to indicate similar components. According to the second digital diagram of the present invention, the preferred digital tracking loop (DCTL) is replaced by a one-way switch, and the delay-locked loop UCTL of the package example includes: one =: department 5 delay Locking the imaginary device 12a, 12b, two squaring devices "two 13:,: integration and resistance 14, loop filter device 15, a digital production device, a device 18, a quantization device Device 19, 2b power: Accumulator device-automatic power normalization loop (APN) 2〇. 曰里电路9, and (DCTL) 10##^ 1 This delay-locked digital tracking, 峪 receives an input signal χ (ΐ – the timing error in this received signal. Since '/, medium, T is to Tc, where Tc uses the multipath search algorithm, the only way to translate this incoming signal is to use the number 3 " interpolation The device η, which fits into the integrated device 2 interpolation 9 method. Therefore, this brother Xuan. I2a, 12b, this digital product
第9頁 1247549 五、發明說明(5) 及此自動功率正規化迴路⑽)2°,係接收 及ΐ遲τ)並產生三個輸出:精確、早期、以 別係此熟f此技藝者所熟知,此等早期及延遲輸出分 信號X (t-Τ)之一對半晶片早期版本及一對 之1曰奸’月版本。此等版本係利用此進入信號X ( t -τ ) 於山Ϊ以得到。待此内插裝置1 1後,下取樣係發生,三個 用此傳輸信號之一上取樣比以進行下取樣。 期及碼追蹤迴路(DCTL) 10之精確輸出、此等早 'Y f輸出係僅用於此數碼追蹤迴路1 0之演算法内部。 A等早期及延遲信號係分別利用此等整合裝置1 2a、 W,在此延遲鎖定數碼追蹤迴路(dctl) ι〇之下分支及 =^中與此參考數碼產生裝置16 (諸如:一導引數碼產 與^等早^輸出相關。—旦相關此數碼產生裝置16之輸出 二 早期及延遲輸出後,此等相關信號係分別轉送至平 :裝置Ua、13b。由於本階段並不需要相位同步,平方: 以取传非同調數碼追縱迴路(C T L )。 孫田待:關及平方後,此兩個分支(早期及延遲)之差異 、-、 生誤差仏號e (t ),其係正比於此時序誤差。 ,誤差信號e (t )隨即係利用此正規化電路14 (其進一 I t明如後)以針對一功率誤差信號(Pe)進行功率正規少 化、並輸出至此迴路濾波襞置i 5。 此迴路濾波裝置15,其耦合於此正規化電路14及此累 力裝置1 7,係濾波此正規化誤差信號e (七)、並將其轉^ 至此累加装置1 7。一範例迴路濾波裝置係一傳統正比積分Page 9 1247549 V. Description of the invention (5) and this automatic power normalization loop (10)) 2°, receiving and delaying τ) and generating three outputs: accurate, early, and other skill It is well known that one of these early and delayed output sub-signals X (t-Τ) is an early version of the semi-chip and a pair of ones. These versions use this incoming signal X ( t -τ ) to obtain the haw. After the interpolation device 1 1 is selected, a downsampling system occurs, and three of the transmission signals are upsampled to perform downsampling. The accurate output of the period and code tracking loop (DCTL) 10, these early 'Y f outputs are only used inside the algorithm of this digital tracking loop 10 . The early and delayed signals of A and the like respectively utilize the integrated devices 1 2a, W, and here the delay-locked digital tracking loop (dctl) 分支 branch and the ^^ with the reference digital generating device 16 (such as: a guide The digital production is related to the output of ^, etc.. After the output of the digital generating device 16 is early and delayed, the relevant signals are respectively transferred to the flat: devices Ua, 13b. Since phase synchronization is not required at this stage. , square: to pass the non-coherent digital tracking circuit (CTL). Sun Tianwait: After closing and square, the difference between the two branches (early and delayed), -, the error 仏 e e (t), which is proportional In this timing error, the error signal e(t) is then used by the normalization circuit 14 (which is as follows) to perform power normalization for a power error signal (Pe) and output to the loop filter. The loop filter device 15 is coupled to the normalization circuit 14 and the force device 17 to filter the normalized error signal e (seven) and transfer it to the accumulator device 17. Example loop filter device is a tradition Than integration
第10頁 1247549 五、發明說明(6) 裝置(pi)濟油 用於本發明:此2 μ接t任何一階低通濾波裝置亦可以適 迴路濾波裝置累加裝置41 i 慮波裝置’其包括- 示。其中,一八± γ * 係具有兩個分支,如第四圖所 之-控制信號,另!分2 2 :差信號之目前數值成正比 成正比之一俨萝、二 產生與此誤差信號之平均數值 )後加以組:Γ在=在乘上兩個不同常數“及b 累加裝置41與下文$明之2裝置(PI )滤波裝置内部之 進行。 文成明之累加裝置Π係以完全相同之方法 此累加裝置1 7,I叙人5 似“ 路濾波裝置15之減波誤增盈電路9,係接收此迴 藝者當瞭解,心加裝U僅並處理ί信號。熟習此技 輸出。啟始時,此累^將其目前輸入加至其先前 加裝置内部係具有!溢::之;出係設定為*。在此累 到二作:;\迴=波裝置⑽-起用來得 號…)至此增益;路9。累加裝置17隨即係轉送此誤差信 此增益電路9,复耦人$ a田 ^ 電路18,係接收此累加。累加裝置17及一限制裝置 之位準以匹配^ 、並調整此遽波信號 變此時序大氣信號中時;平移數值。這個電路係改 此增LI:-,序延遲,領先。-旦完成此步驟, 糸轉4此调整誤差信號e (t )至一限制f置 、路18 ’其係在此誤差信號之過衝(。·*。"超過此Page 10 1247549 V. INSTRUCTIONS (6) Device (pi) liquefied oil is used in the present invention: this 2 μ-th any first-order low-pass filter device can also be adapted to the loop filter device accumulating device 41 i wave device 其- Show. Among them, one eight ± γ * has two branches, as shown in the fourth figure - control signal, another! Divided into 2 2: the current value of the difference signal is proportional to the proportional value of one of the diploids, and the average value of the error signal is added to the group: Γ at = multiplied by two different constants "and b accumulator 41 and below The internal device of the Ming 2 device (PI) filter device is carried out. The accumulating device of Wen Chengming is the same method. The accumulating device is the same as the subtractive wave error-increasing circuit 9 of the road filter device 15 When receiving this essayist, understand that the heart is installed with U and only processes the ί signal. Familiar with this skill output. At the beginning, this tidy ^ adds its current input to its previous device internals! Overflow::; the line is set to *. Here, two are involved:;\back=wave device (10)- is used to get the number...) to this gain; The accumulator 17 then forwards the error signal. This gain circuit 9, the multi-coupler $a field ^ circuit 18, receives this accumulation. The level of the accumulator 17 and a limiting device are matched to match and the chopping signal is adjusted to change into the atmospheric signal of the timing; This circuit is changed by LI:-, sequence delay, leading. Once this step is completed, the adjustment error signal e (t ) is adjusted to a limit f, and the path 18' is overshooted by the error signal (.·*."
麵 IIHI 第11頁 五、發明說明(7) 晶片周期(—m)時 (overshoot )。此限制 棘制此^差信號之過衝 化裝置1 9,其中,+ μ置/係轉送此誤差信號至此量 回到此内插裝置u。在這連續數值係取轉送 置係用以取得Tc /16之— 固二十二階量化裝 置亦可以廡田 、月 又。雖然任何等級之量化妒 置兀:以應用於不同等級之延之里化裝 路。在控制系統標記中,3=^係:個,階回授迴 H (s ),係可以表示為: 白又;之系統函數, H (s ) = (2 f Wns + ω,)/ ( 2 + 2 等式(1 ) ^ +2 ^ ^ns + ωη2 ) 其中,芕係阻尼比(damping rati〇 )、 自然頻率。這些係數係可以利用此 1係此糸統之 (DCTL)之參數表示,如下列所示^遲鎖疋數褐追蹤迴路 等式(2 ) 等式(3 ) Kt =¾](係整體迴路 、且P1 η係輸入信號 等式(4 ) ωη = ( 2 (Pin ) 1/% 石)1/2 f = (KT a (Pin ) 1/2 ) / ωη 其中,α及/3係此迴路濾波裝置參數、 增盈’其包括:S曲線增益及外部增益 功率。 此系統之雙邊雜訊頻寬係表示為: wl = ωη ( ξ +1 /Α ξ ) 舉例來說,具有3·84ΜΗζ之一晶片速率及兩倍J 通用行動電信系統(UMTS)分頻雙工(FDD)使 ^ (UE )接收器設計係使用下列數值:導引| 用者5又備 守引數螞之擴充因子 五、發明說明(8) 256、迴路增益Κ=〇·〇1、j =0.0141、及点=〇 自然頻率之數值及阻尼比(damping rat i〇 )係決定此迴 路之主要特徵,諸如:穩定性、增益及相位邊界、頻寬 收歛時間、及穩態跳動。這些特徵在設計期間係固定的1 且不應該因為輸入而改變。否則,此延遲鎖定數碼追縱回 路(DCTL)可能會失靈(malfunction)、並產生非預其< 結果。然而,如等式(2) 、 (3) 、 (4)所見,這些^ 徵係取決於輸入信號功率,pin,其可能會在通信處理期、 相當程度地改變。 / θΊ 為克服此輸入信號X ( t — T )功率位準變化之效康, 一自動功率正規化迴路(APN) 20係包括在本發明遲 鎖定追蹤迴路10中。此自動功率正規化迴路(ΑΡΝ)2〇, 其耦合至此内插裝置11,係包括:一整合及阻尼電路21、 一平方裝置22、一加法裝置24、以及一移動平均(ΜΑ)濾 波裝置23。此内插裝置1丨之精確輪出係此自動功率正規= 迴路(ΑΡΝ ) 2 0之輸入。此精確信號係隨著此數碼產生裝 置16之信號,由此整合及阻尼電路21接收。此整合及\ $路21係耦合至此數碼產生裝置16、此内插裝置u、以及 $平方裝置22。類似於先前揭露之整合及阻尼電路i2a、 整合及阻尼電路2 1係相關由此内插裝置1 1所接收 =確信號及由此參考數碼產生裳置16所接收之信號。一 號;==以相關,此整合電路21係轉送此相關信 现主此平方裳置2 2。 此平方裝置22 ’其耦合至此整合電路21及此加法裝置Face IIHI Page 11 V. Invention Description (7) Chip cycle (-m) (overshoot). This limitation is an overshooting device 1 that counters this difference signal, wherein + μ sets/transmits the error signal to this amount back to the interpolation device u. In this continuous value, the transfer system is used to obtain Tc / 16 - the solid twenty-second quantization device can also be used for Putian and Yue. Although any level of quantification is placed: it is applied to different grades of extensions. In the control system tag, 3=^ is: one, and the order is returned to H (s), which can be expressed as: white and; the system function, H (s ) = (2 f Wns + ω,) / ( 2 + 2 Equation (1) ^ +2 ^ ^ns + ωη2 ) where, the damping ratio (damping rati〇), natural frequency. These coefficients can be expressed using the parameters of this system (DCTL), as shown below. ^ Late lock number brown tracking loop equation (2) Equation (3) Kt = 3⁄4] (integral loop, And P1 η is the input signal equation (4) ωη = ( 2 (Pin ) 1/% stone) 1/2 f = (KT a (Pin ) 1/2 ) / ωη where α and /3 are the loop filtering Device parameters, gains' include: S-curve gain and external gain power. The bilateral noise bandwidth of this system is expressed as: wl = ωη ( ξ +1 /Α ξ ) For example, one of 3·84ΜΗζ The chip rate and twice the J General Service Telecommunications System (UMTS) Frequency Division Duplex (FDD) enable the (UE) receiver design system to use the following values: Guide | User 5 and the Array of Expansion Factor V. DESCRIPTION OF THE INVENTION (8) 256, loop gain Κ=〇·〇1, j=0.0141, and point=〇 natural frequency value and damping ratio (damping rat i〇) determine the main characteristics of this loop, such as: stability, Gain and phase boundaries, bandwidth convergence time, and steady-state jitter. These features are fixed during design and should not change due to input. This delay-locked digital tracking loop (DCTL) may malfunction and produce non-previous results. However, as seen in equations (2), (3), and (4), these ^ decisions depend on In the input signal power, pin, which may change considerably during the communication processing period. / θΊ To overcome the effect of this input signal X ( t — T ) power level change, an automatic power normalization loop (APN) The 20 series is included in the late lock tracking loop 10 of the present invention. The automatic power normalization loop (〇) is coupled to the interpolation device 11 and includes an integration and damping circuit 21, a squaring device 22, and an addition. Apparatus 24, and a moving average (ΜΑ) filtering means 23. The precise rounding of the interpolating means 1 is the input of the automatic power normal = loop (ΑΡΝ) 20. The precise signal is associated with the digital generating means 16 The signal is received by the integration and damper circuit 21. The integration and circuitry 21 is coupled to the digital generation device 16, the interpolation device u, and the squaring device 22. Similar to the previously disclosed integration and damper circuit i2a, Integration The damper circuit 2 1 is related to the signal received by the interpolation device 1 1 and the signal received by the reference numeral 13 is generated. The number 1 === is related, and the integrated circuit 21 transfers the related signal The squaring device 22' is coupled to the integrated circuit 21 and the adding device.
五、發明說明(9) 24,係將此相關信號平方、並轉并 置24。此加法裝置24係由一表 千方#號至此加法裝 平方裝置22之平方輸出,二號功率(P)令減去此 數值,且俜肩用μ ΐ 此參考信號功率(Ρ )係一預钟 設定參數。如熟習此技藝者所(m設計中以 )可以是任何預定數值。利用此加法準(p 號會導致一功率差異信號,並^,24減去此平方信 濾波裝置23。 八系轉送至此移動平均(MA) 均(MA)濾波裝置23,其麵合至此加法穿置 24及此正規化電路14,係接收此差異 _ ^置 J。此移動平均(M)攄波裝置23係。、慮 實數暫存裝置、一加法裝置、以及具有一因之一: 數乘法裝置。每當一新輪入值、笨$ 吊 裝置23時,此暫存』移動平均(MA)濾波 町此晋孖裝置兀件係向右平移一個元件。最 達凡件(在最右侧)係加以清除、而目前輸入數目則放 於此暫存裝置之最左侧位置。待此平移動作後,此暫存裝 置中之每個元件係予以相加。整體數值係乘以丨/Ν以產生 此功率誤差信號(Pe)之平均數值。在部分實施例中,數 值N最好是選定為二十,其對應於二十個處理符號。此移 動平均(MA )濾波裝置之大小係加以選定,藉以使其能夠 不靈敏於哀落引起之即時功率變化、然而卻能夠補償平均 輪入信號位準變化。一旦此移動平均(MA)濾波裝置23對 此功率差異信號進行濾波,一濾波功率誤差信號以係轉送 至此正規化電路14。 1247549 五、發明說明(10)5. Inventive Note (9) 24, the relevant signals are squared and rotated to 24 . The adding device 24 is outputted by a square of the square meter # to the square of the adding square device 22. The power of the second power (P) is subtracted from this value, and the power of the reference signal is used for the reference signal power (Ρ). Clock set parameters. Anyone skilled in the art (m design) can be any predetermined value. Using this addition (p number will result in a power difference signal, and ^, 24 minus the square signal filtering means 23. The octave is forwarded to this moving average (MA) average (MA) filtering means 23, which is integrated to this addition The 24 and the normalization circuit 14 receive the difference _ ^ J. The moving average (M) chopper device 23, the real number temporary storage device, an adding device, and one of the factors: number multiplication Whenever a new round-in value, stupid $ hang device 23, this temporary storage moving average (MA) filter 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 平移 平移 平移 平移) is cleared, and the current input number is placed at the leftmost position of the temporary storage device. After this translation, each component in the temporary storage device is added. The overall value is multiplied by 丨/Ν To generate an average value of the power error signal (Pe). In some embodiments, the value N is preferably chosen to be twenty, which corresponds to twenty processing symbols. The size of the moving average (MA) filtering device is Selected so that it can be insensitive to sorrow The instantaneous power variation, however, is capable of compensating for the average wheeling signal level change. Once the moving average (MA) filtering device 23 filters the power difference signal, a filtered power error signal is forwarded to the normalizing circuit 14. 1247549 , invention description (10)
If規化電路14,其搞合至此平方裝置133、13b及此 自U正規化迴路(APN)2G,係接收此誤差信號e (t 應於此内插裝置"之延遲及早期輸出及此自動功 路⑽)20之功率誤差信號peFe1之差異。為 誤差信號⑽將此誤差信號e⑴正規化,此 正規化電路14係將此誤差信號e (t )乘以(p) / (p+pe )务It/係在此自動功率正規化迴路(APN )20中使用 之參考彳§號功率位準。 此=信t (而非輸入信號)之正規化會導致一減少 Ϊ Ϊ =正規化),其減少之一因子係等於此擴充因 :丄在杈佳實施例中,一限制裝£ (圖中未示)最小能夠 二:至此正規化電路中’藉以將此乘法因子限制於〇.(至 1 0或一 20dB至2 0dB。此限制梦署怂田 取刺展置係用以避免雜訊放大。 第二圖係"、、、口根據本發明較佳實施例之 追蹤迴路之流程圖。一輸入信號係利 ⑽”。接收(步。此延遲鎖定迴二疋二 ,内插裝置"係產生延遲、早期、精確輸出(步驟302 )二此等延遲及早期輸出係利用此數碼產生裝置Μ相關 ^ t驟303a) 1 i此等相關信號間之差異係加以決定,進 產生-誤差We(t)(步驟3〇4〇。㈤步於此等延遲 係利用此數碼產生裝置相關 即係加以濾波,藉以產生一功率準差二:差異仏號& 力早位率誤差信號Pe (步驟 第15頁 1247549 五、發明說明(π) 3 0 5b )。對應於此等延遲及早期輸出之誤差信號係針對此 自動功率正規化迴路(APN) 20之功率位準誤差信號Pe加 以正規化(步驟3 0 6 )。此正規化誤差信號隨即係加以處 理、並產生一延遲估算(步驟3 0 7 ),其係轉送回到此延 遲鎖定迴路(DLL)追蹤迴路10之輸入(步驟308 )。 雖然本發明已利用較佳實施例說明如上,然而,本發 明範圍内之各種變動,其列於申請專利範圍中,亦應為熟 習此技藝者所瞭解。If the normalization circuit 14, which is coupled to the squaring devices 133, 13b and the U normalization loop (APN) 2G, receives the error signal e (t should be delayed and early output of the interpolation device " The difference of the power error signal peFe1 of the automatic power path (10))20. The error signal e(1) is normalized for the error signal (10), and the normalization circuit 14 multiplies the error signal e(t) by (p) / (p+pe) It is the automatic power normalization loop (APN) The reference used in 20 is the power level of §§. This = normalization of the letter t (rather than the input signal) will result in a reduction Ϊ Ϊ = normalization), one of which is equal to this expansion factor: 杈 In the preferred embodiment, a limit is installed (in the figure) Not shown) Minimum can be two: So far in the normalization circuit, 'by which this multiplication factor is limited to 〇. (to 10 or 20dB to 20dB. This limit is used by the Dream Department to avoid the noise amplification.) The second diagram is a flow chart of a tracking loop according to a preferred embodiment of the present invention. An input signal is (10)". Receiving (step. This delay is locked back to second, interpolating device " Delay, early, accurate output (step 302), two such delays, and early output use of the digital generation device, correlation 303a) 1 i, the difference between these related signals is determined, and the error is generated. (t) (Step 3〇4〇. (5) Steps such delays are filtered using the digital generation device correlation to generate a power quasi-two: difference apostrophe & force early bit rate error signal Pe (step Page 15 1247549 V. Description of invention (π) 3 0 5b ). Correspondence The error signals of the delays and early outputs are normalized for the power level error signal Pe of the automatic power normalization loop (APN) 20 (step 306). The normalized error signal is then processed and A delay estimate is generated (step 307) which is forwarded back to the input of the delay locked loop (DLL) tracking loop 10 (step 308). Although the invention has been described above using the preferred embodiment, the scope of the invention The various changes therein are listed in the scope of the patent application and should be understood by those skilled in the art.
第16頁 Ϊ247549 圖式簡單說明 ί 一圖係—習知延遲鎖定追蹤迴路^ ^^ =圖係根據本發明具有 方塊圖。 數:追蹤迴路之一方塊圖。力车正規化之一延遲鎖 二圖係本發明延遲鎖定數碼追蹤回 範合丨、四圖係包括於本發明延遲鎖定數=、έ之—流程圈。 1迴路ϋ波裝置之—方塊圖。〜數媽追蹤迴路中之— 70件符號說明 9 :增益電路 k遲鎖疋數碼追縱迴路(DCtl) 1 1 :内插裝置 12a 12b、21 :整合及阻尼裝置 13a、13b、22 :平方裝置 1 4 :正規化裝置 1 5 :迴路濾波裝置 1 6 :數碼產生裝置 17 :累加裝置 1 8 :限制裝置 1 9 :量化裝置 2〇 ·自動功率正規化迴路(apn) 41 :迴路濾波裝置累加裝置 23 :移動平均(MA )濾波裝置 9 A :加法裝置 麵 第17頁Page 16 Ϊ247549 Schematic description of the diagram ί A diagram--a conventional delay-locked tracking loop ^^^=The diagram has a block diagram in accordance with the present invention. Number: A block diagram of the tracking loop. One of the delay locks of the normalization of the vehicle is the delay lock digital tracking method of the present invention, and the four pictures are included in the delay lock number of the present invention. 1 block chopper device - block diagram. ~ Number of mothers in the tracking loop - 70 symbols Description 9: Gain circuit k late lock 疋 digital tracking circuit (DCtl) 1 1 : Interpolation device 12a 12b, 21: integration and damping device 13a, 13b, 22: square device 1 4 : normalization device 1 5 : loop filter device 1 6 : digital generation device 17 : accumulation device 1 8 : restriction device 1 9 : quantization device 2 自动 · automatic power normalization circuit (apn) 41 : circuit filter device accumulation device 23: Moving average (MA) filter device 9 A: Adding device face第17页
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US32630801P | 2001-10-01 | 2001-10-01 | |
US10/034,867 US6456648B1 (en) | 2001-10-01 | 2001-12-27 | Code tracking loop with automatic power normalization |
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TW096107299A TW200805909A (en) | 2001-10-01 | 2002-04-25 | Code tracking loop with automatic power normalization |
TW092127573A TWI279094B (en) | 2001-10-01 | 2002-04-25 | Code tracking loop with automatic power normalization |
TW091108597A TWI247549B (en) | 2001-10-01 | 2002-04-25 | Code tracking loop with automatic power normalization |
TW094134743A TWI306700B (en) | 2001-10-01 | 2002-04-25 | Code tracking loop with automatic power normalization |
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TW098102138A TWI381660B (en) | 2001-10-01 | 2002-04-25 | Code tracking loop with automatic power normalization |
TW096107299A TW200805909A (en) | 2001-10-01 | 2002-04-25 | Code tracking loop with automatic power normalization |
TW092127573A TWI279094B (en) | 2001-10-01 | 2002-04-25 | Code tracking loop with automatic power normalization |
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US (5) | US6456648B1 (en) |
EP (2) | EP2056485A1 (en) |
JP (2) | JP4035108B2 (en) |
CN (1) | CN1561582B (en) |
AT (2) | ATE423409T1 (en) |
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DE (2) | DE60231260D1 (en) |
DK (1) | DK1433266T3 (en) |
ES (1) | ES2250650T3 (en) |
MX (1) | MXPA04003019A (en) |
NO (1) | NO20041632L (en) |
TW (5) | TWI381660B (en) |
WO (1) | WO2003030389A1 (en) |
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