TWI247369B - Forming method of conductive bump - Google Patents

Forming method of conductive bump Download PDF

Info

Publication number
TWI247369B
TWI247369B TW089116304A TW89116304A TWI247369B TW I247369 B TWI247369 B TW I247369B TW 089116304 A TW089116304 A TW 089116304A TW 89116304 A TW89116304 A TW 89116304A TW I247369 B TWI247369 B TW I247369B
Authority
TW
Taiwan
Prior art keywords
layer
copper
forming
photoresist pattern
solder paste
Prior art date
Application number
TW089116304A
Other languages
Chinese (zh)
Inventor
Kuo-Wei Lin
Yen-Ming Chen
Fu-Jier Fan
Jeng-Yu Ju
Chiou-Shian Peng
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Priority to TW089116304A priority Critical patent/TWI247369B/en
Application granted granted Critical
Publication of TWI247369B publication Critical patent/TWI247369B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

This invention relates to a forming method of conductive bump, which includes steps of depositing a passivation layer upon a metal pad; further etching the passivation layer to expose the metal pad; then depositing a barrier layer and a copper seed layer in favor of the electroplating of copper material upon the etched passivation layer and the exposed metal pad; using a lithographic process to form a photoresist pattern with aperture upon the copper seed layer; using electroplating process to form copper upon the copper seed layer again forming a nickel layer by electroplating process upon the electroplated copper layer surface; painting solder paste upon the photoresist pattern; next using a scraper to move the solder paste into aperture of the photoresist pattern; removing photoresist pattern to form solder bumps; using the solder bumps as etch mask to etch the exposed nickel layer and the electroplated copper layer; and using heat-flow treatment, to complete a solder ball structure by forming the solder bumps as a spherical structure.

Description

1247369 五、發明說明（1) 發明領域： 本發明與一種積體電路製程有關，特別是有關於一種 應用於形成導電凸塊之製程（bumping process)。 發明背景·· 在極大型積體電路（ULSI)趨勢中，半導體元件的尺寸 不斷地縮小，用以不斷地提昇晶圓上元件之積集度。隨著 電子元件尺寸的縮小化後，在積體電路的製造過程上出現 許多新挑戰。此外，由於電腦以及通訊技術之蓬勃發展， 伴隨需要的是更多不同種類與應用之電子元件。例如，由 語音操作之電腦界面或其他通訊之界面均需要許多义記憶 元件以及不同類型之半導體元件。是敌，積體電路之趨勢 仍然會朝向南積集度發展。然而，近幾年來高密度半導體 元件發展階段早已進入次微米（s u b m i c r ο η)之技術範 圍0 此外’隨著半導體技術之快速演進，電子產品在輕薄 短小、多功能速度快之趨勢的推動下，丨[半導體的〗/0數 目不但越來越多密度亦越來越高，使得封裝元件的引腳數 亦隨之越來越多，速度的要求亦越來越快，導致元件耗功 率越來越大，所以增進封裝之散熱效果，則日趨重要。目 前，封裝也越做越小以符合目前之趨勢，而高數量1/〇之 封裝也伴隨覆晶封裝技術（flip chip techn〇1〇gy)之發展 而有所突破，覆晶封裝技術的特點是，負責1/0的引腳為1247369 V. INSTRUCTIONS (1) Field of the Invention: The present invention relates to an integrated circuit process, and more particularly to a bumping process for forming conductive bumps. BACKGROUND OF THE INVENTION In the trend of the Maximal Integrated Circuit (ULSI), the size of semiconductor components is continually being reduced to continuously increase the integration of components on the wafer. As the size of electronic components has shrunk, many new challenges have arisen in the fabrication of integrated circuits. In addition, due to the booming of computers and communication technologies, there are more electronic components of different kinds and applications. For example, a computer interface operated by voice or other communication interface requires many memory components and different types of semiconductor components. It is an enemy, and the trend of integrated circuits will still develop toward the south. However, in recent years, the development stage of high-density semiconductor components has already entered the submicron (submicr ο η) technology range. In addition, with the rapid evolution of semiconductor technology, electronic products are driven by the trend of thin, short, and versatile.丨[Semiconductor ** / 0 number not only more and more density is getting higher and higher, so that the number of pins of the package components is also more and more, the speed requirements are getting faster and faster, resulting in component power consumption The larger, the more important it is to improve the heat dissipation of the package. At present, the package is getting smaller and smaller to meet the current trend, and the high-volume 1/〇 package is also accompanied by the development of flip chip technology (flip chip techn〇1〇gy), the characteristics of flip chip packaging technology Yes, the pin responsible for 1/0 is

1247369 五、發明說明（2) Ϊ狀ί:?架ί裝元件之細長引腳距離短且不易受損變 及未來數位系統速度的需求。 又嵌了符。目哥 參閱圖六，其為對導電凸塊製作工 前之錫球成分中句冬s 4 y r t努之預眉J，目 Μ Μ K ^ L· ^ 某例之鉛成分。基於環境保護侔# 越趨厫謹，無鉛成分之製程將越來重 ：條件 液组成為丘3去人曰 錫球組成屬於高含鉛成分及固離、、容 展·，且成為共嘁合晶（e u t e c 士 ， …各 季之前將達到盔鉛含量搠、、Ό 在么兀2 003年第四 > Μ荽拄μ山Γ 之趨勢。此外其球體間距（pi tch、 也隨者時間由2 00 0年第四季2f)請* 、Pi tch) 前將為150微米。且二/ 降㈣2 0 03年$四季之 ^ d, ^ ^ ^ 輸出輸入數目也將提升到1 ο 〇 〇以μ 而先刖技術將面臨無鉛球體製 j 1 0 0 0以上。 目為重要課題。 及較回輸出輸入數 中姑^ t卜’覆晶封裝乂 f 1 ip ch i P )為新—代之封驻4i 此技術疋利用導體凸槐 封裝技術， 凸塊的製程中，通常在:：：；塾m成導㈣ 組合層於其上，一般沈積阻障層與導電層之 田Μ 5/也丨 又的組成包含c r / c U、τ彳/ r】， 用微衫製程塗佈光阻且形 Tl/Cu。之後，利 墊上具有一開窗。利用 =的光阻圖案在鋁焊 接觸’然後去除光阻圖案形成级“ '開由之中與導電層 1247369 五、發明說明（3) 凸塊作為蝕刻罩幕去除未被遮 形成錫凸塊製程。 之阻障層與導電層，完成 電鍍液所費不貲，也就 法為一種以更經濟之方 e 、然而，上述製程電鍍設備以及 疋成本較高。而本發明所揭露的 式形成導電凸塊。 發明目的及概述·· 本發明之目的為提供在一種形成導電凸塊之製程。 成- 的為一種形成導電球體之方法包含··形 ；曰曰圓之上’沈積護層於金屬塾之上，豆中 護層之組成可以包含ΡΙ或氮化矽入接著，蝕刻護層 =暴f出金屬墊，沈積阻障層與一利於鋼材質電鍍的銅種 層（seeding layer)於蝕刻後之護層及暴露金屬墊之 上’上述之阻障層可以選用包含鈦或鉻的金屬，銅種子層 為利用減錢方式形成，其組成為Cr/Cu或Ti/Cu。 之後，利用微影製程形成具有開口之光阻圖案於銅種 子層之上。以電鍍法形成銅於銅種子層之上，再以電鍍法 在電鍍銅層表面形成鎳層。塗佈錫膏於光阻圖案之上，接 著利用刮刀刮動錫膏將錫膏刮入光阻圖案之開口中，去除 光阻圖案形成錫凸塊。以錫凸塊做為蝕刻罩幕，將被暴露1247369 V. INSTRUCTIONS (2) ί ί : : : 之 之 之 细长 细长 细长 细长 细长 细长 细长 细长 ί ί ί ί ί ί 。 。 。 。 。 。 。 。 。 Also embedded in the character.目哥 Refer to Figure 6, which is the lead composition of the sentence J 4 y r tnu in the tin ball composition of the conductive bump before fabrication. Based on environmental protection 侔# The more and more rigorous, the process of lead-free ingredients will become heavier: the composition of the conditional liquid is Qiu 3, and the composition of the bismuth ball belongs to high-lead components and is solid, and has a good fit. Crystal (eutec, ... will reach the trend of helmet lead content Ό, Ό 兀 兀 兀 兀 兀 兀 兀 兀 兀 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In the fourth quarter of 2000, 2f) Please*, Pi tch) will be 150 microns before. And two / drop (four) 2 0 03 $ four seasons ^ d, ^ ^ ^ The number of output inputs will also be increased to 1 ο 〇 μ μ 而 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 j j j j j j j j j j j j j j j j j j j j The subject is an important issue. And more than the output of the input number of the ^ ^ 卜 'Flip-chip package 乂 f 1 ip ch i P ) for the new - replaced by 4i This technology 疋 using the conductor embossed packaging technology, the process of the bump, usually in: :: 塾m is guided (4) The composite layer is deposited thereon, generally depositing the barrier layer and the conductive layer of the field Μ 5 / also composed of cr / c U, τ 彳 / r], coated with a micro-shirt process Photoresist and shape Tl/Cu. After that, the pad has an open window. Utilizing the photoresist pattern of the photoresist in the aluminum soldering contact 'and then removing the photoresist pattern forming stage' 'with the conductive layer 1247369 5. The invention description (3) The bump is used as an etching mask to remove the unmasked tin bump process The barrier layer and the conductive layer are expensive to complete the plating solution, and the method is a more economical method. However, the above-mentioned process plating apparatus and the crucible are expensive, and the disclosed method forms the conductive bump. OBJECT AND SUMMARY OF THE INVENTION The object of the present invention is to provide a process for forming a conductive bump. A method for forming a conductive sphere comprises a shape of a conductive layer on a crucible. Above, the composition of the sheath in the bean may include tantalum or tantalum nitride, and then the etching layer = the metal pad, the deposition barrier layer and a copper seed layer for etching the steel layer after etching. The protective layer and the exposed metal pad may be made of a metal containing titanium or chromium, and the copper seed layer is formed by using a money reduction method, and the composition thereof is Cr/Cu or Ti/Cu. Process formation The photoresist pattern of the opening is formed on the copper seed layer. Copper is formed on the copper seed layer by electroplating, and a nickel layer is formed on the surface of the electroplated copper layer by electroplating. The solder paste is coated on the photoresist pattern, and then utilized. The scraper scrapes the solder paste to scrape the solder paste into the opening of the photoresist pattern, and removes the photoresist pattern to form a tin bump. The tin bump is used as an etching mask and will be exposed.

12473691247369

五、發明說明（4) 出 以 完 之電錄銅層蚀刻。之後，執行助溶劑塗佈等程序，並力 ，流（reflow)，將錫凸塊因内聚力等因素形成球狀結^ 成錫球之製作。 發明詳細說明： 在導電凸塊製程（bumping process)中，利用錫膏塗 1於基板之上以利於完成導電凸塊。本發明揭露一種新的 製作之方法，係利用光阻與錫膏塗佈之步驟完成凸塊。詳 細說明如下，所述之較佳實施例只做一說明非用以限定 發明。 參閲圖一’在晶圓2上形成一金屬焊塾（pa(j)4，之後 沈積莩層6於其上，利用蝕刻製程蝕刻護層6以暴露出焊墊 4。再分別沈積阻障層8與一利於銅材質電鍍的銅種子層 (seeding layer)l〇。上述之阻障層8可以選用包含鈦或鉻 的金屬’銅種子層i 〇一般為利用濺鍍方式形成在阻障層8 之表面’其組成為Cr/Cu或Ti/Cu。上述之護層6之組成可 以包含P I或氮化矽。參閱圖二，利用微影製程形成一具有 開口之光阻圖案1 6於銅種子層1 〇上。 歹阅圃二’隨後以電鍍法形成銅1 2於光阻圖案1 6開口 中之後再以電链法在其表面形成一鎳層14，其中銅層12V. Description of the invention (4) Etching of the copper layer after completion. Thereafter, a program such as a solvent-assisted coating is applied, and a reflow is performed to form a ball bump into a solder ball due to factors such as cohesion. DETAILED DESCRIPTION OF THE INVENTION: In a bumping process, a solder paste is applied over the substrate to facilitate the completion of the conductive bumps. The present invention discloses a novel fabrication method that utilizes the steps of photoresist and solder paste coating to complete the bumps. The detailed description is as follows, and the preferred embodiment is not intended to limit the invention. Referring to FIG. 1 'forming a metal solder bump (pa(j) 4 on the wafer 2, and then depositing a germanium layer 6 thereon, etching the cap layer 6 by an etching process to expose the solder pad 4. separately depositing a barrier The layer 8 and a copper seeding layer for facilitating copper plating, the barrier layer 8 may be selected from a metal or copper seed layer containing titanium or chromium, which is generally formed by sputtering on the barrier layer. The surface of 8 is composed of Cr/Cu or Ti/Cu. The composition of the above-mentioned protective layer 6 may include PI or tantalum nitride. Referring to FIG. 2, a photoresist pattern having an opening is formed by using a lithography process. The seed layer 1 is on the top layer. The second layer is subsequently formed by electroplating to form a nickel layer 14 on the surface of the photoresist pattern 16 after the opening of the photoresist pattern 16.

第9頁 1247369 五、發明說明（5) 之厚度約為4至6微米，鎳層14之厚度約為2至4微米。上述 之堆疊金屬組成稱做球下金屬（under ball metal; UBM)。上述所舉之材質與厚度僅做為一實施例用以說明， 非用以限定本發明精神，是故本發明之範圍包含均等功能 材質之替換。之後利用錫膏塗佈於光阻圖案1 6之上。再利 用刮刀2 0刮動錫膏將錫膏刮入光阻圖案1 6中之開口。在此 步驟中，捨棄先期技術利用電鍍之方式形成錫材質於光阻 圖案1 6開口中。因此不必藉由昂貴之電鍍設備以及電鍵 液，而可以達到相同之效果符合經濟之成本。之後去除光 阻形成錫凸塊1 8，如圖四所示。一般在製作錫凸塊時所使 用之材料可以摻雜鉛，依照需求設定混合之比例用α調整 熔點。接著，以錫凸塊1 8做為蝕刻罩幕，將暴露之阻障 層/銅層8、1 0去除。之後經過助熔劑之塗佈（Π ux coating)以及熱流（reflow)，將錫凸塊因内聚力等因素幵> 成球狀結構完成錫球之製作，如圖五所示。若是上述之護 層6包含p I組成，則需要另一 p I之處理步驟。而在製作錫 凸塊過程中，利用刮刀將錫膏分佈於光阻圖案1 6之開口’ 而上述之開口一般對應於金屬墊4。 •本發明之優點如下： 可以製作導電凸塊而不必使用昂貴之設備，以降低裝 作成本增加競爭力，且可以達到相同之功效與目的。此 外，可以提升產能，錫球之塗佈印刷大約為電鑛法成本之 一半0Page 9 1247369 V. Inventive Note (5) The thickness is about 4 to 6 microns, and the thickness of the nickel layer 14 is about 2 to 4 microns. The above stacked metal composition is referred to as an under ball metal (UBM). The above-mentioned materials and thicknesses are for illustrative purposes only and are not intended to limit the spirit of the invention, so that the scope of the invention includes the replacement of the equivalent functional materials. It is then coated on the photoresist pattern 16 with a solder paste. The solder paste is then scraped by the doctor blade 20 to scrape the solder paste into the opening in the photoresist pattern 16. In this step, the prior art is discarded by electroplating to form a tin material in the opening of the photoresist pattern 16. Therefore, it is not necessary to use an expensive plating apparatus and a key liquid to achieve the same effect in an economical cost. The photoresist is then removed to form tin bumps 18, as shown in FIG. Generally, the material used in the production of tin bumps can be doped with lead, and the ratio of mixing is set as required to adjust the melting point by α. Next, the exposed bump/copper layer 8, 10 is removed using the tin bumps 18 as an etch mask. After that, through the coating of the flux and the reflow, the tin bumps are formed into a spherical structure by the cohesive force and the like, as shown in FIG. If the protective layer 6 described above contains a pi composition, then another processing step of pi is required. In the process of fabricating the tin bumps, the solder paste is distributed by the doctor blade to the opening of the photoresist pattern 16 and the opening generally corresponds to the metal pad 4. • The advantages of the present invention are as follows: Conductive bumps can be fabricated without the use of expensive equipment to reduce the cost of installation and increase competitiveness, and can achieve the same efficacy and purpose. In addition, the production capacity can be increased, and the coating and printing of solder balls is about half of the cost of the electric mining method.

第10頁 1247369 五、發明說明（6)Page 10 1247369 V. Description of invention (6)

可以製作細小間距（fine pitch)之導電球體，如可以 小於20 0微米之間距，其方法較電鍍法優良。且本方法可 以提供不含錯成分之錫球製作程序D 此外本發明中使用了到刀來進行填入錫膏至開口中之 步驟，如同圖四所顯示，由於係沿著光阻層表面推擠錫 赍，是以所施予錫膏的壓力，除了能使其順利的沿著開口 灌入外，亦可讓開口中可能的氣泡溢出。此外，以刮刀將 光阻表面上多餘的錫膏刮除，也有利於回收多餘的錫膏， 而降低整體製程的成本。 本發明以較佳實施例說明如上，而熟悉此領域技藝 者，在不脫離本發明之精神範圍内，當可作些許更動潤 飾’其專利保護範圍更當視後附之申請專利範圍及其等同 領域而定。Conductive spheres of fine pitch can be made, such as less than 20 micrometers, which is superior to electroplating. Moreover, the method can provide a solder ball preparation program D without the wrong component. In addition, in the present invention, a step of filling the solder paste into the opening is used, as shown in FIG. 4, because the surface is pushed along the surface of the photoresist layer. The tin squeezing is based on the pressure applied to the solder paste, in addition to allowing it to smoothly fill the opening, it can also allow possible bubbles in the opening. In addition, scraping the excess solder paste on the photoresist surface with a doctor blade also helps to recover excess solder paste, reducing the overall process cost. The present invention has been described above with reference to the preferred embodiments thereof, and those skilled in the art can make a few more modifications in the scope of the invention. Depending on the field.

第11頁 1247369 圖式簡單說明 圖式簡單說明： 本發明的較佳實施例將於下列之說明文字中辅以下列圖形 做更詳細的闡述： 圖一所顯示為本發明形成球體下金屬之半導體晶圓截面 圖。 圖二所顯示為本發明形成光阻圖案之半導體晶圓截面圖。 圖三所顯示為本發明以電鍍法形成銅及鎳層於光阻圖案開 口中之半導體晶圓截面圖。 圖四所顯示為本發明以刮刀形成導電凸塊之半導體晶圓截 面圖。 圖五所顯示為本發明形成導電球體之半導體晶圓截面圖。 圖六為未來導電球體材質組成以及間距演變趨勢圖。 圖號科照表： 晶圓 2 護層 6 銅種子層 10 鎳層 14 刮刀 2 0 金屬焊墊 4 阻障層 8 銅層 12 光阻圖案 16 錫凸塊 18Page 11 1247369 Brief Description of the Drawings Brief Description of the Drawings: The preferred embodiment of the present invention will be explained in more detail in the following description with the following figures: Figure 1 shows a semiconductor forming a metal under the sphere of the present invention. Wafer cross-section. 2 is a cross-sectional view showing a semiconductor wafer in which a photoresist pattern is formed according to the present invention. Figure 3 is a cross-sectional view showing a semiconductor wafer in which a copper and nickel layer is formed in a photoresist pattern opening by electroplating. Figure 4 is a cross-sectional view showing a semiconductor wafer in which a conductive bump is formed by a doctor blade according to the present invention. Figure 5 is a cross-sectional view showing a semiconductor wafer in which a conductive sphere is formed in accordance with the present invention. Figure 6 shows the material composition and spacing evolution trend of the conductive ball in the future. Figure No.: Photovoltaic 2 Protector 6 Copper seed layer 10 Nickel layer 14 Scraper 2 0 Metal pad 4 Barrier layer 8 Copper layer 12 Resistive pattern 16 Tin bump 18

第12頁Page 12

Claims (1)

1247369 六、申請專利範圍 1·一種形成導電球體之方法，該方法包含： 形成一金屬塾於〆晶圓之上， 沈積護層於該金屬墊之上； 蝕刻該護層以暴露出該金屬塾； 沈積阻障層與一利於銅材質電鍵的銅種子層於#刻後之該 護層及該暴露金屬墊之上； 利用微影製程形成具有開口之光阻圖案於該銅種子層之 上； 以電‘鑛法形成銅於該光阻圖案開口中且位於該銅種子層之 上； 再以電鍍法在該電鍍銅層表面形成鎳層； 塗佈錫膏於該光阻圖案之上； 利用刮刀刮動該錫膏將該錫膏刮入該光阻圖案之開口中； 去除該光阻圖案形成錫凸塊，其中利用上述刮刀將該錫膏 =士竽光阻圖案之該開口中，能使該開口中之氣泡溢出以 提向製程良率’或刮除多餘之該錫膏材料而方便回收， 而降低製程成本； 以該錫凸塊做為餘岁丨 _ ., s t 種子層㈣；及 I幕’將被暴露出之3亥阻障層及該銅 以熱流（ref low)，脸 ^ ν 完成錫球之製作。#錫凸塊因内聚力等因素形成球狀結構 2 ·如申請專利範圍 執行該熱流之前， 第1項之形成導電球體之方法，其中在 更包含助溶劑之塗佈（flux coating)。1247369 VI. Patent Application Scope 1. A method of forming a conductive sphere, the method comprising: forming a metal tantalum on a germanium wafer, depositing a protective layer over the metal pad; etching the protective layer to expose the metal germanium Depositing a barrier layer and a copper seed layer for facilitating copper bond on the protective layer and the exposed metal pad; forming a photoresist pattern having an opening on the copper seed layer by a lithography process; Forming copper in the opening of the photoresist pattern and on the copper seed layer by an electric method; forming a nickel layer on the surface of the electroplated copper layer by electroplating; applying a solder paste on the photoresist pattern; Scraping the solder paste to scrape the solder paste into the opening of the photoresist pattern; removing the photoresist pattern to form a tin bump, wherein the solder paste is used in the opening of the solder paste pattern The bubble in the opening is overflowed to lift the process yield' or the excess solder paste material is scraped off to facilitate recycling, and the process cost is reduced; the tin bump is used as the remaining 丨_., st seed layer (4); And the I-screen will be exposed The 3H barrier layer and the copper are produced by the heat flow (ref low) and the face ^ ν. #锡凸形成形成球结构结构 due to factors such as cohesion 2 · As claimed in the patent application, before the execution of the heat flow, the method of forming a conductive sphere of the first item, further comprising a flux coating. 1247369 六、申請專利範圍 3 ·如申請專利範圍第1項之形成導電球體之方法，其中上 述之阻障層可以選用包含鈦或鉻的金屬。 4.如申請專利範圍第1項之形成導電球體之方法，其中上 述之銅種子層為利用濺鍍方式形成，其組成為Cr/Cu或 Ti/Cu。 法 方 之 體 球 一 導 成 形 F 之含 項 h包 第以 圍可 範成 利組 專之 請層 申護 如之 5·述 上 中 其 化 氣 或 法 方 之 體 球 電 導 成 形 之 項 1X 第。 圍鋁 範含 利包 專墊 請電 申導 如之 6述 上 中 其 含 包 法 方 該 法上， 方之上 之圓之 體晶墊 球一屬 電於金 導墊該 成屬於 形金層 種，一護 一成積 7.形沈 包 以 可 成 組 之 層 護 之 述 上 中 其 墊 屬 金 該 出 露 ·，暴 矽以 化層 氮護 或該 η Ρ刻 含# 之含 後包 刻用 蝕選 該以 於可 子障 種阻 銅之 的述 鍍上 電 ， 質上 材之 銅塾 於屬 利金 一 露 與暴 層該 障及 阻層 積護 沈該 之 層 子 種 銅 該 於 案 圖 阻 光 之 D mff, 有 具 成 •，形 屬程 金製 的影 鉻微 或用； 鈦利上1247369 VI. Scope of Patent Application 3 • A method of forming a conductive sphere according to claim 1 of the patent application, wherein the barrier layer may be a metal containing titanium or chromium. 4. The method of forming a conductive sphere according to claim 1, wherein the copper seed layer is formed by sputtering and has a composition of Cr/Cu or Ti/Cu. The body ball of the French side is formed into a part of the F. The package of the H is included in the scope of the Fan. The application of the group is as follows: 5. The item 1X of the body ball or the body of the ball is formed. . The surrounding aluminum fan contains the special package, please apply for the electric power. If it is mentioned in the above method, it should be included in the method. The crystal ball of the circle above the square is electrically connected to the gold guide pad. Kind, one protector and one accumulate 7. The shape of the submerged pack can be grouped in the layer of protection, the mat is gold, the dew, the violent sputum with the layer of nitrogen protection or the η Ρ engraved with # The etching is used to electrify the copper which is resistant to the copper barrier. The copper of the upper material is in the form of Lijin and the layer of the layer and the layer of copper. D mff in the case of light blocking, there is a form of chrome or microscopic use of the form of gold; 第14頁 1247369 六、申請專利範圍 以電鍍法形成銅於該銅種子層之上； 再以電鍍法在該電鍍銅層表面形成鎳層； 塗佈錫膏於該光阻圖案之上； 利用刮刀刮動該錫膏將該錫膏刮入該光阻圖案之開口中； 去除該光阻圖案形成錫凸塊，其中利用上述刮刀將該錫膏 刮入該光阻圖案之該開口中，能使該開口中之氣泡溢出以 提高製程良率，或刮除多餘之該錫膏材料而方便回收，進 而降低製程成本； 以該錫凸塊做為蝕刻罩幕，將被暴露出之該阻障層及該銅 種子層蝕刻； 執行助熔劑塗佈等程序； 以熱流（ref low)，將錫凸塊因内聚力等因素形成球狀結構 完成錫球之製作。 8 ·如申請專利範圍第7項之形成導電球體之方法，其中上 述之銅種子層為利用濺鍍方式形成，其組成為Cr/Cu或 Ti/Cu。 9 ·如申請專利範圍第7項之形成導電球體之方法，其中上 述之導電墊包含鋁。Page 14 1247369 VI. The patent application scope is to form copper on the copper seed layer by electroplating; then forming a nickel layer on the surface of the electroplated copper layer by electroplating; coating a solder paste on the photoresist pattern; using a doctor blade Scratching the solder paste to scrape the solder paste into the opening of the photoresist pattern; removing the photoresist pattern to form a tin bump, wherein the solder paste is scraped into the opening of the photoresist pattern by using the doctor blade The bubble in the opening overflows to improve the process yield, or scrape off the excess solder paste material to facilitate recycling, thereby reducing the process cost; using the tin bump as an etching mask, the barrier layer will be exposed And etching the copper seed layer; performing a flux coating process; and forming a solder ball by a ref low, forming a spherical structure by a cohesive force or the like. 8. The method of forming a conductive sphere according to claim 7, wherein the copper seed layer is formed by sputtering and has a composition of Cr/Cu or Ti/Cu. 9. The method of forming a conductive sphere according to claim 7, wherein the conductive pad comprises aluminum. 第15頁Page 15
TW089116304A 2000-08-11 2000-08-11 Forming method of conductive bump TWI247369B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW089116304A TWI247369B (en) 2000-08-11 2000-08-11 Forming method of conductive bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW089116304A TWI247369B (en) 2000-08-11 2000-08-11 Forming method of conductive bump

Publications (1)

Publication Number Publication Date
TWI247369B true TWI247369B (en) 2006-01-11

Family

ID=37399848

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089116304A TWI247369B (en) 2000-08-11 2000-08-11 Forming method of conductive bump

Country Status (1)

Country Link
TW (1) TWI247369B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102088011A (en) * 2009-12-08 2011-06-08 台湾积体电路制造股份有限公司 Interface structure for copper-copper peeling integrity
TWI397978B (en) * 2007-12-12 2013-06-01 Ind Tech Res Inst Structure of chip and process thereof and structure of flip chip package and process thereof
US8499444B2 (en) 2007-12-26 2013-08-06 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing a package substrate
CN104201121A (en) * 2014-09-17 2014-12-10 北京理工大学 Method for forming copper pillar and bump package structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI397978B (en) * 2007-12-12 2013-06-01 Ind Tech Res Inst Structure of chip and process thereof and structure of flip chip package and process thereof
US8499444B2 (en) 2007-12-26 2013-08-06 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing a package substrate
TWI484605B (en) * 2007-12-26 2015-05-11 Samsung Electro Mech Package substrate and manufacturing method thereof
CN102088011A (en) * 2009-12-08 2011-06-08 台湾积体电路制造股份有限公司 Interface structure for copper-copper peeling integrity
CN102088011B (en) * 2009-12-08 2012-11-21 台湾积体电路制造股份有限公司 Interface structure for copper-copper peeling integrity
CN104201121A (en) * 2014-09-17 2014-12-10 北京理工大学 Method for forming copper pillar and bump package structure

Similar Documents

Publication Publication Date Title
KR100714818B1 (en) Semiconductor device and semiconductor- device manufacturing method
TWI225899B (en) Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
EP1032030B1 (en) Flip chip bump bonding
TWI273682B (en) Method for manufacturing wafer level chip scale package using redistribution substrate
KR100319813B1 (en) method of forming solder bumps with reduced UBM undercut
TW517334B (en) Method of forming barrier layers for solder bumps
US20100132998A1 (en) Substrate having metal post and method of manufacturing the same
EP1267398A2 (en) Barrier cap for under bump metal
US20040007779A1 (en) Wafer-level method for fine-pitch, high aspect ratio chip interconnect
JPH05218043A (en) Formation method of metal contact pad and formation method of metal contact terminal
TWI517273B (en) Semiconductor chip with supportive terminal pad
US20020127836A1 (en) Method to form bump in bumping technology
TW200842996A (en) Method for forming bumps on under bump metallurgy
JP2005513759A (en) Semiconductor device and method for forming the same
US20020146646A1 (en) Fine pitch wafer bumping process
JP2008021950A (en) Semiconductor device, and manufacturing method thereof
JP2006245289A (en) Semiconductor device and packaging structure
US20040185649A1 (en) [a wafer bumping process]
TWI247369B (en) Forming method of conductive bump
US9023727B2 (en) Method of manufacturing semiconductor packaging
TWI419284B (en) Chip bump structure and method for forming chip bump structure
TW201941461A (en) Solder bump, flip chip structure and method for preparing the same
JP2005268442A (en) Semiconductor device and its manufacturing method
US8759210B2 (en) Control of silver in C4 metallurgy with plating process
TW418470B (en) Method for forming solder bumps on flip chips and devices formed

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent