1247366 13894twf 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝結構(chip package structure)及其製程，且特別是有關於一種堆疊晶片結構、 多晶片封裝結構及其製程。 【先前技術】 在高度情報化社會的今日，多媒體應用的市場不斷 地急速擴張著，積體電路(Integral Chip，1C)封裝技術亦 需配合電子裝置的數位化、網路化、區域連接化以及使 用人性化的趨勢發展。為了達成上述的要求，必須強化 電子元件的高速處理化、多機能化、積集化、小型輕量 化以及低價化等多方面的需求，於是積體電路封裝技術 也跟著朝向微型化、高密度化發展。因此，球格陣列式 構裝(Ball Grid Array，BGA)、晶片尺寸構裝(Chip-Scale Package，CSP)、覆晶構裝(Fiip chip package，F/C package) 與多晶片模組(Multi-Chip Module, MCM)等高密度積體 電路封裝技術也應運而生。對於高密度積體電路封裝而 言，縮短連結線路的長度將有助訊號傳遞速度的提昇， 因此凸塊(bump)的應用已逐漸成為高密度封裝的主流。 圖1繪示為一習知多晶片封裝結構的剖面示意圖。 請參照圖1，多晶片封裝結構100係由一承載器 (carrier)110、一第一晶片120、一第二晶片13〇、多條焊 線140及一封裝膠體(molding c〇mp〇und)15〇所構成。其 中，承載器110上具有多個接點112、114與116。第二 晶片120具有一主動表面S1與一晶背S2。主動表面S1 1247366 13894twf 上配置有多個凸塊 曰曰乃 你稭由凸塊一- 與接點112電性連接。第二晶片130具有一主動表面S3 與一晶背S4。第二晶片130係配置於第一晶片120上， 且第一晶片130之晶背S4係與第一晶片120之晶背S2 接觸。第二晶片130之主動表面S3係藉由多條焊線14〇 與承載器110之接點116電性連接。封褒膠體HQ包覆 第一晶片120、第二晶片13〇與焊線14〇,並填充於第 一晶片120與承載器11〇之間。 、、 承上所述，第二晶片13〇係採打線接合(wire b〇nding) 技術而以焊線140與承載器11〇電性連接。但是，在打 線接合的過&巾，為避免焊線碰到晶#邊緣而發生斷線 的問題’焊線14〇之弧高m以及接點116與晶片之距 離D2都必須增加而無法縮短。如此一來，將使承载器 1卜 10，積無法縮小，且封裝膠體15G的高度也無法減 〉。換言之’多晶㈣脑構刚之整解度與大小將 =易縮小’不但不符合封裝技術朝向微型化發展之趨 勢，更會降低產品在市場上的競爭力。 趨 可互二Hi 一晶片120與第二晶片130間的訊號 器110 _十線路118，並利用線路 因與接點116電性連接。如此一來，不僅 時符^匕巧縮小多晶片封装結構之厚度與大小’同 ί=】器之電路佈局’已成為亟待解決的課題。 1247366 13894twf 本發明的目的就是在提供一 封裝結構之厚度與大 縮小種堆疊晶片結構，適於 於縮=片的種多晶片封裝製程，適 之電路佈局。冓居度與大小，同時簡化承載器 器、片出—種多晶片封裝結構，其係由 ;上具有多::點:第第= 由第一凸塊與接點電以= 片之第二晶背片上，且第二 分1性連接於第—凸二第二凸^|觸°多條焊 晶片、多ΐ片封裝結構例如更包括-第 晶片上，且第：：、二個焊球。第三晶片例如配置於第 連接。斑-ί二曰曰片係藉由第二凸塊而與第二晶片雷 著〜=者層例如配置於第—晶片與第二晶片之門電 -心之膠膜。焊球例如配置於承载器" -，-二=:⑼ 一端例如係連接於第二凸塊朝向第二:二 1247366 13894twf 侧。第一晶片與第 L 日日乃刀別可為記憶體晶片。承載罗 例如係電路板或導線架。焊線之材質可為金。再^ ^ -凸塊之部分頂表面例如係顯露於封歸體外。 此外’多晶#封裝結構例如更包括 (underfill)，其填充於承顧與第―晶片之間。同時: J曰片：裝結構例如更包括一封裝膠體 片、第二晶片與焊線。 復弟Ϊ 包覆片多晶Γΐ結構例如更包括一封裝膠體，; 如更:充，承载器與第-晶片之間，並包覆第一凸 Τ 本务明另提出-種堆疊晶片結構，其 Λ 片、：第二晶片及多條焊線所構成。第一晶 ：:Ε ΐ楚 Βθ片具有—第二主動表面與—笛一 配置於第-晶片上，且第第二晶片裔 片ί第一晶背接觸。多條焊線分別電第一晶 與第二凸塊之間。 电f建接於第-凸轉 層，ίί層 層例如係高料_。每―條焊、狀 ^。點著 第二凸塊朝向第一晶片之外緣的一側，而每匕係連接於 另-：例如係連接於第二凸塊朝向第條埤線之 側晶片與第二晶片分別可為記憶體晶片外緣的〜 發明再提出-種多晶片封裝製程’其係先 1247366 13894twf Hί於—承載器上。承載器上具有多個接點。第-曰曰片八有多個第一凸塊。第一晶片係 電性連接。接著，將一第二晶片置於第!晶=點 晶片遠離第-晶片之表面上具有多個第二凸塊。之^ 形成多條烊線，以連接於第-凸塊與第二凸塊之間。 前，ί::第 片精由第二凸塊而與第二晶片電性連接。在電性連接= 二!Π:晶片上，以使第二晶片藉由黏：ΐ ^成焊線之後，例如更填充—底膠材於承 ^成芯;間。同時’在形成底膠材之後，例如 或者，以包覆第-晶片、第二晶片與焊線。 以包覆第—晶片Ϊ線更形成一封裝膠體， 二驟中:例如更將封裝膠體填 之 間，且包覆第-凸塊。 >戟态興弟-晶片之 除部體之步驟後，例如更去 裝膠體外。去除部分封“髏面顯露於封 研磨步驟。 之方法例如係進行一機械 成多個焊球:=:以,體之步驟後’例如更形 再者，在配置第二^日^之表面上。 於第-晶片上之後及形成焊 1247366 13894twf 線之前，例如更翻轉配置有第一晶片與第二晶片之承載 器，以使承載器約略垂直水平面。此外，在形成焊線中 位於第一晶片之同一側的部分之後以及形成焊線中位於 卓一晶片之另一侧的部分之前，例如更將配置有第一晶 片與弟二晶片之承載器旋轉一角度’並保持承載器約垂 直水平面。其中，承載器所旋轉之角度例如是9〇度。 本發明又提出一種多晶片封裝製程，其係先將一第 一晶圓貼合於一第二晶圓上。第一晶圓遠離第二晶圓之 表面上具有多個第一凸塊，而第二晶圓遠離第一晶圓之 表面上具有多個第二凸塊。接著，切割第一晶圓與第二 晶圓以形成多個晶片單元。之後，將這些晶片單元至少 其中之一配置於一承載器上。承載器上具有多個接點， 而晶片單元係以第一凸塊與接點電性連接。然後，形成 多條焊線以連接於第一凸塊與第二凸塊之間。 在本實施例中，於配置晶片單元之後與形成焊線之 前，例如更配置一第三晶片於晶片單元上，並使第三晶 片藉由第二凸塊而與晶片單元電性連接。此外，將第二 晶圓貼合於第二晶圓上之方法例如係配置一黏著層於第 一晶圓上，以使第二晶圓藉由黏著層貼合於第—晶圓 上0 、此外，在形成焊線之後，例如更填充一底膠材於承 載器與晶片單元之間。同時，在形成焊線之後，例如更 形成一封裝膠體，以包覆晶片單元與焊線。 、或者，在形成焊線之後，例如更形成一封裝膠體， 以包覆晶片單元與焊線。在形成封裝膠體之步驟中，例 1247366 13894twf 第如填充於承裁器與晶―，且㈣ 裝膠體 之方法例如係進行一 除部分封裝膠ί上封=體,步驟後，例如更去 外。去除部分:二分頂表面顯露於封 研磨步驟 機械 再者’在配置晶片單元於承脑上之後及 Ϊ、二=轉配置有晶片單元之承載器，以使承载 垂直水平面。此外，在形成烊線中位於晶片單元 5 -侧的部分之後以及形成焊線中位於晶片單元 :側：部分之前’例如更將配置有晶片單元之承載器旋 角度，並保持承載器約垂直水平面。其中，承 所旋轉之角度例如是9〇度。 ° 綜上所述，在本發明之堆疊晶片結構、多晶片封裝 結構及其製程中，第-晶片與第二晶片之間係以焊線連 接兩者之凸塊，因此可縮小多晶片封裝結構之厚度與大 小’同時可簡化承載器之電路佈局。 為讓本發明之上述和其他目的、特徵和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 細ό兒明如下。 【實施方式】 圖2Α〜2Ε繪示為本發明一較佳實施例之多晶片封 裝氣知的流程不意圖。請參照圖2A，本發明^一較佳實 11 1247366 13894twf 多^封I製程係先將—第—晶片22g置於 載器上210。承裁考21〇卜且古夕μ从 秀 承載器210之同3 =上/”點212，其位於 J表面上。此外，承载器210之另一声 面上例如更具有多個接點214 又 板(dmdt board)、導绩加頌為210例如係電路 器。第-日片丄Ϊ、Ϊ 槪)或其他形式之承载 ° 日日 八有一主動表面S5與一晶背士 動表面S5上配置有多個凸塊 。 塊扣與承載器210之接點212電性f〇係以凸 將一第二晶片24〇置於第一晶 片^上。此外，在配置第二晶片240前，例如更配署 勒ίΪ^3()&第"'晶片220上°第二晶片240可藉由 1::二位於第一晶片220上。第二晶片24〇且 有主動表面S7與一晶背S8〇主動表 曰曰 黏者層230例如係高分子膠膜。 汾干例如採用常見的打線接合機台(未 :^成夕料線25〇’其係連接於凸塊242與凸塊拉 222朝向第一曰只”“V:線接合機台例如係由凸塊 242 ^ 接合機台也可由凸塊242朝向緣f-：：:缝打線 將、、％過第一晶片220與第-曰η ’、 250皆緣示出來，實際之同一側緣的焊線 水貰I不上母條焊線25〇係位於第一晶片 12 1247366 13894twf 220與第二晶片240之外緣，而非貫穿第—晶片22〇盥 第二晶片240。 ” 最後請參照圖2D，例如形成一封裝膠體26〇，其至 少包覆第一晶片220、第二晶片240與焊線25〇。另， 封裴膠體260也可更填充於第一晶片22〇與承載器21〇 之間，並包覆凸塊222。封裝膠體260之作用在保護第 二晶片220與第二晶片240 ’使其免於受到濕氣及i或外 力的破壞’同時提升各構件之間電性連接關係的可靠 度。 此外，請參照圖2E，在形成封裝膠體26〇之後， 例如更形成多個焊球270於承載器21〇之接點214上。 圖3A與圖3B緣示為圖2B與圖2C所纷示之步驟 中打線方法的示意圖。請參照圖2B與圖M，在形成焊 線250之前，例如將圖2B中配置有第一晶片2如與第 二晶片240之承載器21〇翻轉，以使承載器2ι〇如圖、3a 繪示般約略垂直水平面。此步驟之目的在使第一晶片22〇 與第二晶片240上，將要進行打線接合的第一:塊從 與第二凸塊242暴露於-打線針1〇的工作方向⑽上， 以便於打騎1G在打職財㈣财向 -晶片220與第二晶片24〇上。接著請參照圖3B，豆係 以圖3A之方向D2〇所獲得的側視圖。在形成位於第二 =同一側的烊線250後’例如更將承載器 旋轉-角度’並保持承載ϋ 21G約略垂直於水平面，且 進行打線製程以形成位於第二晶片24〇之另一側的料 25〇。以此規貝|J ’即可形成所有焊線MO。其中，承載器 13 1247366 13894twf 210每次所旋轉之角度例如是90度。 圖4A與圖4B繪示為圖2E所繪示之步驟後可附加 進，的兩個步驟的示意圖。請參照圖4A，在完成如圖2e 之多晶片封裝結構200後，例如更去除部分封裝膠體 260以使第一凸塊242之部分頂表面顯露於封裝謬體 ^卜260。其中，去除部分封裝膠體260之方法例如係進 行一機械研磨步驟。請參照圖4B，在去除部分封裝膠體 260之後，可更將一第四晶片29〇例如以晶片尺寸構裝 技術而與第二晶片240之第二凸塊242電性連接。、 凊繼續參照圖2E，本發明一較佳實施例之多晶片 封裝結構200主要係由承載器21〇、第一晶片22〇、第 二晶片240及多條焊線250所構成。本實施例之多晶片 封裝結構200中，主要構件以及其他構件已在前面做詳 細敘述，在此僅簡單說明。承載器21〇上具有多個接點 212。第一晶片22〇之主動表面S5上配置有多個凸塊 222。第一晶片220係藉由凸塊222與接點212電性連 接。第二晶片240之主動表面S7上配置有多個凸塊242。 第二晶片240係配置於第一晶片220上，且第二晶片240 之晶背S8係朝向第一晶片22〇之晶背S6。焊線25〇分 別電性連接於凸塊222與凸塊242之間。此外，多晶片 封裝結構200例如更包括封裝膠體26〇，其包覆凸塊 222、凸塊242與焊線250，並填充於第一晶片220與承 載器210之間。第一晶片220與第二晶片240例如是記 憶體晶片或其他晶片。 圖5繪示為本發明另一較佳實施例之多晶片封裝結 1247366 13894twf 構的剖面示意圖。請來昭 々α , 製程係先進行如圖2^^ 裝結構之 日可片更形成一封裝膠體以包 弟—日曰片240與焊線250。之後，可 Hr球顶於承裁器別之接點2Η上。 β面^ Η" 判—較佳實補之堆疊晶片結構的 盥円2Ε之夕日μΓ 本實施例之堆疊晶片結構60〇1247366 13894twf IX. Description of the Invention: [Technical Field] The present invention relates to a chip package structure and a process thereof, and more particularly to a stacked wafer structure, a multi-chip package structure, and a process thereof. [Prior Art] In today's highly information society, the market for multimedia applications is rapidly expanding. The integrated circuit (Integral Chip, 1C) packaging technology also needs to match the digitalization, networking, and regional connectivity of electronic devices. Use human trends to develop. In order to achieve the above requirements, it is necessary to strengthen the high-speed processing, multi-function, accumulation, small size, light weight, and low cost of electronic components. Therefore, the integrated circuit packaging technology is also oriented toward miniaturization and high density. Development. Therefore, Ball Grid Array (BGA), Chip-Scale Package (CSP), Fip Chip Package (F/C package) and Multi-Chip Module (Multi) High-density integrated circuit packaging technology such as -Chip Module, MCM) has also emerged. For high-density integrated circuit packages, shortening the length of the connection line will improve the signal transmission speed, so the application of bumps has gradually become the mainstream of high-density packaging. 1 is a cross-sectional view of a conventional multi-chip package structure. Referring to FIG. 1 , the multi-chip package structure 100 is composed of a carrier 110 , a first wafer 120 , a second wafer 13 , a plurality of bonding wires 140 , and an encapsulating colloid (molding c〇mp〇und). 15 〇 constitutes. There are a plurality of contacts 112, 114 and 116 on the carrier 110. The second wafer 120 has an active surface S1 and a crystal back S2. The active surface S1 1247366 13894twf is provided with a plurality of bumps, and the straw is electrically connected to the contacts 112. The second wafer 130 has an active surface S3 and a crystal back S4. The second wafer 130 is disposed on the first wafer 120, and the crystal back S4 of the first wafer 130 is in contact with the crystal back S2 of the first wafer 120. The active surface S3 of the second wafer 130 is electrically connected to the contact 116 of the carrier 110 by a plurality of bonding wires 14A. The sealing gel HQ coats the first wafer 120, the second wafer 13 and the bonding wires 14〇, and is filled between the first wafer 120 and the carrier 11〇. As described above, the second wafer 13 is electrically connected to the carrier 11 by a bonding wire 140 by a wire bonding technique. However, in the wire bonding & towel, in order to avoid the wire breakage when the wire hits the edge of the crystal #, the arc height m of the bonding wire 14 and the distance D2 between the contact 116 and the wafer must be increased and cannot be shortened. . As a result, the carrier 1 can not be reduced, and the height of the encapsulant 15G cannot be reduced. In other words, the degree of rectification and size of the polycrystalline (four) brain structure will be reduced. It will not only conform to the trend of packaging technology towards miniaturization, but will also reduce the competitiveness of products in the market. The signal 110_10 line 118 between the chip 120 and the second chip 130 can be mutually connected, and the line is electrically connected to the contact 116. In this way, not only does the time and size of the multi-chip package structure reduce the thickness and size of the multi-chip package structure, but the circuit layout of the device has become an urgent problem to be solved. 1247366 13894twf The object of the present invention is to provide a package structure having a thickness and a large reduction type of stacked wafer structure, which is suitable for a multi-chip package process of shrink-film, and suitable circuit layout.冓 度 与 大小 , , 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种On the crystal back sheet, and the second portion is connected to the first-convex second-convex second-contact solder wafer, the multi-turn wafer package structure, for example, further includes a -th wafer, and::, two solder balls . The third wafer is, for example, arranged at the first connection. The plaque-laser film is struck with the second wafer by the second bump, for example, a layer disposed on the gate of the first wafer and the second wafer. The solder ball is disposed, for example, on the carrier " -, - two =: (9) one end is, for example, connected to the second bump toward the second: two 1247366 13894twf side. The first wafer and the Lth day may be memory chips. The carrier is, for example, a circuit board or a lead frame. The material of the wire can be gold. Further, a part of the top surface of the bump is exposed, for example, outside the envelope. Further, the 'polycrystalline # package structure, for example, further includes an underfill which is filled between the carrier and the first wafer. At the same time: J: The mounting structure includes, for example, an encapsulant sheet, a second wafer and a bonding wire. The polysilicon structure of the cladding film, for example, further comprises an encapsulant; for example, charging, between the carrier and the first wafer, and covering the first tenon, the present invention further proposes a stacked wafer structure, The cymbal, the second wafer and a plurality of bonding wires are formed. The first crystal has a second active surface and a flute disposed on the first wafer, and the second wafer is in contact with the first crystal. A plurality of bonding wires are electrically connected between the first crystal and the second bump, respectively. The electric f is connected to the first-convex turn layer, and the ί layer is, for example, a high material _. Every - strip welding, shape ^. Pointing the second bump toward one side of the outer edge of the first wafer, and each of the turns is connected to another: for example, the side wafer and the second wafer connected to the second bump toward the first turn can be respectively memorized The outer edge of the bulk wafer is again proposed - a multi-chip packaging process 'the first 1247366 13894twf Hί on the carrier. There are multiple contacts on the carrier. The first-slice eight has a plurality of first bumps. The first wafer is electrically connected. Next, a second wafer is placed on the surface of the wafer: the wafer has a plurality of second bumps on the surface away from the first wafer. ^ forming a plurality of turns to connect between the first bump and the second bump. Previously, the ί:: first piece is electrically connected to the second wafer by the second bump. On the electrical connection = two! Π: on the wafer, so that the second wafer is bonded to the core by bonding: 更 ^, for example, more filling - the bottom material is formed into a core; At the same time, after the undercoat material is formed, for example, or to coat the first wafer, the second wafer, and the bonding wire. The encapsulating colloid is further formed by coating the first wafer winding. In the second step, for example, the encapsulant is further filled and the first bump is covered. > After the step of removing the body from the wafer, for example, the outer layer of the gel is removed. Removing the partial seal "the surface is exposed in the sealing grinding step. The method is, for example, performing a mechanical welding of a plurality of solder balls: =: to, after the step of the body, for example, the shape is further, on the surface of the second surface ^ After the first wafer and before the welding 1247366 13894twf line is formed, for example, the carrier of the first wafer and the second wafer is flipped so that the carrier is approximately perpendicular to the horizontal plane. Further, the first wafer is formed in the bonding wire. After the portion on the same side and before the portion of the bonding wire that is located on the other side of the wafer, for example, the carrier configured with the first wafer and the second wafer is rotated by an angle 'and the carrier is maintained at a vertical level. The angle at which the carrier rotates is, for example, 9 degrees. The present invention further provides a multi-chip packaging process in which a first wafer is first bonded to a second wafer. The first wafer is away from the second wafer. The surface of the wafer has a plurality of first bumps, and the second wafer has a plurality of second bumps on a surface away from the first wafer. Then, the first wafer and the second wafer are cut to form a plurality of Wafer unit At least one of the wafer units is disposed on a carrier. The carrier has a plurality of contacts, and the wafer unit is electrically connected to the contacts by the first bumps. Then, a plurality of bonding wires are formed to connect. Between the first bump and the second bump. In this embodiment, after the wafer unit is disposed and before the bonding wire is formed, for example, a third wafer is disposed on the wafer unit, and the third wafer is used by the first wafer. The second bump is electrically connected to the wafer unit. Further, the method of bonding the second wafer to the second wafer is, for example, disposing an adhesive layer on the first wafer, so that the second wafer is adhered. The layer is bonded to the first wafer, and further, after the bonding wire is formed, for example, a primer is further filled between the carrier and the wafer unit. Meanwhile, after the bonding wire is formed, for example, an encapsulant is further formed. To encapsulate the wafer unit and the bonding wire, or, after forming the bonding wire, for example, an encapsulant is further formed to cover the wafer unit and the bonding wire. In the step of forming the encapsulant, the example 1247366 13894twf is filled in the bearing. Cutters and crystals - and (4) The method of installing the colloid is, for example, performing a partial encapsulation of the encapsulant, and after the step, for example, the removal is performed. The removal portion: the bifurcation surface is exposed in the sealing step, and the mechanical device is further disposed on the substrate. Thereafter, the carrier of the wafer unit is disposed so as to carry the vertical horizontal plane. Further, after the portion of the tantalum line on the side of the wafer unit 5 - and the formation of the bonding wire is located before the wafer unit: side: portion For example, the carrier of the wafer unit is rotated at an angle, and the carrier is maintained at a vertical level. The angle of rotation of the carrier is, for example, 9 degrees. ° In summary, the stacked wafer structure of the present invention is In the chip package structure and the process thereof, the bump between the first wafer and the second wafer is connected by a bonding wire, so that the thickness and size of the multi-chip package structure can be reduced, and the circuit layout of the carrier can be simplified. The above and other objects, features and advantages of the present invention will become more apparent from [Embodiment] Figs. 2A to 2B illustrate a flow of a multi-wafer package in accordance with a preferred embodiment of the present invention. Referring to FIG. 2A, the present invention is a preferred embodiment. The first wafer 11g is placed on the carrier 210. The test is 21 〇 and the ancient μ μ from the show carrier 210 is the same 3 = up / "point 212, which is located on the J surface. In addition, the other surface of the carrier 210 has, for example, a plurality of contacts 214 The board (dmdt board), the guide is twisted to 210, for example, a circuit breaker. The first-day film Ϊ, Ϊ 槪) or other forms of load ° day 8 has an active surface S5 and a crystal back surface of the S5 configuration There are a plurality of bumps. The bumps of the block and the carrier 210 are electrically connected to the second wafer 24 to be placed on the first wafer. Further, before the second wafer 240 is disposed, for example, The second wafer 240 on the wafer 220 can be placed on the first wafer 220 by the 1:: two. The second wafer 24 has an active surface S7 and a crystal back. The S8〇 active surface adhesive layer 230 is, for example, a polymer adhesive film. For example, a common wire bonding machine is used (not: ^成夕线线25〇' is connected to the bump 242 and the bump pull 222 Toward the first 曰""V: the wire bonding machine, for example, by the bumps 242 ^ the bonding machine can also be bent by the bumps 242 toward the edge f-::: stitching the wire, % over the first wafer 22 0 and the first - 曰 η ', 250 are shown, the actual same side of the wire 贳 I is not on the mother wire 25 〇 is located on the first wafer 12 1247366 13894twf 220 and the second wafer 240 Instead of penetrating through the first wafer 22, the second wafer 240. Finally, referring to FIG. 2D, for example, an encapsulant 26 is formed, which covers at least the first wafer 220, the second wafer 240, and the bonding wires 25A. The sealing gel 260 can also be further filled between the first wafer 22 and the carrier 21A and covered with the bumps 222. The encapsulant 260 acts to protect the second wafer 220 and the second wafer 240 from The reliability of the electrical connection between the components is improved by the damage of the moisture and the i or the external force. In addition, referring to FIG. 2E, after the encapsulant 26 is formed, for example, a plurality of solder balls 270 are formed on the bearing. Figure 3A and Figure 3B are schematic views showing the method of wire bonding in the steps shown in Figures 2B and 2C. Referring to Figure 2B and Figure M, before forming the bonding wire 250, for example, The first wafer 2 is disposed in FIG. 2B, such as the carrier 21 of the second wafer 240, to be flipped over The carrier 2 is approximately perpendicular to the horizontal plane as shown in Fig. 3a. The purpose of this step is to make the first wafer 22 and the second wafer 240, the first: block and the second bump 242 to be wire bonded. It is exposed to the working direction (10) of the wire-punching needle 1〇, so as to facilitate riding the 1G to play the financial (4) financial-wafer 220 and the second wafer 24〇. Then, referring to FIG. 3B, the bean is in the direction D2 of FIG. 3A. The side view obtained by 〇. After forming the ridge line 250 on the second=same side, 'for example, the carrier is rotated-angled' and the carrier ϋ 21G is held approximately perpendicular to the horizontal plane, and a wire bonding process is performed to form the other side of the second wafer 24 〇. 25 〇. All the bonding wires MO can be formed by this rule |J ’. The angle at which the carrier 13 1247366 13894twf 210 is rotated is, for example, 90 degrees. 4A and 4B are schematic views showing two steps that can be added after the step shown in Fig. 2E. Referring to FIG. 4A, after the multi-chip package structure 200 of FIG. 2e is completed, for example, a portion of the encapsulant 260 is further removed to expose a portion of the top surface of the first bump 242 to the package body 260. Among them, the method of removing a part of the encapsulant 260 is, for example, a mechanical grinding step. Referring to FIG. 4B, after the portion of the encapsulant 260 is removed, a fourth wafer 29 can be electrically connected to the second bump 242 of the second wafer 240, for example, by a wafer size. Referring to FIG. 2E, the multi-wafer package structure 200 of the preferred embodiment of the present invention is mainly composed of a carrier 21, a first wafer 22, a second wafer 240, and a plurality of bonding wires 250. In the multi-wafer package structure 200 of the present embodiment, the main components and other components have been described in detail above and will be briefly described herein. The carrier 21 has a plurality of contacts 212 thereon. A plurality of bumps 222 are disposed on the active surface S5 of the first wafer 22A. The first wafer 220 is electrically connected to the contact 212 by bumps 222. A plurality of bumps 242 are disposed on the active surface S7 of the second wafer 240. The second wafer 240 is disposed on the first wafer 220, and the crystal back S8 of the second wafer 240 faces the crystal back S6 of the first wafer 22. The bonding wires 25 are electrically connected between the bumps 222 and the bumps 242, respectively. In addition, the multi-chip package structure 200 further includes, for example, an encapsulant 26, which covers the bumps 222, the bumps 242, and the bonding wires 250, and is filled between the first wafer 220 and the carrier 210. The first wafer 220 and the second wafer 240 are, for example, memory chips or other wafers. FIG. 5 is a cross-sectional view showing a multi-chip package junction 1247366 13894twf according to another preferred embodiment of the present invention. Please come to 昭α, the process is first to carry out the structure as shown in Fig. 2^^. The package can form a package of colloids to cover the brother-day 曰 240 and the bonding wire 250. After that, the Hr ball can be placed on the other end of the bearing. β ^ Η quot 判 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 堆叠 堆叠 堆叠 堆叠 堆叠
J 之片封裝結構的差異在於，堆疊 結構600不包括圖2E中的承載器21〇、焊球謂盥封装 上其餘部分則與多晶片封裝結構200相同： 在此即省略其敘述。The difference in the package structure of J is that the stacked structure 600 does not include the carrier 21 of FIG. 2E, and the rest of the solder ball is the same as the multi-chip package structure 200: The description thereof is omitted here.
圖7綠不為本發明再一較佳實施例之多晶片封装社 構的剖面示意圖。請同時參照圖2a〜2e與圖7，本^ 明另-較佳實施例之多晶片封裝製程係大致與前述實^ 例相同’其差異點係於配置第二晶片之後與形成 線⑽之前’更配置—第三晶片280於第二晶片24〇上， 並使第三^片280藉由凸塊242而與第二晶片24〇電性 連接換°之本實施例之多晶片封裝結構7〇〇與前— 實施例之多晶片封裝結構·的差異在於，多晶片 結構曰700更包括第三晶s 28〇。當然，第一晶片22〇: 第一曰a片240與弟二晶片28G同樣可為記憶體晶片或其 他晶片。 圖8A〜8F繪示為本發明又一較佳實施之多晶片 裝製程的流㈣。本實關之多晶片聽製程所完 15 1247366 13894twf 成的多晶片封裝結構與圖2E所繪示者相同，因此相似 元件將標示為相同標號。 請參照圖8A，首先將一第一晶圓810貼合於一第 二晶圓820上。其中，第一晶圓810遠離第二晶圓820 之表面上具有多個凸塊222(繪示於圖8B中），而第二晶 圓820遠離第一晶圓810之表面上具有多個凸塊242。 將第一晶圓810貼合於第二晶圓820上之方法例如是先 配置一黏著層230(繪示於圖8B中)於第一晶圓810上， 再使第二晶圓820藉由黏著層230而貼合於第一晶圓81〇 上。 接著請參照圖8B，對貼合後的第一晶圓81〇與第 一晶圓820進行切割，以形成多個晶片單元83〇(圖中僅 緣示一個）。換言之，每一個晶片單元830都包括了背對 背貼合的一第一晶片220與一第二晶片240。 接者请參照圖8C ’將至少一個晶片單元83〇配置 於一承載器210上。承載器210上具有多個接點212， 而晶片單元240係以凸塊222與接點212電性連接。 之後，進行圖8D〜8F中所繪示之步驟，這些步驟 與圖2C〜2E所緣示之步驟相同，在此即省略其說明。 當然，本實施例之多晶片封裝製程在完成圖8F所示之 步驟後，亦可更進行如圖3所不之步驟。 值得注意的是，雖然在上述各種實施例之多晶片封 裝結構中，每一個凸塊皆以連接一條焊線為例，但在實 際應用上可視電路設計之需求而改變焊線與凸塊的連接 方式。此外，在承載器上也可增設線路，以連接承载芎 1247366 13894twf 分接點，端視電路設計之需求。_，上述各種 夕曰曰1封裝結構及其製程的變化皆可相互組合使用。 結槿：’在ΐ發明之堆疊晶片結構、多晶片封裝 ^兩去中’第—晶片與第二晶片之間係以焊線連 f兩者之凸塊。此種焊線可極為貼近第一晶片與第二晶 二，因此可縮小承载ϋ的面積與封裝膠體的高度，進而 j小多晶>}封裝結構之整體厚度與大小。啊，由於第 =片與第二晶片之料需歸承載器上的線路而進行 ㈣傳遞’因此可簡化承個之電路佈局。另外，本發 =堆疊晶片結構、多晶片封裝結構及其製程應用於 3領域時，在賴晶片封裝結構之尺寸上更有長足的 進步。 雖然本發明已以較佳實施例揭露如上，然其並非用 =限定本發明，任域習此技藝者，在稀離i發明之 々神和範_ ’當可作些許之更動與潤飾，因此本發明 之保護範圍當視_之申請專職_界定者為準。 【圖式簡單說明】 圖1繪不為一習知多晶片封裝結構的剖面示意圖。 圖2A〜2E繪示為本發明一較佳實施例之多晶片封 裝製程的流程剖面圖。 圖3A與圖3B繪示為圖2B與圖2C所繪示之步驟 中打線方法的示意圖。 圖4A與圖4B %示為圖2E所繪示之步驟後可附加 進行的兩個步驟的示意圖。 圖5繪示為本發明另一較佳實施例之多晶片封裝結 17 1247366 13894twf 構的剖面示意圖。 圖6繪示為本發明一較佳實施例之堆疊晶片結構的 剖面示意圖。 圖7繪示為本發明再一較佳實施例之多晶片封裝結 構的剖面示意圖。 圖8A〜8F繪示為本發明又一較佳實施之多晶片封 裝製程的流程示意圖。 【主要元件符號說明】 100 :多晶片封裝結構 110 :承載器 112、114、116 :接點 118 :線路 120 :第一晶片 122 :凸塊 130 :第二晶片 140 :焊線 150 :封裝膠體 51、 S3 :主動表面 52、 S4 :晶背 D1 :弧高 D2 :距離 10 :打線針 200、500、700 :多晶片封裝結構 210 :承載器 212、214 :接點 18 1247366 13894twf 220 :第一晶片 222、242 :凸塊 230 :黏著層 240 ··第二晶片 250 :焊線 260、520 :封裝膠體 D10、D20 :方向 280 ··第三晶片 290 ··第四晶片 510 :底膠材 600 :堆疊晶片結構 810 ·•第一晶圓 820 :第二晶圓 830 :晶片單元 55、 S7 ··主動表面 56、 S8 :晶背 19Figure 7 is a cross-sectional view of a multi-chip package architecture in accordance with still another preferred embodiment of the present invention. Referring to Figures 2a to 2e and Figure 7, the multi-chip package process of the preferred embodiment is substantially the same as the above-described embodiment. The difference is after the second wafer is disposed and before the line (10) is formed. Further, the third wafer 280 is disposed on the second wafer 24, and the third wafer 280 is electrically connected to the second wafer 24 by the bumps 242. The multi-chip package structure of the embodiment is replaced. The difference between the prior and the multi-chip package structure of the embodiment is that the multi-wafer structure 曰700 further includes the third crystal s 28 〇. Of course, the first wafer 22: the first wafer 240 and the second wafer 28G may be memory wafers or other wafers. 8A-8F illustrate a flow (4) of a multi-wafer mounting process according to still another preferred embodiment of the present invention. The multi-chip package structure of the actual multi-chip listening process is the same as that shown in Fig. 2E, so similar elements will be denoted by the same reference numerals. Referring to FIG. 8A, a first wafer 810 is first bonded to a second wafer 820. The first wafer 810 has a plurality of bumps 222 (shown in FIG. 8B ) on the surface away from the second wafer 820 , and the plurality of bumps on the surface of the second wafer 820 away from the first wafer 810 . Block 242. For example, the first wafer 810 is attached to the second wafer 820 by first disposing an adhesive layer 230 (shown in FIG. 8B) on the first wafer 810, and then the second wafer 820. The adhesive layer 230 is attached to the first wafer 81. Next, referring to FIG. 8B, the bonded first wafer 81A and the first wafer 820 are diced to form a plurality of wafer units 83A (only one of them is shown). In other words, each of the wafer units 830 includes a first wafer 220 and a second wafer 240 that are back-to-back. Referring to Fig. 8C', at least one wafer unit 83 is disposed on a carrier 210. The carrier 210 has a plurality of contacts 212, and the wafer unit 240 is electrically connected to the contacts 212 by bumps 222. Thereafter, the steps shown in Figs. 8D to 8F are performed, and the steps are the same as those shown in Figs. 2C to 2E, and the description thereof will be omitted. Of course, after the multi-chip packaging process of this embodiment completes the steps shown in FIG. 8F, the steps as shown in FIG. 3 can be further performed. It should be noted that although in the multi-chip package structure of the above various embodiments, each bump is connected by a bonding wire, the connection between the bonding wire and the bump is changed in the practical application. the way. In addition, a line can be added to the carrier to connect the 芎 1247366 13894twf tapping point to meet the needs of the circuit design. _, the above various Xiyi 1 package structures and variations of their processes can be used in combination with each other. The knot: 'In the stacked wafer structure of the invention, the multi-chip package, the two wafers, and the bumps of the second wafer are connected by bumps. The wire can be very close to the first wafer and the second crystal, thereby reducing the area of the carrier and the height of the encapsulant, and thus the overall thickness and size of the package structure. Ah, since the material of the first and second wafers needs to be transferred to the line on the carrier (4), the circuit layout can be simplified. In addition, when the stacked wafer structure, the multi-chip package structure, and the process thereof are applied to the field of 3, the size of the package structure is further improved. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art will be able to make some changes and refinements in the invention of the invention. The scope of protection of the invention shall be subject to the definition of the application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a conventional multi-chip package structure. 2A to 2E are cross-sectional views showing the flow of a multi-wafer packaging process in accordance with a preferred embodiment of the present invention. 3A and 3B are schematic diagrams showing the method of wire bonding in the steps illustrated in FIGS. 2B and 2C. 4A and 4B are schematic views showing two steps that can be additionally performed after the step illustrated in Fig. 2E. FIG. 5 is a cross-sectional view showing a multi-chip package junction 17 1247366 13894 twf according to another preferred embodiment of the present invention. 6 is a cross-sectional view showing the structure of a stacked wafer in accordance with a preferred embodiment of the present invention. FIG. 7 is a cross-sectional view showing a multi-chip package structure according to still another preferred embodiment of the present invention. 8A-8F are schematic flow charts showing a multi-wafer packaging process according to still another preferred embodiment of the present invention. [Main component symbol description] 100: Multi-chip package structure 110: carrier 112, 114, 116: contact 118: line 120: first wafer 122: bump 130: second wafer 140: bonding wire 150: encapsulant 51 S3: active surface 52, S4: crystal back D1: arc height D2: distance 10: wire pin 200, 500, 700: multi-chip package structure 210: carrier 212, 214: contact 18 1247366 13894twf 220: first chip 222, 242: bump 230: adhesive layer 240 · second wafer 250: bonding wire 260, 520: encapsulant D10, D20: direction 280 · · third wafer 290 · · fourth wafer 510: primer 600: Stacked wafer structure 810 • First wafer 820: Second wafer 830: Wafer unit 55, S7 · Active surface 56, S8: Crystal back 19