TWI247358B - Etch stop layer of compound material in semiconductor manufacturing process - Google Patents

Etch stop layer of compound material in semiconductor manufacturing process Download PDF

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TWI247358B
TWI247358B TW90116659A TW90116659A TWI247358B TW I247358 B TWI247358 B TW I247358B TW 90116659 A TW90116659 A TW 90116659A TW 90116659 A TW90116659 A TW 90116659A TW I247358 B TWI247358 B TW I247358B
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Taiwan
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layer
etch stop
stop layer
dielectric
low
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TW90116659A
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Chinese (zh)
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Lian-Jong Li
Tien-I Bao
Shwang-Ming Jeng
Syun-Ming Jang
Jun-Lung Huang
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Taiwan Semiconductor Mfg
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Abstract

The present invention relates to a compound etch stop layer structure with low dielectric coefficient. The compound etch stop layer comprises a TEOS material layer, and one among silicon nitride, silicon carbide or silicon carbon nitride. The characteristics of compactness and low dielectric coefficient provided in TEOS material layer is not only used for a water-resistant film to improve the water absorption of porous and low-dielectric-coefficient material, but also possesses lower dielectric coefficient than the conventional etching stop layer material like silicon nitride, silicon carbide or a silicon carbon nitride. Therefore, the partial thickness of the conventional etch stop layer material is replaced by the TEOS material layer, and the dielectric coefficient of the overall etching stop layer is lowered. In addition, the TEOS material layer in the dielectric layer with low k value containing carbon, such as the tetramethylsilane, also has the effect of improving etching selectivity ratio and also effectively solves the problem of residual photoresist for double damascene process.

Description

1247358 五、發明說明(1) 發明領域 崖號 901166591247358 V. Description of invention (1) Field of invention Cliff number 90116659

本發明揭露一種有關於半導骰 於-種鋼製程中以複合材料做為=件製程,肖別是有關 兹,,ν扭^ 馬餘刻終止層進行雙鑲嵌製 魟,从提高低介電常數内連線介雷M 。^ < & ”晃層抗水分吸收之製程。 發明背景: 積 到高密 更是關 接金屬 現的重 相鄰導 所共知 線銅製 介電層 南速度 度及降 鍵,而 導線乃 要因素 線之間 ,此RC 程已有 改用低 ,也是 之製程 低單位 除了電 至内連 ,這是 會有電 值愈低 逐漸取 介電常 目前半 除了使得晶片内元件的體積小,以達 成本之目的之外,元件之最後的性能 晶體元件本身之設計外,最後之内連 線間介電層都是重要影響元件速度表 因導線之阻值R,與上、下層導線及 容C存在’一如熟悉相關技術之人士 代表較低之時間延遲,因此目前内連 代銘製程之趨勢,此外,將内連線間 數之介電層以使寄生電容降低,以提 導體業處理RC延遲的共識。 入不過,内連線介電層(inter level dielectric)除了 ”電層之介電常數k值是一考慮的重點外,製程的填隙能 力’平坦性、低溫的沉積能力、製程成本、防水性甚至於 和蝕刻終止層之接合能力(adhere abiHty)及内連線介電 層相對於餘刻終止層的蝕刻選擇比都是必須一併考慮的。The invention discloses a process in which a composite material is used as a part process in a semi-conducting steel-making process, and a double-inlaid system is used to improve the low dielectric state. The constant interconnect is mediated by M. ^ <& ” 层 抗 抗 抗 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 发明 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Between the factor lines, the RC process has been changed to low, and the low unit of the process is in addition to the power to the interconnect. This is because the lower the electric value, the more the dielectric is usually taken, the lower the size of the components in the wafer. In addition to the purpose of this, the final performance of the component is the design of the crystal component itself. The final inter-wiring dielectric layer is important to affect the component speedometer due to the resistance value of the wire, R, and the upper and lower wires and capacitance C. The existence of 'as familiar with the relevant technology represents a lower time delay, so the current trend of the internal process of the process, in addition, the dielectric layer between the interconnects to reduce the parasitic capacitance, to the conductor industry to deal with RC Delayed consensus. In addition, the interlevel dielectric (inter level dielectric) in addition to the "electrical layer dielectric constant k value is a key consideration, the process's interstitial ability 'flatness, low temperature deposition ability Manufacturing cost, and even waterproof bonding ability (adhere abiHty) etch stop layers and the interconnect dielectric layer with respect to the etch stop layer is engraved I are selectivity must also be considered.

第5頁 2005. 09.15. 006 1247358Page 5 2005. 09.15. 006 1247358

_案號 9011665Q 五、發明說明(2) /此’一,般不需藉助f裝輔助《冗積法沉積之高品質 CVD乳/匕曰一,部不適用於做為内連線介電層。因為沉積的 溫度二i南而不能和金屬導線匹配。同樣地,⑯溫且不藉 助電漿辅助沉積的氧化卜往往由於太過於多孔性而容易 吸水而不適用。 习 、也因此,不同的低k值介電層將因應不同的製程條件 而為半導體業者所選用。舉例而言:有機旋塗式玻璃。“^^ on glass; SOG)就是已知具有低介電常數之材料,其具有 良好之間隙填補能力,但受到蝕刻電漿損傷後,防水能力 就會降低。此外,如以化學氣相沉積法沉積iL〇w κ材 料’例如正甲基石夕燒(tetramethy!Silane),由於不致於 一如SO G有吸水性的問題,且其介電常數不到3,僅2 · 9 5而 已,因此更是廣範使用於雙鑲嵌製程中之金屬内連線介電 層。/不過在進行雙鑲嵌製程時,由於進行雙鑲嵌製程時必 須形成餘刻終止層,以做為介層洞和導線溝渠同時 避免過度蝕刻的指標。 ' 對於銅製程而言,由於碳化矽或氮化矽或含氮碳化矽 都具有阻障銅進入氧化性的介電層中,因此,很自然地為 公認之触刻終止層。然而含碳的值介電層,例如正甲 基矽烷相對上述習知蝕刻終止層面言,蝕刻選擇性較差。 餘刻選擇比(約5 : 1 )要比siLK( —種由Dow Chemical Company所生產的低介電值介電材料)對Sic之蝕刻選擇比 來得差_ Case No. 9011665Q V. Invention Description (2) / This one, generally do not need to use f-assisted "high-quality CVD milk / 匕曰 one deposited by the redundancy method, the Ministry does not apply to the interconnect layer . Because the temperature of the deposition is two, it cannot match the metal wire. Similarly, an oxidation bake that is 16 warm and does not aid in the deposition of plasma is often too water-absorbent and is not suitable for water absorption. Therefore, different low-k dielectric layers will be chosen for semiconductor manufacturers in response to different process conditions. For example: organic spin-on glass. "^^ on glass; SOG) is a material known to have a low dielectric constant, which has a good gap filling ability, but the water resistance is reduced after being damaged by the etching plasma. In addition, by chemical vapor deposition Depositing iL〇w κ material 'such as tetramethy! Silane, because it does not have the problem of water absorption as SO G, and its dielectric constant is less than 3, only 2 · 9 5 , so It is widely used in the metal interconnection layer of the dual damascene process. However, in the double damascene process, the residual termination layer must be formed during the dual damascene process to serve as the via hole and the wire trench. At the same time, avoid the indicator of over-etching. 'For the copper process, since tantalum carbide or tantalum nitride or niobium-containing niobium carbide has barrier copper into the oxidized dielectric layer, it is naturally recognized as a tentacles. However, a carbon-containing dielectric layer, such as n-methyldecane, has a poorer etch selectivity than the conventional etch termination layer described above. The coercive selection ratio (about 5:1) is better than the siLK (of the Dow Chemical Company). Production of low media Electrical value dielectric material) Sic etching selection ratio is poor

1247358 ---J號_年月日 倐正___ 五、發明說明(3) (約20: 1)。此外,Si LK則類似有機SOG具有低介電常數之 材料’具有良好之間隙填補能力。但受到餘刻電聚損傷 後’防水能力就會降低,此外當元件彼覆的是3 i LK時,散 熱性也是個問題。 八基於上述問題與傳統解決方法的不理想,例如低!^值 介電層的吸水性與傳統蝕刻終止層搭配時不能提供對低k =介,層的吸水性提供改善。能提供抗水性的氮ς石夕]卻 於冋介電常數的窘境。本發明將針對上述問題提.供一 新之解決方法。 ’、^ 發明目的及概述: 複合蝕刻終 蝕刻終止層 本發明目的係提供一種應用於銅製程中之 止層結構,具有改善低介電常數介電層與習知 搭配時抗水性不佳及介電常數高的問題。、 做路銅製程且以低介電常數介電; -種。對於銅製程而言,一 ^厚乳化石夕其中之 氮化石夕做為钱刻終止層是必要的:因:::也=石夕或碳 層。但上述氮化矽、碳化矽或 :;2夺$疋鋼的阻障 加強(如碳化矽或碳氮化矽)二 ==疋抗水性有待 高。 )就疋介電常數(如氮化矽)太1247358 ---J No. _ Year Month Day 倐正___ V. Invention Description (3) (about 20: 1). In addition, Si LK is similar to organic SOG materials with low dielectric constants, which have good gap filling ability. However, the waterproof ability is reduced after being damaged by the residual electro-polymerization, and the heat dissipation is also a problem when the component is covered with 3 i LK. Eight is based on the above problems and the conventional solution is not ideal, such as low value of the dielectric layer of the water absorption and the traditional etch stop layer can not provide the improvement of the water absorption of the layer. Nitrogen can provide water resistance, but it is in the dilemma of dielectric constant. The present invention will provide a solution to the above problems. ', ^ Object and Summary of the Invention: Composite Etching Final Etch Stop Layer The object of the present invention is to provide a stop layer structure for use in a copper process, which has improved water resistance and dielectric constant when improving a low dielectric constant dielectric layer and a conventional combination. High problem. , making a copper process and dielectrically with a low dielectric constant; For the copper process, a thick emulsified stone eve is necessary for the nitrite as a money stop: because::: also = Shi Xi or carbon layer. However, the above-mentioned tantalum nitride, tantalum carbide or the barrier of strengthening the steel (such as tantalum carbide or niobium carbonitride) two == water resistance needs to be high. ) the dielectric constant (such as tantalum nitride) is too

第7頁 1247358Page 7 1247358

藉由本發明複合姓刻終止層結構中之TEOS材料層所具 有的緻密性及低介電常數的特性,不但可做為抗水膜,二 改善多孔性低介電常數的吸水性,且由於TE0S材料層具有 較習知蝕刻終止層材料如氮化矽、碳化矽或碳氮化石夕更低 的介電常數。因此,以TE0S材料層取代部分習知蝕刻終止 層材料的厚度可降低整體蝕刻終止層的介電常數。此外, TE0S材料層在含碳之低k值介電層,如正曱基石夕烷 (tetramethylsilane)反也有改善蝕刻選擇比的效果。 此外’當TE0S材料層為複合蝕刻終止層的上層時,若 此複合姓刻終止層係做為雙鑲嵌製程的蝕刻終止層時,也 具有防止因光阻渣(scum)致使雙鑲嵌製程中介層洞不能 利形成的問題。 、 發明詳細說明: 有鑑=如發明背景所述,基於上述介電層及蝕刻終止 二:間的杬水性、介電常數與彼此的蝕刻選擇比,每每呈 相,制的關係,對於製程參數的容忍度而言,相當不 發明將提供上述問題的一種簡易的解決方式。 石々Γ ς ^發明的方法係改變銅製程中傳統蝕刻終止層以氮化 (心單或碳化石夕層(SiC)或含氣碳化石夕層 --_1中之一早層餘刻終止層不管是氮化矽(SiNX)或碳By virtue of the compactness and low dielectric constant of the TEOS material layer in the composite surrogate layer structure of the present invention, not only can it be used as a water-resistant film, but also improve the water absorption of the porous low dielectric constant, and due to TEOS The material layer has a lower dielectric constant than conventional etch stop layer materials such as tantalum nitride, tantalum carbide or carbonitride. Therefore, replacing the thickness of the conventional etch stop layer material with a TEOS material layer can lower the dielectric constant of the overall etch stop layer. In addition, the TE0S material layer also has an effect of improving the etching selectivity ratio in a low-k dielectric layer containing carbon, such as tetramethylsilane. In addition, when the TE0S material layer is the upper layer of the composite etch stop layer, if the composite surname termination layer is used as the etch stop layer of the dual damascene process, it also prevents the double damascene process interposer from being caused by the photoresist scum. The problem that the hole can't be formed. DETAILED DESCRIPTION OF THE INVENTION: According to the background of the invention, based on the dielectric layer and the etch stop two: the water repellency, the dielectric constant and the etching selectivity ratio of each other, each phase, the relationship, for the process parameters In terms of tolerance, it is quite an inconvenient solution to provide the above problems. 々Γ 々Γ ς ^ Invented method to change the traditional etch stop layer in the copper process to nitride (heart singular or carbonized stone layer (SiC) Is tantalum nitride (SiNX) or carbon

11^1 第8頁 2005. 09.15. 〇〇9 124735811^1 Page 8 2005. 09.15. 〇〇9 1247358

化矽層(SiC)或含氮碳化矽層(Si CN)老r夂士 A 1 抗水性佳、介電常數高 常數的優勢但防水性、 佳,如碳化石夕層。 和:出以氮化石夕+碳化石夕之複合鍅 這種複合層仍屬介電常數偏 k刻終 的餘刻 習知技術雖也有提出 止層的概念。不過,這種 終止層。本發明所是出的是一種複合式蝕刻終止層結: 可以選自以TEOS (tetraethylorthosilicate)或稱^ (tetraethoxyethoxysilane) Si(〇c2H5)4 的材料層與碳化石< 層複合層,或TE0S層與含碳氮化矽層(SiCN)複合 去 TE0S層與氮化矽層複合層等其中的一種。上述的以卯層 f約為複合式钱刻終止層結構的2 〇 %至8 〇 %,平均值約各 當複合層提供為低介電常數(或稱低k值)介電層蝕刻 =終止層,以提高低k值介電層之抗水性時,則te〇s層與 1n、XJ)或妷化矽層(Si C)或含氮碳化矽層(SiCN)其中之一種 =f ΐ合#刻終止層結構時並不限定沉積之的先後順序, 對&南防水性都有效。 ,了解TEOS層的確有優於碳化石夕或氮石夕氧化層,發明 a祕^以下的防水性試驗。由於矽氟鍵結(Si—F)對水氣極 "I ’例如當以傅利葉轉換紅外綠公FT T 基The bismuth layer (SiC) or the niobium-containing niobium carbide layer (Si CN) is a good water resistance and a high dielectric constant. However, it is excellent in water repellency, such as a carbonized stone layer. And: The combination of Nitride eve + Carbonized Fossil 夕 This composite layer is still the moment of the dielectric constant bias k. The conventional technique also has the concept of a stop layer. However, this termination layer. The present invention is a composite etch stop layer junction: it may be selected from TEOS (tetraethylorthosilicate) or tetraethoxyethoxysilane Si (〇c2H5) 4 material layer and carbon carbide layer composite layer, or TE0S layer And a carbonitride layer (SiCN) is combined to remove one of a TEOS layer and a tantalum nitride layer. The above-mentioned layer f is approximately 2% to 8% of the structure of the composite layer, and the average value is approximately as the low dielectric constant (or low-k value) dielectric layer etching = termination. When the layer is used to improve the water resistance of the low-k dielectric layer, the te〇s layer is combined with 1n, XJ) or bismuth telluride layer (Si C) or nitrogen-containing tantalum carbide layer (SiCN) = f #刻End layer structure does not limit the order of deposition, and is effective for & south waterproofing. It is understood that the TEOS layer does have a water repellency test which is superior to the carbonized stone or the nitrogen oxide layer. Since the fluorinated bond (Si-F) to the water vapor electrode "I ’, for example, when the Fourier transform infrared green FT T base

1247358 ____案號90116659 年月日 絛正_ 五、發明說明(6) 若有吸水現象,波數將產生位移。因此,首先將依序沉積 厚約1 # m的含FSG(氟摻雜矽酸玻璃)層及鈦刻終止層(es) 於矽基板上,接著,以進行標準壓力烹煮試驗(stan(iard pressure cook test;簡稱PCT)測試水滲透的情況(壓力約 2大氣壓,並以約1 1 〇 °c的水蒸氣灌入水氣) 接著,再以FT IR頻譜分析儀分析Si-F鍵之振盪頻 率。如圖一所示之曲線即為各種不同材質之ES對3丨—F鍵 波數的影響。其詳細的波數記錄則如圖二A所示。 由圖二A所示的表格中可以發現,未進行pct之前, FSG上未覆蓋ES層或者有ES層Si-F鍵波數約為9 39.33 1。 而若已進行PCT,則FSG上未覆蓋ES層或FSG上覆蓋PE0X層 或覆蓋SiC層,表現相同,都有7· 71 5/cm的波數位移。而 或FSG上覆蓋PESiN層’情況較佳,僅有i.929/cm的波數 位移。最佳的情況是FSG上覆蓋PETE0S層則無位移。由上 述的分析結果,若將量度誤差也一併加以考慮,可得到以 下的抗水性排行:1247358 ____ Case No. 90116659 Date of the month 绦正_ 5, invention description (6) If there is water absorption, the wave number will be displaced. Therefore, first, a FSG (fluorine-doped bismuth silicate glass) layer and a titanium engraved layer (es) having a thickness of about 1 #m are sequentially deposited on the ruthenium substrate, followed by a standard pressure cook test (stan(iard) Pressure cook test (referred to as PCT) to test the water infiltration (pressure about 2 atmospheres, and water vapor into the water vapor of about 1 1 〇 °c) Then, analyze the oscillation frequency of Si-F bond with FT IR spectrum analyzer The curve shown in Figure 1 is the effect of ES of different materials on the wave number of 3丨-F key. The detailed wave number record is shown in Figure 2A. It can be shown in the table shown in Figure 2A. It is found that before the pct is performed, the ES layer is not covered on the FSG or the Si-F key wave number of the ES layer is about 9 39.33 1. If the PCT has been performed, the ES layer is not covered on the FSG or the PE0X layer is covered or covered on the FSG. The SiC layer has the same performance and has a wavenumber displacement of 7.71 5/cm. Or the FSG covers the PESiN layer. The case is better, only the wavenumber displacement of i.929/cm. The best case is on the FSG. There is no displacement when covering the PETE0S layer. From the above analysis results, if the measurement error is also taken into consideration, the following water resistance can be obtained. ranking:

SiN 〜PETEOS>SiC>SiCN 〜SilaneOX 因此,由上述實驗結果得知PET EOS和PESiN有相近的 抗水性’但以介電常數考量,顯然的,以k值比較觀點, 利用TE0S和SiC或TE0S和SiCN相結合的複合層,顯然優於 S i C結合S i N。而S i C N的防水性能力僅和石夕甲烧相當。SiN ~ PETEOS > SiC > SiCN ~ SilaneOX Therefore, from the above experimental results, it is known that PET EOS and PESiN have similar water resistance 'but considering the dielectric constant, obviously, using the value of k value comparison, using TEOS and SiC or TEOS and The SiCN-bonded composite layer is clearly superior to S i C in combination with S i N. The water resistance of S i C N is only comparable to that of Shi Xijia.

第10頁 2005. 09.15.011 案號 90116659 1247358 修正 曰 Λ_Ά 五、發明說明(7) 圖一Β則示0.13/zm銅製程在第七層内連線完成對第五層以 comb-meander方法量電容值之結果。縱列三攔分別為^行 化學/機械式研磨製程後、以4〇〇 °c的合金去水分、及又經 歷三天後的情況。由電量的表現,也可發現本發明的複合 蝕刻終止層結構確有防有效果,而習知單層蝕刻終止層的 S i C則相反有吸水現象(電容值升高)。 除此之外,發明人研究發現,本發明以TE0S和31(:複 合蝕刻終止層與Si C單層蝕刻終止層比較顯示,te〇S和SiC 複合蝕刻終止層蝕刻蝕刻選擇比約為5 · 5 : 1比S i C單層蝕刻 終止層(蝕刻選擇比約為5 : 1 )更佳。 本發明的複合蝕刻終止層結構的另一好處是防止光阻 殘渣形成於雙鑲嵌製程中介層洞上方或稱為光阻毒害 (photoresist poi soning)的現象。 請參考圖三所示的橫截面示意圖。當一半導體基板在 進行雙鑲嵌製程以連接被介電層所覆蓋的元件時,如圖示 圖號5係厚約50至1 OOnm之蝕刻終止層,圖號2為導線。圖 號10係CVD低k值含碳介電層。當介層洞15藉由光阻圖 案為罩幕蝕刻後,再定義一溝渠圖案(如虛線30A)所示, 此時係先以一光阻3 0形成於介電層1 0上並填滿整個介層洞 1 5,再以微影技術進行曝光與顯影以形成光阻圖案。但實 際上常發現光阻結塊3 5形成於介層洞1 5内。這塊結塊阻塞 了介層洞,導致蝕刻導線溝渠時,原介層洞又被塞住。此Page 10 2005. 09.15.011 Case No. 90116659 1247358 Revision 曰Λ _ Ά V. Invention Description (7) Figure 1 shows that the 0.13/zm copper process is connected in the seventh layer to the fifth layer by the comb-meander method. The result of the capacitance value. The three columns in the column are the conditions after the chemical/mechanical polishing process, the alloy is dehydrated at 4 ° C, and the weather is three days later. It can also be seen from the performance of the electric quantity that the composite etch stop layer structure of the present invention is effective, and the S i C of the conventional single-layer etch stop layer has a water absorption phenomenon (increased capacitance value). In addition, the inventors have found that the present invention compares TEOS and 31 (the composite etch stop layer with the Si C single layer etch stop layer, and the te 〇 S and SiC composite etch stop layer etch etch selection ratio is about 5 · 5:1 is better than the S i C single-layer etch stop layer (etch selection ratio is about 5:1). Another advantage of the composite etch stop layer structure of the present invention is to prevent photoresist residue from being formed in the dual damascene process interposer. Above or referred to as photoresist poi soning. Please refer to the cross-sectional schematic shown in Figure 3. When a semiconductor substrate is in a dual damascene process to connect the components covered by the dielectric layer, as shown Figure 5 is an etch stop layer with a thickness of about 50 to 100 nm, and Figure 2 is a wire. Figure 10 is a CVD low-k carbon-containing dielectric layer. When the via 15 is masked by a photoresist pattern Then, a trench pattern (as shown by the dashed line 30A) is defined. In this case, a photoresist 30 is formed on the dielectric layer 10 and fills the entire via 15 , and then exposed by lithography. Developing to form a photoresist pattern. However, it is often found that the photoresist agglomerate 35 is formed in the via layer. Inside hole 1 5. This agglomerate blocks the via hole, causing the original via hole to be plugged again when etching the wire trench.

第11頁 2005. 09.15.012 1247358Page 11 2005. 09.15.012 1247358

五、發明說明 即為光阻毒害。 發明人分析其產生的原因,係習知蝕刻終止層,例 沉積碳化石夕層或含氮碳化石夕層,通常需要以氨氣為前Π 體’將造成ΝΗΧ ’其中X介於2·5-3·5之間。而使得氨氣存= 於蝕刻終止層内,另一情況係以含氨氣的電漿處理以提古 奴化石夕層和導線5的接合性。因此,將會使得碳化石夕層含^ 有〜义。這些ΝΗΧ卻會在形成光阻時擴散上來而和光阻^二 用而結塊。而微影曝光時該處因又屬於離焦(def〇cus)位 置(導線溝渠定義之光阻,而致不能完全顯影,而阻塞了 介層洞。 本發明使用了複合蝕刻終止層,則可以防止上述pR 毒害問題的發生。此時,TEOS需形成於碳化矽或含氮碳化 矽層上。由於TEOS具有高緻密性。將足以阻擋上述氮或氨 擴肜上來而導致光阻產生殘渣(PR SCUM)的問題。 以上所述僅為本發明之較佳實施例而已,並非用以限 定本發明之申請專利範圍;凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾,均應包含在下述之申嘖 專利範圍内。例如上述的實施例係以化學氣相沉積法沉^ 的TEOS材料層做為複合蝕刻終止層其中之一層,此為本發 明的最佳實施例。本發明的次佳實施例係以其他電聚輔^ 化學氣相沉積法沉積的緻密的氧化層做為複合蝕刻終止層 其中之一。 、曰V. Description of the invention It is a photoresist poison. The inventors analyzed the reason for the occurrence of the etch stop layer, such as depositing a carbonized stone layer or a nitrogen-containing carbonized stone layer, which usually requires ammonia gas as the precursor ' 'will cause ΝΗΧ ' where X is between 2. 5 Between -3·5. The ammonia gas is stored in the etch stop layer, and the other case is treated with an ammonia-containing plasma to improve the bondability of the corrugated fossil layer and the wire 5. Therefore, it will make the carbonized stone layer contain the meaning of ~. These defects will spread out when forming a photoresist and will be agglomerated with the photoresist. In the case of lithography exposure, the def〇cus position (the photoresist defined by the wire trench) cannot be completely developed, and the via hole is blocked. The present invention uses a composite etch stop layer. To prevent the occurrence of the above pR poisoning problem. At this time, TEOS needs to be formed on the tantalum carbide or niobium carbide layer. Because TEOS has high density, it will be enough to block the above nitrogen or ammonia expansion and lead to photoresist residue (PR). The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; any other equivalent changes or modifications made without departing from the spirit of the present invention, It is intended to be included in the scope of the following claims. For example, the above embodiment is a layer of a TEOS material deposited by chemical vapor deposition as one of the composite etch stop layers, which is a preferred embodiment of the present invention. A sub-optimal embodiment of the present invention is a dense oxide layer deposited by other electro-chemical vapor deposition as one of the composite etch stop layers.

第12頁 20〇5. 09.15. 013 1247358 ___案號90116659_年月日 修正_ 圖式簡單說明 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述: 圖一顯示以FT IR頻譜分析儀分析含氟矽酸玻璃在各種 不同材質之ES覆蓋下Si-F鍵之振盪頻率。 圖二A顯示依據圖一之結果以表格列出s丨—F PCT後與未進行PCT之波數比較圖。 牧選行 圖二B顯示0· 13 //m銅製程在第七層内連線完 層以comb-meander方法量電容值之結果。 战對第五 圖三顯示傳統製程,光阻將因ΝΗχ和光阻的 無法顯影’造成介層洞阻塞的問題。 用結i鬼而 元件符號對照表: 2導線 5 蝕刻終止層 10 CVD低k值含碳介電層 15介層洞 35溝渠圖案 30光阻Page 12 20〇5. 09.15. 013 1247358 ___ Case No. 90116659_Yearly Date Correction _ BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be explained in more detail in the following description with the following figures. : Figure 1 shows the oscillating frequency of Si-F bonds of fluorine-containing bismuth silicate glass under various ES coatings with different materials. Figure 2A shows a graph comparing the wave numbers of PCT and PCT without the PCT according to the results of Figure 1. Pastoral row Figure 2B shows the result of measuring the capacitance value of the 0·13 //m copper process in the seventh layer by the comb-meander method. The battle against the fifth figure shows the traditional process, the photoresist will be blocked due to the inability of the ΝΗχ and the photoresist to develop. Use the i ghost and the component symbol comparison table: 2 wire 5 etch stop layer 10 CVD low-k carbon-containing dielectric layer 15 via hole 35 trench pattern 30 photoresist

Claims (1)

1247358 」多正 ----ί^Μΐ6659_ 年 月 日 六、申請專利範圍 H f:於低介電常數介電層之複合材料蝕刻終止層杜 構,該結構至少包含· 、〜、、、《 一TEOS層及一選自由含氮碳化矽層、碳化 、 組其中之一所組成的複合材料形:於包含 士電⑦數;丨電層之半導體基板上以做為餘刻終止層,1 以EOS層的厚度約為該複合材料蝕刻 ^ 20%-80%。 1尽登骽厚度的 2中範圍第1項之複合材料蝕刻終止層結構,其 :十述之低,電常數介電層至少包含具有碳摻雜的介電 中n: 士 2範圍第1項之複合材料蝕刻終止層結構,其 介”數以層至少形成於一導線層上且被該低 4合材二:2阻毒害之應用於低介電常數介電層之複 〇材枓蝕刻終止層結構;該結構至少包含: 氮化成於一選自由含氮碳化矽層、碳化矽層、 低介電;數介電:群ί其中之一的材料層上且形成於包含 中層之半導體基板上以做為蝕刻終止層,其 2〇= 厚度約為該複合材料餘刻終止層整體厚度的1247358 ”多正---- ί^Μΐ6659_ 约月日日, application patent scope H f: composite etch stop layer of low dielectric constant dielectric layer, the structure contains at least ·, ~,,, a TEOS layer and a composite material selected from the group consisting of a nitrogen-containing tantalum carbide layer, carbonization, and one of the group: on a semiconductor substrate comprising a number of electrodes; a semiconductor substrate on the tantalum layer as a residual stop layer, 1 The thickness of the EOS layer is about 20%-80% of the etching of the composite. 1 The composite etch stop layer structure of the first item of the second range of thickness 2, which is described as follows: the dielectric constant layer contains at least a dielectric having carbon doping: n: the range of the second item Composite etch stop layer structure, which is formed by at least one layer formed on a wire layer and which is applied to the low dielectric constant dielectric layer by the low 4 material 2:2 resistance a layer structure; the structure at least comprising: nitriding on a material layer selected from the group consisting of a nitrogen-containing tantalum carbide layer, a tantalum carbide layer, a low dielectric layer, a dielectric layer: a group, and formed on a semiconductor substrate including a middle layer As an etch stop layer, the thickness of 2 〇 = is about the thickness of the composite layer 2005. 09.15. 0152005. 09.15. 015
TW90116659A 2001-07-06 2001-07-06 Etch stop layer of compound material in semiconductor manufacturing process TWI247358B (en)

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