TWI244691B - Process for polishing a semiconductor wafer - Google Patents
Process for polishing a semiconductor wafer Download PDFInfo
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- TWI244691B TWI244691B TW093113373A TW93113373A TWI244691B TW I244691 B TWI244691 B TW I244691B TW 093113373 A TW093113373 A TW 093113373A TW 93113373 A TW93113373 A TW 93113373A TW I244691 B TWI244691 B TW I244691B
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- Prior art keywords
- polishing
- semiconductor wafer
- disc
- cloth
- wafer
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- 238000005498 polishing Methods 0.000 title claims abstract description 125
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004744 fabric Substances 0.000 claims abstract description 33
- 239000012530 fluid Substances 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 238000005520 cutting process Methods 0.000 claims description 15
- 238000007517 polishing process Methods 0.000 claims description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 description 75
- 239000000463 material Substances 0.000 description 9
- 238000005259 measurement Methods 0.000 description 7
- 238000000227 grinding Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004575 stone Substances 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000004698 Polyethylene Substances 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- -1 polyethylene Polymers 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- 229920002635 polyurethane Polymers 0.000 description 2
- 239000004814 polyurethane Substances 0.000 description 2
- BWHMMNNQKKPAPP-UHFFFAOYSA-L potassium carbonate Chemical compound [K+].[K+].[O-]C([O-])=O BWHMMNNQKKPAPP-UHFFFAOYSA-L 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 241000283690 Bos taurus Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229920001328 Polyvinylidene chloride Polymers 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 240000008708 Vanda coerulea Species 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000003287 bathing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229920001903 high density polyethylene Polymers 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 238000005065 mining Methods 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000005033 polyvinylidene chloride Substances 0.000 description 1
- 229910000027 potassium carbonate Inorganic materials 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 238000007619 statistical method Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000008400 supply water Substances 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
- 239000003643 water by type Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
- B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
1244691 發明說明（1) —、【發明所屬之技術領域】 預定適用於製作線寬低於或等於〇 .丨 邊乃所習知之半導體晶圓奈米位相。$重要< 純 ，，奈米禮材料」（湖）對，，奈米位相”或 办門、、念真二9 η \疋義疋：整個晶圓正面之平坦化偏差在 二間波長0 · 2至2 0公厘（側而相關 ^ 區"内（FCU .固定、翁田 相關長度）圍内並位於"適用 面接Q \ Ϊ區域；產品規範所要求特性之表面 =必須合格）。奈米位相之量測係藉整個晶圓表面之完 =描及利用不同大小量測場（面積；範圍）之重疊。在該 内t發現表面内高度變化(峰至谷)可超過整個晶 51所要求之取大值。量測場之大小視規範而定，舉例言之 ，經界定為2x 2平方公厘、5χ 5平方公厘及1〇χ 1〇平^公 厘。 …半導體晶圓之最終奈米位相係由拋光加工形成。為改 良半導體晶圓之平整度，用以同時拋光半導體晶圓正、反 兩面之器具及方法均日益進步並持續發展。 二、【先前技術】1244691 Description of the invention (1) — [Technical field to which the invention belongs] It is intended to be suitable for making nanometer phases of semiconductor wafers with line widths less than or equal to 0. 丨. $ Important, Pure, Nano-materials (Lake) Pair, Nano-phase ”OR Gate, Ninzhen II 9 η \ 疋 义 疋: The flattening deviation of the entire wafer front is at two wavelengths 0 · 2 to 20 mm (within the relevant ^ area " inside (FCU. Fixed, Wengtian related length) and located in the " applicable surface then Q \ Ϊ area; the surface of the characteristic required by the product specification = must be qualified) The measurement of nanometer phase is based on the complete wafer surface = trace and overlap of measurement fields (area; range) with different sizes. It is found that the height change (peak to valley) in the surface can exceed the entire crystal. The larger value required by 51. The size of the measurement field depends on the specification. For example, it is defined as 2x 2 square millimeters, 5 × 5 square millimeters, and 10 × 10 square meters... The final nanometer phase of the circle is formed by polishing. In order to improve the flatness of the semiconductor wafer, the equipment and methods for polishing the front and back of the semiconductor wafer at the same time have been progressively improved and continuously developed. [Previous technology]
舉例言之，美國專利US 3 6 9 1 6 9 4中曾述及所謂之雙面 拋光。依照歐洲專利ΕΡ 208 3 1 5Β1中所述雙面拋光之具體 實施例，附有適當尺寸切割框之載具盤内之半導體晶圓係 在兩個覆以拋光布之旋轉拋光盤之間、在有拋光流體存在 之情況下、沿機器及加工參數所預定之路徑移動，因而加 以拋光（在專家文獻中，載具盤亦稱作模板）。By way of example, the so-called double-sided polishing is described in U.S. Patent No. 3,691,694. According to the specific embodiment of double-side polishing described in European patent EP 208 3 1 5B1, the semiconductor wafer in the carrier disc with the appropriate size cutting frame is between two rotating polishing discs covered with polishing cloth, between In the presence of a polishing fluid, it moves along a path predetermined by the machine and processing parameters, so it is polished (in expert literature, the carrier plate is also called a template).
第4頁 1244691 五、發明說明（2) 舉例言之，德國專利DE 1 0 0 045 78C1中曾述及··雙面 拋光步驟之實施係利用一由均勻、多孔聚合物泡棉製成、 硬度為60至90(蕭耳A)之拋光布。該文獻亦曾揭示：附在 上拋光盤之拋光布具有凹槽網，附在下拋光盤之拋光布則 無任何該種質地。該量測之目的是：其一，確保拋光過程 中所用拋光研磨劑之均勻分佈，其二，防止拋光工作完成 後上拋光盤舉起時半導體晶圓黏附在上拋光布上。 為實施雙面拋光，半導體晶圓係以適當方法置入載具 盤（托運板）内之切割框中，俾半導體晶圓之背面係立於下 拋光盤上。所以，在拋光過程中，半導體晶圓之背面係由 黏附在下拋光盤上之無紋路拋光布拋光，半導體晶圓之正 面係由黏附在上拋光盤上之有紋路拋光布拋光。該半導體 之正面係預定在其上面製作電子元件之表面。拋光步驟之 後’該等半導體晶圓通常係轉移至一水浴内，例如：藉助 於一真空吸氣裝置。 既有技術之此種方法不能滿足：實施雙面拋光供未來 世代元件、有關半導體晶圓曰益增加之要求。所以，本發 明之目的係提供一種方法，該方法可製得一具有改良奈米 位相之半導體晶圓，俾可滿足製作特殊需要元件之要求。 三、【發明内容】 本發明之内容係一種拋光半導體晶圓之方法，該方法 可達成拋光半導體晶圓之改良奈米構形。此類半導體晶圓 適用於半導體工業，尤其適用於電子元件之製作。 本發明之技術内容是：一種在供有拋光流體之情況下Page 41244691 V. Description of the invention (2) For example, the German patent DE 1 0 0 045 78C1 described the implementation of the double-sided polishing step by using a uniform, porous polymer foam with hardness A polishing cloth of 60 to 90 (Shore A). The document also revealed that the polishing cloth attached to the upper polishing disc has a grooved mesh, and the polishing cloth attached to the lower polishing disc does not have any such texture. The purpose of this measurement is: first, to ensure the uniform distribution of the polishing abrasive used in the polishing process, and second, to prevent the semiconductor wafer from sticking to the upper polishing cloth when the upper polishing disc is lifted after the polishing work is completed. In order to perform double-sided polishing, the semiconductor wafer is placed in a cutting frame in a carrier plate (conveyor board) by an appropriate method, and the back side of the semiconductor wafer is erected on the lower polishing plate. Therefore, during the polishing process, the back surface of the semiconductor wafer is polished by a non-textured polishing cloth adhered to the lower polishing disc, and the front surface of the semiconductor wafer is polished by a textured polishing cloth adhered to the upper polishing disc. The front side of the semiconductor is a surface on which electronic components are intended to be formed. After the polishing step, the semiconductor wafers are usually transferred to a water bath, for example, by means of a vacuum getter. This method of the existing technology cannot meet the requirements of implementing double-sided polishing for future generations of components and increasing the benefits of semiconductor wafers. Therefore, it is an object of the present invention to provide a method which can produce a semiconductor wafer having an improved nanophase, and can satisfy the requirements for manufacturing components with special needs. 3. Summary of the Invention The content of the present invention is a method for polishing a semiconductor wafer, which can achieve an improved nano configuration of polishing a semiconductor wafer. This type of semiconductor wafer is suitable for the semiconductor industry, especially for the manufacture of electronic components. The technical content of the present invention is: when a polishing fluid is supplied
第5頁 1244691 五、發明說明（3) 、於兩個覆以拋光布之旋轉拋光盤之間同時拋光半導體晶 圓正面及背面之方法，下拋光盤之抛光布具有一平、、骨表面 及上抛光盤之抛光布之表面由凹槽加以間隔，半導體曰圓 係位於一載具切割框内且固定在一界定之幾何路彳查上，其 中’在拋光過程中，半導體晶圓之正面係與下拋光盤之拋 光布接觸，而在拋光過程中，半導體晶圓之背面係^上拋 光盤之拋光布接觸。 〃 四、【實施方式】 、 加工之起始產品係以習知方法自一晶體分割而成之半 導體晶圓，例如：自一矽晶體分離出來，經切成_定長度 ’並藉研磨加以圓邊，其正面及/或背面業經藉助於研磨 或精研步驟加以切削。半導體晶圓之邊緣亦可在加工順序 之某處藉助於一適當分佈之研磨輪加以磨圓。再者，繼研 磨步驟之後亦可將半導體晶圓之表面加以蝕刻。 依照本發明，準備實施雙面拋光時，以適當之方式， 將半導體晶圓置入載具（托運板）之切割框内，俾其正面支 撐在下拋光盤之拋光布上。所以，在實施雙面拋光之過程 中半導體晶圓之正面係與下拋光盤之平滑拋光布接觸， 而半導體晶圓之背面係與上拋光盤之有紋路拋光布接觸。 否則’雙面抛光加工係依照精於此項技術者習知之方式實 施〇 、 本方法所得最終產品係業經實施雙面拋光及業經獲致 大幅改良奈米位相之半導體晶圓。 原則上本發明之方法可用以製造晶圓形狀之物體，該Page 51244691 V. Description of the invention (3) Method for simultaneously polishing the front and back of a semiconductor wafer between two rotating polishing discs covered with a polishing cloth. The polishing cloth of the lower polishing disc has a flat surface, a bone surface and an upper surface. The surface of the polishing cloth of the polishing disc is spaced by grooves. The semiconductor circle is located in a cutting frame of the carrier and fixed on a defined geometric pattern. Among them, 'the surface of the semiconductor wafer is connected to The polishing cloth of the lower polishing disc is in contact, and during the polishing process, the back surface of the semiconductor wafer is in contact with the polishing cloth of the upper polishing disc.实施 IV. [Embodiment] The starting product of processing is a semiconductor wafer divided from a crystal by conventional methods, for example, it is separated from a silicon crystal, cut into a _ fixed length, and rounded by grinding. Edges, whose front and / or back sides are cut by means of grinding or lapping steps. The edges of the semiconductor wafer can also be rounded somewhere in the processing sequence by means of a suitably distributed grinding wheel. Furthermore, the surface of the semiconductor wafer may be etched after the grinding step. According to the present invention, when double-side polishing is to be performed, a semiconductor wafer is placed in a cutting frame of a carrier (conveyor board) in an appropriate manner, and its front surface is supported on a polishing cloth of a lower polishing disc. Therefore, in the process of performing double-side polishing, the front surface of the semiconductor wafer is in contact with the smooth polishing cloth of the lower polishing disc, and the back surface of the semiconductor wafer is in contact with the textured polishing cloth of the upper polishing disc. Otherwise, the double-side polishing process is performed in a manner familiar to those skilled in the art. The final product obtained by this method is a semiconductor wafer that has undergone double-side polishing and has been substantially improved in nanophase. In principle, the method of the invention can be used to make wafer-shaped objects.
第6頁 1244691 五、發明說明（4) $ =體係由使用常用化學—機械雙面拋光方法可以加工之 豆;、'' 二二成舉例s之，此類材料（半導體工業主要實施 /、、 , 且不限於此種特殊應用場合）包含：石夕、 ^鍺一氧化矽、氮化矽、砷化鎵及其他冚—v半導體。 動式之石夕(例如：藉左科拉斯基拉晶法或浮 佳。尤以具有（100)、⑴0)或 」nn本方法尤其特別適於製造直徑2 0 0公厘、300公厘、 f /ifoo及^5+〇公厘及厚度自數百微米至數公分（尤以40 0微 米至1200微米更祛、+ ^ 作製作半導體元件之之夕Ba®。該等半導體晶圓可直接用 拋光步驟之後及/或智二'料，或依照既有技術實施最終 矽或其他適當半導體材If/·/層（❹：f面密封層或用 藉助於熱處理實施調；塗層)之後及/或 兹藉製造石夕晶圓為供作預定之用途。 ^ P1I, ^ ®為例，將本發明方法作進一步說明。 及鑛割方法種法㈣丨而成及（視直徑 區域之石夕晶圓可直接^/ϋ。晶格子深達1 〇至4 〇微米 在實施雙面拋光之前，最二二轭以雙面拋光步驟。但’ 輪）將清晰界定及（戶斤以）機^助f適#外形之研磨盤（砂 圓。再者，為改良幾饤;Λ鬲度敏感之晶圓邊緣加以磨 該矽晶圓施以機械研磨牛 移除又扣日日體層，可對 本發明拋光步驟内之如··精研或研磨），以減低 難免受損之晶圓表面及邊之=日為移除機械加工步驟内 緣之、、、〇日日區域及移除可能出現之Page 61244691 V. Description of the invention (4) $ = The system can be processed by common chemical-mechanical double-side polishing methods; '' 22% are examples of such materials (mainly implemented in the semiconductor industry / ,, And is not limited to such special applications) including: Shi Xi, ^ GeSi, SiN, GaAs, and other 冚 -v semiconductors. Moving stone eve (for example: by using the left Kolaskira crystal method or Fujia. Especially with (100), ⑴0) or "nn" This method is particularly suitable for making diameters of 200 mm, 300 mm , F / ifoo and ^ 5 + 0 mm and thickness from hundreds of microns to a few centimeters (especially from 400 microns to 1200 microns), + ^ is used to make semiconductor components Ba®. These semiconductor wafers can be Directly after the polishing step and / or Chi'er material, or after the implementation of the final silicon or other appropriate semiconductor material if / · / layer (❹: f-side sealing layer or adjustment by heat treatment; coating) according to the existing technology And / or hereby manufacture Shi Xi wafer for intended use. ^ P1I, ^ ® as an example, the method of the present invention will be further explained. And the method of mining and cutting method and the (depending on the diameter of the stone in the area) Even the wafer can be directly ^ / ϋ. The crystal lattice depth is 10 to 40 microns. Before the double-sided polishing is performed, the second and second yokes are double-sided polished. But the 'round' will be clearly defined and ^ 助 fsuit # Shaped grinding disc (sand round. Furthermore, to improve the wafer edge, the silicon wafer is polished to improve the sensitivity. Mechanical polishing cattle is used to remove and deduct the solar body layer, which can be used in the polishing step of the present invention (such as lapping or grinding) to reduce the surface and edges of the wafer that are unavoidably damaged. Fate ,,, and 0-day zones and removals may occur
1244691 發明說明（5) 任何雜貝（例如.文扣部分連在—起之金屬雜質），此處可 繼之以蝕刻步驟。該蝕刻步驟之實施方式可以是··於一鹼 性或酸性蝕刻混合物内矽晶圓之湯化學處理或電漿處理。 舉例言之，美國電腦製造公司（IBM)技術報告以 22. 234 2中曾述及一種可商購、適當尺寸之雙面拋光機， =面拋光機可用以實施本發明之拋光步驟。該拋光機主1244691 Description of the invention (5) Any miscellaneous shells (for example, metal impurities connected to the buckle part) can be followed by an etching step. The embodiment of the etching step may be a chemical treatment or a plasma treatment of the silicon wafer in a basic or acidic etching mixture. For example, a technical report of the United States Computer Manufacturing Company (IBM) as 22.234 2 described a commercially available, double-sided polishing machine of an appropriate size. A surface polishing machine can be used to implement the polishing step of the present invention. The polisher master
括：一下拋光盤（可在水平面上自由旋轉），及一上拋 士 1、可在水平面上自由旋轉），該等拋光盤均經覆以拋光 布’並且可對半導體晶圓（此處即矽晶圓）之兩面施以材料 移除拋光作用，同時連續供以適當化學組成物之拋光流體 可 同時抛 定。該 拋光機 具有足 銷齒輪 一通常 ，因而 拋 徑之參 光盤、 矽 曰曰 多矽晶 能僅拋光 光多個石夕 等矽晶圓 及載具盤 以容納石夕 傳動或漸 反向（對） 載具盤在 光操作過 數實例包 下拋光盤 圓，矽晶 圓偏心地 一個矽晶 晶圓為佳 係固定在 在拋光過 晶圓尺寸 開線齒輪 轉動外銷 兩個抛光 程中，影 含：拋光 及載具盤 圓則沿圍 安置在一 圓。但，通常，為節省成本，以 ’貫際數目則視拋光機之結構而 一幾何形狀路徑上，該路徑係由 程中之加工參數界定，該載具盤 之切割框。舉例言之，藉助於針 傳動（經由一轉動内銷或齒環及 或齒環）使載具盤與拋光機接觸 盤之間旋轉運動。 響石夕晶圓相關上及下拋光盤之路 盤之尺寸’載具盤之設計及上拋 之轉速。若載具盤之中央總是有 繞抛光機中心之圓環移動。若許 載具盤内’載具盤圍繞本身軸線 1244691 五、發明說明（6) 之轉動則形成一内擺線路徑。 =為佳。尤以同時使用四至六個二先力:工以内擺線 有至少三個石夕晶圓、間隔規律、配置；；路母：载具盤載 原則上，本發明方法所用載 仫上）更佳。 該等材料對驅動所引起機 ^ f/ 壬何材料製得， γ足夠之機械穩定性。再 1負; 體及抛光布之重大化學及機械侵室，以受所用拋 足夠使用壽命並防止拋光後矽晶圓遭i污毕：載具盤之 料必須適於製造高度平I、無應力及 伏：者，該材 期厚度及幾何形狀之載具盤。原則上：舉例：=、具有預 :盤可由金屬、塑膠、玻璃纖維強化 U塑 鋼製之載具盤更佳。 仏。尤以不銹 載具盤具有一個或更多個切割框 圓。為確保…可在 内自由移動，士刀割框之直#必須較待拋光石夕晶圓者略大。 以直徑略大〇. 1至2公厘為佳，尤以直徑略大〇. 3至丨3公厘 更佳。為防止拋光過程中晶圓邊緣遭受載具盤中切割框内 緣，傷，如歐洲專利EP 2083 1 5B1中所建議：切割框之内 側最好加上一層與載具盤同樣厚之塑膠襯墊。 如德國專利DE 1 990 573 7A1中所述，本發明拋光加工 所用載具盤之厚度以400至1 20 0微米為佳，尤以視經拋光 石夕晶圓之最終厚度而定則更佳。拋光步驟内之石夕移除量以 5至100微米為佳，但以丨〇微米至60微米較佳，尤以2〇至5〇 1244691 五、發明說明（7) 微米更佳。Including: a lower polishing disc (which can be rotated freely on the horizontal plane), and an upper polisher 1, which can be rotated freely on the horizontal plane), these polishing discs are covered with a polishing cloth 'and can be used for semiconductor wafers (here Silicon wafers) are applied with material removal and polishing on both sides, while a polishing fluid continuously supplied with an appropriate chemical composition can be simultaneously polished. The polishing machine has a pin gear, usually, so the diameter of the reference disc, the silicon wafer can polish only a plurality of silicon wafers such as Shi Xi and the carrier disc to accommodate Shi Xi transmission or gradually reverse (to ) The carrier disk is polished under the light operation example package. The silicon wafer is eccentrically. A silicon wafer is preferably fixed during the two polishing processes of the polished wafer size wire gear and the external pin. The shadow includes: Polished and carrier disc circles are placed in a circle along the circumference. However, generally, in order to save costs, the number of passes depends on the structure of the polishing machine and is on a geometric path, which is defined by the processing parameters in the process and the cutting frame of the carrier disc. By way of example, the carrier disc and the polishing machine contact disc are rotated by means of a needle drive (via a rotating internal pin or ring gear and / or ring gear). The size of the upper and lower polishing discs related to the Xiangshixi wafer is the design of the carrier disc and the rotation speed of the upper disc. If the center of the carrier disc always moves around the center of the polishing machine. If the 'tray' of the carrier disc is about its own axis 1244691 V. Description of the invention (6) The rotation will form an inner cycloid path. = Better. Especially using four to six two advance forces at the same time: the cycloid has at least three Shi Xi wafers within the industry, the interval is regular, and the configuration; the road mother: the carrier is mounted on the disk, in principle, the method used in the method of the present invention is better) . These materials are made of mechanical materials caused by driving, and have sufficient mechanical stability. 1 more negative; serious chemical and mechanical invasion of the body and the polishing cloth, in order to withstand the use of sufficient life and prevent silicon wafers from being polluted after polishing: the material of the carrier plate must be suitable for the manufacture of highly flat I, no stress And volts: the carrier plate of the thickness and geometry of the material period. In principle: For example: =, with a pre-: disc can be reinforced by metal, plastic, glass fiber U plastic steel carrier disc is better. Alas. Especially stainless carrier discs have one or more cutting frame circles. To ensure that ... can be moved freely within, the knife knife cutting frame of the straight # must be slightly larger than the person who is polishing the stone wafer. A slightly larger diameter of 0.1 to 2 mm is preferred, and a slightly larger diameter of 0.3 to 3 mm is more preferred. In order to prevent the edge of the wafer from being damaged by the inner edge of the cutting frame in the carrier plate during the polishing process, as suggested in European Patent EP 2083 1 5B1: It is best to add a layer of plastic liner as thick as the carrier plate inside the cutting frame. . As described in German Patent DE 1 990 573 7A1, the thickness of the carrier disk used in the polishing process of the present invention is preferably from 400 to 120 micrometers, especially depending on the final thickness of the polished wafer. The stone removal amount during the polishing step is preferably from 5 to 100 microns, but preferably from 0 to 60 microns, especially from 20 to 50 1244691. V. INTRODUCTION (7) Micron is better.
在有關正面朝下半導體晶圓定向所作說明之背景範圍 内’雙面拋光步驟最好係以精於此項技術者習知之方式實 施。具有廣泛性能範圍之拋光布均可商購。最好利用可商 購、硬度為40至120(蕭耳A)聚胺甲酸酯拋光布實施拋光作 用。尤以混以聚乙烯纖維、硬度為6 〇至9 〇 (蕭耳A )之聚胺 甲酸酯布料更佳。若係拋光矽晶圓類，建議連續供以酸度 值為9至12(尤以10至11更佳）、包括1至1〇%重量比（尤以1 至5 %重置比更佳）水中S i 〇2之抛光流體、拋光壓力以〇 . 〇 5至 0.5巴為佳，尤以0.1至〇·3巴更佳。石夕移除速率以至 1.5微米/分鐘為佳，尤以〇·4至〇·9微米/分鐘更佳。 將拋光後之半導體晶圓自下拋光盤上卸下時，最好將 该等半導體晶圓置於標準加工支架上，俾進一步將其加以 處理俾其表面在隨後之加工步驟中呈正確定向。與傳統雙 面拋光（其中半導體晶圓拋光時係正面朝上）相較，若容納 半導體晶圓之支架係配置得旋轉1 8 0。，則儘量避免需將半 導體晶圓旋轉1 8 0。。此項工作可用手動卸下或機器人自動 卸下均可獲得同樣優良效果。將半導體晶圓裝在下拋光盤 上時，此種性質之工作亦屬可能。Within the context of the description of face-down semiconductor wafer orientation, the 'double-side polishing step is preferably performed in a manner familiar to those skilled in the art. Polishing cloths with a wide range of properties are commercially available. The polishing is preferably performed using a commercially available polyurethane polishing cloth having a hardness of 40 to 120 (Shore A). Polyurethane cloth with a hardness of 60 to 90 (Shore A) mixed with polyethylene fibers is particularly preferred. For polishing silicon wafers, it is recommended to continuously supply water with an acidity value of 9 to 12 (especially 10 to 11), including 1 to 10% by weight (particularly 1 to 5% reset ratio) in water. The polishing fluid and polishing pressure of S i 〇 2 are preferably from 0.05 to 0.5 bar, and more preferably from 0.1 to 0.3 bar. The removal rate of Shi Xi is preferably 1.5 micrometers / minute, and more preferably 0.4 to 0.9 micrometers / minute. When removing polished semiconductor wafers from the lower polishing disc, it is best to place the semiconductor wafers on a standard processing stand and further process them so that their surfaces are oriented correctly in subsequent processing steps. Compared with the conventional double-sided polishing (where the semiconductor wafer is polished with its front side facing up), if the holder containing the semiconductor wafer is configured to rotate 180 °. , Try to avoid the need to rotate the semiconductor wafer by 180. . This work can be achieved by manual unloading or robotic unloading. This type of work is also possible when mounting a semiconductor wafer on a lower polishing disc.
拋光後之半導體晶圓可用手動或藉助於一自動移動（ 去除）裝置自下拋光盤上取下；在該兩種情況下，以使用 真空吸氣器具為佳。德國專利DE 1 9 958077Α1(第6頁，第 23至30行）曾述及一種適當之真空吸氣器具。自拋光盤上 取下之後’隶後將半導體晶圓送入一液體浴内（尤以水性The polished semiconductor wafer can be removed from the lower polishing disc manually or by means of an automatic moving (removing) device; in both cases, a vacuum suction device is preferred. German patent DE 1 9 958077 A1 (page 6, lines 23 to 30) describes a suitable vacuum suction device. After being removed from the polishing disc, the semiconductor wafer is then sent into a liquid bath (especially water-based
1244691 五、發明說明（8) 浴内更佳）。如此，則可有效地防止拋光研磨劑變乾及防 止真空吸氣器具或（一般名稱）卸除器材形成印記。 生抛光加工完成後，將任何附著之拋光流體自矽晶圓上 清洗掉並將晶圓烘乾。 視其進一步用途而定，該等晶圓之正面也許需要依照 既有技術施以最終拋光，例如··利用一柔軟拋光布及藉助 於一以S i 〇2為主要成分之鹼性拋光流體。 諸實驗例： 下列實驗例及比較例所使用者係一可商購、AC 2 0 0 0 =2型雙面拋光機，彼德、華特斯出品、倫茲堡、德國）。 _ 該拋光機裝有五個不銹鋼製、具有精研表面、厚度為72〇 微米之載具盤，每個載具盤具有六個内徑為2〇〇· 5公厘之 圓，切割框，該等切割框以等距配置在一圓形路徑上並襯 以聚二氣偏乙烯層，該機每批可同時拋光3〇個直徑2〇〇公 厘t矽晶圓。上、下拋光盤覆以可商購、羅德爾公司製、 商標2稱為SUBA 5 0 0、硬度為74(蕭耳A)、用聚乙烯纖維強 化之水胺曱酸g旨拋光布。緊繃於下拋光盤上之拋光布具有 3滑表面；緊繃於上拋光盤上之拋光布，其表面具有由壓 衣而成、見度1 · 5公厘及深度〇 · 5公厘、呈部分圓環狀之凹 槽所形成之棋盤狀圖案，該等凹槽之配置間距為3 〇公厘。_ 比較例 總是以手動方式將3 0個、具有蝕刻表面、直徑為2 0 0 么厘之石夕晶圓置入載具盤之切割框内，並使其正面朝下。 實施抛光加工時，連續供以水性拋光研磨劑（Levasi丨2〇〇1244691 V. Description of the invention (8) Better in the bath). In this way, it can effectively prevent the polishing abrasive from drying out and prevent the vacuum suction appliances or (general name) removal equipment from forming a mark. After the green polishing process is completed, any attached polishing fluid is cleaned from the silicon wafer and the wafer is dried. Depending on its further use, the front side of these wafers may need to be final polished in accordance with existing techniques, such as using a soft polishing cloth and with an alkaline polishing fluid containing Si02 as the main component. Experimental examples: The users of the following experimental examples and comparative examples are a commercially available, AC 20000 = 2 type double-sided polishing machine, produced by Peter, Waters, Rendsburg, Germany). _ This polishing machine is equipped with five stainless steel carrier discs with a polished surface and a thickness of 72 microns. Each carrier disc has six circles with a diameter of 20.5 mm and a cutting frame. The cutting frames are equidistantly arranged on a circular path and lined with a layer of polyvinylidene chloride. Each batch of the machine can simultaneously polish 30 silicon wafers with a diameter of 200 mm. The upper and lower polishing discs are coated with a commercially available polishing cloth made by Rodel Corporation under the trademark 2 called SUBA 50, having a hardness of 74 (Shore A), and reinforced with polyethylene fibers. The polishing cloth taut on the lower polishing disc has a 3-slip surface; the surface of the polishing cloth taut on the upper polishing disc is made by pressing, with a visibility of 1.5 mm and a depth of 0.5 mm, A checkerboard pattern formed by partially annular grooves, and the arrangement pitch of these grooves is 30 mm. _ Comparative Example Always place 30 Shixi wafers with an etched surface and a diameter of 2000 μm into the cutting frame of a carrier tray with the front side always. During the polishing process, water-based polishing abrasives (Levasi 丨 200) were continuously supplied.
12446911244691
，、拜耳公司出品，列佛庫森，德國），其固定s丨〇2固體含 莖為3 · 1 %重$比及其酸度值係藉添加碳酸鉀及氫氧化鉀而 設定在11. 4。。該拋光加工係在壓力〇·2巴及上、下拋光盤 溫度總疋3 8 C之情況下實施，其材料移除速率為〇 · 5 8微米 /分鐘。自晶圓每個面移除之矽為丨5微米。俟經拋光晶圓 之厚度達725微米之後，終止供應拋光研磨劑，並代之以 供應停止劑’歷時2分鐘。所用停止劑係日本藤見公司出 品、Glanzox 36 0 0型之1%重量比水溶液。俟停止步驟終止 之後’將设備打開，位於載具盤内之矽晶圓則完全由停止 液潤濕。利用可商購、彼德華爾特斯製之卸取站將矽晶圓 运至位於水浴内之框架内。之後，於一分批清洗設備内將 該等石夕晶圓烘乾，該設備之洗浴順序為：氫氧化四甲基銨 /¾¾ ; HF/HC1 ;臭氧；HC1及利用一可商賭之烘乾裝置並 依照瑪蘭格尼原理操作。經清洗晶圓之奈米位相係利用量 測場2公厘x2公厘（HCT 2><2)及10公厘χίο公厘（HCT 10 X 10)於一ADE SQM CR83裝置上量測。總計拋光1 96 8個矽 晶圓’隨後將其奈米位相加以鑑定。 實驗例 以類似於比較例之方法將總計2 1 5 7個、具有蝕刻表面 、直彳兰為2 0 〇公厘之矽晶圓加以處理。唯一與比較例不同 的疋·置入載具盤切割框之石夕晶圓，其正面係朝下’之後 沿此定向拋光。所得奈米值之統計分析結果如表内所示。, Produced by Bayer Corporation, Leverkusen, Germany), its fixed s0 02 solid stem with a weight ratio of 3.1% and its acidity value is set at 11.4 by adding potassium carbonate and potassium hydroxide . . The polishing process was carried out under a pressure of 0.2 bar and a temperature of the upper and lower polishing discs totaling 38 C, and its material removal rate was 0.58 micrometers / minute. The silicon removed from each side of the wafer is 5 microns. (2) After the thickness of the polished wafer reaches 725 m, the supply of the polishing abrasive is terminated, and the supply of the stopper is replaced for 2 minutes. The stopping agent used is a 1% by weight aqueous solution of Glanzox 3600 manufactured by Fujimi Corporation of Japan.之后 After the stop step is terminated ', the device is opened, and the silicon wafer in the carrier tray is completely wetted by the stop liquid. A commercially available, Peter Walters pick-up station is used to transport the silicon wafers into a frame located in a water bath. After that, the Shixi wafers are dried in a batch cleaning equipment. The bathing sequence of this equipment is: tetramethylammonium hydroxide / ¾¾; HF / HC1; ozone; HC1 and a commercially available baking oven. Dry the device and operate in accordance with Marangani principles. The nanometer phase system of the cleaned wafer was measured on a ADE SQM CR83 device using a measurement field of 2 mm x 2 mm (HCT 2 > < 2) and 10 mm x ίο mm (HCT 10 X 10). A total of 1,96 8 silicon wafers were polished 'and their nanophases were subsequently identified. Experimental Example In a manner similar to the comparative example, a total of 2 157 silicon wafers with an etched surface and a straight blue orchid of 200 mm were processed. The only difference from the comparative example is that the Shi Xi wafer, which is placed in a carrier disc cutting frame, has its front side facing down 'and is polished in this direction. The results of the statistical analysis of the obtained nano values are shown in the table.
1244691 五、發明說明（10) 比較例： 19 6 8個矽晶圓 實驗例： 2157個矽晶圓 量測場 HCT 2x2 HCT 10x10 HCT 2x2 HCT 10x10 平均 18.50 40.48 15.24 33.06 標準偏差 4.87 9.65 2.06 5.66 若該等矽晶圓係以正面朝下之方式拋光，由比較顯示 :對兩種尺寸之量測場而言，矽晶圓之奈米位相獲得大幅 改良。 ❿1244691 V. Description of the invention (10) Comparative example: 19 6 8 silicon wafers Experimental example: 2157 silicon wafers measurement field HCT 2x2 HCT 10x10 HCT 2x2 HCT 10x10 Average 18.50 40.48 15.24 33.06 Standard deviation 4.87 9.65 2.06 5.66 If this The silicon wafer is polished in a face-down manner, and the comparison shows that the nano-phase of the silicon wafer has been greatly improved for the measurement fields of two sizes. ❿
第13頁 1244691 圖式簡單說明 本申請案無圖式。 # 11111 第14頁Page 13 1244691 Schematic description There is no schema for this application. # 11111 Page 14
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| DE10321940 | 2003-05-15 |
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| TWI244691B true TWI244691B (en) | 2005-12-01 |
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| US (1) | US20040229548A1 (en) |
| JP (1) | JP2004343126A (en) |
| KR (1) | KR20040098559A (en) |
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| TW (1) | TWI244691B (en) |
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| JP4092993B2 (en) * | 2002-09-13 | 2008-05-28 | 信越半導体株式会社 | Single crystal growth method |
| DE202006004193U1 (en) * | 2006-03-14 | 2006-06-08 | Richter, Harald | Adapter plate for a vacuum suction device |
| DE102006032455A1 (en) * | 2006-07-13 | 2008-04-10 | Siltronic Ag | Method for simultaneous double-sided grinding of a plurality of semiconductor wafers and semiconductor wafer with excellent flatness |
| JP5401683B2 (en) * | 2008-08-01 | 2014-01-29 | 株式会社Ｓｕｍｃｏ | Double-sided mirror semiconductor wafer and method for manufacturing the same |
| DE102009025242B4 (en) * | 2009-06-17 | 2013-05-23 | Siltronic Ag | Method for two-sided chemical grinding of a semiconductor wafer |
| DE102009030292B4 (en) * | 2009-06-24 | 2011-12-01 | Siltronic Ag | Method for polishing both sides of a semiconductor wafer |
| WO2011083667A1 (en) * | 2010-01-05 | 2011-07-14 | 住友電気工業株式会社 | Method and apparatus for processing compound semiconductor wafer |
| DE102011083041B4 (en) * | 2010-10-20 | 2018-06-07 | Siltronic Ag | Support ring for supporting a semiconductor wafer of single crystal silicon during a heat treatment and method for heat treatment of such a semiconductor wafer using such a support ring |
| US10354905B2 (en) * | 2015-03-11 | 2019-07-16 | Nv Bekaert Sa | Carrier for temporary bonded wafers |
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| US3691694A (en) * | 1970-11-02 | 1972-09-19 | Ibm | Wafer polishing machine |
| JPH09270401A (en) * | 1996-01-31 | 1997-10-14 | Shin Etsu Handotai Co Ltd | Polishing method of semiconductor wafer |
| JP3664593B2 (en) * | 1998-11-06 | 2005-06-29 | 信越半導体株式会社 | Semiconductor wafer and manufacturing method thereof |
| US6227944B1 (en) * | 1999-03-25 | 2001-05-08 | Memc Electronics Materials, Inc. | Method for processing a semiconductor wafer |
| DE20004223U1 (en) * | 1999-10-29 | 2000-08-24 | Wolters Peter Werkzeugmasch | Device for removing semiconductor wafers from the rotor wafers in a double-sided polishing machine |
| US6376395B2 (en) * | 2000-01-11 | 2002-04-23 | Memc Electronic Materials, Inc. | Semiconductor wafer manufacturing process |
| US6376335B1 (en) * | 2000-02-17 | 2002-04-23 | Memc Electronic Materials, Inc. | Semiconductor wafer manufacturing process |
| US20010024877A1 (en) * | 2000-03-17 | 2001-09-27 | Krishna Vepa | Cluster tool systems and methods for processing wafers |
| DE10058305A1 (en) * | 2000-11-24 | 2002-06-06 | Wacker Siltronic Halbleitermat | Process for the surface polishing of silicon wafers |
| DE10117612B4 (en) * | 2001-04-07 | 2007-04-12 | Infineon Technologies Ag | polishing system |
| US6582279B1 (en) * | 2002-03-07 | 2003-06-24 | Hitachi Global Storage Technologies Netherlands B.V. | Apparatus and method for reclaiming a disk substrate for use in a data storage device |
-
2004
- 2004-05-12 TW TW093113373A patent/TWI244691B/en active
- 2004-05-12 KR KR1020040033533A patent/KR20040098559A/en not_active Application Discontinuation
- 2004-05-12 CN CNA2004100431526A patent/CN1610069A/en active Pending
- 2004-05-12 US US10/843,778 patent/US20040229548A1/en not_active Abandoned
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| US20040229548A1 (en) | 2004-11-18 |
| CN1610069A (en) | 2005-04-27 |
| JP2004343126A (en) | 2004-12-02 |
| KR20040098559A (en) | 2004-11-20 |
| TW200425322A (en) | 2004-11-16 |
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