1244001 玖、發明說明 【發明所屬之技術領域】 本發明是有關於一種仲裁器及其仲裁方法，且特別是有 關於一種應用於多裝置系統中，對各裝置發出的匯流排使用 請求進行快速有效地仲裁，從而提高匯流排效率的仲裁器 (Arbiter)及其仲裁方法。 【先前技術】 半導體產業的迅速發展大大推動了積體電路設計業的 發展，特別是半導體產業中，深次微米（DSM ; Deep Sub-Mi cron)技術的出現把單晶片系統 （System-on-Chip ; SoC)設計推到了積體電路設計的前沿。單晶片系統技術， 是把以前分散在多個不同的晶片上的多個處理器集合在同 一塊晶片上，以形成一個功能完善、性能優越的完整系統。 由於單晶片系統的物理面積和封裝針腳相對於多晶片系統 有大幅的減少，使得整個系統的生產成本也大幅降低。而另 一方面，系統中智財模組（Intellectual Property ; IP)的重複 使用也縮短了單晶片系統的設計週期，使系統的設計成本也 得以降低。 單晶片系統中可能包括各種處理器，如中央處理器 (CPU )、數位訊號處理器（DSP )和各種針對專門應用的 電路（ASIC )等，以及儲存單元（storage unit )，甚至可能 包括各種内建處理器核心（kernel)的子系統。整個系統規模 的擴大使系統的複雜性較之以前的多晶片系統高，因而如何 !2440〇1 合理有效地調節系統中各個處理器 整個系統設計過程中成為題統的運行，在 達成系統中各個處理器或者子==::構 的合力工作有著至關重要的影響。㈣又相於整個系統 在匯流排系統内多個裝置之間〃 發出請求，要长進彳-% ° 迗中，向匯流排 ^ 4求進㈣號傳送的| device);而主穿詈 勹王展置（master 屬裝置（siaved ⑼號料的目標裝置貞彳稱為從 萄及置（slavedevlee)。對於多裝置的通訊， 用仲裁器來對多個穿晉藤山 系、、先中採 據各種,、t v x 、匯流排使用請求作出判斷，根 據各種次异法決定給予匯流排佔有權的裝 ::置情況’目前匯流排架構主要分為兩大類，即：= ==ΓΓ其中分散式匯流排架構是對系統二 、卜： 對應的仲裁器，由各個仲裁器相互競爭來 二：由匿流排上哪-個裝置獲得授權而佔用匯流排 匯流排是指對於整個*** ^非，集中式 仲裁器根據預設的仲裁方:;斟用—個統一的仲裁器，由這個 置=理=出判斷’確定授權使用匯流排的裝 置。易於理解的是，胜如Η π 集中式匯流排“’仲裁器對匯 冰排使用效率有著決定性的作用。 現有技術中，一曰主姑 並獲得匯流排授權，：/主,仲裁器發出匯流排使用請求 〖扠％在该主裝置請求的傳送運算完成前，將 一直由該主裳置你古蹈、夫Μ 求則得不到回庫。因Γι 他主裝置提出的匯流排請 …口此，设計人員往往會對主裝置設置一定 7 1244001 的優先順序別，在仲裁器 序別較高的主裝置發出計:裁““、件下，優先順 應。也有的設計人員提出用請求能優先得到回 ,, 、 、I置叙出的匯流排使用請求分 級，仲裁器按各個匯流排使用請求的㈣ “疋支先做出回應的匯流排使用請求。但是仲裁 2裁時，若是同時對各個不同等級的匯流排使用請求奸 ::具將使仲裁器的硬體和演算法複雜化，並可能使仲裁週 期延長。1244001 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to an arbiter and its arbitration method, and more particularly, to an application in a multi-device system to quickly and effectively request the use of the bus from each device. Arbiter and its arbitration method to improve bus efficiency. [Previous technology] The rapid development of the semiconductor industry has greatly promoted the development of integrated circuit design industry, especially in the semiconductor industry, the emergence of deep sub-micron (DSM; Deep Sub-Mi cron) technology has brought single-chip systems (System-on- Chip; SoC) design is pushed to the forefront of integrated circuit design. The single-chip system technology is to integrate multiple processors that were previously scattered on multiple different chips on the same chip to form a complete system with complete functions and superior performance. Because the physical area and package pins of the single-chip system are greatly reduced compared to the multi-chip system, the production cost of the entire system is also greatly reduced. On the other hand, the reuse of Intellectual Property (IP) modules in the system also shortens the design cycle of single-chip systems and reduces the design cost of the system. The single-chip system may include various processors, such as a central processing unit (CPU), a digital signal processor (DSP), and various circuits (ASICs) for special applications, as well as a storage unit, and may even include various internal Build a processor core (kernel) subsystem. The expansion of the entire system scale makes the complexity of the system higher than the previous multi-chip system, so how! 2440001 Reasonably and effectively adjust the various processors in the system to become a unified operation in the entire system design process. The combined work of processors or sub == ::: constructs has a crucial impact. ㈣Compared with the entire system among multiple devices in the bus system, 〃 send a request to grow 彳-% ° ，, and ask the bus ^ 4 for the number to be transmitted | device); and the main wear Wang Zhanzhi (the target device of the master-owned device (siaved) is called slavedevlee. For multi-device communication, an arbiter is used to collect data from multiple Jinshan Mountains, Xianzhong schools Various, tvx, and bus use requests are used to make judgments, and devices based on various sub-laws are determined to give the bus ownership: :: Settings' The current bus architecture is mainly divided into two categories, namely: = == ΓΓ The bus architecture is for system two. The corresponding arbiters are competed by each arbiter. Second: which device on the bus is authorized to occupy the bus. Bus refers to the entire system, not centralized. The arbiter is based on a preset arbiter: a unified arbiter is used to determine which device is authorized to use the bus. It is easy to understand that it is better than Η π centralized bus " 'Arbiter arbitrates the exchange ice Efficiency has a decisive role. In the prior art, the master and the master obtained the authorization of the bus: / master, the arbiter issues a request for the use of the bus [fork%] until the transfer operation requested by the master device is completed, the master will always be the master You do n’t get back to the library if you want to perform the ancient dance and the husband ’s request. Because of the bus proposed by his master device, the designer often sets a priority order of 7 1244001 for the master device. The master device with a higher order issues a plan: "", the file, the priority is to comply. Some designers have also proposed to use the request to get back the priority, the bus use request graded by the arbiter, the arbiter according to each The request for the use of the bus: "The support responds to the request for the use of the bus first. However, if the arbitration is decided at the same time, if the request for the use of different levels of bus is used at the same time: :: The hardware and algorithm of the arbiter will be used. It complicates and may lengthen the arbitration period.
另一方面，對於支援分離式讀運算 transaction of 〇,· ,、 P gna)的匯流排系統，例如具有多個執 ;=e:d)的匿流排主裂置，某-主裝置的某-個執行緒 :此發出讀運算’而在與其運算相對應的從屬裝置做出回應 則也允μ主裝置的其他執行緒發出訊號傳送運算（ 當然也包括讀運算）。在产锸主 /、 等待f^ τ，可能有多個執行緒在 對應從屬裝置發出資料，而較早發出的讀運 ik屬裝置可能f要較長的資料準備時間，如果按讀 ，=出的先後次序進行資料回傳，必將影響其他執行緒的 頃運异：行。為了提高匯流排的使用效率，在設計中我們可 二允許讀數據越序回傳，即對於已準備好的讀數據，可 响發出項運算請求的先後次序，優先回傳。但是這 的:序：傳也有可能出現不同從屬裝置在同—時刻用匯= y l貝數據的情形，繼而引起讀數據在回傳時的彼此衝 犬。这樣反而會增加存取延€ ’並使匯流排#率降低。 本發明提出-種改良的仲裁器及其仲裁方法，既可進行 1244001 正向仲裁，又可進;^ & a yj_、 同的匯流排使用請求等級，』:在正向仲裁令’可以針對不 了乂對夕個從屬裝置的讀數據回傳的請求做出仲裁裁 【發明内容】 本發明的目的就是在提供一 方法，用以針對不同的「, 的仲裁器及其仲裁 裁時機，以提高仲裁^排使用請求等級而設立不同的仲 本發明的另高匯流排使用效率。 仲裁方法，該仲裁二右 供一種改良的仲裁器及其 效率的前提下，避免讀數據回傳的相互衝在突^⑸排使用 相連=2明之上述目的’匯流排系統包括分別與匯流排 流排使用裝置和仲裁器。主裝置向仲裁器發出匯 求授權，發明出==里過仲裁後，對選中的匯流排使用請 岸的勵二 求的主裝置便佔有匯流排與相 靖求可由^ 料傳送運算。主裝置發出的匯流排使用 =不=置成不同的優先等級’仲裁以仲裁狀態機 先順序的匯流排使用請求進行仲裁，：:^ 序較=匯流排使用請求；在間隔週期較長的仲裁時機，具 =二;=Γ排使用請求和具較低優先順序的匯流 F使用明求可同時由仲裁器進行仲裁。 根據本發明之另一目的，匯流排系統支援分離式的讀運 异，在不同的從屬震置同時發出回傳f料運算的匯流排使用 1244001 請求情況下，仲裁器根據—定的演曾 求進杆你 、％去對回傳資料運算的請 R進仃仲裁。在本發明的一個實 #的- 從屬裝置回傳資料、靈管认广T，由軟體配置對各個 衣罝W 1寻貝枓運异的匯流排使用凡〜 權等級，仲裁栌攄佟 明求，彡又疋不同的優先 Τ觀杰根據優先權等級來進行仲裁。 根據本發明的一個實施例，仲 置進行分声仲斿，π _ & 哉时對匯流排上的多個裝 丁刀層仲裁，對回應速度要求較低 裁模組中進行㈣，而對回應速度 ^ ^低級的仲 級的仲裁模組中r $,丨沾从1 車乂问的碩求和從較低 仃仲^裁盗包括第—階段仲 ： 組，相對地，仲裁器的仲裁運算包括笛二弟-p“又仲裁模 段仲裁。1摔作；^ gli > 弟愍段仲裁和第二階 -牛首先將匯流排系統中的主裝置進 步为成重要主裝置和次要主 戒置進 中，由仲裁fi ^ f ± "，在進行第二階段仲裁 田1r m态對夂要主裝置發出 裁，然後把仲裁結果送入第一階段仲;排=求先進行仲 所要做的，則是將第二階 ：階段仲裁 #置1出的匯流排㈣請求—起進行仲裁。 根據本黍明的一個實施例，在仲裁器 組中還進一步畔古 木 丨白奴仲裁模 各種… 式(η — )，可在篩檢程式中5置 各種不同的過遽單元（fiher u 叹置 八，/、仲裁。如在本發明的一個 有··從屬裝1忙碌狀能迅喷 、 ，即設 , 狀心過濾早兀，也就是說，暫時血法谁一 貝科傳送運算的從屬裝 去進仃 而匯流排使用… ”請給篩檢程式， 月、進灯仲裁前要先由篩檢程式進行判 1244001 斷，若資料傳送運算的目標從屬裝置為SBusy訊號所對應 的從屬裝置，則該匯流排使用請求將被忽略。又如在本發明 的另一個實施例中，為達成匯流排管線（pipeUne)仲裁而設 有最後請求控制過遽單元，使每個正在進行中的流脈衝 (Stream Burst)的最後一個時脈的請求被遮罩。再如在本發 明的另一個實施例中，設有配對讀寫運算過濾單元，在匯流 排處理配對的項寫運料’當匯流排作讀存取時，便使其處 於鎖定狀態’此時若有其他主裝置發出配對的讀寫運算匯流 排使用請求，將被忽略。 因此’本發明提出了 一種分級的仲裁時機，既提高了對 需優先回應的資料傳送運算的回應速度 率，繼而從整體上提高了匯流排效率。 中裁效 Μ 6 Θ Θ對支#分離式讀運算的匯流排系統提出了 回傳請求時，反向仲裁機：：屬4置同時：匯流排發出資料 流排堵塞的情形，因而：二避免：：貝料衝突而造成匯 率。 4另一方面提高了匯流排的使用效On the other hand, for a bus system that supports a separate read operation (transaction of 〇, ..., P gna), for example, a hidden bus main split with multiple executions; = e: d), a certain-a certain of the main device -A thread: This issue of a read operation 'and a response from a slave device corresponding to its operation also allows other threads of the μ master device to issue a signal transmission operation (including a read operation, of course). In the production master / waiting f ^ τ, there may be multiple threads sending data in the corresponding slave device, and the earlier read and read ik slave device may take longer data preparation time. If you press read, = output The sequence of data back will be different for other threads: line. In order to improve the use efficiency of the bus, in the design we can allow the read data to be sent out of order, that is, for the read data that has been prepared, the order of the item operation request can be sent, and the return is given priority. But this: Sequence: It is also possible for different slave devices to use sink = y lbe data at the same time, which may cause the read data to collide with each other when returning data. This will instead increase the access delay and reduce the bus # rate. The present invention proposes an improved arbiter and its arbitration method, which can perform both 1244001 forward arbitration and advancement; ^ & a yj_, the same bus use request level, ": in the forward arbitration order can be targeted I ca n’t make an arbitration ruling on a request to read back data from a slave device. [Summary of the Invention] The purpose of the present invention is to provide a method for different arbiters and their arbitration timing to improve The arbitration queue uses request levels to set up different high-efficiency bus utilization efficiency of the present invention. The arbitration method, the arbitration method provides an improved arbiter and its efficiency, avoiding conflicts between read data returns and conflicts ^ The use of the bus connection = 2 of the above purpose 'The bus system includes a bus device and an arbiter, respectively. The master device issues a request for authorization to the arbiter and invents == After arbitration, the selected The main device of the bus using the request of the bank will occupy the bus and the phase can be calculated by the data transmission. The bus issued by the main device uses = not = set to a different priority level. The arbitration of the bus use request in the order of the arbitration state machine: :: ^ sequence comparison = bus use request; in the arbitration time with a long interval, with = two; = Γ use request and with lower priority The bus F can be arbitrated by an arbiter at the same time. According to another object of the present invention, the bus system supports separate read and operation differences. In the case of the request, the arbiter requested you to perform the calculation according to the given performance, and to perform the calculation on the returned data, please R to perform arbitration. In a practical embodiment of the present invention-the slave device returns the data, and the control is recognized. T, the software configuration is used for each bus W1 to find different buses using different levels of power, the arbitration is explicitly required, and different priorities are determined according to the priority level. According to the invention In an embodiment, Zhong Zhi performs a split voice, and π _ & 仲裁 arbitrates multiple mounting knife layers on the bus, arbitrates the response speed in the module with lower response speed requirements, and responds to the response speed ^ ^ Lower level In the first-level arbitration module, r $, 丨 from the summation of 1 乂 乂 from the lower 裁 ^ arbitration includes the first stage-group: In contrast, the arbiter's arbitration operation includes Di Er-p "And arbitration module arbitration. 1 wrestling; ^ gli > junior arbitration and second order-Niu first improved the main device in the bus system into an important main device and a secondary main ring, and arbitrated fi ^ f ± " In the second stage of arbitration, the host device will issue a ruling, and then send the arbitration result to the first stage of the arbitration. To arrange for the first stage of arbitration, the second stage: stage arbitration # Set the bus request to 1 for arbitration. According to an embodiment of the present invention, in the arbiter group, there are various types of ancient wood 丨 white slave arbitration modes ... (η —), and a variety of different transition units (fiher u can be set in the screening program) Eighth, arbitration. If one of the present invention has a slave device, the busy device can quickly spray, that is, the center filter is early, that is, the slave device who temporarily calculates the blood is a Beco transfer. Go to the bus and use the bus ... "Please give the screening program. Before the arbitration of the month and the lamp, the screening program must judge the 1244001 interruption. If the target slave device for the data transfer operation is the slave device corresponding to the SBusy signal, then The bus use request will be ignored. As in another embodiment of the present invention, a final request control unit is provided to achieve the pipeline Une arbitration, so that each ongoing flow pulse ( Stream Burst) The last clock request is masked. For another example, in another embodiment of the present invention, a paired read-write operation filtering unit is provided, and the paired items are processed and written on the bus. Read access So that it is in a locked state. 'At this time, if another master device sends a paired read / write operation bus use request, it will be ignored. Therefore, the present invention proposes a hierarchical arbitration time, which improves the priority response The response speed rate of the data transfer operation improves the bus efficiency as a whole. The intermediate efficiency M 6 Θ Θ makes a return request to the bus system supporting the #separate read operation, and the reverse arbiter:: belongs to 4 sets at the same time: the bus sends out a situation where the data stream is blocked, so: two avoids: the conflict between the shell material and the exchange rate. 4 On the other hand, the use of the bus is improved
L貫施万式J 請參照第1圖甘一 統。該匯流排系統至小二示本發明—個實施例的匯流排系 排⑻相連的主包括一匯流排101’以及分別與匯流 105置Al02、主裝置B103、主裝置C104、 主叙置D 105、從屈骷 ^ Γ 108 ^ ^ S 、置A 106、從屬裝置B 107、從屬裝 置C 1 08和從屬裝番 代’衣 9。匯流排上設有仲裁器11 〇分別 1244001 與匯/瓜排上各裝置相連，用以對連 提出的匯流排使用請求做出仲裁。“排上的各裝置所 在具有多個主裝置單元的匯 中的幾個主裝置單& ，丨L排系統晨，可以將系統 在置早兀配置成一個匯流 —)，而這幾個主裝置單元 ：主#置(_er 裝置的-個執行緒伽ead)。 冉為《流排上的主 提前在-個匯流排上的主裝置内部進=的==!可 流排上仲裁器的使用效率。 仃仲裁，因而可提尚匯 在本實施例中，主奘罟Δ 裝…有2個執行緒:中：具=執行緒，匯流排主 他c或者是子***/ ^τΛ 緒可以是cpu、崎、 執行绪^ : 和主裝置D則不包含多個 ：l：,：：r^^CPU'DSP'ASIC--- 本實施例還將主裝晉公#舌庙 表置刀成重要主裝置和次要主裝置。主 政置A和主裝置b為重要主穿f 茺王展置，而主裝置C和主裝置1) 為次要主裝詈。一私而士 — t 古 又a，可以把對匯流排回應速度要求較 的凌fa又為重要主褒置，々σ需進行即時處王里的裝置等， ，把對回應速度要求不是太高的裝置設為次要主裝置。從屬 裝置可以是同步動態隨機存取記憶體（sdram)或直接記 憶體存取（DMA )等。 仲裁器對主裝置A、主裝置B、主裝置c和主裝置D 毛出的匯流排使用請求做出回應時，將通過AMNum訊號線 把回應的主裝置號碼送給對應的主裝置。對主裝置進行編碼 的代號分別對應如下：〇為主裝置A，丨為主裝置B，2為 12 1244001 主裝置C，3為主裝置D。此外，主裝置A和主裝置b分別 配有一條執行緒識別訊號線MthreadID。當主裝置A或主裝 置B中的某個執行緒發出匯流排使用請求得到仲裁器回應 時，仲裁器通過AMNum訊號線把回應的主裝置號碼送給對 應的主裝置，並同時通過MThreadID訊號線把相對應的執 行緒號碼傳送給該主裝置中相對應的執行緒。 主裳置與從屬裝置都分別設有各類訊號線與仲裁器相 連，用來傳送資料傳送運算中的各類控制訊號，如 訊號為主裝置送給仲裁器以請求從屬裝置的號碼。在本實施 例中，4個從屬裝置的編碼代號分別對應如下：〇為從屬參 置A’ 1為從屬裝置B，2為從屬裝置c，3為從屬裝置D。 主裝置發出的匯流排使用請求分成不同的級別，本實施 例中，每一主裝置有一 MReq匯流排請求訊號線與仲裁器相 連’ 5亥成號線傳送的MReq訊號可用來表示匯流排使用請求 的級別。通過MReq匯流排請求訊號線發出的MReq匯流排 使用請求訊號分成REQ、CREQ和LREQ三類，其解碼如下 表所示。 表1 MReq 訊號 說明 ~ 0 0 IDLE 無請求 0 1 REQ 一般讀寫請求 10 LREQ —---- —般和MCmd配合。如果MCmd為〇，是要求 LOCK的讀運算； t果MCmd為1，是解除LOCK的寫運曾。 13 1244001 11 CREQ —-~~~~— 強制性讀寫請求，具有比REQ更高的優先順 序° ~------- 其中MCmd為讀寫運算請求，低為讀，高為寫。 MReq匯流排使用請求訊號中，creq和LREQ 比REQ 優先順序要咼，因此，如果主裝置發出的MReq為CREQ或 LREQ，較之REQ往往能更快速地獲得回應。其中，ereq 的請求是一種配對的讀寫運算請求，它請求的是一個讀寫運 算的配對運算，由於該讀寫運算需要連續進行，而不能*** 其他的運算’因此將其設為一種優先順序別較高的請求。 MReq可以在每一次資料傳送時由編寫程式等方式靈 活設定，因此，主裝置發出的匯流排使用請求的優先權等級 可以按實際需求而決定。在其他實施例中，MReq的匯流排 使用請求訊號可以按需要設定一定的等級，其編碼也可隨之 改變’本技術領域人員對此應易於理解和實現。 在本實施例中，主裝置和從屬裝置之間還採用了 一種流 脈衝（Stream Burst)形式的資料傳送方式。這種資料傳送方 式可一次性地傳送大量資料，每次流脈衝傳送的資料中可包 括多個單一資料（Single)和多個脈衝資料（Burst)。同一個 流脈衝中的單一資料或一個完整的位址連續的脈衝資料可 稱為一個分段脈衝，而分段脈衝之間的位址可以不連續，在 本實施例中，一個流脈衝中的不同分段脈衝還可發送給不同 的目標從屬裝置。在本發明的實施例中，還可要求分段脈衝 的長度是2的整數次冪，且位址對齊。 14 l244〇〇l 相對於流脈衝形式的資料傳送，每一主裝置或主裝置中 的每—執行緒設有傳送狀態MLast訊號線，該訊號線中傳 运的，MLast訊號指出了該主裝置或主裝置中的該執行緒要 ^進^的貝7料冑送運算的狀態。本實施例中為流脈衝資料傳 逐運算定義了四種狀態’包括c〇NT，same，DIF]m〇 Μα 四類訊號，如表2中所示分別對其進行了編碼。 表2 一訊號 說明 上0 CONT 示一，分段脈衝沒有結束。 〇 1 —— J^AST 流脈衝 1 0 SAME 表不一個分段脈衝的結束，預告下一個分 ^^ 1 1 -------- 段脈衝和本分段脈衝存取同樣的從屬裝 置，且存取請求的等級相同（即都為REQ 或 CREQ) 〇 A 1 diff 表示一個分段脈衝的結束，預告下一個分 ^ ---- 段脈衝和本分段脈衝存取不同的從屬裝 取請求的等級不同。 ^—— 衝還在運算中，以C0NTm號來表示—個分段脈 完整的流脈衝已經傳送仲裁。而LAST訊號則表示-個 就需要仲裁”：元成’此時若要進行資料傳送運算， "重新對所有的匯流排使用請求做仲裁。 15 1244001 SAME和DIFF訊號均表示一個分段脈衝已經傳送完 成，而一個流脈衝尚未結束。其不同之處主要在於，8αμ"ε 訊號是用來預告下一個分段脈衝和本分段脈衝存取相同的 從屬裝置，只是位址和本分段脈衝可能不連續，並且下一個 分段脈衝和本分段脈衝存取請求的等級相同，即都為req 或CREQ等。DIFF訊號則是用來預告下—個分段脈衝和本 分段脈衝存取不同的從屬裝置，或者是下—個分段脈衝和本 分段脈衝存取請求的等級不相同。 同樣地，MLast的編碼也可根據實際需要的資料傳送 算狀態的種類做調整。 、田匯机排上的裝置要求使用匯流排進行資料傳送運曾 的:先=出匯流排使用請求給仲裁器，由仲裁器按照； 、次异/ 1斷出可優先進行的言奮求。本發明 ::::::正向仲裁和反向仲裁兩個部分。正向仲裁= : = 的匯流排使用請求進行仲裁;反向仲裁是指對 請求進行仲裁。因而要日傳貝枓而發出的匯流排使用 仲裁圖，本實施例中，仲裁器包括正向第二階段 組207':正Γ、正向第一階段仲裁模組202以及反向仲裁模 給相庫的主# ^ Π解碼5 206解碼後，送 二二Γ從屬裝置’·反向仲裁的各訊號經過反向解 :208解碼後，送給相對應的從屬 —階段仲裁模’组201是對次要 4置正向弟 求進行仲舞，£收、 哀置务出的匯流排使用請 ，：仲裁結果送入第一階段仲裁模組202,·第 16 1244001 一階段仲裁模組202則扣 求和笛-购机 、j把重要主裝置發出的匯流排使用請 j矛弟^ 一 p白段的伸與么士 | ^ ^ 、、、σ果一起進行仲裁。在其他實施例中， 也可癌略第二階段。 j τ ，第二階段仲裁模組不進行仲裁處理，即第二階段仲裁 ㈣大態時，正向仲裁的第二階段可開始進㈣ 處裁所'用的仲裁演算法可以是熟悉相關技術人員所知 :的各種廣#法。為簡單起見，在本實施例中，正向第二階 段仲裁模組是採用gj定優先權演算》（fixed pri〇dty g hm )進行仲裁，即對每_個次要主裝置設定一個確 定7優先權等級，在同一時間有兩個或兩個以上的次要主裝 置提出請求時，則選中優先順序別較高的主裝置進入第一階 段。如第3圖所示，主裝置c和主裝置〇為次要主裝置， 其優先權等級分別設定為1級和2級。主裝置C的訊號包 括MReq3 ’ MLast3和MDstnum3，分別指出請求的級別、 資料傳送狀態和目標從屬裝置的號碼，同樣地，主裝置D 的訊號包括MReq4，MLast4和MDstnum4。當主裝置c和 主裝置D同時提出匯流排使用請求時，根據優先權等級， 仲裁器將優先選中主裝置C提出的匯流排使用請求。在主 裝置C的匯流排使用請求響應結束後的時序裏，仲裁器將 對主裝置D此時的匯流排使用請求做出回應。第二階段仲 裁模組發出的仲裁訊號包括A2Req，A2Last、 A2Dstnum 和A2Mnum等，分別指示匯流排使用請求級別、資料傳送 狀態、目標從屬裝置號碼和回應的主裝置號碼。這些仲裁訊 號作為仲裁結果，送入第一階段仲裁模組參與仲裁。在本實 17 1244001 施例中，假定在第一 用請求參與仲裁n tb & *組仲裁時’無其他18流排使 先選中，則ά ^ —卩自段仲裁模組送出的仲裁結果被優 由向解碼器發出仲裁訊號’包括圖中所示的匯L Guan Shiwan Shi J Please refer to Figure 1 for the unified system. The busbar system to elementary two shows that the busbar system according to an embodiment of the present invention includes a busbar 101 ′, and a bus 105, an Al02, a main device B103, a main device C104, and a main device D105. , Cong Qukui ^ Γ 108 ^ ^ S, set A 106, slave device B 107, slave device C 108, and slave equipment Fan 'Yi 9. The bus is provided with an arbiter 11 〇 1244001 is connected to each device on the bus / melon to arbitrate the bus use request made by the company. "Each device on the row has several main unit orders in the sink with multiple main unit units, and the L-row system can be configured as a bus early in the morning.), And these main units Device unit: main #set (_er device's one thread gaad). Ran "The master on the bus advances in advance of the master on a bus ===! Can be streamed to the arbiter The efficiency of use. 仃 Arbitration, so it can be improved. In this embodiment, the main unit Δ is equipped with 2 threads: Medium: with = thread, the main bus c or subsystem / ^ τΛ can be It is cpu, saki, thread ^ :, and the main device D does not include multiple: l:, :: r ^^ CPU'DSP'ASIC --- In this embodiment, the main installation Jingong # Tongmiao table is also set with a knife Become an important main device and a secondary main device. The main device A and the main device b are important main wear f, and the main device C and the main device 1) are secondary main devices. A private person — t Gu Youa, you can set Ling fa, which has a relatively fast response speed on the bus, as an important main device. 々Σ needs to be installed in the real-time device, etc., and the response speed is not too high. The device is set as the secondary master device. The slave device can be synchronous dynamic random access memory (sdram) or direct memory access (DMA), etc. The arbiter controls the master device A, master device B, master device c, and master device. When the bus used by Device D responds to the request, it will send the number of the responding master device to the corresponding master device through the AMNum signal line. The codes that encode the master device correspond to the following: 0 Master device A, 丨Master device B, 2 is 12 1244001 Master device C, 3 is master device D. In addition, master device A and master device b are each equipped with a thread identification signal line MthreadID. When master device A or master device B When each thread sends a request for use of the bus to get a response from the arbiter, the arbiter sends the number of the responding master device to the corresponding master device through the AMNum signal line, and at the same time sends the corresponding thread number to the host through the MThreadID signal line Corresponding thread in the device. The master and slave devices are provided with various signal lines connected to the arbiter, which are used to transmit various control signals in the data transmission operation. For example, the signal is The device sends the arbiter to request the numbers of the slave devices. In this embodiment, the coding codes of the 4 slave devices correspond to the following: 0 is the slave parameter A ′ 1 is the slave device B, 2 is the slave device c, and 3 is Slave device D. The bus use request sent by the master device is divided into different levels. In this embodiment, each master device has a MReq bus request signal line connected to the arbiter. The MReq signal transmitted by the Hai Hai line can be used to indicate The level of the bus use request. The MReq bus use request signal sent through the MReq bus request signal line is divided into three types of REQ, CREQ and LREQ, and the decoding is shown in the following table. Table 1 MReq signal description ~ 0 0 IDLE No request 0 1 REQ General read and write request 10 LREQ —---- — Normally cooperate with MCmd. If MCmd is 0, it is a read operation that requires LOCK; if MCmd is 1, it is a write operation that releases LOCK. 13 1244001 11 CREQ —- ~~~~ — Mandatory read and write requests have a higher priority than REQ ° ~ ------- where MCmd is a read and write operation request, low is read, and high is write. In the MReq bus use request signal, creq and LREQ have higher priority than REQ. Therefore, if the MReq sent by the master device is CREQ or LREQ, the response is often faster than REQ. Among them, the ereq request is a paired read and write operation request. It requests a paired read and write operation. Because the read and write operation needs to be performed continuously and cannot be inserted into other operations, it is set as a priority order. Don't make higher requests. MReq can be flexibly set by programming and other methods at each data transmission. Therefore, the priority level of the bus use request issued by the master device can be determined according to actual needs. In other embodiments, the MReq bus use request signal can be set to a certain level as required, and its coding can be changed accordingly. Those skilled in the art should easily understand and implement this. In this embodiment, a data transmission method in the form of a stream burst (Stream Burst) is also used between the master device and the slave device. This data transmission method can transmit a large amount of data at one time, and the data transmitted by each stream pulse can include multiple single data (Single) and multiple pulse data (Burst). A single piece of data in the same stream pulse or a complete pulse with continuous address can be called a segmented pulse, and the addresses between the segmented pulses can be discontinuous. In this embodiment, the Different segmented pulses can also be sent to different target slaves. In the embodiment of the present invention, it is also required that the length of the segmented pulse is an integer power of two and the addresses are aligned. 14 1244. Compared to the data transmission in the form of stream pulse, each master device or each thread in the master device is provided with a transmission status MLast signal line. In the signal line, the MLast signal indicates the master device. Or the state of the thread in the host device that needs to be processed. In this embodiment, four states are defined for the streaming pulse data transmission operation, including four types of signals: coNT, same, DIF] m0 Mα, which are respectively encoded as shown in Table 2. Table 2 One-signal description The upper 0 CONT indicates one, the segmentation pulse is not over. 〇1 —— J ^ AST stream pulse 1 0 SAME indicates the end of a segmented pulse, foretelling the next segment ^^ 1 1 -------- The segmented pulse accesses the same slave device as this segmented pulse And the access request has the same level (that is, both REQ or CREQ) 〇A 1 diff indicates the end of a segmented pulse, foretelling the next minute ^ ---- The segmented pulse and this segmented pulse access different slave devices Fetch requests have different levels. ^ —— The impulse is still in operation, and it is represented by C0NTm—a segmented pulse. The complete stream pulse has been transmitted to arbitration. The LAST signal indicates that one needs arbitration ": Yuan Cheng 'if you want to perform data transfer operations at this time, " re-arbitrate all bus usage requests. 15 1244001 SAME and DIFF signals indicate that a segmentation pulse has been The transmission is complete, but a stream pulse has not ended. The main difference is that the 8αμ " ε signal is used to foretell the next sub-pulse and the sub-pulse accessing the same slave device, only the address and the sub-pulse. May be discontinuous, and the next segmented pulse and this segmented pulse access request have the same level, that is, req or CREQ, etc. The DIFF signal is used to predict the next segmented pulse and this segmented pulse access Different slave devices, or the next segmented pulse and the level of this segmented pulse access request are not the same. Similarly, the encoding of MLast can also be adjusted according to the type of data transmission calculation status actually required. The device on the bus requires the use of a bus for data transmission. First: the request for the use of the bus is sent to the arbiter, which is followed by the arbiter; Strive for words. The present invention :::::: two parts of forward arbitration and reverse arbitration. The bus of forward arbitration =: = uses request for arbitration; reverse arbitration refers to arbitration of request. Therefore The arbiter diagram is used for the buses sent by the Japanese company. In this embodiment, the arbiter includes a forward second phase group 207 ': positive Γ, a forward first phase arbitration module 202, and a reverse arbitration module. The master of the library # ^ Π decodes 5 206 after decoding, sends two two Γ slave devices'. Each signal of the reverse arbitration is reverse-resolved: 208 is decoded and sent to the corresponding slave-stage arbitration module. The secondary 4 is asking the younger to perform a secondary dance. Please use the bus for collection and resignation. The arbitration result is sent to the first stage arbitration module 202, and the 16th stage of the 124001 first stage arbitration module 202 is deducted. Summing up the flute-purchasing machine, and using the buses issued by important master devices, please use the spear ^ ^ a white segment of the extension with Mo Shi | ^ ^, ,, σ results in arbitration. In other embodiments, also The second stage of the cancer can be omitted. J τ, the second stage arbitration module does not perform arbitration processing, that is, the second stage In the general state, the second stage of forward arbitration can begin. The arbitration algorithm used by the arbitration tribunal can be a variety of methods known to those skilled in the relevant art. For simplicity, in this embodiment, The forward second-stage arbitration module is using arbitrated priority calculus (fixed pri 0dty g hm) for arbitration, that is, a certain 7 priority level is set for each _ secondary master device, and there are two at the same time. When two or more secondary master devices make a request, the master device with a higher priority is selected to enter the first stage. As shown in FIG. 3, the master device c and the master device 0 are secondary master devices. Its priority levels are set to 1 and 2 respectively. The signals of the master device C include MReq3 'MLast3 and MDstnum3, which indicate the requested level, data transmission status, and number of the target slave device. Similarly, the signals of the master device D include MReq4, MLast4, and MDstnum4. When the master device c and the master device D simultaneously submit a bus use request, according to the priority level, the arbiter will preferentially select the bus use request submitted by the master device C. At the timing after the response of the bus device use request from the master device C, the arbiter will respond to the bus use request from the master device D at this time. The arbitration signals issued by the second-stage arbitration module include A2Req, A2Last, A2Dstnum, and A2Mnum, etc., which indicate the bus usage request level, data transmission status, target slave device number, and responding master device number. These arbitration signals are sent to the first stage arbitration module to participate in arbitration as the result of arbitration. In the present embodiment of 171244001, it is assumed that in the first application request to participate in arbitration n tb & * group arbitration, 'no other 18 streamers will be selected first, then ^ — 卩 the arbitration result sent from the segment arbitration module Yuyou sends an arbitration signal to the decoder 'including the sink shown in the figure
:響= 和授權主裝置訊號AI 曰μ - C和主裝置D的匯流排使用請求。 长經W二仲裁的第階段首先要求所有需要參與仲裁的請 ===的筛檢程式⑹时筛檢程式會按照肅 夂盥二 的請求遮罩下來。而通過篩檢程式可繼續 ^、、的凊求則稱為有效請求。本實施例中，篩檢程式主 要包括三個過濾單元。 士第個疋k屬裝置忙碌狀態（SBusy )過濾單元，當匯 流錢用請求所存取的從屬裝置不處於忙碌狀態時，才可通 過筛檢程式’例如在本實施财，所存取的從屬裝置的接收 緩衝器要能接收主裝置發出的命令。對於這個過濾條件，本 實施例中每一個從屬$置都配置一健收緩衝器，用來接收 仲裁器發出的接收指令和相關資料。這裏所說的接收緩衝器 可以疋先進先出暫存器（FIF〇)。當從屬裝置緩衝器的剩餘 可用空間接近零，即緩衝器的剩餘空間只能支援一個脈衝資 料的長度或者是一個脈衝資料加丨個資料長度的長度時，由 α亥從屬咸置發出從屬裝置忙碌狀態訊號SBUSy訊號給仲裁 器’ SBusy訊號中指出該從屬裝置的號碼。 第二個為配對讀寫請求控制（LREQ )過濾單元，是針 對本實施例中的LREQ類型的匯流排使用請求的。對於一個 LREQ請求的讀存取，只當匯流排不處於鎖定狀態時才會予 18 1244001 以響應。匯流排如果虛於a ;鎖疋狀態，就要把這個lreq請求 的讀存取遮罩掉。在此，蹈、、ώ u i 〔Μ排處於鎖定狀態，就意味著先 前有其他的主裝置或直#搞> 、、 不直4八他執仃緒已經發出了一個LREQ請 求’並且該請求正在勃并綠 Μ 口貝運异。這樣就可以防止有新的 LREQ請求獲得匯流排授權 讲议％進仃躓存取運异，而使先前的 LREQ運算發生錯誤。 第三個過料元是最後請求控制過料元，可用來保證 匯流排系統能夠連續處理多個匯流排使用請求，而達到管線 ㈣仲裁的效果。對於每個正在傳送中的流脈衝的最 個時脈的請求’仲裁器需要判斷該流脈衝的資料傳送狀 悲訊號ALast訊號以確定下一個仲裁狀態，因此仲裁器要對 該流脈衝最後一個時脈的請求進行遮罩。 本發明的其他實施例中還可在篩檢程式中設置其他的 過濾單元。 請參照第4圖，仲裁器的筛檢程式4〇6設置了三個控制 埠，分別連接著從屬裝置忙碌狀態訊號線4〇2、匯流排=定 控制線403和最後請求控制訊號線4〇4。篩檢程式的輸入端 是來自主裝置的匯流排使用請求4〇1，篩檢程式的輸出端輸 出的是經過篩檢程式但未被遮罩掉的請求，稱為有效請求 4 0 5，仲裁益將採用仲裁演算法對有效請求進行仲裁。 第5-7圖分別是篩檢程式中三個過濾單元工作的示範 性時序圖。在SBusy過濾單元，仲裁器先將從各個從屬裝 置送到SBusy控制端的SBusy訊號鎖定後，篩檢程式再^ ά s月1j的SBusy §fL號和MDstnum訊號進行遮罩運瞀（历化 19 1244001 operation)，其中MDstnum訊號指出了該請求所要存取的從 屬裝置號碼。若MDstnum訊號所指示的從屬裝置號碼與 SBusy作用的從屬裝置相同，就表示該請求所存取的從屬裝 置當前無法接收命令，此時篩檢程式就遮罩該請求。請參照 第5圖，MReqO訊號為主裝置A發出的匯流排使用請求訊 號，MDstnum訊號指明該請求所要存取的從屬裝置， MVReqO訊號為經過篩檢程式後輸出的有效請求訊號。 SBusyO訊號在鎖定後的下一個時脈生效，使MReq〇對從屬 裝置A (對應的MDstnum訊號為〇 )存取的最後一個時脈 的運算被遮罩（即MVReqO為IDLE);而在對從屬裝置β (對應的MDstnum訊號為1 )的存取期間，篩檢程式未出 現生效的SBusyl訊號，因此對從屬裝置B的存取未受遮罩。 在匯流排鎖定控制過濾單元，是在匯流排鎖定控制端施 加一 ALock訊號，若匯流排處於鎖定狀態，則AL〇ck訊號 為咼，並與輸入端的MReq訊號做遮罩運算，如果匯流排在 鎖定狀態而MReq訊號顯示為LREQ，則篩檢程式將遮罩該 請求。在第6圖所示的實施例中，MReq〇和MCmd〇為主装 置A叙出的匯流排請求訊號；AReq和ACmd為仲裁器發 出的回應訊號，分別表示獲權請求的級別和讀寫狀況， ^Grant為仲裁器的授權訊號；MVReq〇為輸出端送出的主 衷置A的有效請求。在AGrant訊號為高期間，當為 類型，且ACmd為低（表示為讀請求）時，匯流排鎖 定控制端❸AL0Ck訊號為高；而ACmd為高（表示為寫請 求）時，匯流排鎖定控制端訊號為低。在AL〇ck訊號為^ 20 1244001 日寸，匯流排處於鎖定狀態，此時仲裁器將不對其他的[REq 的項運异進行仲裁。圖中MReq〇的第一個LREQ請求為讀 運算，而ALock訊號在這個LREQ請求的第一個時脈内為 咼，因此從MVReqO反映出來這個時脈内的LREQ就被遮 罩掉了。 對於最後請求控制過濾單元，本發明的一個實施例中對 於母個正在傳送中的流脈衝的最後—個時脈的請求，仲裁器 會結合AGrant、AMNum#仏“訊號一起進行判斷，當 AGrant訊號有效，而AMNum所指的是當前佔有匯流排: 行流脈衝傳送的主|置，且ALast指明該主裝置的請求已進 行到最後-個時脈的請求’仲裁器就把這個流脈衝最後一個 時脈的請求遮罩掉。請參照第7圖所示，通_訊號為主 裝置A發出的匯流排使用請求訊號，訊號表示仲裁 器對該匯流排請求訊號解碼後發出的資料傳送狀離 AMNum訊號時序可以看出當前正在佔有匯流排的為：裝置 圖中，MVReq0訊號的時序顯示出對應於仏 最後一個時脈的請求被遮罩了。 ° ^ 正向仲裁的第一階段並不是在任何時間都可進行新的 仲裁，而只是在滿足一定條件而允許仲裁的時 裁。-般情況下，第一階段可以進行 、此進灯仲 仲裁器處於間置狀態。本實施例中，仲裁器|條件是當前 訊號，當該訊號為IDLE時，表示仲教w ° /、了 Arb—state 即當前無正在進行中的仲裁=仲^當前處於閒置狀態， 第一階段的分級仲裁，在本實施例中，包括了啊仲 21 1244001 裁時機和CREQ仲裁時機。對應於這兩個仲裁時機，分別 設有AREQ_arb和ACREQ—arb仲裁時機控制訊號。 在本實施例中，採用的資料傳送方式為流脈衝形式，且 規定MLast訊號來代表主裝置給仲裁器的分段脈衝資料傳 送狀態碼。其中MLast訊號有三種值用來表示當前分段脈 衝已經結束：LAST表示一個完整的流脈衝已經結束；SAME 表示一個流脈衝尚未結束，當前分段脈衝已經結束，而下一 個分段脈衝存取的從屬裝置與當前分段脈衝相同；DIFF表 示一個流脈衝尚未結束，當前分段脈衝已經結束，而下一個 分段脈衝存取的從屬裝置與當前分段脈衝不相同。仲裁狀態 機中，在出現這三種分段脈衝結束碼時，才可能進入仲裁狀 態。在本實施例中，一個流脈衝過程只能被CREQ級別的 其他請求中斷，而REQ級別的其他請求是不能中斷一個流 脈衝的。在出現LAST訊號時，AREQ_arb訊號與ACREQ_arb 訊號同時有效；在出現 SAME或 DIFF訊號時，只有 ACREQ_arb訊號有效。 請參照第8圖，圖中以仲裁時機時序對此做了說明。在 主裝置發出的MLast訊號經仲裁器仲裁後，仲裁器的正向 解碼器會發出ALast訊號，對應於MLast訊號共有四類值， 即CONT、SAME、DIFF和LAST，可用來輔助判斷下一個 時脈仲裁器的仲裁狀態，以加快匯流排管線處理。圖中， ALast訊號有三個範例，分別為LAST、SAME和DIFF。LAST 訊號表示一個流脈衝結束，AREQ_arb和ACREQ—arb兩個 訊號同時有效；SAME和DIFF均只表示一個分段脈衝已經 22 1244001 結束，而流脈衝未結束，只有ACREQ_arb訊號有效。 ACREQ_arb訊號有效在流脈衝結束和流脈衝中的分段 脈衝結束時均出現，而AREQ_arb訊號有效僅在流脈衝結束 時出現，顯然，ACREQ—arb訊號有效比AREQ_arb訊號有 效出現得更為頻繁，換言之，CREQ仲裁時機的時間間隔比 REQ仲裁時機的時間間隔要短。 請參考第9圖與表3，本實施例的仲裁狀態機共包括三 個狀態：IDLE、ARBLEVEL1 和 ARBLEVEL2。ARBLEVEL1 和ARBLEVEL2分別為前文所述的REQ仲裁時機和CREQ 仲裁時機。以下說明請配合參照表3。 表3 條件1 沒有一個有效請求是CREQ或LREQ，至少有 1個有效請求是REQ 條件2 在AREQ_arb有效時，且沒有一個有效請求是 REQ、CREQ 或 LREQ 條件3 至少有1個有效請求是CREQ或LREQ 條件4 在ACREQ—arb有效時，且沒有一個有效請求 是 REQ、CREQ 或 LREQ 條件5 在ACREQ—arb有效且AREQ—arb無效時，至 少有1個有效請求是CREQ或LREQ，且記 AEnterST2 為 1 條件6 在ACREQ—arb有效時，且沒有一個有效請求 是 CREQ 或 LREQ，以及 AEnterST2 為 1，同 23 1244001 時把AEnterST2歸零 從第9圖的仲裁狀態機可以看到，仲裁器並不是在任何 時刻都進行仲裁的，只有在 ARBLEVEL1和 ARBLEVEL2 兩個狀態下才進行仲裁。當Arb_state訊號為IDLE，並且滿 足條件1，即只有REQ級別的有效請求而沒有CREQ或 LREQ級別的有效請求，同時AREQ—arb訊號有效時，仲裁 器進入ARBLEVEL1仲裁狀態。在ARBLEVEL1仲裁狀態 下，仲裁器可以對主裝置發出的REQ、CREQ和LREQ級別 的匯流排使用請求進行仲裁。當Arb —state訊號為IDLE，並 且滿足條件3，即只要有CREQ或LREQ級別的有效請求， 而無論是否有 REQ級別的有效請求，並且同時有 ACREQ—arb訊號有效，貝|J仲裁器進入ARBLEVEL2仲裁狀 態。在ARBLEVEL 2仲裁狀態下，仲裁器只對主裝置發出 的CREQ或LREQ級別的匯流排使用請求進行仲裁，而REQ 級別的匯流排使用請求不參與仲裁。 從第9圖也可以看到，仲裁狀態機中ARBLEVEL1和 ARBLEVEL2兩個狀態在一定的條件也可以相互轉換。因 此，在本實施例中，引入了 AEnterST2訊號，用來記錄被 中斷的仲裁狀態。當仲裁器正在ARBLEVEL1狀態下仲裁 時，由於出現較高級別的有效請求，如CREQ或LREQ請求， 需要轉換仲裁狀態到ARBLEVEL2狀態下，記AEnterST2 訊號為1。這樣，在AEnterST2訊號為1的情況下，就進入 ARBLEVEL2狀態直到當ARBLEVEL2狀態下的仲裁運算完 24 1244001 成後’此㈣只有REQ級別的有效請求而沒有其他c 或LREQ級別的有效請求，仲裁器將不進行重新仲 曰 返回到原先的仲裁狀態，並在返回的同時將Ah㈣Μ = 號歸零。在轉換仲裁狀態進行仲裁時，需要保留仲裁哭的内 部狀態（int⑽al state)，要保留的訊號量暫時放在緩 (滅e〇中’要保留的訊號量主要有仲裁器送給主裝置^ 應主裝置的號碼AMNum和仲裁器送給從屬裝置以回應從 屬裝置的號碼ASNum等。在從咖狀態直接轉= ARBLEVEL2狀態下時，當仲裁器完成細咖虹2狀能下 的仲裁任務後’㈣ϋ將重新對全部的有效請求進行仲裁。 *仲裁器進行仲裁過程中，在ACREQ—_訊號有效時， 若仲裁H是從ARBLEVEL1狀態下直接轉換到繼咖此2 狀態下’為防止有效的匯流排使用請求要存取的對應從屬裝 置超載’本實施例中再次以從屬裝置忙綠狀態訊號沾叩 訊號作為判斷依據，來判斷從屬裝置當前的狀況。如果從屬 裝置的接收緩衝器當前無法接收時，該從屬裝置即發出 SBusy訊號，仲裁器將SBusy訊號鎖定後，與匯流排使用請 长中表示目；^攸屬裝置號碼的訊號MDstnum進行遮罩運 算，若二者所對應的從屬裝置一致時，該匯流排使用請求將 被遮罩掉。 在ARBLEVEL1狀態下，仲裁器採用一般演算法，公平 地對各個主裝置發出的各類匯流排使用請求進行仲裁，從中 選出一個請求，並對發出該請求的主裝置傳送授權訊號，主 裝置接到授權訊號後開始資料傳送。在ARBLEVEL2狀態 25 1244001 下，仲裁n將採H寅算法對優 π的請求進行仲裁，從中選出-個。二=: =，並對發“請求的主裝置傳送授權 = 榷訊號後縣資料傳送運算。在ARBLEVEL2 ^ t 求將被忽略掉。這裏的—般演算法，指:迴圈： 肩^法（Round Robin)或其他為本技術 演算法，在此不再贅述。 、3貝么知的仲裁 實丄2=:=r/B:r仲裁一。本 狎王衷置3都具有多執行緒，杏女 執行緒獲得授權使用匯流排時，仲裁器會發出主裝置 和該執行緒的號碼。—個執行緒的請求未被執行二 Ί =其讀取的資料所在的從屬裝置還未準備好時，二主二 :的其他執行緒可以發出請求，因此可能會有幾執— 在八他實知例中，也可能出現幾個不同 =，從各自所在的不同從屬裝置同時回傳的情形:;： =器對從屬裝置發出的反向請求進行反向仲裁後^裁二 :有匯流排進行資料回傳運算。一K號為 所共用，在高準位狀態時為有效。 "置 本實施例將從屬裝置也分成重要從屬裝置和 义置，如從屬裝置A、從屬震置3為重要從屬裝置，二： 26 !244〇〇ι :裝置c和從屬裝i D為次要從屬裝置。 進行反向資料傳送時或是反向資料傳送的目標是次= 置時’採用的資料傳送速率比重要主裝置和重要 間的諸傳送速率低。例如，當重要主裝置和重要從屬 1置 間的貝料傳运速率為1個資料/時脈’次要從屬裝置進行反 向貝料傳送時或是反向f料傳送目標是次要主裝， =速率為丨個資料/2時脈。在速率是i個資料,2時脈 的反向育料傳送期間，仲裁器不進行仲裁，因此仲裁器的反 向仲裁也有仲裁時機。 請參照第1G圖，圖中示範性地對反向仲裁的仲裁時機 進行說明。圖+ ARSNum訊號表示進行反向資料傳送的從 屬裝置，ARGrant訊號表示仲裁器對反向資料傳送的從屬= 置和對應主裝置發出回應，ARMNum訊號表示反向資料傳 送的目標主裝置，仲裁時機訊號ARArb—forbid為低時，表 示允許對反向傳送的從屬裝置的有效請求做出仲裁。從第 10圖中可以看出，從屬裝置A為重要從屬裝置，主裝置^ 為重要主裝置，在從屬裝置A向主裝置B進行反向資料傳 送時，ARArb—forbid訊號為低，可進行仲裁；從屬裝置B 向主裝置D進行反向資料傳送期間，由於主裝置Β為次要 主裝置，ARArb一forbid訊號將變高，不可進行仲裁；從屬 裝置C和從屬裝置D均為次要從屬裝置，二者與任何主裝 置進行資料傳送時，ARArb一forbid訊號都會變高，不可進 行仲裁。 本實施例中，反向請求也分成不同等級，包括SREQ級 27 1244001 別的反U和CSREQ級別的反向請求，其中CSREQ級 別的反向清求優弁川g ^ >_Λ 〇 頁序阿於SREQ級別的反向請求。在仲裁 $對反向#求進仃仲裁時’首先回應csreq級別的反向請 求同、及別的反向清求則按發出反向請求的從屬裝置的固 疋盔先順序來决疋。例如，可將從屬裝置A、從屬裝置Β、 :屬裝置C和從屬裝置D的固定優先順序由高到低設定， 這樣’若從屬裝置A、從屬裝置B、從屬裝置C和從屬裝置 D同牯么出反向凊求’且均有效’則仲裁器將優先回應從屬 义置A的反向凊求；而若只有從屬裝置b和從屬裝置^同 k舍出反向明求且均為有效請求時’仲裁器將優先回應從屬 裝置B的反向請求。在其他實施例中，也可採用一般演曾 法對反向請求進行仲裁，其變化同樣應該屬於本發明。开 雖然本發明已以-實施例揭露如上，然其並非用以限定 本發明，任㈣習此技藝者，在不脫離本㈣之精神和範圍 内，當可作各種之更動與潤飾，因此本發明之保護範圍當視 後附之申請專利範圍所界定者為準。 【圖式簡單說明】 以下附圖為對本發明實施例的辅助說明，結合以下 :本發明實施例的閣述，是為進一步揭露本發明的特徵： ，但並不限制本發明，圖中相同符號代表實施例中相 件或步驟，其中： 〜〜 =1圖緣示本發明_實施例的匯流排系統結構圖； 第2圖繪示本發明一實施例的仲裁器結構示意圖； 28 1244001 第3圖繪示本發明一實施例之第二階段仲裁的一時序 圖； 第4圖繪示本發明一實施例之篩檢程式工作原理圖； 第5圖繪示本發明一實施例之篩檢程式的從屬裝置忙 碌狀態過濾單元之時序圖； 第6圖繪示本發明一實施例之篩檢程式的匯流排鎖定 控制過濾單元之時序圖； 第7圖繪示本發明一實施例之篩檢程式的最後請求控 制過濾單元之時序圖； 第8圖繪示本發明一實施例之正向仲裁時機時序圖· 第9圖繪示本發明一實施例的仲裁狀態機工作原理 圖；以及 第10圖繪示本發明一實施例的反向仲裁時機時序圖。 102 :主裝置a 104 :主裝置c 106 :從屬裝置a 1〇8 :從屬裝置c 11 0 :仲裁器 【元件代表符號簡單說明】 101 :匯流排 103 :主裝置B 105 :主裝置D 107 :從屬裝置B 109 :從屬裝置d 201 : 202 : 203 : 205 : 正向第二階段仲裁模組 正向第一階段仲裁模組 篩檢程式 204 :仲裁狀態機 緩衝器 206 :正向解碼器 29 1244001 207:反向仲裁模組 208:反向解碼器 401 :匯流排使用請求訊號 402 :從屬裝置忙碌狀態訊號 403 :匯流排鎖定訊號 404 :最後請求控制訊號 405 :有效請求 406 :篩檢程式 30: Ring = and authorize the master device signal AI to μ-C and master device D to use the bus request. The first stage of the long-term W2 arbitration requires that all screening programs that need to participate in the arbitration, please ===, and the screening program will be masked according to the request of the government. A request that can be continued through the screening program is called a valid request. In this embodiment, the screening program mainly includes three filtering units. The first 属 K belongs to the device busy state (SBusy) filtering unit. When the slave device accessed by the request for money transfer is not in a busy state, it can pass the screening program. For example, in this implementation, the slaves accessed The device's receive buffer must be able to receive commands from the host device. For this filtering condition, each slave device in this embodiment is configured with a receive buffer for receiving a receiving instruction and related data sent by the arbiter. The receive buffer mentioned here can be a first-in-first-out register (FIF). When the remaining free space of the slave device's buffer is close to zero, that is, the remaining space of the buffer can only support the length of one pulse data or the length of one pulse data plus one data length, the slave device sends out the slave device busy The status signal SBUSy signal to the arbiter 'SBusy signal indicates the number of the slave device. The second is a paired read and write request control (LREQ) filtering unit, which is directed to the LREQ type bus use request in this embodiment. For a read access requested by an LREQ, it will respond to 18 1244001 only when the bus is not locked. If the bus is in a false state, the read access of this lreq request must be masked. Here, 蹈, ui ui [M row is locked, which means that there are other master devices or direct ## > ,, not direct 八 he has issued a LREQ request 'and the request It is different in green and green mouth. In this way, a new LREQ request can be prevented from obtaining the bus authorization. The access rate will be different, and the previous LREQ operation will be wrong. The third pass element is the last request control element, which can be used to ensure that the bus system can continuously process multiple bus use requests to achieve the effect of pipeline / arbitration. For the request of the most clock of each stream pulse being transmitted, the arbiter needs to judge the data transfer status of the stream pulse, the ALast signal, to determine the next arbitration state, so the arbiter must The pulse request is masked. In other embodiments of the present invention, other filtering units may be provided in the screening program. Please refer to Figure 4. The screening program 406 of the arbiter is provided with three control ports, which are connected to the slave device busy status signal line 402, the bus = fixed control line 403, and the last request control signal line 4. 4. The input of the screening program is a bus usage request from the host device. The output of the screening program is a request that has passed the screening program but is not masked. It is called a valid request. Yi will use an arbitration algorithm to arbitrate valid requests. Figures 5-7 are exemplary timing diagrams of the work of the three filter units in the screening program. In the SBusy filter unit, the arbiter first locks the SBusy signal sent from each slave device to the SBusy control end, and then the screening program ^ ά SBusy §fL and MDstnum signal of the month 1j for masking operation (Episode 19 1244001 operation), where the MDstnum signal indicates the number of the slave device to be accessed by the request. If the number of the slave device indicated by the MDstnum signal is the same as that of the slave device acting on SBusy, it means that the slave device accessed by the request cannot currently receive the command. At this time, the screening program masks the request. Please refer to Figure 5. The MReqO signal is the bus use request signal sent by the master device A. The MDstnum signal indicates the slave device to be accessed by the request. The MVReqO signal is a valid request signal output after the screening program. The SBusyO signal becomes effective at the next clock after locking, so that the operation of the last clock accessed by MReq0 to slave device A (the corresponding MDstnum signal is 0) is masked (that is, MVReqO is IDLE); During the access of the device β (the corresponding MDstnum signal is 1), the screening program does not show a valid SBusyl signal, so the access to the slave device B is not masked. In the bus lock control filter unit, an ALock signal is applied to the bus lock control terminal. If the bus is locked, the ALOck signal is 咼 and a mask operation is performed with the MReq signal at the input terminal. When the status is locked and the MReq signal is displayed as LREQ, the screener will mask the request. In the embodiment shown in FIG. 6, MReq0 and MCmd0 are the bus request signals described by the master device A; AReq and ACmd are the response signals sent by the arbiter, which indicate the level and read / write status of the authorization request, respectively ^ Grant is the authorization signal from the arbiter; MVReq0 is a valid request from the main party to send A to the output. During the period when the AGrant signal is high, when it is a type and ACmd is low (indicated as a read request), the bus lock control terminal ❸AL0Ck signal is high; and when ACmd is high (indicated as a write request), the bus lock control terminal The signal is low. When the ALOck signal is ^ 20 1244001 inches, the bus is locked. At this time, the arbiter will not arbitrate other [REq item differences. In the figure, the first LREQ request of MReq0 is a read operation, and the ALock signal is 咼 in the first clock of this LREQ request, so the LREQ in this clock reflected from MVReqO is masked. Regarding the last request control filtering unit, in one embodiment of the present invention, for the request of the last clock of the streaming pulse being transmitted by the parent, the arbiter will determine the AGrant and AMNum # 仏 signals together. When the AGrant signal Valid, and AMNum refers to the current occupancy bus: the master of the streaming pulse transmission, and ALast indicates that the request of the master device has been made to the last-clock request. The arbiter puts this stream pulse last The clock request is masked. Please refer to Figure 7. The communication signal sent by the master device A is the request signal for the use of the bus. The signal indicates that the data sent by the arbiter after decoding the bus request signal is away from AMNum. The timing of the signal can be seen that the bus currently occupying is: The timing of the MVReq0 signal in the device diagram shows that the request corresponding to the last clock is masked. ° ^ The first stage of forward arbitration is not in any New arbitration can be conducted at any time, but only when a certain condition is met and arbitration is allowed.-In general, the first stage can be conducted. In this embodiment, the arbiter | condition is the current signal. When the signal is IDLE, it means that the secondary education w ° /, Arb-state, that is, there is no arbitration currently in progress = secondary ^ is currently in In the idle state, the first-stage hierarchical arbitration includes, in this embodiment, Ah Zhong 21 1244001 arbitration timing and CREQ arbitration timing. Corresponding to these two arbitration timings, AREQ_arb and ACREQ-arb arbitration timing control signals are respectively provided. In this embodiment, the data transmission method used is a stream pulse format, and the MLast signal is specified to represent the segmented pulse data transmission status code of the master device to the arbiter. The MLast signal has three values to indicate that the current segmented pulse has been End: LAST indicates that a complete stream pulse has ended; SAME indicates that a stream pulse has not ended, the current segment pulse has ended, and the slave device for the next segment pulse access is the same as the current segment pulse; DIFF indicates a stream pulse It is not over yet, the current segmentation pulse has ended, and the slave device for the next segmentation pulse access is not the same as the current segmentation pulse. In the arbitration state machine, it is possible to enter the arbitration state when these three segmentation pulse end codes appear. In this embodiment, a stream pulse process can only be interrupted by other requests at the CREQ level, while other requests at the REQ level cannot. A stream pulse is interrupted. When the LAST signal appears, the AREQ_arb signal and the ACREQ_arb signal are valid at the same time; when the SAME or DIFF signal appears, only the ACREQ_arb signal is valid. Please refer to Figure 8 for the timing of arbitration timing. After the MLast signal sent by the master device is arbitrated by the arbiter, the forward decoder of the arbiter will issue the ALast signal. There are four types of values corresponding to the MLast signal, namely CONT, SAME, DIFF and LAST, which can be used to help determine the next one. Arbitration state of the clock arbiter to speed up the processing of the bus pipeline. In the figure, there are three examples of ALast signals: LAST, SAME, and DIFF. The LAST signal indicates the end of a stream pulse, and the two signals AREQ_arb and ACREQ_arb are valid at the same time; SAME and DIFF only indicate that a segmented pulse has ended 22 1244001, and the stream pulse has not ended, and only the ACREQ_arb signal is valid. The ACREQ_arb signal is valid at both the end of the stream pulse and the end of the segment pulse in the stream pulse, while the AREQ_arb signal is valid only at the end of the stream pulse. Obviously, the ACREQ_arb signal is valid more frequently than the AREQ_arb signal. The time interval of the CREQ arbitration opportunity is shorter than the time interval of the REQ arbitration opportunity. Please refer to Figure 9 and Table 3. The arbitration state machine in this embodiment includes three states: IDLE, ARBLEVEL1, and ARBLEVEL2. ARBLEVEL1 and ARBLEVEL2 are the REQ arbitration timing and CREQ arbitration timing described above, respectively. Please refer to Table 3 for the following descriptions. Table 3 Condition 1 None of the valid requests are CREQ or LREQ, at least 1 valid request is REQ condition 2 When AREQ_arb is valid, and none of the valid requests are REQ, CREQ or LREQ condition 3 At least 1 valid request is CREQ or LREQ condition 4 when ACREQ_arb is valid, and none of the valid requests are REQ, CREQ, or LREQ condition 5 When ACREQ_arb is valid and AREQ_arb is invalid, at least one valid request is CREQ or LREQ, and AEnterST2 is recorded as 1 Condition 6 When ACREQ_arb is valid, and no valid request is CREQ or LREQ, and AEnterST2 is 1, same as 23 1244001, AEnterST2 is reset to zero. As can be seen from the arbitration state machine in Figure 9, the arbiter is not in Arbitration is performed at any time, and arbitration is performed only in the states of ARBLEVEL1 and ARBLEVEL2. When the Arb_state signal is IDLE and meets condition 1, that is, only valid requests at the REQ level and no valid requests at the CREQ or LREQ level, and at the same time the AREQ-arb signal is valid, the arbiter enters the ARBLEVEL1 arbitration state. In the ARBLEVEL1 arbitration state, the arbiter can arbitrate the REQ, CREQ, and LREQ-level bus usage requests issued by the master device. When the Arb —state signal is IDLE and condition 3 is satisfied, that is, as long as there is a valid request at the CREQ or LREQ level, regardless of whether there is a valid request at the REQ level, and at the same time an ACREQ—arb signal is valid, the Bayer J arbiter enters ARBLEVEL2 Arbitration status. In the ARBLEVEL 2 arbitration state, the arbiter only arbitrates the CREQ or LREQ-level bus use requests issued by the master device, while the REQ-level bus use requests do not participate in arbitration. It can also be seen from Figure 9 that the two states of ARBLEVEL1 and ARBLEVEL2 in the arbitration state machine can also switch to each other under certain conditions. Therefore, in this embodiment, the AEnterST2 signal is introduced to record the interrupted arbitration status. When the arbiter is arbitrating in the ARBLEVEL1 state, due to a higher-level valid request, such as a CREQ or LREQ request, it is necessary to switch the arbitration state to the ARBLEVEL2 state, and record the AEnterST2 signal as 1. In this way, when the AEnterST2 signal is 1, it enters the ARBLEVEL2 state until the arbitration operation in the ARBLEVEL2 state is completed. 24 1244001 is completed. 'There are only valid requests at the REQ level and no other valid requests at the c or LREQ level. The arbiter No re-entry will be returned to the original arbitration state, and Ah㈣M = will be reset to zero at the same time as the return. When the arbitration state is switched for arbitration, the internal state of the arbitration cry (int 哭 al state) needs to be retained, and the amount of signals to be retained is temporarily put on hold (in e0), the amount of signals to be retained is mainly given to the master device by the arbiter ^ Response The number of the master device AMNum and the arbiter are sent to the slave device in response to the number of the slave device ASNum, etc. When the slave state is directly transferred = ARBLEVEL2 state, when the arbiter completes the arbitration task under the fine coffee rainbow 2 state, '㈣ϋ All valid requests will be arbitrated again. * During the arbiter's arbitration process, when the ACREQ__ signal is valid, if the arbitration H is directly transferred from the state ARBLEVEL1 to the state 2 following the coffee, 'to prevent a valid bus Use the corresponding slave device that is requested to be accessed to be overloaded. In this embodiment, the slave device ’s busy green state signal is used as the judgment basis to determine the current status of the slave device. If the receiving buffer of the slave device is currently unable to receive, The slave device sends a SBusy signal. After the arbiter locks the SBusy signal, please use it with the bus; The signal MDstnum is used for mask calculation. If the corresponding slave devices are the same, the bus use request will be masked. In the state of ARBLEVEL1, the arbiter uses a general algorithm to fairly send the Various types of buses use requests for arbitration, select a request from them, and send an authorization signal to the master device that sent the request. The master device starts data transmission after receiving the authorization signal. Under ARBLEVEL2 state 25 1244001, the arbitration n will use H The algorithm arbitrates the request of superior π, and selects one of them. Two =: =, and sends the "authorized request for the master device to send the authorization = the data transmission operation after the signal. The request in ARBLEVEL2 ^ t will be ignored. Here —General algorithm, refers to: loop: shoulder Robin (Round Robin) or other algorithms based on this technology, will not repeat them here. 3 arbitration practice known as 贝 2 =: = r / B: r arbitration 1. Ben Wang Zhizhi 3 has multiple threads. When the apricot thread is authorized to use the bus, the arbiter will issue the master device and the number of the thread. A request for a thread has not been executed. its When the slave device on which the data is read is not ready, the other threads of the two masters can issue requests, so there may be a few holdouts — in the other eight examples, there may be several differences =, from Cases where different slave devices return at the same time:;: = After the device reversely arbitrates the reverse request sent by the slave device ^ Cut 2: There is a bus for data return operation. A number K is shared and used in It is effective when the high level is set. &Quot; Setting the slave device in this embodiment is also divided into important slave devices and meaning devices, such as slave device A, slave shock device 3 is an important slave device, 2: 26! 244〇〇: device c and the slave device i D are secondary slave devices. The purpose of the reverse data transfer or reverse data transfer is to use the data transfer rate lower than that of the important master device and the transfer rate between important devices. For example, when the shell material transfer rate between the important master device and the important slave device is 1 data / clock, the secondary slave device performs reverse shell material transfer or the reverse material transfer target is the secondary master device. , = Rate is 丨 data / 2 clocks. The arbiter does not perform arbitration during the reverse breeding transfer of data with 2 clocks, so the reverse arbitration of the arbiter also has the opportunity to arbitrate. Please refer to Figure 1G, which illustrates the arbitration timing of reverse arbitration as an example. Figure + ARSNum signal indicates the slave device for reverse data transmission, ARGrant signal indicates that the arbiter responds to the slave of the reverse data transmission = device and the corresponding master device, and ARMNum signal indicates the target master device for reverse data transmission, the signal of arbitration timing When ARArb-forbid is low, it means that arbitration is allowed for valid requests from slave devices transmitted in the reverse direction. It can be seen from Fig. 10 that the slave device A is an important slave device, and the master device ^ is an important master device. When the slave device A transmits reverse data to the master device B, the ARArb-forbid signal is low and arbitration can be performed ; During the reverse data transfer from slave B to master D, since master B is the secondary master, the ARArb_forbid signal will become high and arbitration will not be allowed; slave C and slave D are both secondary slaves When the two are transmitting data with any host device, the ARArb-forbid signal will become high and arbitration cannot be conducted. In this embodiment, the reverse request is also divided into different levels, including SREQ level 27 1244001 other reverse U and CSREQ level reverse requests, where the reverse clearing of CSREQ level is optimized. 弁 > _Λ 〇 Page order A Reverse requests at the SREQ level. In the arbitration $ 对 逆 # request for arbitration, the first response to the csreq level reverse request, and other reverse clear requests are determined in the order of the fixed helmet of the slave device that issued the reverse request. For example, the fixed priorities of slave device A, slave device B, slave device C, and slave device D can be set from high to low, so that 'if slave device A, slave device B, slave device C, and slave device D are the same If the reverse request is 'and both are valid', the arbiter will give priority to the reverse request of the slave A; if only the slave device b and the slave device ^ round out the reverse request and are both valid requests The 'arbiter' will give priority to the reverse request from slave B. In other embodiments, the general request method can also be used to arbitrate the reverse request, and the changes should also belong to the present invention. Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. [Brief description of the drawings] The following drawings are supplementary descriptions of the embodiments of the present invention, combined with the following: The description of the embodiments of the present invention is to further disclose the features of the present invention: but does not limit the present invention, the same symbols in the drawings Representative components or steps in the embodiment, where: ~~ = 1 Figure edge shows the structure of the bus system of the embodiment of the present invention; Figure 2 shows a schematic diagram of the arbiter structure of an embodiment of the present invention; 28 1244001 3 Figure 4 shows a timing diagram of the second stage arbitration according to an embodiment of the invention; Figure 4 shows the working principle of a screening program according to an embodiment of the invention; Figure 5 shows a screening program according to an embodiment of the invention Timing chart of the busy state filter unit of the slave device; FIG. 6 illustrates the timing chart of the bus lock control filter unit of the screening program according to an embodiment of the present invention; FIG. 7 illustrates the screening program of an embodiment of the present invention The timing diagram of the last request to control the filtering unit; FIG. 8 is a timing diagram of the forward arbitration timing according to an embodiment of the present invention; and FIG. 9 is a working principle diagram of the arbitration state machine according to an embodiment of the present invention; FIG 10 illustrates the timing of the present invention, the arbitration counter a timing chart of the embodiment. 102: Master device a 104: Master device c 106: Slave device a 108: Slave device c 11 0: Arbiter [Simplified description of component representative symbols] 101: Bus 103: Master device B 105: Master device D 107: Slave device B 109: Slave device 201: 202: 203: 205: forward second-stage arbitration module forward first-stage arbitration module screening program 204: arbitration state machine buffer 206: forward decoder 29 1244001 207: Reverse arbitration module 208: Reverse decoder 401: Bus use request signal 402: Slave device busy status signal 403: Bus lock signal 404: Last request control signal 405: Valid request 406: Screening program 30