案號 90106030 1242927 修正 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關一種延遲閃趣 特別是關於一種降低延遲閂迴路中DLL)之延遲電路， 平延遲電路之功率消耗 者。 【先前技術】 延遲閃迴路係利用一可變延 相位校準其輸出信號之相位。因=路，以對輸人^虎之 相位差於趨近信號㈣之最小公信ί和輸出信號之 ^ ^ ^ ^ ^ 取J Α倍數時，其相位差為〇 ， 故輸…以，號週期之整最小公倍數而延遲。延遲問迴 路一般由若干具可變延遲之若干級聯增益階段組成，通 用於電腦作業“巾，處理時脈歪斜問題。近 逐Λ廣J乏應用於例如同步動態隨機記憶體 SDRAM) # ^二貝枓Ϊ輸率之同步動態隨機記憶體（_ SDRAf)等冋速數位設計之記憶體裝置領域。為了能 分=相# u鎖，#範圍及⑼需之最小·脈歪斜，一般 延、"*迴路需要長的延遲電路，而利用反相 為最簡易之方式者。 π器之延遲技藝 μ二t閱第一圖，習知一種同步動態隨機記憶體之延遲 的延遲電路p ^要由諸多反相器11串接而成， ^ : 11付視實際應用情形分為若干級（通常為六十四 ，）i輪入信號V i n將經過一依據外部控制信號Φ輸入之 夕工器（Multiplexer) 12來取決若干級之反相器Η後， 將延遲時間之信號輸出Vout。 1242927 _____ 案號90106030__〜月 日 修正 五、發明說明（2) 前揭習用同步動態隨機記憶體之延遲閂迴路中的延遲 電路雖具延遲功效，然於實際使用時，依據該延遲電路 1，該長串反相器1 1皆處於、、開"的狀態中，以備所需延 遲功能，而大多之實際應用情況，僅需少數級之反相器 1 1，故而極易造成功率浪費，進而影響性能之缺失。 美國專利第六〇八七八六八號專利，已針對前揭缺 失，揭示延遲電路1之未被使用部分反相器得予以關閉， 以避免該未被使用之部分反相器的無謂功率消耗。 【發明内容】 有鑑於此，本發明之目的，主要在提供降低習知同步 動態隨機記憶體之延遲問迴路中延遲，電路的功率消耗，且 至少對降低延遲問迴路中延遲電路的功率消耗方式，提供 另一種選擇。 本發明之又一目的，係在提供以電流控制延遲電路之 延遲時間長短，減少反相器使用數目，以降低延遲電路功 率之消耗。 本發明之另-目的，在於提供以電容控制延 延遲時間長短，以降低延遲電路功.率之消耗。 $ _ < 根據本發明之提供，一種降低功率消耗 控制信號藉一控制裝置擇取所需用以延遲之 ^電2, 之功率消耗效能。 要u ’達降低延遲電路Case No. 90106030 1242927 Amendment V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a delay flash, in particular to a delay circuit that reduces the DLL in the delay latch loop, and a power consumer of the flat delay circuit. [Prior art] The delay flash circuit uses a variable delay phase to calibrate the phase of its output signal. Because = road, the phase difference between the input signal and the minimum signal of the approaching signal ㈣ and the output signal ^ ^ ^ ^ ^ When taking a multiple of J Α, the phase difference is 0, so the input ... The integer least common multiple. The delay loop is generally composed of several cascaded gain stages with variable delays. It is commonly used in computer operations to deal with clock skew problems. It is widely used in, for example, synchronous dynamic random memory SDRAM) # ^ 二In the field of high-speed digital design memory devices such as synchronous dynamic random access memory (_SDRAf), in order to be able to separate = phase # u 锁, # range and the minimum required, pulse skew, generally extended, " * The loop requires a long delay circuit, and the use of inversion is the easiest way. The delay technique of the π device is shown in the first figure, and a delay circuit p that synchronizes the delay of the dynamic random memory is required. Many inverters 11 are connected in series. ^: 11 is divided into several stages (usually sixty-four) depending on the actual application situation. The i-round input signal V in will pass through a xi input device based on the external control signal Φ ( Multiplexer) 12 depends on several stages of inverters, and then outputs the delay time signal to Vout. 1242927 _____ Case No. 90106030__ ~ Month and Day Amendment V. Description of the invention (2) Delayed latch circuit of synchronous dynamic random access memory used in the previous study in Although the delay circuit has a delay effect, in actual use, according to the delay circuit 1, the long string of inverters 1 1 are in the state of "ON" to prepare for the required delay function, and most of them are practical. In the application, only a few stages of inverters 11 are needed, so it is very easy to cause power waste and then affect the performance loss. US Patent No. 6,087,868 has already revealed the delay circuit 1 for the lack of previous disclosure. The unused part of the inverter must be turned off to avoid unnecessary power consumption of the unused part of the inverter. [Summary of the Invention] In view of this, the purpose of the present invention is mainly to reduce the conventional synchronous dynamic randomness. The delay in the memory delay circuit and the power consumption of the circuit provide at least another option for reducing the power consumption of the delay circuit in the delay circuit. Another object of the present invention is to provide a current-controlled delay circuit. The length of the delay time reduces the number of inverters used to reduce the power consumption of the delay circuit. Another object of the present invention is to provide a capacitor-controlled delay The length of time is to reduce the power consumption of the delay circuit. According to the present invention, a control signal for reducing power consumption selects the power consumption performance of the power required for delay by a control device. To u 'up to reduce the delay circuit
種降低功率消耗的延遲電Delay power
年月曰_ 案號 90106030 1242927 五、發明說明（3) 丨路，控制信號藉一裝置擇取所需用以延遲之電容數，決定 延遲之時間，達降低延遲電路之功率消耗效能。 茲為明示本發明之技術特徵暨顯著進步功效，爰配合 丨下列諸圖式說明，舉例說明本發明之主要設計如后。 ;【實施方式】 i 請參閱第二圖，一種降低功率消耗之延遲電路2，包 i括若干電流源2卜多工器22、外接電容2 3及反相器24，控 I制信號Φ藉多工器2 2僅擇取用以延遲時間所需之電流源2 1 |數目，使輸入信號Vi η經一外接電容2 3及一級反相器24 i後，再予輸出信號Vout。因為眾多不必要的反相器數目業 ί i已顯著減少，故可降低功率之消耗達百分之五十以上。Year and month_ Case No. 90106030 1242927 V. Description of the invention (3) 丨 The control signal selects the required number of capacitors for delay by a device, determines the delay time, and reduces the power consumption efficiency of the delay circuit. The technical features of the present invention and the markedly improved effects are hereby shown, and in conjunction with the following illustrations, the main design of the present invention is illustrated below. [Embodiment] i Please refer to the second figure, a delay circuit 2 for reducing power consumption, including a plurality of current sources 2 multiplexer 22, external capacitor 23, and inverter 24, which control the I signal Φ borrow The multiplexer 2 2 only selects the number of current sources 2 1 | required to delay the time, so that the input signal Vi η passes an external capacitor 23 and a first-stage inverter 24 i, and then outputs a signal Vout. Because the number of unnecessary inverters has been significantly reduced, power consumption can be reduced by more than 50%.
I i 請參閱第三圖，一種降低功率消耗之延遲電路3，包I i Please refer to the third figure, a delay circuit 3 for reducing power consumption, including
I i括一固定電流源3卜 多工器32、電容器組3 3及信號緩衝 i器3 4，控制信’號Φ藉多工器3 2僅擇取用以延遲時間所需之 電容器組3 3數目，決定延遲之時間，再使輸入信號V i η經 信號緩衝器34後，再予輸出信號Vout。該電容器組33得為 空乏型金屬氧化半導體製作者。根據本實施例，由於固定 電流源3 1之電流業已固定，電容器組3 3之各電容器之電寥 並不隨電壓而改變，故實際延遲時間和所擇取電容間可達 如第四圖所示之線性關係。 根據本發明上揭諸實施例，熟習本技藝人士明顯可 知，本案之延遲電路確實具備降低延遲閃迴路功率消耗之 進步功效。故本發明當可迎合日趨高速之數位設計技術趨 勢，誠為一具備產業利用性之新發明。I i includes a fixed current source 3, a multiplexer 32, a capacitor group 3 3, and a signal buffer device 3 4, and the control signal 'number Φ is borrowed from the multiplexer 3 2 and only the capacitor group 3 required for delay time is selected. 3, determine the delay time, make the input signal V i η pass the signal buffer 34, and then output the signal Vout. The capacitor bank 33 has to be a manufacturer of an empty metal oxide semiconductor. According to this embodiment, since the current of the fixed current source 31 is already fixed, the electricity of each capacitor of the capacitor group 3 3 does not change with the voltage, so the actual delay time and the selected capacitance can be as shown in the fourth figure. Shows the linear relationship. According to the disclosed embodiments of the present invention, those skilled in the art will obviously know that the delay circuit in this case does have the improved effect of reducing the power consumption of the delay flash circuit. Therefore, the present invention should be able to cater to the trend of digital design technology that is becoming increasingly high-speed, and is a new invention with industrial applicability.
第7頁 1242927 案號90106030___年 月———曰 修正______ 圖式簡單說明 【圖式簡單說明】 第一圖為習知一種同步動態隨機記憶體之延遲閂迴路 中的延遲電路示意圖。 第二圖為一種根據本發明實施例之延遲電路示意圖。 第三圖為根本發明另一實施例之延遲電路示意圖。 第四圖為根據本發明第三圖所示實施例之延遲時間與 電容間的相對應關係圖。 【主要元件符號說明】 ❹ 1、2、3〜延遲電路 · 2 1、3 1〜電流源 12、 22、 32〜多工器 2 3〜外接電容 1 1、2 4〜反相向器 3 3〜電容器組 3 4〜信號緩衝器 V i η〜輸入信號 V 〇 u t〜輸出信號 Φ〜外部控制信號 ΛPage 7 1242927 Case No. 90106030 Month ——————————————————————————————————————————————————————————————————————————————————————————————— A simple illustration of the diagram. The first diagram is a schematic diagram of the delay circuit in the delay latch circuit of a synchronous dynamic random memory. The second figure is a schematic diagram of a delay circuit according to an embodiment of the present invention. The third figure is a schematic diagram of a delay circuit according to another embodiment of the fundamental invention. The fourth figure is a corresponding relationship between the delay time and the capacitance according to the embodiment shown in the third figure of the present invention. [Description of main component symbols] ❹1,2,3 ~ delay circuit · 2 1,3 1 ~ current source 12,22,32 ~ multiplexer 2 3 ~ external capacitor 1 1,2 4 ~ inverter 3 3 ~ Capacitor bank 3 4 ~ Signal buffer V i η ~ Input signal V 〇ut ~ Output signal Φ ~ External control signal Λ