TWI242810B - Manufacturing method for forming bit line spacer with fine rectangular contour - Google Patents

Abstract

The present invention discloses a manufacturing method for forming bit line spacer with fine rectangular contour, which forms a patterned oxide layer, a polysilicon layer and an oxide layer on a semiconductor substrate, and further sequentially utilizes a breakthrough step, a main etch step, an oxide etch step, and an over etch step pertaining to the etch step of each respective stage to complete the manufacture of the bit line spacer. Using the residual oxide layer at the corners of the polysilicon layer can attain a vertical spacer etch characteristic and such characteristic is remained in the subsequent etch steps to ensure a fine spacer contour. Consequently, the method of the present invention not only removes the resulting fence structure, but also manufactures the bit line spacer with fine rectangular contour.

Description

1242810 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關一種在半導體製程中製作側壁間隙壁 (s i d e w a 1 1 s p a c e r)的方法，特別是關於一種形成良好 方形輪廓之字元線間隙壁的製造方法。 【先前技術】 按，隨著半導體積體電路的持續發展，在進入超大型 積體電路的製程後，為了使積體電路的設計可符合高積集 度之要求，晶片中所含有之元件數量不斷增加，元件的尺 寸也因積集度的提升而不斷地縮小。 然而無論元件尺寸如何縮小化，在晶片各個元件之間 仍必須有適當地絕緣或隔離，方可得到良好的元件特性。 此項技術係稱之為元件隔離技術，其主要係在各元件間形 成隔離物，並在確保良好隔離效果的強況下，盡量縮小隔 離物的區域，以藉此容納更多的元件。除了隔離元件的淺 溝槽隔離（ST I)結構之外，最常見的是間隙壁，其係一 種以絕緣材料形成在閘極（字元線）周圍之基底上用來避 免閘極與源極/汲極導通而造成漏電流的絕緣元件，間隙 壁的高度與閘極的高度相同乃為一種較佳的設計，可有效 避免閘極與源極/汲極相導通。 間隙壁除了作為隔離元件使用之外，亦可作為字元線 的多晶矽間隙壁，習知係利用蝕刻多晶矽層以製作多晶矽 間隙壁之步驟，如第一（a)圖所示，其係在已定義出半導 體基底10之主動區域後，依序形成一圖案化氧化層12、一 多晶矽層1 4及一氧化層1 6 ;再藉由微影蝕刻製程進行主蝕1242810 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for making sidewa 1 1 spacers in a semiconductor process, and particularly to a word line gap that forms a good square outline. Manufacturing method of wall. [Previous technology] According to the continuous development of semiconductor integrated circuits, after entering the process of super large integrated circuits, in order to make the integrated circuit design meet the requirements of high integration, the number of components contained in the chip Increasingly, the size of components has also been continuously reduced due to the increase in the degree of accumulation. However, no matter how the component size is reduced, there must still be proper insulation or isolation between the various components of the wafer to obtain good component characteristics. This technology is called component isolation technology. It mainly forms spacers between components, and under the strong condition of ensuring good isolation effect, the area of the spacers is minimized to accommodate more components. In addition to the shallow trench isolation (ST I) structure of the isolation element, the most common is a gap wall, which is an insulating material formed on the substrate around the gate (word line) to avoid the gate and source Insulation components that cause leakage current due to / drain conduction, the height of the gap wall is the same as the gate height, which is a better design, which can effectively prevent the gate and source / drain conduction. In addition to being used as an isolation element, the spacer can also be used as a polycrystalline silicon spacer for word lines. The conventional method is to etch a polycrystalline silicon layer to make a polycrystalline silicon spacer, as shown in the first (a) figure. After the active area of the semiconductor substrate 10 is defined, a patterned oxide layer 12, a polycrystalline silicon layer 14 and an oxide layer 16 are sequentially formed; and then the main etching is performed by a lithography etching process.

第5頁 1242810 五、發明說明（2) 刻步驟，先利用乾式蝕刻技術對氧化層1 6進行蝕刻，而後 對多晶矽層1 4進行蝕刻步驟，可移除該氧化層1 6及部份該 多晶矽層1 4，如第一（b )圖所示，以形成多晶矽間隙壁1 8 於圖案化氧化層1 2的側壁上，同時曝露出半導體基底1 0的 上表面。Page 5 1242810 V. Description of the invention (2) Engraving step. First, the oxide layer 16 is etched by dry etching technology, and then the polycrystalline silicon layer 14 is etched. The oxide layer 16 and part of the polycrystalline silicon can be removed. The layer 14, as shown in the first (b) diagram, forms a polycrystalline silicon spacer wall 18 on the sidewall of the patterned oxide layer 12 while exposing the upper surface of the semiconductor substrate 10.

但是，上述製作多晶矽間隙壁1 8之方式亦容易在間隙 壁邊緣產生如第一（b)圖所示之尖角（fence)結構20，此 種尖角結構2 0可能會成為微粒來源（p a r t i c 1 e s 〇 u r c e) ，亦可能對後續薄膜沈積製程造成嚴重的影響，導致製作 出之元件具有嚴重的缺陷問題而影響製程良率。另外，為 了清除半導體基底1 0上多餘的多晶矽層1 4以及在蝕刻過程 中產生的微粒、碎屑等物質，在主要蝕刻步驟結束後，通 常會進行一過度蝕刻程序。其中，此過度蝕刻程序雖然不 致對間隙物造成嚴重的侵蝕，但往往亦會使得多晶矽間隙 壁1 8的上表面高度降低，甚至曝露出部份圖案化氧化層的 上緣側壁。 因此，就現階段半導體製程而言，如何定義出形成良 好的方形多晶矽字元線間隙壁，將可進一步的提高積體電 路製程的良率。However, the above-mentioned method of making polycrystalline silicon spacers 18 also easily generates a sharp structure 20 as shown in the first (b) figure at the edges of the spacers. Such sharp structures 20 may become a source of particles (partic 1 es 〇urce), may also have a serious impact on the subsequent thin film deposition process, leading to the production of components with serious defect problems and affect the process yield. In addition, in order to remove the excess polycrystalline silicon layer 14 on the semiconductor substrate 10 and the particles, debris, and other materials generated during the etching process, an over-etching process is usually performed after the main etching step is completed. Among them, although the excessive etching process does not cause serious erosion to the spacers, it often lowers the upper surface height of the polycrystalline silicon spacers 18 and even exposes the upper edge sidewalls of the patterned oxide layer. Therefore, in terms of the current semiconductor manufacturing process, how to define a good square polycrystalline silicon word line spacer will further improve the yield of the integrated circuit manufacturing process.

【發明内容】 本發明之主要目的係在提供一種字元線間隙壁的製造 方法，其係可去除生成之尖角輪廓，以製作出具有良好方 形輪廓的字元線間隙壁。 本發明之另一目的係在提供一種字元線間隙壁的製造[Summary of the Invention] The main object of the present invention is to provide a method for manufacturing a character line gap wall, which can remove the generated sharp-angled contours to produce a character line gap wall with a good square outline. Another object of the present invention is to provide a method for manufacturing word line spacers.

第6頁 1242810 五、發明說明（3) 方法，其係對所定義字元線間隙壁的寬度、高度與形狀進 行有效地控制，以得到具有良好的方形輪廓的字元線間隙 壁，進而提高積體電路製程的良率。 為達到上述之目的，本發明先在一半導體基底上依序 形成一圖案化氧化層、一多晶矽層及一氧化層；利用氧化 物對多晶矽之高選擇比，進行一突破步驟，以去除部份之 氧化層；接著，進行一主蝕刻步驟，蝕刻多晶矽層與少部 份氧化層，直至此多晶矽層於半導體基底上成為一薄膜為 止，並使位於角落凸出之氧化層成為一尖角結構；再進行 一氧化物蝕刻步驟，對氧化層之尖角結構進行等向蝕刻， 以移除凸出多晶矽層外之尖角結構，並使多晶矽層角落圓 弧化；最後進行一過度蝕刻步驟，其係蝕刻去除圖案化氧 化層上方多餘之多晶矽層，使剩餘之多晶矽層分別在該圖 案化氧化層二側形成良好方形輪廓之字元線間隙壁。 底下藉由具體實施例配合所附的圖式詳加說明，當更 容易瞭解本發明之目的、技術内容、特點及其所達成之功 效。 【實施方式】 由於習知在製作多晶矽間隙壁之方式容易在間隙壁邊 緣產生尖角（fence)輪廓，此種尖角結構可能會成為微 粒來源，亦會對後續薄膜沈積製程造成嚴重的影響，導致 製作出之元件具有嚴重的缺陷問題而影響製程良率；因此 ，本發明提出一種字元線間隙壁的製造方法，其係可去除 生成之尖角輪廓，並同時製作出具有良好方形輪廓的字元Page 6 1242810 V. Description of the invention (3) The method is to effectively control the width, height and shape of the defined character line gap wall to obtain a character line gap wall with a good square outline, thereby improving Yield of integrated circuit process. In order to achieve the above object, the present invention first sequentially forms a patterned oxide layer, a polycrystalline silicon layer, and an oxide layer on a semiconductor substrate; using a high selectivity ratio of oxide to polycrystalline silicon, a breakthrough step is performed to remove a portion An oxide layer; then, a main etching step is performed to etch the polycrystalline silicon layer and a small part of the oxide layer until the polycrystalline silicon layer becomes a thin film on the semiconductor substrate, and the oxide layer protruding at the corner becomes a pointed structure; An oxide etching step is performed to etch the pointed structure of the oxide layer isotropically to remove the pointed structure protruding outside the polycrystalline silicon layer and round the corners of the polycrystalline silicon layer. Finally, an over-etching step is performed. The polycrystalline silicon layer above the patterned oxide layer is removed by etching, so that the remaining polycrystalline silicon layers form a good-shaped square-shaped word line spacer on each side of the patterned oxide layer. In the following, detailed descriptions will be made with specific embodiments and accompanying drawings to make it easier to understand the purpose, technical content, features and functions of the present invention. [Embodiment] As the conventional method for making polycrystalline silicon spacers is prone to generate sharp contours at the edges of the spacers, such sharp structures may become a source of particles and have a serious impact on subsequent thin film deposition processes. As a result, the produced component has serious defect problems that affect the yield of the process; therefore, the present invention proposes a method for manufacturing word line spacers, which can remove the generated sharp-angled contours and simultaneously produce a good square-shaped contour. Character

1242810 五、發明說明（4) 線間隙壁。 如第二（a )圖所示，首先提供一具&lt; 1 〇 〇&gt;晶向之單晶 矽的半導體基底3 0 ; —般而言，其他種類之半導體材料， 例如砷化鎵或是位於絕緣層上之矽底材（S0 I)皆可作為 此半導體基底3 0使用。另外，由於半導體基底表面的特性 對本發明而言，並不會造成特別之影響，所以半導體基底 3 0之晶向亦可選擇&lt; 1 1 〇&gt;或&lt; 1 1 1&gt;。1242810 V. Description of the invention (4) Line spacer. As shown in the second (a) diagram, a semiconductor substrate with a single crystal silicon <1 00> is first provided. Generally, other types of semiconductor materials, such as gallium arsenide or The silicon substrate (S0 I) on the insulating layer can be used as the semiconductor substrate 30. In addition, since the characteristics of the surface of the semiconductor substrate do not particularly affect the present invention, the crystal orientation of the semiconductor substrate 30 can also be selected as &lt; 1 1 0 &gt; or &lt; 1 1 1 &gt;.

然後，在半導體基底30表面沈積一墊氧化層（pad ox i de) 3 2，其材質通常為氧化矽；並利用微影蝕刻製程 ，在半導體基底3 0之墊氧化層32表面形成一已定義之圖案 化氧化層34 ;接續利用化學氣相沈積（CVD)方式先於半 導體基底3 0上沈積一多晶矽層3 6，使其覆蓋該圖案化氧化 層3 4和墊氧化層3 2，再利用化學氣相沈積方式、熱氧化方 式或是其他適當之製程進行沈積，於多晶矽層3 6表面形成 一氧化層3 8。Then, a pad oxide layer 3 2 is deposited on the surface of the semiconductor substrate 30, which is usually made of silicon oxide; and a lithography process is used to form a defined surface on the pad oxide layer 32 of the semiconductor substrate 30 A patterned oxide layer 34; successively using chemical vapor deposition (CVD) to deposit a polycrystalline silicon layer 36 on the semiconductor substrate 30 so as to cover the patterned oxide layer 34 and the pad oxide layer 32 before reuse A chemical vapor deposition method, a thermal oxidation method, or other suitable processes are used to deposit an oxide layer 38 on the surface of the polycrystalline silicon layer 36.

隨後，即可進行各階段之蝕刻步驟，首先，進行一突 破步驟（Breakthrough Step)，係利用氧化物對多晶石夕 之高選擇比的高離子轟擊來去除部份之表面部份氧化層38 ，以形成如第二（b)圖所示之結構。另外，亦可利用濕式 蝕刻或乾式蝕刻方式去除部份氧化層3 8。 完成突破步驟之後，進行一主蝕刻步驟（Main Etch Step)，利用濕式蝕刻或乾式蝕刻方式對半導體基底30進 行蝕刻，以蝕刻去除部份多晶矽層3 6與少部份之氧化層3 8 ，如第二（c )圖所示，直至多晶矽層3 6於該半導體基底3 0Then, the etching steps of various stages can be performed. First, a Breakthrough Step is performed, which uses a high ion bombardment with a high selectivity ratio of oxide to polycrystalline stone to remove a part of the surface oxide layer 38. To form the structure shown in Figure 2 (b). In addition, a part of the oxide layer 38 can be removed by wet etching or dry etching. After the breakthrough step is completed, a main etching step is performed. The semiconductor substrate 30 is etched by wet etching or dry etching to remove a portion of the polycrystalline silicon layer 36 and a portion of the oxide layer 3 8 by etching. As shown in the second (c) diagram, until the polycrystalline silicon layer 36 is on the semiconductor substrate 30

第8頁 1242810 五、發明說明（5) 上成為一薄膜為止，且位於角落凸出之該氧化層3 8係成為 一尖角（fence)結構40。其中，角落殘留之氧化層38可 作為襯氧化層（1 i n e r ο X i d e)使用來達到垂直間隙壁姓 刻之目的，將有利於後續蝕刻步驟中，保持良好的輪廓高 度與寬度。Page 8 1242810 V. Description of the invention (5) The oxide layer 38 which protrudes at the corner until it becomes a thin film becomes a fence structure 40. Among them, the residual oxide layer 38 at the corner can be used as a liner oxide layer (1 i n er ο X i d e) to achieve the purpose of engraving the vertical gap wall, which will be beneficial to maintaining a good contour height and width in the subsequent etching step.

接著，進行一氧化物钱刻步驟（0 X i d e E t c h S t e p) ，其係利用氧化物蝕刻速率大於多晶矽蝕刻速率之蝕刻方 式對尖角結構4 0進行等向蝕刻，例如濕式蝕刻，以蝕刻去 除凸出多晶矽層3 6輪廓外之尖角結構4 0，如第二（d )圖所 示，僅留下角落之部份氧化層3 8，並利用高偏壓能量對其 進行離子轟擊（bombard)，以使多晶矽層36角落圓弧化 〇Next, an oxide etching step (0 X ide E tch S tep) is performed, which is an isotropic etching of the pointed structure 40 using an etching method in which the oxide etching rate is greater than the polycrystalline silicon etching rate, such as wet etching, to The sharp corner structure 40 outside the contour of the polycrystalline silicon layer 36 is etched away by etching. As shown in the second (d) diagram, only a part of the oxide layer 38 at the corner is left, and ion bombardment is performed with high bias energy. (Bombard) to round the corners of the polycrystalline silicon layer 36.

最後，進行一過度#刻步驟（Over Etch Step)，其 係利用多晶矽對氧化物之高選擇比，以蝕刻去除圖案化氧 化層3 4上多餘之多晶矽層3 6，以露出該圖案化氧化層3 6表 面，如第二（e )圖所示，使剩餘之多晶石夕層3 6分別在該圖 案化氧化層3 4二側壁形成方形輪廓之字元線間隙壁4 2。在 此步驟中，利用多晶矽對氧化物之高選擇比可以保持良好 的蝕刻一致性而用以控制間隙壁之寬度，進而得到良好方 形輪廓之字元線間隙壁4 2。 由於本發明係依序藉由突破步驟、主蝕刻步驟、氧化 物蝕刻步驟及過度蝕刻步驟的各階段蝕刻步驟來完成字元 線間隙壁之製作；再利用多晶矽層角落殘留之氧化層可達 到垂直間隙壁蝕刻之特性，使其於後續蝕刻步驟中，能夠Finally, an Over Etch Step is performed, which utilizes a high selection ratio of polycrystalline silicon to oxide to remove the excess polycrystalline silicon layer 36 on the patterned oxide layer 3 4 by etching to expose the patterned oxide layer. On the 36 surface, as shown in the second (e) diagram, the remaining polycrystalline stone layers 36 are formed on the two side walls of the patterned oxide layer 3 4 to form square-shaped word line spacers 42. In this step, the high selectivity ratio of polycrystalline silicon to oxide can be used to maintain a good etching consistency to control the width of the spacers, thereby obtaining a good-line-shaped word line spacer 42. Since the present invention sequentially completes the fabrication of word line spacers through the etching steps in each of the breakthrough step, the main etching step, the oxide etching step, and the over-etching step; the residual oxide layer in the corner of the polycrystalline silicon layer can be used to achieve verticality. The characteristics of the spacer etching make it possible to

第9頁 1242810 五、發明說明（6) 保 持 良 好 的 間 隙 壁 輪 廓 高 度 與寬 度。 因 此 1 本 發 明 可 利 用 上 述之 製程有效去 除 生 成 之 尖 角 結 構 並 可 對 所 定 義 之 字 元 線間 隙壁的寬度 高 度 與 形 狀 進 行 有 效 地 控 制 1 以 得 到 具 有良 好的方形輪 廓 的 字 元 線 間 隙 壁 ， 進 而 提 高 積 體 電 路 製 程的 良率。 以 上 所 述 之 實 施 例 僅 係 為說 明本發明之 技 術 思 想 及 特 點 其 目 的 在 使 熟 習 此 項 技 藝之 人士能夠瞭 解 本 發 明 之 内 容 並 據 以 實 施 y 當 不 能 以 之 限定 本發明之專 利 範 圍 即 大 凡 依 本 發 明 所 揭 示 之 精 神 所 作之 均等變化或 修 飾 1 仍 應 涵 蓋 在 本 發 明 之 專 利 範 圍 内 〇 [ 圖 號 說 明 ] 10 半 導 體 基 底 12 圖案化氧化1 14 多 晶 矽 層 16 氧化層 18 多 晶 矽 間 隙 壁 20 尖角結構 30 半 導 體 基 底 32 塾氧化層 34 圖 案 化 氧 化 層 36 多晶矽層 38 氧 化 層 40 尖角結構 42 間 隙 壁Page 9 1242810 V. Description of the invention (6) Maintain the height and width of the gap wall wheel profile. Therefore, the present invention can effectively remove the generated sharp corner structure by using the above process, and can effectively control the width, height and shape of the defined character line gap wall1 to obtain a character line gap wall with a good square outline , Thereby improving the yield of the integrated circuit manufacturing process. The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the contents of the present invention and implement them based on the scope of the present invention. Equivalent changes or modifications made in accordance with the spirit disclosed in the present invention 1 should still be covered by the patent scope of the present invention. [Illustration of Drawing No.] 10 Semiconductor substrate 12 Patterned oxidation 1 14 Polycrystalline silicon layer 16 Oxidation layer 18 Polycrystalline silicon spacer 20 Tip Corner structure 30 semiconductor substrate 32 hafnium oxide layer 34 patterned oxide layer 36 polycrystalline silicon layer 38 oxide layer 40 sharp corner structure 42 spacer

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Claims (1)

1242810 六、申請專利範圍 1 、一種形成良好方形輪廓之字元線間隙壁的製造方法， 包括下列步驟： 在一半導體基底上形成一圖案化氧化層，並於其上形 成一多晶石夕層及一氧化層； 進行一突破步驟，係利用氧化物對多晶矽之高選擇比 ，以去除部份之該氧化層；1242810 VI. Scope of patent application 1. A method for manufacturing a zigzag line spacer with a good square outline, including the following steps: forming a patterned oxide layer on a semiconductor substrate, and forming a polycrystalline layer thereon And an oxide layer; performing a breakthrough step, using a high selectivity ratio of oxide to polycrystalline silicon to remove a portion of the oxide layer; 進行一主蝕刻步驟，蝕刻該多晶矽層與少部份該氧化 層，直至該多晶矽層於該半導體基底上成為一薄膜為 止，且位於角落凸出之該氧化層係成為一尖角 (f e n c e)結構； 進行一氧化物蝕刻步驟，其係對該氧化層之尖角結構 進行等向蝕刻，以移除凸出該多晶矽層外之該尖角結 構，並使該多晶矽層角落圓弧化；以及 進行一過度蝕刻步驟，其係蝕刻去除該圖案化氧化層 上多餘之該多晶矽層，使剩餘之該多晶矽層分別在該 圖案化氧化層二側形成方形輪廓之字元線間隙壁。 2 、如申請專利範圍第1項所述之形成良好方形輪廓之字 元線間隙壁的製造方法，其中在該突破步驟中，係利 用高離子轟擊來移除部份之該氧化層。A main etching step is performed to etch the polycrystalline silicon layer and a small part of the oxide layer until the polycrystalline silicon layer becomes a thin film on the semiconductor substrate, and the oxide layer protruding at the corner becomes a fence structure. Performing an oxide etching step, which is isotropically etching the pointed structure of the oxide layer to remove the pointed structure protruding from the polycrystalline silicon layer and rounding the corner of the polycrystalline silicon layer; and An over-etching step is performed by etching to remove the excess polycrystalline silicon layer on the patterned oxide layer, so that the remaining polycrystalline silicon layer forms a square-shaped word line gap wall on each side of the patterned oxide layer. 2. The method for manufacturing a zigzag line spacer with a good square outline as described in item 1 of the scope of patent application, wherein in the breakthrough step, high ion bombardment is used to remove part of the oxide layer. 3 、如申請專利範圍第1項所述之形成良好方形輪廓之字 元線間隙壁的製造方法，其中該多晶矽層係利用化學 氣相沈積方式完成者。 4 、如申請專利範圍第1項所述之形成良好方形輪廓之字 元線間隙壁的製造方法，其中該氧化層係利用化學氣3. The method for manufacturing a partition wall of a zigzag line forming a good square outline as described in item 1 of the scope of patent application, wherein the polycrystalline silicon layer is completed by a chemical vapor deposition method. 4. The manufacturing method of the partition wall of the zigzag line forming a good square outline as described in item 1 of the scope of the patent application, wherein the oxide layer uses a chemical gas 第12頁 1242810 六、申請專利範圍 5 字 之 〇 廊 者輪 成形 形方 所好 一 良 之成 中形 其之 的述 式所 方項 化1 氧第 熱圍 及範 式利 方專 積請 沈申 相如 中刻 驟蝕 步之 刻率 蝕速 物刻 化餘 氧碎 該晶 在多 中於 其大 ，率 法速 方刻 造蝕 製物 勺匕 白 ΤΊ 壁氧 隙用 間利 線係 元， 6 輪 形 方 好 。 良 構成 結形 角之 尖述 該所 之項 外5 層第 碎或 日ΘΒ1 多第 該圍 出範 凸利 除專 移請 式申 方如 方 刻 # 物 化 氧 該 中 其 9 ο 法之 方成 造完 製式 的方 壁刻 隙# 間式 線濕 元用 字採 之係 廓式 7 字中 之驟 廓步 輪刻 形餘 方物 好化 良氧 成該 形在 之中 述其 所’ 項法 1方 第造 圍製 範的 利壁 專隙 請間 申線 如元 8 角 字 層 之 ^ 廓 晶 輪 多 形 該 方 使 好 以 良 ， 成 擊 形 轟 之 行 述 進 所 量 項 能 1 壓 第 偏 圍 高 範 用。利 利化專 可弧請 更 111] ，落如 ， 刻 中# 驟式 步乾 破及 突刻 該# 行式 進濕 在自 中選 其係 ，式 法方 方之 造層 製化 的氧 壁該 隙份 間部 線除 元去 9 字 之 廓 輪 形 方 好 良 成 形 之 述 所 項 r—Η 。第 一圍 之範 中利 其專 的請 式申 方如 其一 ，之 中中 驟其 步的 刻式 蝕方 主刻 該# 在式 中乾 其及 ，刻 法蝕 方式 造濕 製自 的選 壁係 隙式 間方 線刻元# 字， 之中 廓驟 輪步 形刻 方蝕 好度 良過 成該 形在 之中 述其 所， 項法 1方 第造 圍製 範的 利壁 專隙 請間 申線 如元 餘 多 除 清 以 比 擇 選 高 之 物 化 氧 對 矽 晶 。 多層 用矽 利晶 用多 利該 係之 第13頁 1242810Page 12 1242810 VI. Application for Patent Range 5 Words. The shape of the square is good. The formula is good. The formula is the formula. 1 Oxygen heat zone and the paradigm and profit side. Please Shen Shenxiang Ruzhong. The ablation step is etched at a rate of etch, and the remaining oxygen is broken. The crystal is more large than it is, and the rate method is used to etch the etched spoon. The wall oxygen gap is made of thin lines, 6 rounded squares. it is good. The good point of the formation of the knot-shaped angle is described by the 5th floor of the office. The first or fifth day is ΘΒ1. Finished the square wall carved gap # Interline line Wet element with the character profile of the 7-step sculpting step wheel inscribed in the word Remaining objects to improve the good oxygen into the shape described in its' The method of the first wall of the method of the 1st party to build a control system, please apply the line like the 8 yuan of the corner layer, the crystal wheel is multi-shaped, the party is good, and the performance of the strike is described. The first round of high-profile use. Lilihua special arc can be more 111], such as, 刻 中 # Step dry break and sudden engraving # The way to enter the wet in the selection of the system, the method of the formation of the oxygen wall The interstitial part of the gap is divided by r-Η as described in the 9-shaped contour-wheel-shaped Fanghaoliang formation. The first round of the application method is one of the special application parties, and the etched etched party that is in the middle and the middle step is engraved. # Do it in the form, etched to create a wet selection wall.系 圈 式 间 方 线 刻 元 # The word, the middle contour step shape engraving the square etch is better than the shape described in its place. The Jianshen line, such as Yuan Yuduo, is divided by the higher physical oxygen than silicon. Page 13 1242810 Silicon for Multi-layer Silicon Crystal 第14頁Page 14