TWI242273B

TWI242273B - Bump structure

Info

Publication number: TWI242273B
Application number: TW093119201A
Authority: TW
Inventors: Min-Lung Huang
Original assignee: Advanced Semiconductor Eng
Priority date: 2004-06-29
Filing date: 2004-06-29
Publication date: 2005-10-21
Also published as: TW200601515A

Abstract

A wafer bump structure mainly comprises wafer pads, under bump metallurgy layers and bumps. Therein, the wafer pads are formed on an active surface of the wafer and exposed out of openings formed in a passivation layer over the active surface, and each under bump metallurgy layer is formed over the corresponding wafer pad. Each under bump metallurgy layer includes an adhesive layer, a barrier layer, and a wetting layer which are sequentially formed on the wafer pads. Specifically, the wetting layer mainly includes a titanium layer and a copper layer sequentially formed on the barrier layer.

Description

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、發明說明（1) 發明所屬之技術領域善曰本發明係關於一種凸塊結構，且特別是有關於一種改 "曰曰曰圓銲墊與銲料凸塊間接合強度之晶圓凸塊結構。【先前技術】速在局度資訊化社會的今日’多媒體應用市場不斷地条網^張’積體電路封裝技術也隨之朝電子裝置的數位化Γ 上略化、區域連接化以及使用人性化的趨勢發展。為達成積ί Γ要求，電子元件必須配合高速處理化、多~功能化、體小型輕量化及低價化等多方面之要求，也因此積 ^路封裝技術也跟著朝向微型化、高密度化發展。其中才〇陣列式構裝（Ball Grid Array，BGA )，f κ ρ斗碰 II r pu · v日日λ尺寸構、Chip-Scale Package，CSP )，覆晶構裝（Flip Chip’ F/C )’ 多晶片模組（Multi—Chip Module， MCM ) 等高密度積體電路封裝技術也因應而生。其中覆晶構裝技術（FI ip Chip Packaging Techno 1 〇gy )主要是利用面陣列（ar ea ar ray )的排列方式’將多個晶片輝墊（b ο n d i n g p a d )配置於晶片（d i e )之主動表面（active surface)，並在各個晶片銲墊上形成凸塊 (b u m p) ’接著再將晶片翻面（f 1 i p )之後，利用晶片銲塾上^ 的凸塊分別電性（e 1 e c t r i c a 1 1 y )及機械（m e c h a n i c a U y )連接至基板（substrate )或印刷電路板（PCB)之表面所對應的接合墊（mounting pad)。再者，由於覆晶接合技術係可應用於高接腳數（High Pin Count)之晶片封裝結構，並同時1. Description of the Invention (1) The technical field to which the invention belongs The present invention relates to a bump structure, and more particularly, to a wafer bump structure that improves the bonding strength between a circular pad and a solder bump . [Previous technology] Today's 'information-oriented society' today's 'multimedia application market is constantly expanding.' Integrated circuit packaging technology is also gradually becoming more digital, electronic, regionally connected, and user-friendly. Trends. In order to meet the requirements of electronic products, electronic components must meet the requirements of high-speed processing, multi-functionalization, small size, light weight, and low cost. Therefore, the packaging technology of micro-circuits is also moving toward miniaturization and high density. development of. Among them, the array structure (Ball Grid Array, BGA), f κ ρ bucket bump II r pu · v day λ size structure, Chip-Scale Package (CSP), flip chip structure (Flip Chip 'F / C ) 'High-density integrated circuit packaging technology such as Multi-Chip Module (MCM) was also developed. Among them, the flip chip packaging technology (FI ip Chip Packaging Techno 1 0gy) is mainly an active arrangement of a surface array (ar ea ar ray) to arranging multiple wafer glow pads (b ο ndingpad) on the chip (die). Surface (active surface), and bumps are formed on each wafer pad. Then the wafer is flipped (f 1 ip), and the bumps on the wafer pad are electrically (e 1 ectrica 1 1) y) and machinery (mechanica U y) are connected to the mounting pad corresponding to the surface of the substrate or printed circuit board (PCB). Furthermore, the flip-chip bonding technology can be applied to high-pin-count chip packaging structures, and at the same time

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具有縮小封裝面積及縮短訊號傳輸路徑等多項優點，所以覆晶接合技術目前已經廣泛地應用在晶片封裝領域。而所謂的晶圓凸塊製程，則常見於覆晶技術（f丨i p c h i p )中，主要係在形成有多個晶片的晶圓上之對外的接點（通常是金屬銲墊；亦即為晶圓銲墊）上形成球底金屬層結構（UBM，Under Bump Metallurgy structure)，接著於球底金屬層結構之上形成凸塊或植接銲球以作為後續晶片與基板（substrate)電性導通之連接介面。請參照圖1，係為習知之半導體晶圓1 〇〇結構。晶圓 1 〇〇係具有保護層1 0 2及複數個暴露出於保護層1 〇 2開口的曰曰圓銲墊1 〇 4。另外，於晶圓銲墊1 〇 4上形成有一球底金屬層1〇6(亦稱為球底金屬層結構），且球底金屬層ι〇6上形成有一銲料凸塊108。其中，球底金屬層1〇6係配置於晶圓銲塾1 0換銲料凸塊1 〇 8之間，用以作為晶圓銲墊丨〇 4及銲料凸塊1 0 8間之接合介面。請再參考圖1，習知之球底金屬層i 〇 6主要包括黏著層 (adhesion layer) 106a、阻障層（barrier Uyer)曰 1〇6級潤濕層（^1:1^叩18761〇1〇6(：。黏著層1〇6樣用以增加晶圓銲墊104及阻障層l〇6b間的接合強度，其材質例如為鋁或鈦等金屬。而阻障層i 〇 6b係用以防止阻障層 10 61)之上下兩側的金屬發生擴散（（1丨^1^1〇11)的現象，其$用材質例如為鎳釩合金或鎳等金屬。另外，潤濕層 10 6c係用以增加球底金屬層106對於銲料凸塊1〇8之沾^力 (wetability)，其常用材質包括銅等金屬。值得注意的It has many advantages such as reducing the package area and shortening the signal transmission path. Therefore, the flip-chip bonding technology has been widely used in the field of chip packaging. The so-called wafer bump process is commonly used in flip chip technology (f 丨 ipchip), which is mainly the external contacts (usually metal pads) on the wafer where multiple wafers are formed. Under the bump metal layer structure (UBM, Under Bump Metallurgy structure) is formed, and then bumps or implanted solder balls are formed on the bottom metal layer structure to serve as the subsequent electrical conduction between the wafer and the substrate. Connection interface. Please refer to FIG. 1, which is a conventional semiconductor wafer 100 structure. The wafer 100 has a protective layer 102 and a plurality of round solder pads 104 exposed through the opening of the protective layer 102. In addition, a ball-bottom metal layer 106 (also referred to as a ball-bottom metal layer structure) is formed on the wafer pad 104, and a solder bump 108 is formed on the ball-bottom metal layer 106. Among them, the ball bottom metal layer 106 is disposed between the wafer soldering pad 10 and the solder bump 108, and is used as a bonding interface between the wafer pad 104 and the solder bump 108. Please refer to FIG. 1 again. The conventional ball-bottom metal layer i 〇6 mainly includes an adhesion layer 106a and a barrier Uyer, which is a 106-grade wetting layer (^ 1: 1 ^ 叩 18761〇1). 〇6 (:. The adhesive layer 106 is used to increase the bonding strength between the wafer pad 104 and the barrier layer 106b. The material is, for example, aluminum or titanium. The barrier layer i 〇6b is used for In order to prevent the diffusion of the metal on the upper and lower sides of the barrier layer 10 61) ((1 丨 ^ 1 ^ 11)), the material used is, for example, a metal such as nickel-vanadium alloy or nickel. In addition, the wetting layer 10 6c is used to increase the wetability of the ball-bottom metal layer 106 to the solder bump 108, and its commonly used materials include metals such as copper. It is worth noting

1242273 五、發明說明（3) 是，由於錫鉛合金具有較佳之銲接特性，所以銲料凸塊 1 0 8之材質經常採用錫斜合金，惟錯對於自然環境的影響甚矩’故有無錯銲料（lead free solder)之誕生，其中含鉛或無鉛之銲料其組成成分均包括錫。請繼續參考圖1 ;一般而言，錫極易與銅發生反應，所以當球底金屬層1 0 6之潤濕層1 〇 6 c的組成成分包括銅時，在迴銲（R e f 1 ow)期間，銲料凸塊1 〇 8之錫極易與潤濕層 1 0 6 c之銅發生反應而在潤濕層1 〇 6 c及銲料凸塊1 〇 8間生成介金屬化合物（Inter-Metallic Compound，IMC)，即生 ^ Cu6Sn5°此外，當球底金屬層1 06之阻障層1 〇6b的組成成分主要包括鎳飢合金或鎳時，在迴銲期間，銲料凸塊1 〇 8 之錫先與潤濕層1 0 6 c之銅反應生成介金屬化合物，即生成 C u 6S η 5 ’接者鲜料凸塊1 0 8之錫再與阻障層106 b之錦反應生成另一種介金屬化合物，即生成N i sS η尸值得注意的是，由於銲料凸塊1 0 8之錫與阻障層1 〇 6b之鎳於較長時間反腐下，所產生的介金屬化合物（即NhSnJ係為不連續之^ 狀結構’如此將使得銲料凸塊1 〇 8易於從此處脫落。'因此，如何解決上述問題，實為本發明之重要課題。【發明内容】有鑑於此，本發明之目的係在於提出一凸塊龄構，其包含一球底金屬層，適於配置在晶圓銲墊與銲料凸塊之八間，用以減緩介金屬化合物（即N i 3Sn 4)之生成速率’ 解決鮮料凸塊易於脫落之問題，故可長時間地維持;j曰料^'1242273 V. Description of the invention (3) Yes, because tin-lead alloy has better soldering characteristics, the material of the solder bump 108 is often made of tin oblique alloy, but the impact on the natural environment is wrong, so there is no fault solder ( lead free solder), the composition of which contains lead or lead-free solder includes tin. Please continue to refer to Figure 1; in general, tin is susceptible to react with copper, so when the composition of the wetting layer 1 0 6 c of the ball-bottom metal layer 106 is copper, the reflow (R ef 1 ow ), The tin of the solder bump 1 0 8 easily reacts with the copper of the wetting layer 10 6 c to generate an intermetallic compound (Inter-Metallic) between the wet layer 1 06 c and the solder bump 1 08. Compound (IMC), that is, Cu6Sn5 ° In addition, when the composition of the barrier layer 1 〇6b of the ball bottom metal layer 1 06 mainly includes nickel alloy or nickel, during reflow, the solder bump 1 〇8 Tin first reacts with the copper of the wetting layer 1 0 6 c to form an intermetallic compound, that is, Cu 6S η 5 'then the fresh material bump 1 0 8 tin is reacted with the barrier layer 106 b to form another Intermetallic compounds, that is, the formation of Ni sS η corpses It is worth noting that, due to the long-time anticorrosion of the solder bump 108 and the nickel of the barrier layer 106b, the intermetallic compounds (ie NhSnJ It is a discontinuous structure. 'This will make the solder bump 1 08 easily come off from here.' Therefore, how to solve the above problem [Abstract] In view of this, the object of the present invention is to propose a bump age structure, which includes a ball-bottom metal layer, which is suitable for being disposed on a wafer pad and a solder bump. Bajian, used to slow down the generation rate of intermetallic compounds (ie, Ni 3Sn 4) 'solves the problem that the fresh material bumps easily fall off, so it can be maintained for a long time; j 长时间料 ^'

1242273 五、發明說明（4) 塊與晶圓銲墊間之接合強度，進而提高晶片封裝結構之使用壽命。緣是，為達上述目的，本發明係提出一晶圓凸塊結構，其係包含一晶圓，複數個晶圓銲墊，複數個球底金屬層及複數個凸塊。該複數個晶圓銲墊係配置於該晶圓之該主動表面上且暴露出設置於該晶圓之該主動表面之保護層。該球底金屬層至少具有：一黏著層，配置於晶圓銲墊上；一阻障層，配置於黏著層上；一潤濕層，配置於該阻障層上。其中，阻障層主要係由鎳魏合金、钻合金或鐵合金所組成，而潤濕層係至少由一鈦金屬層及一銅金屬層依序形成於阻障層與凸塊間，用以減緩阻障層與銲料凸塊間之介金屬化合物之形成速率，以避免銲料凸塊之錫與阻障層反應而在球底金屬層中生成接合強度較差之介金屬化合物，來解決銲料凸塊易於脫落之問題。綜前所述，由於本發明中，形成於阻障層與凸塊間之潤濕層中之鈦金屬層可進一步防止銲料凸塊之錫與阻障層之鎳反應生成不連續塊狀結構之介金屬化合物（即生成 N i 3Sn 4)，故可提高凸塊與球底金屬層之接合可靠度。1242273 V. Description of the invention (4) The bonding strength between the block and the wafer pad, thereby improving the service life of the chip package structure. The reason is that, in order to achieve the above object, the present invention proposes a wafer bump structure, which includes a wafer, a plurality of wafer pads, a plurality of ball-bottom metal layers, and a plurality of bumps. The plurality of wafer pads are disposed on the active surface of the wafer and expose a protective layer disposed on the active surface of the wafer. The ball bottom metal layer has at least: an adhesive layer disposed on the wafer pad; a barrier layer disposed on the adhesive layer; and a wetting layer disposed on the barrier layer. Among them, the barrier layer is mainly composed of nickel-wei alloy, diamond alloy, or iron alloy, and the wetting layer is formed at least between a titanium metal layer and a copper metal layer in order between the barrier layer and the bump to slow down The formation rate of the intermetallic compound between the barrier layer and the solder bump, to avoid the reaction between the solder bump tin and the barrier layer to generate an intermetallic compound with poor joint strength in the ball-bottom metal layer, to solve the solder bump easily The problem of falling off. In summary, since the titanium metal layer formed in the wetting layer between the barrier layer and the bump in the present invention can further prevent the tin of the solder bump and the nickel of the barrier layer from reacting to form a discontinuous block structure. The intermetallic compound (that is, N i 3Sn 4) is formed, so the reliability of bonding between the bump and the metal layer at the bottom of the ball can be improved.

式圖關相照 1參式將方下施以實 rL 凸之例施實佳較明發本依其示 2 面圖剖考的。參構構請結結塊塊凸圓晶之例施實佳較之明發本據根示顯圖意The formula maps the relative photos 1 The example of applying the real rL convex to the bottom of the formula is better than the clear one. Participating in the construction of the example of agglomerates and convex round crystals, the implementation is better than that of Mingfa.

m 1m 1

III I 1 第9頁 1242273 五、發明說明（5) 請參考圖2，係表示晶圓2〇〇之部分結構示意圖。晶圓 2 0 0係具有保護層2 0 2及晶圓銲墊2 04,且晶圓銲墊2〇4上係形成有一球底金屬層2 0 6。保護層2 0 2係配置於晶圓表面上，用以保護晶圓2 0 0表面並具有開口暴露出銲墊2〇4以作為晶圓對外電性連接之接點，而球底金屬層主要由黏著層 2 0 6 a、阻障層2 0 6 b及潤濕層2 0 6 c所組成，其中，阻障層 2 0 6b主要係由錄飢合金、鈷合金、鐵合金所組成，而潤渴層係至少由一鈦金屬層及一銅金屬層或銅合金層依序形成於阻障層與凸塊間。當晶圓銲墊2〇4為鋁銲墊時，黏著層/ 阻障層/潤濕層較佳地可為鋁/鎳銅合金/鈦/鋼四層結構曰。而當晶圓銲墊2 0 4為銅銲墊時，黏著層/阻障層/潤曰濕層較佳地可為鈦/鎳銅合金/鈦/銅四層結構。惟不論其黏著層、阻障層、潤濕層是由何材料所組成，一般而言，黏著 ::材質係選自於由鈦、鎢、鈦鎢合金、·、鋁；組：族群中之-種材質。其中，黏著層、阻障層及潤濕層可利用錢渡之方式或電鍍之方式形成之。承上所述，由於銲料凸塊2 0 8 (較佳地係由錫鉛重量比約為5: 95或3 : 97或1〇 : 90所形成），最後係形成於潤濕層 2 0 6 c上，故於本發明中，銲料凸塊2〇8迴銲時，銲料凸塊 2 0 8中之錫係先與潤濕層2〇6c中之銅互相反應，之後再往較下層之阻障層2 〇 6 b反應，因此能減緩錫與阻障層2 〇 6 鎳之反應速率，所以能避免過多之錫繼續與阻障層2 0 6b中之鎳於較長時間下反應，而在球底金屬層内形成不連續之塊狀結構之介金屬化合物（即生成Ni $、），而降低銲料凸III I 1 Page 9 1242273 V. Description of the invention (5) Please refer to FIG. 2, which is a schematic diagram showing a part of the wafer 2000. The wafer 200 has a protective layer 202 and a wafer pad 204, and a wafer bottom metal layer 206 is formed on the wafer pad 204. The protective layer 202 is disposed on the surface of the wafer to protect the surface of the wafer 200 and has an opening exposing the solder pad 204 as a contact point for external electrical connection of the wafer. It consists of an adhesive layer 2 0 6 a, a barrier layer 2 6 b, and a wetting layer 2 6 c. Among them, the barrier layer 2 6b is mainly composed of a hungry alloy, a cobalt alloy, and an iron alloy. The thirst layer is formed at least from a titanium metal layer and a copper metal layer or a copper alloy layer in order between the barrier layer and the bump. When the wafer bonding pad 204 is an aluminum bonding pad, the adhesion layer / barrier layer / wetting layer may preferably have a four-layer structure of aluminum / nickel-copper alloy / titanium / steel. When the wafer pad 204 is a copper pad, the adhesion layer / barrier layer / wet layer may be a four-layer structure of titanium / nickel-copper alloy / titanium / copper. No matter what the adhesive layer, barrier layer, and wetting layer are composed of, generally speaking, the adhesive :: material is selected from the group consisting of titanium, tungsten, titanium tungsten alloy, aluminum -A variety of materials. Among them, the adhesive layer, the barrier layer and the wetting layer can be formed by means of Qiandu or electroplating. As mentioned above, the solder bump 2 0 8 (preferably formed by a tin-lead weight ratio of about 5: 95 or 3: 97 or 10: 90) is finally formed on the wetting layer 2 0 6 c. Therefore, in the present invention, when the solder bump 208 is re-soldered, the tin system in the solder bump 208 first reacts with the copper in the wetting layer 206c, and then the resistance of the lower layer is lower. The barrier layer 2 0 6 b reacts, which can slow the reaction rate of tin and the barrier layer 2 06 nickel, so it can prevent excessive tin from continuing to react with the nickel in the barrier layer 2 06b over a long period of time. A discontinuous block-like intermetallic compound is formed in the metal layer of the ball bottom (that is, Ni $, is formed), and the solder bump is reduced.

1242273 五、發明說明（6) 塊2 0 8於迴銲後與球底金屬層20 6之接合強度；再者，潤濕層206c中之鈦金屬層較不易與錫相互反應及作用之特性”、、，故可降低錫向阻障層2 0 6b擴散之速率，而減緩球底金屬層、内不連續之塊狀結構之形成速率，以避免銲料凸塊之锡^ 阻障層中之鎳反應而在球底金屬層内生成接合強度較差^ 介金屬化合物，來解決銲料凸塊易於脫落之問題^ 由上可知，本發明之主要特徵係藉由潤濕層中之鈦金屬層較不易與錫相互反應及作用之特性，用以減緩阻障層中之鎳與銲料凸塊間之介金屬化合物之形成速率，以避免銲料凸塊中之錫與球底金屬層中之其他下層結構中所含之鎳於較長時間反應下形成不連續之塊狀結構之介金屬化合物（即在阻障層與黏著層間生成接合強度較差之介金屬化合物，N i J，而降低銲料凸塊與球底金屬層之接合強度。此外，當銲料凸塊於進行迴銲步驟或在一定之時間内於銲料凸塊熔點以下之溫度進行加熱反應時，能使鮮料凸塊中之錫與來自於球底金屬層之銅反應形成連續塊狀之錫銅合金層。值得注意的是，上述之球底金屬層結構，亦可適用於一般基板之銅銲墊（如圖3 A及圖3 B所示）上，亦即基板3 〇〇上之銲罩層302 (solder mask)之開口所暴露之基板銲墊 30 4上，可依序形成有鈦金屬層306a、鎳釩合金層306b、鈦金屬層306 c及銅金屬層306d’以作為基板銲墊3〇 4與銲球或凸塊接合之過渡層3 0 6 ’以提昇銲球或凸塊與基板3 〇〇接合之強度。其中，圖3A係表示該基板銲墊3 04係部分被1242273 V. Description of the invention (6) The bonding strength between block 20 and ball bottom metal layer 20 6 after re-soldering; furthermore, the titanium metal layer in wetting layer 206c is less likely to interact with and interact with tin. " Therefore, it can reduce the diffusion rate of tin to the barrier layer 206b, and slow down the formation rate of the ball-bottom metal layer and the discontinuous block structure inside, so as to avoid the tin of the solder bump ^ the nickel in the barrier layer The reaction results in poor bonding strength in the metal layer of the ball bottom. ^ Metal compounds are used to solve the problem that solder bumps are easy to fall off. ^ As can be seen from the above, the main feature of the present invention is that the titanium metal layer in the wetting layer is harder to contact. The characteristic of tin's interaction and action is used to slow down the formation rate of the intermetallic compound between the nickel in the barrier layer and the solder bump, so as to avoid the tin in the solder bump and other underlying structures in the ball-bottom metal layer. The contained nickel forms a discontinuous block structure of the intermetallic compound under a longer time reaction (that is, the intermetallic compound with a poor joint strength between the barrier layer and the adhesive layer, N i J, is reduced, and the solder bumps and the ball bottom are reduced. Bonding of metal layers In addition, when the solder bump is subjected to a reflow step or a heating reaction at a temperature below the melting point of the solder bump within a certain period of time, the tin in the fresh bump and the copper from the metal layer at the bottom of the ball can be made. The reaction forms a continuous bulk tin-copper alloy layer. It is worth noting that the above-mentioned ball-bottom metal layer structure can also be applied to the copper pads of general substrates (as shown in Figs. 3A and 3B), that is, A titanium metal layer 306a, a nickel-vanadium alloy layer 306b, a titanium metal layer 306c, and a copper metal may be sequentially formed on the substrate pad 304 exposed by the opening of the solder mask layer 302 (solder mask) on the substrate 300. The layer 306d 'is used as a transition layer 3006' for the substrate pad 300 to be bonded to the solder ball or bump. The layer 306d 'is used to improve the strength of the bonding between the solder ball or bump and the substrate 300. Among them, FIG. Pad 3 04 series part quilt

第11頁 1242273Page 11 1242273

五、發明說明（7) 銲罩層3 0 2所覆蓋；而圖3B係表示露出該銲罩層3 0 2,之一開口。 μ 土板銲墊3 04係全部暴另外’如圖4Α所示，本發明夕沖— 可由第一導電層4〇6a及第二導電；屬層結構406亦層40 6a之材質係選自於由鈦、轉：成，第-導電成族群中之一種材質，而第二太=:金、鉻、銘所組巧、總人a臨爷電層406b係包含鎳金屬V. Description of the invention (7) Covered by the solder mask layer 302; and FIG. 3B shows that one of the solder mask layers 302 is exposed. μ soil plate solder pads 3 04 series are all exposed. In addition, as shown in FIG. 4A, the present invention can be conducted by the first conductive layer 406a and the second conductive layer; the material of the layer structure 406 and the layer 40 6a is selected from From titanium, turn: into, a material of the first-conductive group, and the second too =: gold, chromium, Mingsuoqiao, general manager a Linye electrical layer 406b contains nickel metal

二:成S 、鎳釩合金層、鈷合金層、鐵合金層、複數個鈦金屬層及銅金屬層或銅合金層相互交替地形成於第一導電層40 6a及銲料凸塊40 8間所形成；其中，第一導電層 4 0 6a係直接設置與晶圓銲墊404上，而第二導電層4〇^之銅金屬層或銅合金層則可直接與銲料凸塊4 〇 8相連接。再者’當球底金屬層於晶圓上延伸以為一線路重分佈層4 1 0時（如圖4 B )，球底金屬層之一部份亦可形成線路重分佈銲墊，亦即由線路重分佈層4 1 0暴露出介電層（介電保護層）4 1 2之開口 4 1 2 a所形成之，且線路重分佈銲墊之最上層金屬層之材質係主要為銅或銅合金。其中，線路重分佈層可包含第一導電層410 a及第二導電層410b，且介電層 (介電保護層；dielectric layer)412可由聚亞醯胺II: S, nickel-vanadium alloy layer, cobalt alloy layer, iron alloy layer, a plurality of titanium metal layers and copper metal layers or copper alloy layers are alternately formed between the first conductive layer 40 6a and the solder bump 40 8 Wherein, the first conductive layer 406a is directly disposed on the wafer bonding pad 404, and the copper metal layer or copper alloy layer of the second conductive layer 406 may be directly connected to the solder bump 408. Furthermore, when the ball-bottom metal layer extends on the wafer as a circuit redistribution layer 4 10 (as shown in FIG. 4B), a part of the ball-bottom metal layer can also form a circuit redistribution pad, that is, by The redistribution layer 4 1 0 is formed by exposing the opening 4 1 2 a of the dielectric layer (dielectric protection layer) 4 and the material of the uppermost metal layer of the redistribution pad is mainly copper or copper. alloy. The circuit redistribution layer may include a first conductive layer 410a and a second conductive layer 410b, and the dielectric layer (dielectric protection layer) 412 may be made of polyimide.

(polyimide，PI)或苯併環丁烯（Benzocyclobutene，BCB)等高分子聚合物之材質所組成。於本實施例之詳細說明中所提出之具體的實施例僅為了易於說明本發明之技術内容，而並非將本發明狹義地限制於該實施例，因此，在不超出本發明之精神及以下申請專利範圍之情況，可作種種變化實施。(Polyimide, PI) or Benzocyclobutene (BCB) and other polymer materials. The specific embodiments proposed in the detailed description of this embodiment are only for easy explanation of the technical content of the present invention, and do not limit the present invention to this embodiment in a narrow sense. Therefore, the spirit and the following applications are not exceeded. The scope of patents can be implemented in various ways.

第12頁 1242273 圖式簡單說明【圖式之簡單說明】圖1為習知之球底金屬層結構剖面示意圖。圖2為依照本發明較佳實施例之凸塊結構剖面示意圖。圖3 A為依照本發明應用於基板銲墊之一較佳實施例中之基板銲墊結構剖面示意圖。圖3 B為依照本發明應用於基板銲墊之另一較佳實施例中之基板銲墊結構剖面示意圖。Page 12 1242273 Brief description of the drawings [Simplified description of the drawings] Figure 1 is a schematic cross-sectional view of a conventional ball-bottom metal layer structure. FIG. 2 is a schematic cross-sectional view of a bump structure according to a preferred embodiment of the present invention. FIG. 3A is a schematic cross-sectional view of a substrate pad structure applied to a substrate pad according to a preferred embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of a substrate pad structure according to another preferred embodiment of the present invention applied to a substrate pad.

圖4A為依照本發明另一較佳實施例之凸塊結構剖面示意圖。圖4B為依照本發明另一較佳實施例之凸塊結構剖面示Fig. 4A is a schematic sectional view of a bump structure according to another preferred embodiment of the present invention. 4B is a cross-sectional view of a bump structure according to another preferred embodiment of the present invention

意圖。【元件符號說明】 100 晶圓 102 保護層 104 晶圓銲墊 106 球底金屬層 106a 黏著層 106b 阻障層 106c 潤濕層 108 銲料凸塊 200 晶圓 202 保護層intention. [Element symbol description] 100 wafers 102 protective layer 104 wafer pads 106 ball-bottom metal layer 106a adhesive layer 106b barrier layer 106c wetting layer 108 solder bump 200 wafer 202 protective layer

第13頁 1242273Page 13 1242273

第14頁圖式簡單說明 204 晶圓銲墊 206 球底金屬層 2 0 6 a 黏著層 2 0 6 b 阻障層 2 0 6 c 潤濕層 208 銲料凸塊 300 基板 302 銲罩層 3 0 2，銲罩層 304 基板銲塾 306 過渡層 3 0 6 a 鈦金屬層 3 0 6b 鎳釩合金層 3 0 6 c 鈦金屬層 3 0 6 d 銅金屬層 400 晶圓 402 保護層 404 晶圓銲墊 406 球底金屬層 4 0 6 a 第一導電層 4 0 6b 第二導電層 408 鲜料凸塊 410 線路重分佈層 410a 第一導電層 1242273 圖式簡單說明 410b 第二導電層 412 介電層（介電保護層） 412a 開口Brief description of the drawings on page 14 204 Wafer pads 206 Ball-bottom metal layer 2 0 6 a Adhesive layer 2 0 6 b Barrier layer 2 0 6 c Wetting layer 208 Solder bump 300 Substrate 302 Solder mask layer 3 0 2 Solder mask layer 304 Substrate welding pad 306 Transition layer 3 0 6 a Titanium metal layer 3 0 6b Ni-V alloy layer 3 0 6 c Titanium metal layer 3 0 6 d Copper metal layer 400 Wafer 402 Protective layer 404 Wafer pad 406 Ball-bottom metal layer 4 0 6 a First conductive layer 4 0 6b Second conductive layer 408 Fresh bump 410 Circuit redistribution layer 410a First conductive layer 1242273 The diagram briefly illustrates the 410b second conductive layer 412 dielectric layer ( Dielectric protection layer) 412a opening

第15頁Page 15

Claims

1242273 六、申請專利範圍 6 ·如申請專利範圍第4項所述之晶圓凸塊結構，其中該銲料凸塊之材質由錯及錫所組成。 7 ·如申請專利範圍第6項所述之晶圓凸塊結構，其中該銲料凸塊之錫錯重量比為5 : 9 5。 8. 如申請專利範圍第5項所述之晶圓凸塊結構，其中該銲料凸塊之錫热重量比為3 : 9 7。 9. 如申請專利範圍第5項所述之晶圓凸塊結構，其中該銲料凸塊之錫錯重量比為1 0 : 9 0。 1 〇.如申請專利範圍第1項所述之晶圓凸塊結構，其中該第一導電層之材質係選自於由鈦、鎢、鈦鎢合金、鉻、鋁所組成族群中之一種材質。1242273 6. Scope of patent application 6 • The wafer bump structure described in item 4 of the scope of patent application, wherein the material of the solder bump is composed of tin and tin. 7 · The wafer bump structure as described in item 6 of the scope of the patent application, wherein the solder bump has a tin-to-scatter weight ratio of 5:95. 8. The wafer bump structure as described in item 5 of the scope of patent application, wherein the solder thermal weight ratio of tin to solder is 3: 97. 9. The wafer bump structure as described in item 5 of the scope of patent application, wherein the solder bump has a tin-to-scatter weight ratio of 10:90. 10. The wafer bump structure according to item 1 of the scope of the patent application, wherein the material of the first conductive layer is one selected from the group consisting of titanium, tungsten, titanium-tungsten alloy, chromium, and aluminum. .

1242273 六、申請專利範圍 1 3 .如申請專利範圍第1 1項之晶圓凸塊結構，其中該介電層之材質係包含苯併環丁稀（Benzocyclobutene，BCB)。 1 4 .如申請專利範圍第1 1項所述之晶圓凸塊結構，更形成一銲料凸塊於該線路重分佈銲墊上。 1 5.如申請專利範圍第1項所述之晶圓凸塊結構，其中該第二導電層更包含一钻金屬層。 1 6.如申請專利範圍第1項所述之晶圓凸塊結構，其中該第二導電層更包含一鐵金屬層。 1 7.如申請專利範圍第1項所述之晶圓凸塊結構，其中該第二導電層更包含一始合金層。 1 8 .如申請專利範圍第1項所述之晶圓凸塊結構，其中該第二導電層更包含一鐵合金層。 1 9.如申請專利範圍第4項所述之晶圓凸塊結構，其中該球底金屬層更包含一錫銅合金層’且該錫銅合金層係為一連續塊狀體。 2 0. —種球底金屬層結構，適於配置在一晶圓之一晶圓銲1242273 VI. Scope of patent application 1 3. For the wafer bump structure of item 11 of the patent application scope, wherein the material of the dielectric layer includes Benzocyclobutene (BCB). 14. The wafer bump structure described in item 11 of the scope of patent application, further forming a solder bump on the circuit redistribution pad. 1 5. The wafer bump structure according to item 1 of the scope of patent application, wherein the second conductive layer further comprises a diamond metal layer. 16. The wafer bump structure according to item 1 of the scope of patent application, wherein the second conductive layer further comprises a ferrous metal layer. 1 7. The wafer bump structure according to item 1 of the scope of patent application, wherein the second conductive layer further comprises a starting alloy layer. 18. The wafer bump structure according to item 1 of the scope of patent application, wherein the second conductive layer further comprises an iron alloy layer. 19. The wafer bump structure according to item 4 of the scope of the patent application, wherein the spherical metal layer further comprises a tin-copper alloy layer 'and the tin-copper alloy layer is a continuous block. 2 0. —Spherical bottom metal layer structure, suitable for disposing on one wafer

第18頁 1242273 六、申請專利範圍墊上，該晶圓上更具有一保護層以暴露出該晶圓銲墊，其中該球底金屬層結構係包括：一黏著層，配置於該晶圓銲墊上；一阻障層，配置於該黏著層上；及一潤濕層，配置於該阻障層上，其中該潤濕層係包含複數個鈦金屬層及複數個銅金屬層，且依序相互交替地形成於該阻障層上。 2 1 .如申請專利範圍第2 0項所述之球底金屬層結構，更包含一銲料凸塊且該銲料凸塊係設置於該潤濕層上。 2 2 .如申請專利範圍第2 1項所述之球底金屬層結構，其中該銲料凸塊係與該等銅金屬層之一相接合。 2 3 .如申請專利範圍第2 2項所述之球底金屬層結構，其中該鲜料凸塊之錫船重量比係為5 : 9 5。 2 4 .如申請專利範圍第2 1項所述之球底金屬層結構，其中該銲料凸塊之錫鉛重量比係為3 : 9 7。 2 5 .如申請專利範圍第2 1項所述之球底金屬層結構，其中該銲料凸塊之錫鉛重量比係為1 0 : 9 0。 2 6 .如申請專利範圍第2 0項所述之球底金屬層結構，其中Page 18 1242273 6. On the patent application pad, there is a protective layer on the wafer to expose the wafer pad. The ball-bottom metal layer structure includes: an adhesive layer disposed on the wafer pad. A barrier layer disposed on the adhesive layer; and a wetting layer disposed on the barrier layer, wherein the wetting layer includes a plurality of titanium metal layers and a plurality of copper metal layers, and sequentially each other Alternately formed on the barrier layer. 2 1. The ball-bottom metal layer structure described in item 20 of the scope of patent application, further comprising a solder bump, and the solder bump is disposed on the wetting layer. 2 2. The ball-bottom metal layer structure according to item 21 of the patent application scope, wherein the solder bump is bonded to one of the copper metal layers. 2 3. The ball-bottom metal layer structure described in item 22 of the scope of the patent application, wherein the weight ratio of the tin boat of the fresh material bump is 5:95. 24. The ball-bottom metal layer structure described in item 21 of the scope of patent application, wherein the solder-to-lead weight ratio is 3:97. 25. The ball-bottom metal layer structure described in item 21 of the scope of the patent application, wherein the solder-to-lead weight ratio is 10:90. 2 6. The ball-bottom metal layer structure described in item 20 of the patent application scope, wherein

第19頁 1242273 六、申請專利範圍該黏著層之材質係選自於由鈦、鎢、鈦鎢合金、鉻、鋁所組成族群中之一種材質。 2 7 ·如申請專利範圍第2 0項所述之球底金屬層結構，其中該阻障層之材質係選自於鎳、鎳合金、鎳釩合金、鈷合金、鐵合金、鐵及鈷所組成族群中之一種材質。 2 8 .如申請專利範圍第2 0項所述之球底金屬層結構，其中該阻障層係以電鍍之方法形成。 2 9 .如申請專利範圍第2 0項所述之球底金屬層結構，其中該阻障層係以濺渡之方法形成。 3 0 .如申請專利範圍第2 0項所述之球底金屬層結構，更包含一介電層，其中該球底金屬層係為一線路重分佈層，且該介電層係形成於該線路重分佈層上並具有一開口暴露出該線路重分佈層以形成一線路重分佈銲墊。 3 1. —種基板銲墊結構，該基板銲墊結構係形成於一基板上，且該基板之一銲罩層之一開口係暴露出該基板銲墊結構，其中該基板銲墊結構係包含：一基板銲墊；一第一金屬層，配置於該基板鲜塾上；一錄合金層，配置於該第一金屬層上；及Page 19 1242273 VI. Scope of patent application The material of the adhesive layer is one selected from the group consisting of titanium, tungsten, titanium-tungsten alloy, chromium, and aluminum. 2 7 · The ball-bottom metal layer structure described in item 20 of the scope of patent application, wherein the material of the barrier layer is selected from the group consisting of nickel, nickel alloy, nickel vanadium alloy, cobalt alloy, iron alloy, iron and cobalt. A material in the ethnic group. 28. The ball-bottom metal layer structure as described in item 20 of the patent application scope, wherein the barrier layer is formed by electroplating. 2 9. The ball-bottom metal layer structure described in item 20 of the scope of patent application, wherein the barrier layer is formed by a sputtering method. 30. The ball-bottom metal layer structure described in item 20 of the scope of patent application, further comprising a dielectric layer, wherein the ball-bottom metal layer is a circuit redistribution layer, and the dielectric layer is formed on the The circuit redistribution layer has an opening to expose the circuit redistribution layer to form a circuit redistribution pad. 3 1. A substrate pad structure, the substrate pad structure is formed on a substrate, and an opening of a solder mask layer of the substrate exposes the substrate pad structure, wherein the substrate pad structure includes : A substrate pad; a first metal layer disposed on the substrate; an alloy layer disposed on the first metal layer; and

1242273 六、申請專利範圍一第二金屬層，配置於該鎳合金層上，其中該第二金屬層係至少包含一欽金屬層。 3 2 .如申請專利範圍第3 1項所述之基板銲墊結構，其中該銲罩層係覆蓋該第二金屬層。 3 3 ·如申請專利範圍第3 1項所述之基板銲墊結構，其中該開口係完全暴露出該第二金屬層。 3 4 .如申請專利範圍第3 1項所述之基板銲墊結構，其中該第一金屬層之材質係選自於由鈦、鐫、鈦嫣合金、鉻、I呂所組成族群中之一種材質。 3 5 .如申請專利範圍第3 1項所述之基板銲墊結構，其中該第二金屬層係包含一鈦金屬層及一銅金屬層依序形成於該鎳合金層上。 3 6 .如申請專利範圍第3 1項所述之基板銲墊結構，其中該第二金屬層係包含一鈦金屬層及一銅合金層依序形成於該鎳合金層上。 3 7. —種基板銲墊結構，該基板銲墊結構係形成於一基板上，且該基板之一銲罩層之一開口係暴露出該基板銲墊結構，其中該基板銲墊結構係包含：1242273 VI. Scope of patent application A second metal layer is disposed on the nickel alloy layer, wherein the second metal layer includes at least one metal layer. 32. The substrate pad structure according to item 31 of the scope of patent application, wherein the solder mask layer covers the second metal layer. 3 3 · The substrate pad structure according to item 31 of the scope of patent application, wherein the opening completely exposes the second metal layer. 34. The substrate pad structure as described in item 31 of the scope of the patent application, wherein the material of the first metal layer is one selected from the group consisting of titanium, titanium, titanium alloy, chromium, and aluminum. Material. 35. The substrate pad structure according to item 31 of the scope of the patent application, wherein the second metal layer comprises a titanium metal layer and a copper metal layer sequentially formed on the nickel alloy layer. 36. The substrate pad structure according to item 31 of the scope of the patent application, wherein the second metal layer comprises a titanium metal layer and a copper alloy layer sequentially formed on the nickel alloy layer. 3 7. A substrate pad structure, the substrate pad structure is formed on a substrate, and an opening of a solder mask layer of the substrate exposes the substrate pad structure, wherein the substrate pad structure includes :

第21頁 1242273 六、申請專利範圍一基板銲塾；一第一金屬層，配置於該基板銲塾上；一鎳金屬層，配置於該第一金屬層上；及一鈦金屬層及一銅金屬層依序形成於該鎳金屬層上；其中該銲罩層係覆蓋該銅金屬層之一部份。Page 21 1242273 VI. Patent application scope-a substrate solder; a first metal layer disposed on the substrate solder; a nickel metal layer disposed on the first metal layer; and a titanium metal layer and a copper Metal layers are sequentially formed on the nickel metal layer; wherein the solder mask layer covers a portion of the copper metal layer.

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