九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝製程與覆晶封裝結 構，且特別是有關於一種適用於製作一導線架型式封裝體 (lead frame type package)的晶片封裝製程與覆晶封裝結 構0 【先前技術】 近年來，隨著電子技術的日新月異，高科技電子產 業的相繼問世，使得更人性化、功能更佳的電子產品不斷 地推陳出新，並朝向輕、薄、短、小的趨勢設計。就晶片 構裝的技術而言，每一顆由晶圓（wafer)切割所形成的 裸晶片（die)，例如以導線接合（wire b〇nding)或覆晶 接合（flip chip bonding)等方式，而配置於一載板（carrier) 之，面，其中此載板例如為導線架或基板（substrate)等， =曰片之絲表面（aetive suiW)财有乡個接合塾， 塾得以經由承載器之傳輸線路及接點，而 罨性連接至外部之電子裝置。 圖1A!會示為習知之一種導線架 參照圖1A，習知的導線架型式丄 導缘芊式而讓晶片與導線架之間電性^接。此 导綠架支式之封裝體刚至安 材料層120、—晶只⑽，匕3 H卞U〇、一銲接 以下列數個步爾所製作而成H塊體⑽係 此導線架η。例如包含多個引腳，接刷 124097 §585twf.doc (printing)製程形成一銲接材料層12〇於導_ ii〇之引腳 110a的表面112上，其中銲接材料層⑽具有多個凸起 之圖案。之後，提供一晶片130，並將多個凸塊140配置 於晶片130之多個接點132上。然後，將晶片13〇配置於 導線架110之表面112上，以使得晶片13〇上之每一凸塊 140位於對應之銲接材料層120上。 圖1B繪示為習知之一種導線架型式之封裝體，其迴 銲並填上封裝膠體後之剖面示意圖。請參照圖1β ,接著， 進行一迴銲(reflow)步驟，以使得晶片13〇藉由凸塊14〇 以及銲接材料層120與導線架110之表面112電性與結構 f連接最後，藉由注模製程(molding process)形成一封 裝膠體150,以包覆住凸塊14〇、導線架11〇之引腳11〇a 的部分區域以及晶片13〇的部分區域，即完成導線架型式 之封裝體100的製作。 、一值得注意的是，在進行迴銲時，凸塊14〇會處於微 熔融的狀悲，此時各個凸塊丨4〇與導線架11〇的引腳n〇a 之間的沾附面積(wetting area)大小將無法十分精確地控 制。換言之，在經過迴銲之後，晶片13〇與導線架11〇之 間的凸塊140高度將無法有效地控制，進而影響到導線架 型式之封裝體1〇〇的信賴性(reliability)。 【發明内容】 •有鑑於此，本發明之目的就是在提供一種晶片封裝 製，，其適用於製作一導線架型式的封裝體，可有效地控 制每一凸塊的高度，而讓晶片能夠平坦地接合於導線架 12彻7§585_ 上。 本發明之目的就是在提供一種覆晶封裝結構，其適 用於-導_型式的縣體，可有效地控制每—凸塊的高 度，而讓晶片能夠平坦地接合於導線架上。 ^為達本發明之上述目的，本發明提出一種晶片封裝 製私，其適用於製作一導線架(leadframe)型式的封裝體， 此晶片封裝製程包含下列數個步驟，首先，提供一導線架， 此導線架具有多個引腳。接著，形成—具有助銲劑之塑膠 材料層於導線架之引腳上。之後，形成一銲接材料層於具 有助銲劑之塑膠材料層上。然後，提供一晶片，此晶片係 具有多個凸塊。接著，將晶片配置於導線架上，以使得這 些凸塊位於知接材料層上。之後，進行一迴銲步驟，以使 得晶片可藉由這些凸塊以及銲接材料層而與導線架之引腳 電性連接，其中具有助銲劑之塑膠材料層係環繞於這些凸 塊之外，以限制這些凸塊與導線痦之間的接合面積。 為達本發明之上述目的，本發明提出另一種晶片封 裝製程’其適用於製作一導線架(lead franie)型式的封裝 體，此晶片封裝製程包含下列數個步驟，首先，提供一導 線架’此導線架具有多個引腳。接著，形成一銲接材料層 於導線架之多個引腳上。之後，形成一具有助銲劑之塑膠 材料層於鲜接材料層上。然後，提供一晶片，此晶片係具 有多個凸塊。接著，將晶片配置於導線架上，以使得這些 凸塊位於具有助銲劑之塑膠材料層上。之後，進行一迴銲 步驟，以使得晶片可藉由這些凸塊以及銲接材料層而與導 I24097§ 585twf.doc 繞^這’其中具有助鲜劑之塑膠材料層係環 面積。 卜’以限制這些凸塊與導線架之間的接合 中具例所述之晶片封_，其 印刷製程， ，且Γ助、二Τ:的較佳實施例所述之晶片封裝製程，其 胺等有助W之塑踢材料層之材質包含環氧樹脂或聚乙酿 中在發：的較佳實施例所述之晶片封裝製程，其 配置於這此Ϊ鮮步，之後’此具有助銲劑之塑膠材料層係 部分區域r塊與廷些引腳之接合區之外以及這些凸塊之 ，照^發_難實施綱叙晶片封裝製程 銲步驟之後，更包含形成-封裝膠體，以ϊ _覆甘沒二凸塊、此導線架的部分區域以及晶片的部分 「成、中此導線架係一無外引腳型式之導線架(ν、 ea e type ieadframe)，且此封裝膠體係顯露部分之這此 引腳之下表面。 ‘ 為達本發明之上述目的，本發明提出一種覆晶封 構’此覆晶封裝結構包括—導線架、—晶片、—塑膠^ 料，及-封褒膠體，其中導線架具有多個引腳，而晶片具 有夕個凸塊，且晶片係配置於導線架上，並藉由這些凸 與這些引腳電性連接。塑膠材料層係環繞配置於這些凸塊 124097§585twf,〇c 積，而封裝膠 之外’以限制這些凸塊與此導線架的接合面 體係覆蓋於晶片及導線架上。 依照本發明的較佳實施例所狀覆晶封裝結構，其 中塑膠材料層之材質包括環氧樹脂或聚乙_。 依照本發明的較佳實施觸狀覆晶封裝結構，其 中導線架係-無外弓丨腳型式之導線架(Ncm_leaded type leadframe)，且封裝膠體係顯露出部分這些引腳之下表面。 基於上述’本發明之晶片封裝製程與覆晶封裝結構 因在線架上形成一具有助銲劑之塑膠材料層。因此，當 封裝體在進行迴銲步驟時，環繞於凸塊外之娜材料層可 有效限制住凸塊底部則腳之表面的沾附面積，進而維持 凸塊的高度，以提昇封裝體的信賴性。 為讓本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉-較佳實施例，並配合所關式，作詳細說明如 p 〇 一 【實施方式】 【第一實施例】 圖2A〜2E繪不為依照本發明第一實施例的一種晶 片封裝製程。本發明之晶片封裝製程係適用於製作一導線 架(lead frame)型式的封裝體，其係以覆晶接合的方式而讓 晶片與導線架之間連接。請先參照圖2C，此導線架型式 之覆晶封裝結構200例如至少包含一導線架21〇、具有助 銲劑之塑膠材料層220、一銲接材料層23〇、一晶片24〇、 多個凸塊250及一封裝膠體260等。 124097§585twf,oc 數個=== 具有多個引腳210a。接著，形成_具有助=:=: 料層220於導線架210之這些引腳⑽的表:=材 而此具有助銲劑之塑膠材料層22〇之形成方法例 刷(printing)製程或是其他塗佈製程。本實 1』 的材質例如為環氧樹脂㈣二 ίίί 胸㈣等’且上述之具有助銲劑之塑膠 材料層220例如具有多個凸起的圖案，而各個 幸 係分別對應於導線架210的接腳21〇a。之後，形成2 接材料層230於具有助銲劑之塑膠材料層22〇上，而此带 ，接材料層230的方法例如為—印刷(priming)製程或是 佈製程。本實施例中，銲接材料層23()例如為_ 以solder paste)等。同樣地，銲接材料層23〇例如 之圖案’且各個凸起之㈣齡麟應於^線架 、接腳21Ga。更詳細而言，凸_案之塑膠材料層⑽ 例如係位於各個接腳21〇a ’且凸起圖案之銲接材料層23〇 例如係位於凸起圖案之塑膠材料層22〇上。 請參照圖2B，接著，提供-晶片24G，此晶片240 例如具有多個凸塊25G與多個接點242，其中凸塊25〇係 =於接點242上’且這些凸塊25〇的形成方法例如為一 塊製程(bumping process)。 ，同時參照圖2C及2D，接著，將晶片24〇配置於 線架210上，使得這些凸塊25〇可分別位於銲接材料層 124097§58_c 上。之後，再進行—迴銲步驟，以使得晶片24〇能夠 藉由凸塊250以及銲接材料層23〇而與導線架21〇之引腳 210a電性及結構性連接。在進行迴銲的過財，鲜接材 料2 230與具有助銲劑之塑膠材料層22〇冑處於微炫融的 狀悲，因此，凸塊250與銲接材料層23〇會自然地熔融為 -體’並焊接在導線架21〇之引腳21〇a上，而具有助鲜 劑士塑膠材料層220則會環繞於這些凸塊細外，並配置 於适些凸塊250與這些引腳21Ga之接合區之外以及這些 凸塊250之部分區域，以限制凸塊25〇與導線架21〇之間 的沾附面積。 請參照圖2E ’最後，形成—封裝賴，以包覆 住凸塊250、導_ 21G之⑽施的部分區域以及晶 片240的部分區域，完成導線架型式之覆晶封裝結構綱 的製作本實把例中’封裝膠體細例如係藉由注模製程 所形成。 - 值知注意的是，相較於習知的晶片封裝製程，本發 =之晶片封裝製程，因在導線架型式覆晶封裝結構200之 ¥線采210上配置有一具有助鮮劑之塑膠材料層，其 中之助銲劑可幫助凸塊250及導線架21〇之間的焊接。因 此，當覆晶封裝結構200在進行上述之迴銲步驟時，環繞 於這些凸塊250外之_材料層22〇可有效限制住凸^ 250底部與引腳21〇a之表面212的沾附面積，進而維持 凸塊250的高度。換言之，本發明之二次印刷的技術可提 供凸塊250良好的疲勞(fatigue)支撐，進而提昇覆晶封裝 124〇97§585twf,〇c 結構200的信賴性。 【第二實施例】 圖2A’、2B、2C、2D至2E繪示為依照本發明第二 實施例的一種晶片封裝製程。請參照圖2A，，相較於第一 實施例之晶片封裝製程，第二實施例之晶片封裝製程的特 色在於具有助焊劑之塑膠材料層222以及銲接材料層232 的形成順序不同。有別於第一實施例，本實施例係先形成 銲接材料層232,之後才形成具有助焊劑之塑膠材料層 222，其餘步驟及其製程順序則與第一實施例之晶片封裝 鲁 製程相同，故本實施例在此便不再進行細部之說明。 值得注意的是，相較於第一實施例，具有助焊劑之 塑膠材料層222以及銲接材料層232的形成順序並不影響 到迴焊之後的結構，因此，本實施例具有與第一實施例相 同之優點與功效。 【第三實施例】 圖2A、2B、2C、2D至2E，繪示為依照本發明第三 實施例的一種晶片封裝製程。請參照圖2E，，相較於第一 實施例之晶片封裝製程，第三實施例之晶片封裝製程係適 用於製作一無外引腳型式之導線架（N〇n-leaded type leadframe)。有別於第一實施例，本實施例之封裝膠體26〇a 係包覆住這些凸塊250、晶片240以及導線架210之部分 區域，而顯露出部分之這些引腳210a之下表面。其餘步 驟及其製程順序則與第一實施例之晶片封裝製程相同，故 本實施例在此便不再進行細部之說明。 12 124097 85twf.doc 至於本實施例具有與第一實施例相同之優點與功 效，在此便不再贅述。 【第四實施例】 圖2A’、2B、2C、2D至2E，繪示為依照本發明第四 實施例的一種晶片封裝製程。請參照圖2A，，相較於第三 實施例之晶片封裝製程，本實施例係先形成銲接材料層 232，之後才形成具有助焊劑之塑膠材料層222，其餘步 驟及其製程順細與第三實施例之晶片封裝製程相同，而 本實施例與第三實施例具有相同之優點與功效，故在此便 不再贅述。 綜上所述，本發明的晶片封裝製程與覆晶封裝結構 至少具有下列優點： height) 1·本發明之晶片封裝製程與覆晶封裝結構中，所採用 有助銲劑之塑膠材料層可有效地控制凸塊高度(bump 本發明之晶M ^製程與覆晶封裝結構係將助焊的 =整合於具有助銲劑之塑膠材料層中，因此具有助鮮劑 娜材料層可同時兼顧助焊以及限制凸塊沾附面積的功 雖然本發明已以 孝父佳實施例揭露如上，然盆並非 用以限定本發明，任何孰羽+朴菇土 — ’ W、亚非 掉#— 7j篇此技藝者，在不脫離本發明之 精神和乾圍内，當可作此哞 保護範圍~1彳_誠稱，目此本發明之 乾I視後附之巾睛專利範圍所界定 【圖式簡單說明】 124097&驗doc 示意示為習知之—種導線架型式之封装體的剖 圖1B纷示為習知> ^ ., 辉並填上封裝膠體後之:二線架型式之封裝 封^程M〜2E_為依照本㈣第-實施例的-種晶片 圖 2A，、2B、2C、2D -、 實施例的-種晶>{封裝製程至2E緣不為依照本發明第二 面 其迴 圖 2A、2B、2C、2D 一、 實施例的—種晶片封裝製程至2E’繪示為依照本發明第三 圖 2A’、2B、2C、 實施例的-種晶片封I製程至2E’緣不為依照本發明第四 【主要元件符號說明】 100 :封裝體 11(^導線架 110a ·•引腳 112 ·表面 120 :銲接材料層 130 ·晶片 132 :接點 134 :表面 140 ·凸塊 15〇 :封裝膠體 2〇〇 :覆晶封裝結構 210 ··導線架 Ι24097§„ 210a :引腳 212 :表面 220、222 :具有助銲劑之塑膠材料層 230、232 :銲接材料層 240 :晶片 242 :接點 244 :表面 250 :凸塊 260、260a :封裝膠體 15Nine, the description of the invention: [Technical field to which the invention belongs] The present invention relates to a chip packaging process and a flip-chip packaging structure, and more particularly to a chip suitable for making a lead frame type package. Packaging process and flip-chip packaging structure 0 [Previous technology] In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and better-functioning electronic products continue to be introduced, and they are light and thin. , Short, small trend design. In terms of wafer assembly technology, each bare die formed by wafer cutting is, for example, by wire bonding or flip chip bonding. It is arranged on the surface of a carrier, where the carrier is, for example, a lead frame or a substrate, etc. = aetive suiW There is a bonding joint 塾, and 塾 can pass through the carrier The transmission lines and contacts are connected to external electronic devices. FIG. 1A! Will be shown as a conventional lead frame. Referring to FIG. 1A, the conventional lead frame type (lead edge) type allows the chip and the lead frame to be electrically connected. This green-frame-supported package has just arrived at the material layer 120, a crystal frame, a dagger 3 H, U 0, and a solder. An H block made by the following steps is a lead frame η. For example, it includes a plurality of pins, and the brush 124097 §585twf.doc (printing) process forms a layer of soldering material 120 on the surface 112 of the pin 110a, wherein the layer of soldering material ⑽ has a plurality of protrusions. pattern. Thereafter, a wafer 130 is provided, and a plurality of bumps 140 are disposed on a plurality of contacts 132 of the wafer 130. Then, the wafer 130 is disposed on the surface 112 of the lead frame 110 so that each bump 140 on the wafer 130 is located on the corresponding solder material layer 120. FIG. 1B is a schematic cross-sectional view of a conventional lead frame type package after being re-soldered and filled with a packaging gel. Please refer to FIG. 1β. Next, a reflow step is performed so that the chip 13 is electrically connected to the structure f through the bump 14 and the solder material layer 120 and the surface 112 of the lead frame 110. The molding process forms a packaging gel 150 to cover the bumps 140, a portion of the pins 11a of the lead frame 11a, and a portion of the chip 13o, thereby completing the lead frame type package. Production of 100. First, it is worth noting that, during the re-soldering, the bumps 140 will be in a slightly molten state. At this time, the adhesion area between each bump 丨 40 and the lead n〇a of the lead frame 110. The size of the (wetting area) cannot be controlled very precisely. In other words, after the reflow, the height of the bump 140 between the chip 13 and the lead frame 110 cannot be effectively controlled, which further affects the reliability of the lead frame type package 100. [Summary of the Invention] In view of this, the object of the present invention is to provide a chip package, which is suitable for making a lead frame type package, which can effectively control the height of each bump, so that the chip can be flat. The ground is connected to the lead frame 12 through 7§585_. The object of the present invention is to provide a flip-chip package structure, which is suitable for a conductive body of a conductive type, and can effectively control the height of each bump, so that the chip can be flatly bonded to the lead frame. ^ In order to achieve the above-mentioned object of the present invention, the present invention proposes a chip packaging system, which is suitable for making a leadframe type package. The chip packaging process includes the following steps. First, a lead frame is provided. This lead frame has multiple pins. Next, a layer of plastic material with flux is formed on the leads of the lead frame. After that, a solder material layer is formed on the plastic material layer with the flux. Then, a wafer is provided, the wafer having a plurality of bumps. Next, the wafer is arranged on the lead frame so that the bumps are located on the junction material layer. Then, a re-soldering step is performed so that the chip can be electrically connected to the lead of the lead frame through the bumps and the layer of solder material. The plastic material layer with the flux surrounds the bumps to Limit the joint area between these bumps and the conductor 痦. In order to achieve the above object of the present invention, the present invention proposes another chip packaging process 'which is suitable for manufacturing a lead franie type package. This chip packaging process includes the following steps. First, a lead frame is provided' This lead frame has multiple pins. Next, a layer of solder material is formed on the pins of the lead frame. After that, a plastic material layer with a flux is formed on the fresh material layer. Then, a wafer is provided, the wafer having a plurality of bumps. Next, the chip is arranged on the lead frame so that the bumps are located on a plastic material layer with a flux. Then, a re-soldering step is performed so that the wafer can be guided by the bumps and the solder material layer to the area of the ring of the plastic material layer having the freshener therein. In order to limit the bonding between these bumps and the lead frame, the wafer sealing process described in the example, its printing process, and the wafer packaging process described in the preferred embodiment of Γ, Τ :, its amine The material of the plastic kick material layer that helps W includes the epoxy resin or polyethylene in the preferred embodiment: the chip packaging process described in the preferred embodiment is configured here, and then 'this has a flux The plastic material layer is part of the area outside the bonding area between the r block and the pins and the bumps. It is difficult to implement the outline of the chip packaging process after the soldering step, and it further includes forming-encapsulating colloids. Covered with two bumps, a part of the lead frame and a part of the chip, the lead frame is a lead frame (ν, ea e type ieadframe) without external lead type, and the exposed part of the encapsulation system The lower surface of this pin. 'In order to achieve the above-mentioned object of the present invention, the present invention proposes a flip-chip package structure. This flip-chip package structure includes-lead frame,-chip,-plastic material, and-sealing gel Where the lead frame has multiple pins and the wafer has There are bumps, and the chip is arranged on the lead frame, and is electrically connected to these pins through the bumps. A layer of plastic material is arranged around the bumps 124097 §585twf, 0c, and outside the encapsulation 'In order to limit the bonding surface system of these bumps and the lead frame to cover the chip and the lead frame. According to a preferred embodiment of the present invention, a flip-chip package structure, wherein the material of the plastic material layer includes epoxy resin or polyethylene. _. According to a preferred embodiment of the present invention, a contact-like flip-chip package structure is adopted, in which the lead frame is a lead frame (Ncm_leaded type leadframe), and the lower surface of these pins is exposed by the encapsulation system. Based on the above-mentioned chip packaging process and flip-chip packaging structure of the present invention, a plastic material layer with a flux is formed on the wire frame. Therefore, when the package is subjected to the reflow step, the material layer surrounding the bumps may Effectively limit the adhesion area of the bottom of the bump and the surface of the foot, thereby maintaining the height of the bump to improve the reliability of the package. In order to make the above-mentioned objects, features and advantages of the present invention more Obviously easy to understand, the following is a detailed description of the preferred embodiment and the related formula, such as p 〇 [Embodiment] [First Embodiment] Figures 2A to 2E are not the first embodiment according to the present invention. A chip packaging process. The chip packaging process of the present invention is suitable for making a lead frame type package, which connects the chip and the lead frame by flip-chip bonding. Please refer to the figure first 2C. This lead frame type flip chip package structure 200 includes at least a lead frame 21, a plastic material layer 220 with a flux, a solder material layer 23, a wafer 24, a plurality of bumps 250, and a package. Colloid 260, etc. 124097§585twf, oc number === has multiple pins 210a. Next, form a table with these leads 助 with the help layer =: =: material layer 220 on the lead frame 210, and the method of forming the plastic material layer 22 with the flux, such as a printing process or other Coating process. The material of this example 1 is, for example, epoxy resin, chest, etc., and the above-mentioned plastic material layer 220 with flux has, for example, a plurality of raised patterns, and each of them corresponds to the connection of the lead frame 210 respectively. Feet 21〇a. After that, a two-contact material layer 230 is formed on the plastic material layer 22 with a flux, and the method of connecting the material layer 230 to this belt is, for example, a priming process or a fabricating process. In this embodiment, the solder material layer 23 () is, for example, solder paste). Similarly, the layer 23 of the solder material, such as a pattern, and the protrusions of each protrusion should be on the wire frame and the pins 21Ga. In more detail, the convex plastic material layer ⑽ is, for example, a solder material layer 23o located on each pin 21o 'and the convex pattern is, for example, located on the convex material 22o. Please refer to FIG. 2B. Next, a wafer 24G is provided. This wafer 240 has, for example, a plurality of bumps 25G and a plurality of contacts 242, where the bumps 250 are on the contacts 242 'and the formation of these bumps 25 The method is, for example, a bumping process. Referring to FIGS. 2C and 2D at the same time, the wafer 240 is arranged on the wire frame 210 so that the bumps 250 can be respectively located on the solder material layer 124097§58_c. After that, a re-soldering step is performed so that the wafer 240 can be electrically and structurally connected to the lead 210a of the lead frame 21 through the bump 250 and the solder material layer 23. After making money in re-soldering, the fresh joint material 2 230 and the plastic material layer 22 ° with flux are in a slightly fused state. Therefore, the bump 250 and the solder material layer 23 ° will naturally melt into a body. 'And soldered on the lead 21o of the lead frame 21o, and the plastic material layer 220 with a freshener is surrounded by these bumps, and is arranged on the bumps 250 and the pins 21Ga. Outside the bonding area and a part of these bumps 250, the adhesion area between the bumps 25 and the lead frame 21 can be limited. Please refer to FIG. 2E 'Finally, the formation-encapsulation cover is used to cover the bump 250, a part of the conductive region 21G and a part of the chip 240 to complete the fabrication of the lead frame type flip-chip package structure outline. In the example, the encapsulating colloid is formed by, for example, an injection molding process. -It is important to note that compared to the conventional chip packaging process, the present chip packaging process is because a plastic material with a freshener is arranged on the lead frame type flip-chip packaging structure 200 and the wire mining 210. Layer, among which the flux can help the soldering between the bump 250 and the lead frame 21o. Therefore, when the flip-chip packaging structure 200 performs the above-mentioned re-soldering step, the material layer 22o surrounding the bumps 250 can effectively limit the adhesion of the bottom of the bump 250 and the surface 212 of the lead 21a. Area, thereby maintaining the height of the bump 250. In other words, the secondary printing technology of the present invention can provide good fatigue support for the bump 250, thereby improving the reliability of the flip-chip package 124〇97§585twf, 〇c structure 200. [Second Embodiment] Figs. 2A ', 2B, 2C, 2D to 2E illustrate a chip packaging process according to a second embodiment of the present invention. Please refer to FIG. 2A. Compared with the wafer packaging process of the first embodiment, the wafer packaging process of the second embodiment is different in the forming order of the plastic material layer 222 and the solder material layer 232 with flux. Different from the first embodiment, in this embodiment, a solder material layer 232 is formed first, and then a plastic material layer 222 with a flux is formed. The remaining steps and the process sequence are the same as those of the wafer packaging process of the first embodiment. Therefore, this embodiment will not be described in detail here. It is worth noting that, compared with the first embodiment, the formation order of the plastic material layer 222 and the solder material layer 232 with the flux does not affect the structure after reflow. Therefore, this embodiment has the same structure as the first embodiment. The same advantages and effects. [Third Embodiment] Figs. 2A, 2B, 2C, 2D to 2E illustrate a chip packaging process according to a third embodiment of the present invention. Please refer to FIG. 2E. Compared with the chip packaging process of the first embodiment, the chip packaging process of the third embodiment is suitable for making a non-leaded type leadframe. Different from the first embodiment, the packaging gel 260a of this embodiment covers a part of the bumps 250, the chip 240, and the lead frame 210, and exposes the lower surface of the pins 210a. The remaining steps and process sequence are the same as those of the wafer packaging process of the first embodiment, so detailed descriptions are not given here in this embodiment. 12 124097 85twf.doc As this embodiment has the same advantages and functions as the first embodiment, it will not be repeated here. [Fourth Embodiment] Figs. 2A ', 2B, 2C, 2D to 2E are shown as a chip packaging process according to a fourth embodiment of the present invention. Please refer to FIG. 2A. Compared with the wafer packaging process of the third embodiment, in this embodiment, a solder material layer 232 is formed first, and then a plastic material layer 222 having a flux is formed. The chip packaging process of the three embodiments is the same, and this embodiment has the same advantages and effects as the third embodiment, so it will not be repeated here. In summary, the chip packaging process and the flip-chip packaging structure of the present invention have at least the following advantages: height) 1. In the wafer packaging process and the flip-chip packaging structure of the present invention, the plastic material layer with flux can be effectively used Controlling the bump height (bump The crystal M ^ process and the flip-chip packaging structure of the present invention integrate the soldering flux = in the plastic material layer with the flux, so the material layer with the freshener can simultaneously take care of fluxing and restrictions The work of sticking the area of the bumps Although the present invention has been disclosed above with the embodiment of the filial piety, but the basin is not used to limit the present invention. Any 孰 羽 + 朴 菇 土 — 'W 、 亚非 掉 # — 7j ARTISTS Without deviating from the spirit and scope of the present invention, the scope of protection can be taken as ~ 1 彳. Sincerely, the scope of the present invention is defined by the patent scope attached to the eyesight [simple description of the diagram] 124097 & inspection doc is schematically shown as a cross section of a package of a lead frame type as shown in Figure 1B. It is shown as conventional ^. After filling with the encapsulation gel: a two-wire frame type package seal process M ~ 2E_ is a wafer according to the first embodiment of the present invention Figures 2A, 2B, 2C, 2D-,-Seeds of the embodiment > {Packaging process to 2E edge is not in accordance with the second aspect of the present invention and returns to Figures 2A, 2B, 2C, 2D The chip packaging process to 2E 'is shown in accordance with the third figure 2A', 2B, 2C, embodiment of the present invention-a kind of chip package I process to 2E 'edge is not in accordance with the fourth of the present invention [the description of the main component symbols] 100: Package 11 (^ lead frame 110a · lead 112 · surface 120: solder material layer 130 · wafer 132: contact 134: surface 140 · bump 150: package gel 2000: flip chip package structure 210 ·· Lead frame I24097 § 210a: Pin 212: Surface 220, 222: Plastic material layer with flux 230, 232: Solder material layer 240: Wafer 242: Contact 244: Surface 250: Bump 260, 260a: Packaging gel 15