TWI240972B

TWI240972B - Manufacturing method of self-aligned contact structure

Info

Publication number: TWI240972B
Application number: TW92130773A
Authority: TW
Inventors: Yun-Jun Huh
Original assignee: Grace Semiconductor Mfg Corp
Priority date: 2003-11-04
Filing date: 2003-11-04
Publication date: 2005-10-01
Also published as: TW200516676A

Abstract

This invention is to provide a manufacturing method of self-aligned contact structure, wherein onto one semiconductor base are formed at least two gate-stacking structures, onto which is covered with one dielectric layer, and the gate-stacking structure contains one nitride-layer surface: remove parts of dielectric layer to expose the semiconductor base and the nitride layer surface between two gate-stacking structures to form one self-aligned contact structure. Then, to the nitride layer surface is carried out the thermal-oxidation treatment to reduce the value of dielectric constant of the nitride layer surface. When the disclosed self-aligned contact structure is formed, the nitride layer surface with surrounding oxidation will make the device to have lower parasitic capacitance during operation.

Description

1240972 五、發明說明（1) 【發明所屬之技術領域】本發明係有關一種自行對準接觸窗（s e 1 f - a 1 i g n e d contact，SAC)之製造方法，特別是關於一種具有較低寄生電容（parasitic capacitance)之自行對準接觸窗結構的製造方法。【先前技術】現今的半導體工業是朝向持續不斷的改良半導體元件效能，或降低這些半導體元件的製造成本，且隨著微型化之趨勢或使用次微米等級所製造之半導體元件能夠達到兼顧使用與成本的目標。次微米元件的使用特色係在具有更小的半導體晶片尺寸，使一般的元件内佈局密集增加，進而可在一特定尺寸基板上容納較多的半導體元件。因此，特定的半導體結構製程，例如微影、乾蝕刻等製程已經成為進入次微米製程的主要關鍵製程因素。然而，於介層洞製程上的貢獻，係為利用新進的半導體製程技術與使用如自行對準接觸窗結構（SAC)的特殊結構設計，來增進微小化與加快運作速度，進而使半導體產業能夠成功的獲取利益。自行對準接觸窗結構的概念為形成一個位於閘極結構間之接觸洞，且為了保留在閘極結構間之最小空間，此接觸洞的直徑係小於目前顯影技術所能提供者。在一般的自行對準接觸窗製程中，閘極結構係包含一氮化矽之頂層以及位於閘極結構兩側之氮化矽間隙壁，然而，此氮化矽間隙壁因具有較高的介電常數而將導致形成較高的寄生電容。1240972 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a self-aligned contact window (se 1 f-a 1 igned contact, SAC), and more particularly to a method with low parasitic capacitance. (Parasitic capacitance) manufacturing method of self-aligned contact window structure. [Previous technology] The current semiconductor industry is continuously improving the performance of semiconductor devices, or reducing the manufacturing cost of these semiconductor devices. With the trend of miniaturization or the use of sub-micron semiconductor devices, both use and cost can be considered. The goal. The characteristics of sub-micron devices are that they have a smaller semiconductor wafer size, which makes the layout of general components densely increased, so that more semiconductor components can be accommodated on a specific size substrate. Therefore, specific semiconductor structure processes, such as lithography and dry etching processes, have become the main key process factors for entering the sub-micron process. However, the contribution to the via manufacturing process is to use new semiconductor process technology and special structural design such as self-aligned contact window structure (SAC) to promote miniaturization and speed up the operation, so that the semiconductor industry can Successfully reap the benefits. The concept of self-aligning the contact window structure is to form a contact hole between the gate structures, and in order to keep the smallest space between the gate structures, the diameter of this contact hole is smaller than that currently provided by the development technology. In a general self-aligned contact window process, the gate structure includes a top layer of silicon nitride and silicon nitride spacers on both sides of the gate structure. However, this silicon nitride spacer has a high dielectric The electrical constant will result in higher parasitic capacitance.

1240972 五、發明說明（2) 有鑑於此，本發明係在針對上述之問題，提出一種具有較低寄生電容之自行對準接觸窗的製造方法，以解決上述缺點。【發明内容】本發明之主要目的係在提供一種自行對準接觸窗結構的製造方法，其係將毗鄰自行對準接觸窗的閘極結構之氮化物間隙壁進行一氧化處理製程，使製作出之自行對準接觸窗結構係具有較低之寄生電容。本發明之另一目的係在提供一種於插塞製程前的自行對準接觸窗的製造方法，其係利用熱處理的氧化方式或氧化劑來氧化該氮化物間隙壁表面，以降低其介電常數。為達到上述之目的，本發明提供一種自行對準接觸窗結構的製造方法’其係先提供一半導體基底，其上係設有至少二閘極堆疊結構與一覆蓋於其上之介電層；此二閘極堆疊結構皆具有一氮化物表面，且一自行對準介層窗係位於閘極堆疊結構間而與其相毗鄰；然後，移除部分介電層，暴露出部分半導體基底與氮化物表面，此暴露出之半導體基底係位於該二閘極堆疊結構之間；然後，對氮化物表面進行一熱氧化處理，用以減少氮化物表面的介電常數。因此，當後續形成自行對準接觸窗結構時，因其周圍具有已氧化之氮化物表面，使其於運作時能夠具有較低的寄生電容。底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明之目的、技術内容、特點及其所達成之功1240972 V. Description of the invention (2) In view of this, the present invention is directed to the above-mentioned problems, and proposes a method for manufacturing a self-aligned contact window with low parasitic capacitance to solve the above disadvantages. [Summary of the Invention] The main object of the present invention is to provide a method for manufacturing a self-aligning contact window structure, which is subject to an oxidation treatment process on a nitride spacer wall of a gate structure adjacent to the self-aligning contact window, so that The self-aligned contact window structure has lower parasitic capacitance. Another object of the present invention is to provide a method for manufacturing a self-aligned contact window before a plug process, which uses a heat-treated oxidation method or an oxidizing agent to oxidize the surface of the nitride spacer wall to reduce its dielectric constant. In order to achieve the above object, the present invention provides a method for manufacturing a self-aligned contact window structure, which firstly provides a semiconductor substrate on which at least two gate stacked structures and a dielectric layer covering the semiconductor substrate are provided; Both of the two gate stacked structures have a nitride surface, and a self-aligned dielectric window is located between and adjacent to the gate stacked structure; then, a portion of the dielectric layer is removed to expose a portion of the semiconductor substrate and the nitride. On the surface, the exposed semiconductor substrate is located between the two gate stacked structures. Then, a thermal oxidation treatment is performed on the nitride surface to reduce the dielectric constant of the nitride surface. Therefore, when a self-aligned contact window structure is subsequently formed, it has an oxidized nitride surface around it, which enables it to have a lower parasitic capacitance during operation. In the following, detailed descriptions are provided by specific embodiments in conjunction with the accompanying drawings, so that it is easier to understand the purpose, technical content, characteristics and achievements of the present invention.

1240972 五、發明說明（3) 效。【實施方式】本發明的半導體設計可被廣泛地應用到許多半導體設計中，並且可利用許多不同的半導體材料製作，當本發明以一較佳實施例來說明本發明之方法時，一般此領域的人士應有的認知是許多的步驟可以改變，材料及雜質也可替換，這些一般的替換無疑地亦不脫離本發明的精神及範疇〇本發明提出一種在半導體基底上製作自行對準介層窗結構之製程，其係藉由對暴露出之氮化層表面進行氧化處理，來降低其表面介電常數；且其使用之氧化製程可使用包含氧氣、水、氧化亞氮、氧化氮或氧化氘等來進行熱氧化，或是利用氧化劑植入的方式，或使用UV臭氧、臭氧電漿或氧氣來進行熱退火。請參閱第一（a )圖所示，在一半導體基底1 0上係形成有許多閘極堆疊結構，每一閘極堆疊結構係包含有一墊氧化層1 8，一導電電極1 2，一絕緣層1 4與一絕緣間隙壁結構 2 0。，並有一介電層1 6覆蓋於閘極堆疊結構上；接著，形成一位於兩個閘極堆疊結構之間且與該閘極堆疊結構相毗鄰之自行對準介層窗。其中，上述之導電電極1 2可以是多晶矽之單一導電層或是如氧化物-氮化物-氧化物 (Oxide-Nitride-Oxide，0N0)之堆疊結構的導電層。絕緣層1 4係視為一硬罩幕，如氮化物罩幕，用以保護電極1 2 於後續製程中產生不當蝕刻。絕緣間隙壁結構2 0係為一包1240972 V. Description of the invention (3) Effectiveness. [Embodiment] The semiconductor design of the present invention can be widely applied to many semiconductor designs, and can be made of many different semiconductor materials. When the present invention is described in a preferred embodiment, the method of the present invention is generally in this field People should know that many steps can be changed, and materials and impurities can be replaced. These general replacements undoubtedly do not depart from the spirit and scope of the present invention. The present invention proposes a self-aligned interposer on a semiconductor substrate. The manufacturing process of the window structure is to reduce the surface dielectric constant of the exposed nitride layer by oxidizing the surface of the exposed nitride layer; and the oxidation process used may include oxygen, water, nitrous oxide, nitrogen oxide, or oxidation Deuterium is used for thermal oxidation, or oxidant implantation is used, or UV ozone, ozone plasma or oxygen is used for thermal annealing. Referring to the first (a) diagram, a plurality of gate stacked structures are formed on a semiconductor substrate 10, and each gate stacked structure includes a pad oxide layer 18, a conductive electrode 12, and an insulation layer. Layer 14 and an insulating spacer structure 20. A dielectric layer 16 covers the gate stack structure. Next, a self-aligned dielectric window is formed between the two gate stack structures and adjacent to the gate stack structure. Wherein, the above-mentioned conductive electrode 12 may be a single conductive layer of polycrystalline silicon or a conductive layer of a stacked structure such as an oxide-nitride-oxide (Oxide-Nitride-Oxide, 0N0). The insulating layer 14 is regarded as a hard mask, such as a nitride mask, to protect the electrode 12 from being etched inappropriately in subsequent processes. Insulation wall structure 20 is a pack

1240972 五、發明說明（4) 含多層絕緣層之雙側壁結構，例如氧化層與氮化層。於此，必須被強調的是不論該絕緣層是如何被設計，該絕緣間隙壁結構2 0的最外層係為氮化層，且其與介電層1 6相毗鄰。再者，半導體基底10上係可有許多離子植入區（圖中未示），例如輕摻雜汲極區（LDD)或源/汲極區域；介電層 1 6可以為一氧化層來作為一内介電層（ILD)。上述所提及之結構可以藉由習知技術來實行之。接著，如第一（b )圖所示，將部分介電層1 6移除，以暴露出位於該二閘極堆疊結構間的半導體基底1 0表面與絕緣間隙壁2 0之氮化層表面，進而形成一作為自行校準接觸窗2 2的空間；其中，部分之絕緣層1 4在此步驟中也會被同時移除。然後，在進行導電接觸之插塞製程之前，將圍繞在自行對準接觸窗2 2周圍的絕緣間隙壁2 0之氮化層表面進行一氧化處理，用以降低間隙壁2 0的介電常數值。在本發明中，絕緣間隙壁2 0之氮化層表面係利用熱氧化法進行氧化處理，或是使用如氧氣（0 2)、水、氧化亞氮（N20)、氧化氮（N0)或氧化氘（D20)等不同氣體來進行快速熱氧化（RT0);在一較佳實施例中，熱氧化製程的溫度係介於6 0 0°C到1 0 0 0°C之間，壓力值是介於1 0托耳（torr)到7 6 0 torr之間。另外，也可利用氧化劑來對絕緣間隙壁2 0之氮化層進行氧化處理，此氧化劑係包含有紫外光臭氧（UV〇3)、臭氧電漿、氧離子植入與退火等等。在進行氧化處理之後，該氮化層表面的介電常數可以降低並可減少後續形成之導電接觸的寄生電容。因此，此種1240972 V. Description of the invention (4) Double sidewall structure with multiple insulating layers, such as oxide layer and nitride layer. Here, it must be emphasized that no matter how the insulating layer is designed, the outermost layer of the insulating barrier wall structure 20 is a nitride layer, and it is adjacent to the dielectric layer 16. Furthermore, the semiconductor substrate 10 may have many ion implanted regions (not shown), such as a lightly doped drain region (LDD) or a source / drain region; the dielectric layer 16 may be an oxide layer. As an internal dielectric layer (ILD). The structures mentioned above can be implemented by conventional techniques. Next, as shown in the first (b) diagram, a part of the dielectric layer 16 is removed to expose the surface of the semiconductor substrate 10 between the two gate stacked structures and the surface of the nitride layer of the insulating spacer 20. Therefore, a space for self-calibrating the contact window 22 is formed. Among them, part of the insulating layer 14 is also removed in this step. Then, before conducting the plug process of conducting contact, the surface of the nitrided layer of the insulating spacer wall 20 around the self-aligned contact window 22 is subjected to an oxidation treatment to reduce the dielectric constant of the spacer wall 20 Value. In the present invention, the surface of the nitrided layer of the insulating spacer 20 is subjected to an oxidation treatment by a thermal oxidation method, or using, for example, oxygen (02), water, nitrous oxide (N20), nitrogen oxide (N0), or oxidation. Deuterium (D20) and other gases for rapid thermal oxidation (RT0); in a preferred embodiment, the temperature of the thermal oxidation process is between 60 ° C and 100 ° C, and the pressure is Between 10 torr (torr) and 7 6 0 torr. In addition, an oxidizing agent can also be used to oxidize the nitrided layer of the insulating spacer 20. The oxidizing agent includes ultraviolet light ozone (UV03), ozone plasma, oxygen ion implantation and annealing, and the like. After the oxidation treatment, the dielectric constant of the surface of the nitride layer can be reduced and the parasitic capacitance of the conductive contacts formed later can be reduced. Therefore, this kind of

1240972 五、發明說明（5) 製程方法可提供一具有較低寄生電容的自行對準接觸窗結構。其中，在完成上述自行校準接觸窗及其後之氧化處理的步驟後，更可接續進行一插塞製程，以形成導電接觸結構。第二圖為本發明利用一熱氧化製程（In —Si tu Steam Generation，ISSG)來對氮化層進行氧化處理的數據表。如圖所示，在樣品8的氧化層（f i na 1 οX i d e)厚度大約為 1 0 0 1. 8埃（A)，介電常數約為3 . 9 ;在樣品6的間隙壁結構之氮化層（final nitride)的原始厚度為13 5埃，沒有經過氧化處理的氮化層的等量厚度（E T0)為70. 2，且其介電常數為7 · 9。任何一個比例的獲得是經過百分比計算個別樣品與樣品6間的介電常數值差異，然後借由單氧化層的介電常數來區分差異性。例如，樣品1是在9 0 0°C與包含3 3%的反應氣體情況下進行氧化處理，然後其介電常數為5. 9 9，與未經過熱處理的樣品6之氮化層做比較，樣品1 有4 7. 7%的介電常數降低量。因此，本發明可以使圍繞在自行對準接觸窗四周的間隙壁之氮化層表面具有較低介電常數。以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍内。1240972 V. Description of the invention (5) The manufacturing method can provide a self-aligned contact window structure with low parasitic capacitance. Among them, after the steps of self-calibrating the contact window and the subsequent oxidation treatment are completed, a plug process can be further performed to form a conductive contact structure. The second figure is a data table of the present invention using a thermal oxidation process (In-Situ Steam Generation, ISSG) to oxidize the nitride layer. As shown in the figure, the thickness of the oxide layer (fi na 1 ο X ide) in sample 8 is about 100.18 angstroms (A), the dielectric constant is about 3.9; nitrogen in the bulkhead structure of sample 6 The original thickness of the final nitride layer was 135 angstroms, the equivalent thickness (ET0) of the nitride layer without oxidation treatment was 70. 2 and its dielectric constant was 7 · 9. Any ratio is obtained by calculating the percentage of the dielectric constant between the individual sample and sample 6, and then distinguishing the differences by the dielectric constant of the single oxide layer. For example, sample 1 was oxidized at 900 ° C and containing 33% of the reaction gas, and then its dielectric constant was 5.9 9 compared with the nitrided layer of sample 6 without heat treatment. Sample 1 had a decrease in dielectric constant of 47.7%. Therefore, the present invention can make the surface of the nitrided layer surrounding the spacer wall around the self-aligned contact window have a lower dielectric constant. The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. When the scope of the patent of the present invention cannot be limited, That is, any equivalent changes or modifications made in accordance with the spirit disclosed in the present invention should still be covered by the patent scope of the present invention.

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第ίο頁 1240972 圖式簡單說明第一（a )圖至第一（b )圖係為本發明之一較佳實施例之代表圖，其係用來說明本發明之自行對準介層窗製程。第二圖係為在本發明中之一較佳實施例圖表，其係利用一熱氧化製程對氮化層進行氧化的數據表。Page 1240972 Brief description of the drawings The first (a) to the first (b) diagrams are representative diagrams of a preferred embodiment of the present invention, and are used to explain the self-aligned interlayer window manufacturing process of the present invention. . The second figure is a diagram of a preferred embodiment of the present invention, which is a data table for oxidizing a nitride layer by a thermal oxidation process.

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Claims

1240972 六、申請專利範圍 1 、一種自行對準接觸窗結構的製造方法，其步驟係包括提供一半導體基底，其上係依序形成至少二閘極堆疊結構及覆蓋於其上之一介電層，其中該閘極堆疊結構係具有一氮化層表面；移除部分該介電層以暴露出部分之該半導體基底與該氮化層表面；以及對該氮化層表面進行一氧化處理，用以降低該氮化層表面的介電常數。 2 、如申請專利範圍第1項所述之自行對準接觸窗結構的製造方法，其中該閘極堆疊結構係包含有：一導電電極；一位於該導電電極上的絕緣層；以及一間隙壁結構，係位於該導電電極二側，且該間隙壁結構之外表面為該氮化層表面。 3 、如申請專利範圍第2項所述之自行對準接觸窗結構的製造方法，其中更可於該絕緣層兩側形成該間隙壁結構。 4 、如申請專利範圍第2項所述之自行對準接觸窗結構的製造方法，其中該絕緣層係由氮化層所組成。 5 、如申請專利範圍第1項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係使用氧氣來進行熱氧化處理。 6 、如申請專利範圍第1項所述之自行對準接觸窗結構的1240972 VI. Scope of Patent Application 1. A method for manufacturing a self-aligned contact window structure, the steps of which include providing a semiconductor substrate on which at least two gate stacked structures are sequentially formed and a dielectric layer covering the same Wherein the gate stack structure has a surface of a nitride layer; removing a part of the dielectric layer to expose a part of the semiconductor substrate and the surface of the nitride layer; and performing an oxidation treatment on the surface of the nitride layer, using In order to reduce the dielectric constant of the surface of the nitride layer. 2. The method for manufacturing a self-aligned contact window structure as described in item 1 of the scope of patent application, wherein the gate stack structure includes: a conductive electrode; an insulating layer on the conductive electrode; and a gap wall The structure is located on two sides of the conductive electrode, and the outer surface of the spacer structure is the surface of the nitride layer. 3. The method for manufacturing a self-aligning contact window structure as described in item 2 of the scope of the patent application, wherein the spacer structure can be formed on both sides of the insulating layer. 4. The method for manufacturing a self-aligned contact window structure as described in item 2 of the scope of patent application, wherein the insulating layer is composed of a nitride layer. 5. The method for manufacturing a self-aligning contact window structure as described in item 1 of the scope of patent application, wherein the oxidation treatment uses oxygen for thermal oxidation treatment. 6. Self-aligning contact window structure as described in item 1 of the scope of patent application

第12頁 1240972 六、申請專利範圍製造方法，其中該氧化處理係使用水來進行熱氧化處理。 7 、如申請專利範圍第1項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係使用氧化亞氮來進行熱氧化處理。 8 、如申請專利範圍第1項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係使用氧化氮來進行熱氧化處理。 9 、如申請專利範圍第1項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係使用氧化氘來進行熱氧化處理。 1 〇、如申請專利範圍第1項所述之自行對準接觸窗結構的製造方法，其中氧化處理係使用臭氧紫外光離子植入來進行熱氧化處理。 11、如申請專利範圍第1項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係使用臭氧電漿離子植入來進行熱氧化處理。 1 2、如申請專利範圍第1項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係使用氧離子植入來進行熱氧化處理。 1 3、一種自行對準接觸窗結構的製造方法，其係於一半導體基底上依序形成二閘極堆疊結構及及覆蓋於其上之一介電層，其中該閘極堆疊結構係具有一氮化層表面，再移除部分該介電層以暴露出部分之該半導體基Page 12 1240972 VI. Scope of Patent Application Manufacturing method, wherein the oxidation treatment uses water for thermal oxidation treatment. 7. The method for manufacturing a self-aligned contact window structure as described in item 1 of the scope of patent application, wherein the oxidation treatment uses nitrous oxide for thermal oxidation treatment. 8. The method for manufacturing a self-aligned contact window structure as described in item 1 of the scope of patent application, wherein the oxidation treatment uses nitrogen oxide for thermal oxidation treatment. 9. The method for manufacturing a self-aligning contact window structure as described in item 1 of the scope of patent application, wherein the oxidation treatment uses deuterium oxide for thermal oxidation treatment. 10. The method for manufacturing a self-aligned contact window structure as described in item 1 of the scope of the patent application, wherein the oxidation treatment uses ozone ultraviolet light ion implantation for thermal oxidation treatment. 11. The method for manufacturing a self-aligned contact window structure as described in item 1 of the scope of the patent application, wherein the oxidation treatment uses ozone plasma ion implantation for thermal oxidation treatment. 1 2. The method for manufacturing a self-aligned contact window structure as described in item 1 of the scope of the patent application, wherein the oxidation treatment is performed by oxygen ion implantation for thermal oxidation treatment. 1 3. A method for manufacturing a self-aligned contact window structure, which sequentially forms a two-gate stacked structure on a semiconductor substrate and a dielectric layer covering the same, wherein the gate stacked structure has a Nitriding the surface of the layer, and then removing a portion of the dielectric layer to expose a portion of the semiconductor substrate

第13頁 1240972 六、申請專利範圍底與該氮化層表面；其特徵在於：對該氮化層表面進行氧化處理，用以降低該氮化層表面的介電常數。 1 4、如申請專利範圍第1 3項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係包括以氧氣來進行熱氧化處理。 1 5、如申請專利範圍第1 3項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係包括以水來進行熱氧化處理。 1 6、如申請專利範圍第1 3項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係包括以氧化亞氮來進行熱氧化處理。 1 7、如申請專利範圍第1 3項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係包括以氧化氮來進行熱氧化處理。 1 8、如申請專利範圍第1 3項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係包括以氧化氘來進行熱氧化處理。 1 9、如申請專利範圍第1 3項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係包括以氧化劑離子植入來進行熱氧化處理。 2 0、如申請專利範圍第1 3項所述之自行對準接觸窗結構的製造方法，其中該氧化處理係包括以氧化劑退火製程來進行熱氧化處理。Page 13 1240972 6. Scope of patent application The bottom and the surface of the nitride layer; characterized in that: the surface of the nitride layer is oxidized to reduce the dielectric constant of the surface of the nitride layer. 14. The method for manufacturing a self-aligning contact window structure as described in item 13 of the scope of patent application, wherein the oxidation treatment includes thermal oxidation treatment with oxygen. 15. The method for manufacturing a self-aligned contact window structure as described in item 13 of the scope of patent application, wherein the oxidation treatment includes thermal oxidation treatment with water. 16. The method for manufacturing a self-aligned contact window structure as described in item 13 of the scope of patent application, wherein the oxidation treatment includes thermal oxidation treatment with nitrous oxide. 17. The method for manufacturing a self-aligning contact window structure as described in item 13 of the scope of patent application, wherein the oxidation treatment includes thermal oxidation treatment with nitrogen oxide. 18. The method for manufacturing a self-aligned contact window structure as described in item 13 of the scope of patent application, wherein the oxidation treatment includes thermal oxidation treatment with deuterium oxide. 19. The method for manufacturing a self-aligned contact window structure as described in item 13 of the scope of patent application, wherein the oxidation treatment includes thermal oxidation treatment by oxidizing ion implantation. 20. The method for manufacturing a self-aligned contact window structure as described in item 13 of the scope of the patent application, wherein the oxidation treatment includes thermal oxidation treatment using an oxidizing agent annealing process.

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