TWI240812B

TWI240812B - Display panel and producing method of the same

Info

Publication number: TWI240812B
Application number: TW92129357A
Authority: TW
Inventors: Yoshihiro Morimoto; Ya-Shiang Dai; Yau-Ming Tsai; Shr-Chang Jang
Original assignee: Toppoly Optoelectronics Corp
Priority date: 2003-10-22
Filing date: 2003-10-22
Publication date: 2005-10-01
Also published as: JP2005128467A; TW200515029A

Abstract

A display panel and a producing method therefore are provided. The panel includes at least a substrate, a channel layer formed above the substrate, an insulation layer formed above the channel layer and including a first and a second contact windows for exposing therefrom a portion of the channel layer, a second conductive line layer formed above the portion of the channel layer and filling the first contact window, a planarization layer formed above the insulation layer and a portion of the second conductive line layer, and filling the second contact window, and a conductive layer formed above the planarization layer and a portion of the second conductive line layer. By the use of the second contact window for measuring the flatness of the planarization layer, the planarization layer and the conductive layer can be formed with highly planarization.

Description

1240812 五、發明說明（1) 一、發明所屬之技術領域：本案係關於一種顯示器面板及其形成方法，尤指一種具有薄膜電晶體陣列（TFT Array)之顯示器面板及其形成方法。二、先前技術：1240812 V. Description of the invention (1) 1. Field of the invention: The present invention relates to a display panel and a method for forming the same, and more particularly to a display panel with a thin film transistor array (TFT Array) and a method for forming the same. Second, the prior art:

在習知具有薄膜電晶體陣列（TFT Array)之顯示器面板中’有關透明像素電極（p i x e 1 e 1 e c t r 〇 d e )部分，往會因為其平坦度（flatness)不夠，致使對經過其中 4 形成干擾，並產生所謂的光線干涉現象。一、光線申言之，請參閱第一圖，其係為習知顯示器圖。於第一圖中，習知顯示器面板丨〇係至少包括：j不例 11，其材質可為破璃或石英、一第一導線層丨2，基板述基板11之上、以及一通道層13，其形成於第一、於前之上。等線層1 2 係接觸、另外，上述顯示器面板10更包括有一絕緣屉成於通道層1 3之上；其中，該絕緣層1 4係包括:In the conventional display panel with a thin-film transistor array (TFT Array), the portion related to the transparent pixel electrode (pixe 1 e 1 ectr ode) will cause interference with passing 4 because of its flatness. And produce the so-called light interference phenomenon. I. Light In conclusion, please refer to the first picture, which is a conventional monitor picture. In the first figure, the conventional display panel includes at least: j is not an example 11, the material of which can be broken glass or quartz, a first wire layer, 2 above the substrate 11 and a channel layer 13 It is formed on the first and the front. The isoline layer 1 2 is in contact. In addition, the above display panel 10 further includes an insulation drawer formed on the channel layer 13; wherein the insulation layer 14 includes:

141，用以曝露出通道層13之部分表面131。至〜之部分表面上方與第一接觸窗丨4 i之中，係形；古、巴緣層: 導線層15。其中第—、第二12，15，通常有閘極（gate)之掃描導線（scan line)層與—】為〜包 (data line)層。貝枓導線141 is used to expose a portion of the surface 131 of the channel layer 13. Above the part of the surface and in the first contact window 丨 4 i, the shape is; the ancient and the marginal layer: the wire layer 15. Among them, the second, the second and the fifteenth, and usually the scan line layer and gate with the gate are the data line layer. Behr wires

1240812 五、發明說明（2) 再者’平坦層1 6係形成於絕緣層1 4之另一部分表面上方以及第二導線層1 5之部分表面。最後，導電層1 7則形成於平坦層16上方與未被平坦層16所遮蓋之第二導線層15之另一部分表面。自第一圖所示之習知顯示器面板1 〇中可知，於形成平坦層1 6時’因不易測量到其平坦度（f 1 a t n e s s )，致使後續於其上方形成導電層17 —-即為一呈現透明狀態之銦錫氧' 化物（Indium Tin Oxide，ΙΤ0)層（其係用以作為像素電極 (pixel electrode)之用）時，會因為該導電層17所呈現出之不平坦結果而產生前述的光線干涉現象。而如何改呈上述缺失，係為發展本案之主要目的。三、發明内容種具有高度平1240812 V. Description of the invention (2) Furthermore, the 'flat layer 16' is formed on the surface of another part of the insulating layer 14 and a part of the surface of the second wire layer 15. Finally, the conductive layer 17 is formed on the surface of the other part of the second wire layer 15 which is above the flat layer 16 and not covered by the flat layer 16. From the conventional display panel 10 shown in the first figure, it can be known that when the flat layer 16 is formed, its flatness (f 1 atness) is difficult to measure, which leads to the subsequent formation of a conductive layer 17 above it. An indium tin oxide (ITO) layer (which is used as a pixel electrode) in a transparent state is generated due to the uneven result of the conductive layer 17 The aforementioned light interference phenomenon. The main purpose of developing this case is to present the above-mentioned defects. 3. Summary of the invention

因此，本案之主要目的，在於提供化之像素電極之顯示器面板。本案之另一目的，在於提供一種可形成具有化之像素電極之顯示器面板之方法。又千Therefore, the main purpose of this case is to provide a display panel with a pixel electrode. Another object of the present application is to provide a method for forming a display panel having pixel electrodes. Again

，達上述之目的，本案提出一種顯示器面板，至+ •二基板 '一通道層，形成於前述基板之上、一二曰，形成於通道層之上，且該絕緣層包括有一拉二 …第二接觸窗，用以曝露出通道層之：分接觸二=，，，形成於絕緣層之部分表面上方並填人於 ®中、一平坦層，形成於絕緣層與第二導線層之部In order to achieve the above-mentioned purpose, this case proposes a display panel to + • two substrates and a channel layer formed on the aforementioned substrate, one or two, and formed on the channel layer, and the insulating layer includes a pull-two ... Two contact windows for exposing the channel layer: sub-contact two = ,, formed on a part of the surface of the insulating layer and filled with ®, a flat layer formed on the part of the insulating layer and the second wire layer

第8頁 1240812Page 8 1240812

五、發明說明（3) 二並填人於第二接觸窗之中、以及一導電層，形成二；&總二之上與第二導線層之部分表面上方，其中藉由第 ^忐*自作為測量平坦層之平坦度（f latneSS)之用，可以九"成出呈右古危τ 有回度平坦化之平坦層與導電層。依據具有薄膜依據線層，且 (gate)之 1 i ne)層 < 依據層。依據合物層。依據窗（dummy 依據化物（I n d (pixel e 另外下列步驟一絕緣層成一第一本案所揭露之技術，其中顯示器面板係可為一種電晶體陣列（TFT Array)之顯示器面板。本案所揭露之技術，其中基板更包括有一第一導 $ 一、第二導線層係可分別為一包括有閘極掃描導線（scan line)層與一資料導線（(131^ 複晶碎本案所揭露之技術，其中通道層係可為本案所揭露之技術，其中平坦層係可為一有機聚本案所揭露之技術，其中第二接觸窗係可 contact hole)。本案所揭露之技術，其中導電層係 -Tln0xlde，ITO)層，用C lectrode)。像素電極，本案亦提供一種形成顯示器面板之 •提供一基板；形成一通道層於基 ^ 於通道層之上；罩幕餘刻去除部；：匕；形成接觸窗及一第二接觸窗；形成=層，以形 X 弟一導線層於絕V. Description of the invention (3) Two are filled in the second contact window and a conductive layer to form two; & above the total second and above a part of the surface of the second wire layer, wherein the first ^ 忐 * Since it is used to measure the flatness of flat layers (f latneSS), it can be used to form flat and conductive layers that are flattened to the right and have a retrograde flatness. The basis has a thin-film basis line layer, and a (gate) 1 i ne) layer < basis layer. According to the composition layer. According to the window (dummy (pixel e) and the following steps, an insulating layer is formed into a technology disclosed in the first case, wherein the display panel can be a display panel of a transistor array (TFT Array). The technology disclosed in this case The substrate further includes a first conductive layer and a second conductive layer, which can be respectively a gate line and a scan line layer and a data line ((131 ^ multiple crystal fragmentation technology disclosed in this case, of which The channel layer can be the technology disclosed in this case, wherein the flat layer can be the technology disclosed in this case, and the second contact window can be the contact hole. The technology disclosed in this case, where the conductive layer is -Tln0xlde, ITO) layer, using C lectrode). The pixel electrode, this case also provides a substrate to provide a display panel; forming a channel layer on the base layer on the channel layer; mask removal section ;: dagger; forming contact Window and a second contact window; form = layer, form a X layer and a wire layer at the insulation

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I 1240812I 1240812

之部分表面上方並填入於第一接觸窗之 f «於絕緣層與第二導線層之部分表面上方按形成一平 ί觸窗之中；卩及形成-導電層於平坦層之工於第二曰之部分表面上方。其中藉由第二接觸窗作：二導線 =平坦度（f iatness)之用，係可形成出ϋ、1 Ϊ平坦層層與導電層。 ’十垣化之平坦依據本案所揭露之技術，其中顯示器面具有薄膜電晶體陣列（TFT Array)之顯示器面板，、。可為一種Part of the surface and filled in the first contact window f «on the surface of the insulating layer and the second wire layer to form a flat contact window; and-the formation of the conductive layer on the flat layer in the second Above the surface. Among them, the second contact window is used as: two wires = flatness, which can form a ϋ, 1 Ϊ flat layer and a conductive layer. The flatness of the ten-granularization According to the technology disclosed in this case, the display panel has a thin-film transistor array (TFT Array) display panel. Can be a

依據本案所揭露之技術，其中基板更包線層，且第-與第二導線層係可分別為—包:第一導 (gate)之掃描導線（scan Hne)層與一資料極 line)層。 1蜍線（仏1:& 依據本案所揭露之技術，其中通道層係、層。馬複晶碎依據本案所揭露之技術，其中平坦層係合物層。 m T為一有機聚依據本案所揭露之技術，其中第二接觸窗（dummy contact hole)。，、σ :、、啞According to the technology disclosed in this case, the substrate is more covered with a wire, and the first and second wire layers can be respectively-clad: a scan Hne layer and a data line layer of the first gate . 1 Toad line (仏 1: & according to the technology disclosed in this case, where the channel layer system, layer. Ma Fujing broken according to the technology disclosed in this case, where the flat layer system layer. M T is an organic polymer according to this case Technology, in which the second contact window (dummy contact hole)., Σ: ,, dumb

依據本案所揭露之技術，其中導電層係 ^ 化物（Indium Tin 〇xide，no)層，用以作為.因錫氧 (Pixel electrode) 〇下為像素電極本案得藉由下列圖式及詳細說明，俾得一文味入之了According to the technology disclosed in this case, the conductive layer is an Indium Tin Oxide (no) layer, which is used as a pixel electrode because the pixel electrode is below 0. This case can be explained with the following drawings and details. I got it all in

1240812 五、發明說明（5) 解：圖式簡單說明：第一圖：其係為習知顯示器面板示例圖。第二圖：其係為本案之一較佳實施示例圖。第三圖（a)〜（e ):其係為本案之一較佳實施步驟示例圖。圖式中所包含之各元件列示如下第一圖：顯示器面板 10 第一導線層 12 通道層 13 絕緣層 14 第二導線層 15 導電層 17 基板 11 通道層之部分表面第一接觸窗 141 平坦層 16 131 基板 21 第一表面2 3 1 第一接觸窗2 4 1 平坦層 26 t 第二圖〜第三圖（a)〜（e): 顯示器面板 20 第一導線層 22 通道層 23 第二表面 232 絕緣層 24 第二接觸窗 242 第二導線層 251240812 V. Description of the invention (5) Solution: Brief description of the diagram: The first diagram: It is an example diagram of a conventional display panel. The second picture: it is a diagram of a preferred embodiment of the present invention. The third diagram (a) ~ (e): It is an example of a preferred implementation step of the present case. The components included in the drawing are listed as follows in the first figure: Display panel 10 First wire layer 12 Channel layer 13 Insulation layer 14 Second wire layer 15 Conductive layer 17 Substrate 11 Part of the surface of the channel layer The first contact window 141 is flat Layer 16 131 Substrate 21 First surface 2 3 1 First contact window 2 4 1 Flat layer 26 t Second to third images (a) to (e): Display panel 20 First wire layer 22 Channel layer 23 Second Surface 232 Insulating layer 24 Second contact window 242 Second wire layer 25

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I 1240812 I 五、發明說明I 1240812 I V. Description of the invention

⑹ 導電層 27 四、發明實施方式：首先請參閱第二圖，其係為本案之一較佳實施示意圖。如第二圖所不，顯示器面板20至少包括有：一基板 21 :其材質可為玻璃或石#、一第一導線層以，其係形成於前述基板21之上、以及一通道層23，形成於第一導線層 22之上。⑹ Conductive layer 27 4. Embodiments of the invention: First, please refer to the second figure, which is a schematic diagram of a preferred embodiment of the present application. As shown in the second figure, the display panel 20 includes at least: a substrate 21: its material may be glass or stone #, a first wire layer, which is formed on the aforementioned substrate 21, and a channel layer 23, It is formed on the first wiring layer 22.

再者，於通道層2 3之上形成有一絕緣層2 4，其中絕緣層24包括有第/接觸窗241及第二接觸窗242，用以分別曝露出通道層23之第一表面231及第二表面232。另外，有一第二導線層2 5係形成於絕緣層2 4之部分表面上方與第一接觸窗241之中。而平坦層26，則係形成於絕緣層24之部分表面上方、第二接觸窗242中與第二導線層25之部分表面。又，於平坦層26上方與未被平坦層26所遮蓋之第二導線層2 5之部分表面，係可形成一導電層2 7。In addition, an insulating layer 24 is formed on the channel layer 23, wherein the insulating layer 24 includes a first / second contact window 241 and a second contact window 242 for exposing the first surface 231 and the first contact layer 23 of the channel layer 23, respectively. Two surface 232. In addition, a second wire layer 25 is formed over a part of the surface of the insulating layer 24 and in the first contact window 241. The flat layer 26 is formed over a part of the surface of the insulating layer 24, a part of the second contact window 242, and a part of the surface of the second wire layer 25. Furthermore, a conductive layer 27 can be formed on the surface of the second conductive layer 25 above the flat layer 26 and a part of the surface of the second conductive layer 25 not covered by the flat layer 26.

於本案之較佳做法中，該第一導線層2 2與第二導線層 2 5係可々別為一包括有閘極（忌ae)之掃描線（s c & ^ 1丨n e) 層與一資料線（data line)層。而通道層23與平坦層26，則可分別為一複晶矽層與一有機聚合物層。至於該導電層 27 ’其係可為一銦錫氧化物（Indium Tin Oxide，ΙΤ0) 層以作為j象素電極（pixel electrode)使用。本案與習知技術間之主要不同處在於：於絕緣層24之In a preferred method of the present case, the first wire layer 22 and the second wire layer 25 can be distinguished as a scan line (sc & ^ 1 丨 ne) layer including a gate electrode (avoiding ae) and A data line layer. The channel layer 23 and the flat layer 26 may be a polycrystalline silicon layer and an organic polymer layer, respectively. As for the conductive layer 27 ', it can be an indium tin oxide (ITO) layer to be used as a j-pixel electrode. The main difference between this case and the conventional technology lies in:

第12頁 1240812Page 12 1240812

五、發明說明（7) 中多形成有一第二接觸窗242。該第二接觸窗242之功能係為―亞窗（dummy contact hole)，以作為測量平坦層“之平坦度（flatness)之用。進一步而言，因第二接觸^242 會使後續沉積於其上方的平坦層26產生凹陷效應，如此一來’平坦層26之厚度變化將轉變為更明顯，意即，假如填入第二接觸窗242中之平坦層26與後續進行之平坦化製程、可成功將第二接觸窗242填平，便表示該平坦層26的$質與後續進行之平坦化製程可有效達到平坦化之目的。對μ於平坦層2 6之平坦度將較易於掌握與測量之。故，亦較易形成出具有高度平坦化之平坦層26與導電層27。再請進一步參閱第三圖（a)〜（e)，其係為本案之一較佳實施步驟示例圖。其中，係包括下列步驟：第三圖（a)所示之步驟：提供一基板21，其上依序形成有一第一導線層22、一通道層23、以及一絕緣層24 ; 第三圖（b )所示之步驟··以罩幕姓刻方式去除部分絕緣層24，以形成第一接觸窗241及第二接觸窗242，其中第一接觸窗241係曝露出通道層23之第一表面231，而第二接觸窗242係曝露出通道層23之第二表面232; 第三圖（c )所示之步驟··形成一第二導線層2 5於絕緣層24之部分表面上方益填入於第一接觸窗241之中；第三圖（d)所示之步驟：形成一平坦層2 6於絕緣層2 4 與第二導線層25之部分表面上方、並填入於第二接觸窗 242之中；以及第三圖（e)所示之步驟：形成導電層27於平坦層26上5. Description of the Invention A second contact window 242 is formed in (7). The function of the second contact window 242 is a “dummy contact hole” to measure the flatness of the flat layer. Further, the second contact 242 will cause subsequent deposition on it. The flat layer 26 above has a depression effect, so that the change in the thickness of the flat layer 26 will become more obvious. That is, if the flat layer 26 filled in the second contact window 242 and the subsequent planarization process, The successful filling of the second contact window 242 indicates that the quality of the flat layer 26 and the subsequent flattening process can effectively achieve the purpose of flattening. The flatness of μ on the flat layer 26 will be easier to grasp and measure. Therefore, it is also easier to form a flat layer 26 and a conductive layer 27 having a high level of planarity. Please refer to the third diagrams (a) to (e), which are exemplary diagrams of a preferred implementation step of the present application. Among them, the following steps are included: The step shown in the third figure (a): providing a substrate 21 on which a first wire layer 22, a channel layer 23, and an insulating layer 24 are sequentially formed; b) The steps shown ... Part of the insulating layer 24 is removed to form a first contact window 241 and a second contact window 242. The first contact window 241 exposes the first surface 231 of the channel layer 23, and the second contact window 242 exposes the channel layer 23 The second surface 232; the step shown in the third figure (c) ... forming a second wire layer 25 and filling the first contact window 241 over a part of the surface of the insulating layer 24; the third figure ( Step d): forming a flat layer 26 over a part of the surface of the insulating layer 2 4 and the second wire layer 25 and filling in the second contact window 242; and as shown in the third figure (e) Step: forming a conductive layer 27 on the flat layer 26

第13頁 1240812 五、發明說明（8) 方與未被平坦層26所遮蓋之第二導線層25之部分表面。綜上所述，本案可於不必大幅增加成本（僅增設一第二接觸窗2 4 2 )之情況下，即可獲致較習知技術更易測量其平坦度之平坦層，與藉此所形成出之具有高度平坦化之像素電極。故，本案實為一極具產業價值之作。本案得由熟習此技藝之人士任施匠思而為諸般修飾，然皆不脫如附申請專利範圍所欲保護者。Page 13 1240812 V. Description of the invention (8) Square and part of the surface of the second wire layer 25 not covered by the flat layer 26. In summary, the present case can obtain a flat layer that is easier to measure its flatness than the conventional technology without having to increase the cost significantly (only adding a second contact window 2 4 2), and formed by this It has a highly flattened pixel electrode. Therefore, this case is indeed a work of great industrial value. This case may be modified by people who are familiar with this skill, but they are not inferior to those who want to protect the scope of patent application.

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Claims

1240812 六、申請專利範圍種顯示器面板，至少包括基板之通道層接觸窗一基板；一通道層，形成於該一絕緣層，形成於該一第一接觸窗以及一第二部分表面；一第二導線層，形成入於該第一接觸窗之中；一平坦層，形成於該面上方並填入於該第二接一導電層，形成於該分表面上方。 2、如申請專利範圍第1項器面板係可為一種具有薄示器面板。 3、如申請專利範圍第1項更包括有一第一導線層，為一包括有閘極（gate)之料導線（data 1 ine)層。 4、如申請專利範圍第1項層係可為一複晶$夕層。 5、如申請專利範圍第1項層係可為一有機聚合物層 6、如申請專利範圍第1項上；之上，且該絕緣層包括有，用以曝露出該通道層之於該絕緣層之部分表面上方並填絕緣層與該第二導線層之部分表觸窗之中；以及平坦層之上與該第二導線層之部所述之顯示器面板，其中該顯示膜電晶體陣列（T F T A r r a y )之顯所述之顯示器面板，其中該基板且該第一與第二導線層係可分別掃描導線（scan line)層與一資所述之顯示器面板，其中該通道所述之顯示器面板，其中該平坦〇所述之顯示器面板，其中該第二1240812 Six kinds of patent application display panels, including at least a channel layer of the substrate contact window a substrate; a channel layer formed on the one insulation layer formed on the first contact window and a second partial surface; a second A wire layer is formed in the first contact window; a flat layer is formed over the surface and filled in the second-to-a-conductor layer and formed over the sub-surface. 2. If the patent application scope item 1 is a panel with a thin display. 3. For example, the scope of the patent application includes a first wire layer, which is a data wire layer including a gate. 4. If the first item of the scope of patent application, the layer system can be a polycrystalline layer. 5. If the layer in the scope of the patent application is No. 1, the layer may be an organic polymer layer. 6. If the layer in the scope of the patent application is No. 1; and the insulation layer is included to expose the channel layer to the insulation. A part of the surface of the layer and filled with an insulating layer and a part of the surface contact window of the second wire layer; and a display panel described above the flat layer and the part of the second wire layer, wherein the display film transistor array ( TFTA rray) display panel, wherein the substrate and the first and second wire layers are respectively a scan line layer and a display panel according to the above, wherein the display panel described in the channel Wherein the flat display panel as described above, wherein the second

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六、申請專利範圍接觸窗係可為一口亞窗（dummy contact hole)。 7、如申請專利範圍第1項所述之顯示器面板，其中該導電層係可為一銦錫氧化物（Indium Tin Oxide，IT〇)層，用以作為像素電極（pixel electrode)。 8、一種形成顯示器面板之方法，至少包括下列步驟：提供一基板；形成一通道層於該基板之上；形成一絕緣層於該通道層之上；6. Scope of patent application The contact window system can be a dummy contact hole. 7. The display panel according to item 1 of the scope of patent application, wherein the conductive layer may be an indium tin oxide (ITO) layer, which is used as a pixel electrode. 8. A method for forming a display panel, comprising at least the following steps: providing a substrate; forming a channel layer on the substrate; forming an insulating layer on the channel layer;

罩幕蝕刻去除部分該絕緣層，以形成一第一接觸窗及一第二接觸窗；形成一第二導線層於該絕緣層之部分表面上方並填入於該第一接觸窗之中；形成一平坦層於該絕緣層與該第二導線層之部分表面上方並填入於該第二接觸窗之中；以及形成一導電層於該平坦層之上與該第二導線層之部分表面上方A part of the insulating layer is removed by mask etching to form a first contact window and a second contact window; a second wire layer is formed over a part of the surface of the insulating layer and filled in the first contact window; A flat layer over a part of the surface of the insulating layer and the second wire layer and filled in the second contact window; and forming a conductive layer over the flat layer and over a part of the surface of the second wire layer

9、如申請專利範圍第8項所述之形成顯示器面板之方法，其中該顯示器面板係可為一種具有薄膜電晶體陣列（TFT A r r a y)之顯不為面板。 i 0、如申請專利範圍第8項所述之形成顯示器面板之方法，其中該基板包括有一第/導線層，且該第一與第二導線層係玎分別為一包括有閘極（gate)之掃描導線（scan iine)層與一資料導線（data line)層。 1 1、如申請專利範圍第8項所述之形成顯示器面板之方9. The method for forming a display panel as described in item 8 of the scope of patent application, wherein the display panel is a display panel having a thin film transistor array (TFT A r r a y). i 0. The method for forming a display panel as described in item 8 of the scope of the patent application, wherein the substrate includes a first / conductor layer, and the first and second conductor layers are respectively one including a gate A scan iine layer and a data line layer. 1 1. The method of forming a display panel as described in item 8 of the scope of patent application

第17頁 1240812 六、申請專利範園法，其中該通道層係可為/複晶矽層。 12、法， 13、法， hole 如申請專利範圍第R 付〔之彡廿山47乐8項所迷之形成顯示器面板之方其中鑪平一層係可為一有機聚合物層。如申請專利範園諸π 使由％堃 N ^ 8項所速之形成顯示器面板之方其中該第二接觸念 -係可為一 ρ亞 6i(dummycontact 1 4、如申請專利範法，其中誃逡 @弟8項所述之形成顯示器面板之方 Oxide 5 I T〇) ^ '、『為一銦錫氧化物（Indium Tin 用以作為像素電極（pixel electrode) tPage 17 1240812 VI. Patent application Fanyuan method, where the channel layer can be / multicrystalline silicon layer. 12, method, method 13, hole, as described in the scope of the application for the patent R, [Payment 廿山 47 乐 8 Item 8 of the formation of the display panel, where the furnace flat layer can be an organic polymer layer. For example, in the patent application, the display panel formed by the% 堃 N ^ 8 items can be used as a display panel. The second contact concept can be a dya 6i (dummycontact 1 4).弟 @ 弟 8 The method of forming a display panel Oxide 5 IT〇) ^ ', "is an indium tin oxide (Indium Tin is used as a pixel electrode) t

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