TWI240362B - Method of fabricating shallow isolation structures and trenches thereof - Google Patents
Method of fabricating shallow isolation structures and trenches thereof Download PDFInfo
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- TWI240362B TWI240362B TW92132511A TW92132511A TWI240362B TW I240362 B TWI240362 B TW I240362B TW 92132511 A TW92132511 A TW 92132511A TW 92132511 A TW92132511 A TW 92132511A TW I240362 B TWI240362 B TW I240362B
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- memory cell
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- 238000002955 isolation Methods 0.000 title claims abstract description 108
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 238000000034 method Methods 0.000 claims abstract description 95
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 30
- 230000002093 peripheral effect Effects 0.000 claims description 87
- 238000005530 etching Methods 0.000 claims description 61
- 239000000758 substrate Substances 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 7
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000007789 gas Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 230000002902 bimodal effect Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical group 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000012925 reference material Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
Description
1240362 五、發明說明（1) 【發明所屬之技術領域】 本發明是有關於一種半導體的製造方法。且特別是有 關於一種同時製造多種淺溝渠隔結構的方法，使某些淺溝 渠隔離結構具有圓角化頂角，其它淺溝渠隔離結構不具有 圓角化頂角。 【先前技術】 積體電路已為眾所皆知的。積體電路通常廣泛應用於 各種電子元件，如記憶體晶片。目前對於縮小積體電路元 件尺寸有很強的要求，以便增加其個別構件的密度，如此 可增進積體電路之功能。 例如：當要求縮小記憶晶體積體電路的尺寸。藉由縮 φ 小積體電路的尺寸，每一個記憶晶片能有更多容量，進而 變得更實用。 然而，由極小化產生了較高的半導體元件密度，會導 致相鄰元件間不必要的電子互相干擾的可能性增加。 例如：半導體元件密度增加時，寄生内元件電流 (inter-device current)會增強。當電子或電洞載子 (carrier)漂移（drift)於半導體基底上鄰接的主動元件 (active devices) 之間，就產生寄生内元件電流。當主 動元件間距離減少時，這種載子的漂移更為顯著。 因此，在積體電路的製造時，必須隔離半導體元件， 以降低電壓，以避免不必要的電子互相干擾。 · 區域氧化（L0C0S)法被廣泛使用於隔離鄰接的金氧半導 體（M0S)電路。在區域氧化法中，無罩幕（unmask)非主動1240362 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor. In particular, there is a method for manufacturing multiple shallow trench isolation structures at the same time, so that some shallow trench isolation structures have rounded corners, and other shallow trench isolation structures do not have rounded corners. [Prior art] Integrated circuits are well known. Integrated circuits are commonly used in a variety of electronic components, such as memory chips. At present, there is a strong demand for reducing the size of integrated circuit components in order to increase the density of individual components, which can improve the function of integrated circuits. For example: when it is required to reduce the size of the memory crystal volume circuit. By reducing the size of the φ small integrated circuit, each memory chip can have more capacity and thus become more practical. However, miniaturization results in a higher density of semiconductor elements, which leads to an increased possibility of unnecessary electron interference between adjacent elements. For example, as the density of semiconductor devices increases, the inter-device current increases. When an electron or hole carrier drifts between adjacent active devices on a semiconductor substrate, parasitic internal device currents are generated. When the distance between the active elements decreases, this carrier drift becomes more significant. Therefore, in the manufacture of integrated circuits, semiconductor elements must be isolated to reduce the voltage to avoid unnecessary electronic interference. · The area oxidation (LOC0S) method is widely used to isolate adjacent metal-oxide semiconductor (MOS) circuits. In the area oxidation method, unmask is inactive
9888twf.ptd 第7頁 12403629888twf.ptd Page 7 1240362
區域（non-active)或矽基底場區被暴露於加熱氧化空氣 中’藉以成長出鑲壁式（recessed)或半鑲壁式 ' (s e m i - r e c e s s e d )的二氧化矽（例如：場氧化）區。在無罩 幕區上的二氧化；5夕通常長得夠厚以降低或許會出現遍及半 導體基底上鄰接的主動元件之間的寄生電容（parasitie capacitance)，但不會厚到產生階梯覆蓋（step coverage)問題。基底區與非主動區不同是基底區被製作 成主動區並由罩幕所保護，以有利於後續在主動區主動元 件（active devices)的幵》成 °Areas (non-active) or silicon substrate field areas are exposed to heated oxidizing air, 'recessed or semi-recessed' silicon dioxide (eg, field oxide) areas are grown . Dioxide on the unmasked area; May is usually thick enough to reduce parasitie capacitance that may occur across adjacent active components on the semiconductor substrate, but not thick enough to produce step coverage coverage) issues. The base area is different from the non-active area in that the base area is made into an active area and protected by a mask to facilitate the subsequent development of active devices in the active area.
然而，區域氧化（L0C0S)法在應用上並非沒有限制。例 如一般知道的限制是罩幕角落氧化不完全時，二氧化石夕逐 漸成長侵入底下罩幕邊緣部份，以及侵蝕到主動區基底。 這就是所謂的鳥嘴（bird’s beak)效應。鳥嘴會造成元 件效能降低，主動區面積減少，增加基底壓力，進而無法 完全提供絕緣效果。並且，氧化物在罩幕下氧化成長，罩 幕層會形成非平面（non-planar)的氧化缺陷。在某種程 $上’這個缺陷係因為在熱氧化過程，生成的氧化物約為 /肖耗的石夕厚度的兩倍。所形成之非平面（non-planar)將 會給後來層的一致性及微影（photolithography)帶來問 題0However, the area oxidation (LOC0S) method is not without its application. For example, the commonly known limitation is that when the corners of the mask are incompletely oxidized, the dioxide will gradually grow into the bottom edge of the mask and erode to the base of the active area. This is the so-called bird ’s beak effect. The bird's beak will reduce the efficiency of the component, reduce the area of the active area, increase the substrate pressure, and then fail to provide a complete insulation effect. In addition, oxides grow under the mask, and the mask layer will form non-planar oxidation defects. In a certain way, this defect is because the oxide produced during the thermal oxidation process is about twice the thickness of Shi Xi. The formed non-planar will cause problems for the consistency of subsequent layers and photolithography.
在瞭解區域氧化法（L0C0S)隔離技術缺點之後，目前互 補式金氧半導體（CM0S )在主動區逐漸採用淺溝，尤其是 淺溝渠隔離（Shallow Trench Isolation，STI )結構。 淺溝渠隔離結構的形成典型是使用非等向蝕刻製程用一個After understanding the shortcomings of the L0C0S isolation technology, the current complementary metal-oxide semiconductor (CM0S) gradually adopts shallow trenches in the active area, especially Shallow Trench Isolation (STI) structures. Shallow trench isolation structures are typically formed using an anisotropic etching process with a
9888twf.ptd 第8頁 1240362 五、發明說明（3) 罩幕去定義以及圖案化一基底上的淺溝渠。然後將絕緣物 填入淺溝渠，在之後的步驟中，將絕緣物平坦化，來形成 淺溝渠隔離。淺溝渠隔離結構能減弱或消除氧化侵蝕主動 區所產生的鳥嘴（b i r d ’ s b e a k )問題。因此可用空間加 大，隔離所用空間變小。 淺溝渠隔離結構包含陡削形（A b r u p t 1 y - S h a p e d )邊 角，例如，係因為使用非等向性蝕刻技術形成溝渠隔離， 這些陡削幾何形會導致不必要的電子特性。例如，邊際傳 導（Edge conduction)，其中過量遺漏電流發生在隔離 溝渠結構頂部及鄰接的主動元件間的上面區域。主動元件 若接近於隔離溝渠的一小半徑邊角，會產生包含不必要的 寄生遺漏路徑的高邊緣傳導電性，此一不必要的效應就是 習知的主動元件I - V曲線（美國專利第6，0 7 4，9 3 1號）的雙 峰(Double hump )性質。 除此之外，溝渠隔離結構陡削邊角也能導致隨後介電 物質沉積於溝渠的困難度。例如，溝渠上方開口處的陡削 邊角在介電物質沉積期間且於溝渠完全被填滿前會在溝渠 開口導致夾斷（pinching-off)現象，而於溝渠填充物中 留下多餘不必要的孔洞。隨著趨勢繼續往構件小型化與元 件密度發展，更需要較窄的深溝渠隔離結構，其具有更大 的高寬比。然而，當溝渠隔離結構之高寬比增大時，孔洞 形成的問題更為惡化。 例如，若形成具有較大高寬比的隔離溝渠，則很可能會在 用二氧化矽填入隔離溝渠期間，因二氧化矽的形成在溝渠9888twf.ptd Page 8 1240362 V. Description of the invention (3) The mask defines and patterns a shallow trench on a substrate. The insulation is then filled into the shallow trench, and in a subsequent step, the insulation is planarized to form a shallow trench isolation. The shallow trench isolation structure can reduce or eliminate the bird's beak (b i r d s s b e a k) problem caused by the oxidative erosion active area. Therefore, the available space is increased, and the space used for isolation is reduced. Shallow trench isolation structures include sharp-cut corners (Abrupt 1 y-Shaped), for example, because trench isolation is formed using anisotropic etching techniques. These sharp-cut geometries can cause unnecessary electrical characteristics. For example, edge conduction, where excess leakage current occurs at the top of the isolation trench structure and above the area between adjacent active components. If the active device is close to a small radius corner of the isolation trench, it will produce high-edge conductive electrical properties including unnecessary parasitic leakage paths. This unnecessary effect is the conventional active device I-V curve (U.S. Patent No. 6, 0 7 4, 9 3 1) Double hump properties. In addition, the steeply cut corners of the trench isolation structure can also cause difficulty in subsequent deposition of dielectric material in the trench. For example, the sharp-cut corners at the opening above the trench can cause pinching-off at the trench opening during the deposition of dielectric material and before the trench is completely filled, leaving excess unnecessary in the trench fill. Hole. As the trend continues toward component miniaturization and component density development, narrower deep trench isolation structures are needed more, which have larger aspect ratios. However, as the aspect ratio of trench isolation structures increases, the problem of hole formation becomes worse. For example, if an isolation trench with a large aspect ratio is formed, it is likely that during the filling of the isolation trench with silicon dioxide, the silicon dioxide will form in the trench.
9888twf.ptd 第9頁 1240362 五、發明說明（4) 出口之開口變小而阻礙二氧化矽完全填滿溝渠，並導致空 洞的產生。 將淺溝渠隔離結構的邊緣的圓角化或頂角的圓角化， 可降低一些上述陡削邊角的問題。不論如何，在一些實例 上，溝渠隔離結構頂角圓角化是有必要的，但在其他實例 溝渠隔離結構頂角圓角化有時不可能做到或又不適合。 例如，在記憶元件中關鍵尺寸亦即在記憶胞區的淺溝 渠隔離結構寬度一般小於在週邊區的淺溝渠隔離結構的關 鍵尺寸。雖然圓角化在記憶元件之週邊區中的淺溝渠隔離 結構的頂角可降低I - V曲線特有的雙峰效應，但是不能維 持在記憶胞區中淺溝渠隔離結構的相對小地關鍵尺寸中。 在這實例，頂角圓角化會使在記憶胞區的淺溝渠隔離 結構關鍵尺寸減小，又不能被接受。此外，如前述的討 論，寬度減小的淺溝渠隔離結構，要將絕緣物填入淺溝渠 隔離結構更加困難。根據這例子，記憶胞區的淺溝渠隔離 結構為頂角非圓角化是必要的。 然而，在週邊區使用頂角圓角化淺溝渠隔離結構仍然是值 得的。在形成積體電路時，有必要有一些具圓角化頂角的 淺溝渠隔離結構和有非圓角化頂角的淺溝渠隔離結構。當 然，使用不同的製程去形成圓角化頂角及非圓角化頂角淺 溝渠隔離結構會導致無效率、昂貴且影響產率。 因此需要一種方法，可以同時形成圓角化頂角淺溝渠 隔離結構與非圓角化頂角淺溝渠隔離結構。 【發明内容】9888twf.ptd Page 9 1240362 V. Description of the invention (4) The opening of the outlet becomes smaller, which prevents the silicon dioxide from completely filling the trench, and causes a void. Rounding the edges or rounding the corners of a shallow trench isolation structure can reduce some of the above-mentioned problems with sharp corners. However, in some instances, corner filleting of trench isolation structures is necessary, but in other instances, corner filleting of trench isolation structures is sometimes impossible or inappropriate. For example, the critical dimension of the memory element, that is, the width of the shallow trench isolation structure in the memory cell region is generally smaller than the critical dimension of the shallow trench isolation structure in the peripheral region. Although rounded corners of the shallow trench isolation structure in the peripheral area of the memory element can reduce the bimodal effect unique to the I-V curve, it cannot be maintained in the relatively small critical size of the shallow trench isolation structure in the memory cell area. . In this example, the rounding of the apex corners would reduce the critical dimensions of the shallow trench isolation structure in the memory cell area, and would not be acceptable. In addition, as discussed earlier, the shallow trench isolation structure with reduced width makes it more difficult to fill the shallow trench isolation structure with insulation. According to this example, it is necessary for the shallow trench isolation structure of the memory cell area to be non-rounded. However, the use of apex filleted shallow trench isolation structures in the peripheral area is still worthwhile. When forming integrated circuits, it is necessary to have some shallow trench isolation structures with rounded corners and shallow trench isolation structures with non-rounded corners. Of course, the use of different processes to form rounded corners and non-rounded corners with shallow trench isolation structures can lead to inefficiencies, cost, and impact on productivity. Therefore, there is a need for a method that can simultaneously form a rounded corner shallow trench isolation structure and a non-rounded corner shallow trench isolation structure. [Summary of the Invention]
9888twf.ptd 第10頁 1240362 五、發明說明（5) 本發明的目的就是在提供一種淺溝渠隔離結構的製造 方法，以提高產率與增加其價值以及解決習知溝渠隔離區 陡削邊角導致介電物質填充於溝渠困難度。 本發明的再一目的是提供一種形成淺溝渠隔離結構之 溝渠的方法，可解決習知因在記憶胞區淺溝渠隔離結構不 能達到小尺寸，且在週邊區使用非圓角化溝渠隔離結構， 而產生無效率、昂貴且影響產率等問題。 本發明的另一目的是提供一種形成淺溝渠隔離結構之 溝渠的方法，以解決習知溝渠隔離區陡削邊角而導致介電 物質填充於溝渠的困難度，並減低鄰接主動元件的I-V曲 線雙峰特性。 φ 本發明的又一目的是提供一種淺溝渠隔離結構，解決 習知在記憶胞區淺溝渠隔離結構不能達到小尺寸的問題以 及解決習知在週邊區使用非圓角化溝渠隔離結構，而產生 無效率、昂貴且影響產率等問題。 本發明的又一目的是提供一種積體電路，解決習知在 記憶胞區淺溝渠隔離結構不能達到小尺寸的問題以及解決 習知在週邊區使用非圓角化溝渠隔離結構，而產生無效 率、昂貴且影響產率等問題。 本發明的又一目的是提供一種淺溝渠隔離結構，解決 習知在記憶胞區淺溝渠隔離結構不能達到小尺寸的問題以 及解決習知在週邊區使用非圓角化溝渠隔離結構，而產生 β 無效率、昂貴且影響產率等問題。 本發明的又一目的是提供一種積體電路，解決習知在9888twf.ptd Page 10 1240362 V. Description of the invention (5) The purpose of the present invention is to provide a method for manufacturing a shallow trench isolation structure in order to increase productivity and increase its value, and to solve the problems caused by steep corners in the trench isolation area. Difficulty of filling a trench with a dielectric substance. Another object of the present invention is to provide a method for forming a trench with a shallow trench isolation structure, which can solve the conventional problem that a shallow trench isolation structure in a memory cell area cannot reach a small size, and a non-rounded trench isolation structure is used in a peripheral area. Problems such as inefficiency, cost, and impact on productivity arise. Another object of the present invention is to provide a method for forming a trench with a shallow trench isolation structure, in order to solve the difficulty of filling the trench with a dielectric substance caused by the steep edges of the trench isolation area, and reduce the IV curve of the adjacent active device. Bimodal characteristics. φ Another object of the present invention is to provide a shallow trench isolation structure, which solves the problem that the conventional shallow trench isolation structure cannot reach a small size in the memory cell area, and solves the problem of using a non-rounded trench isolation structure in the peripheral area. Problems such as inefficiency, cost, and impact on productivity. Another object of the present invention is to provide an integrated circuit, which solves the problem that the conventional shallow trench isolation structure in the memory cell area cannot reach a small size, and solves the conventional use of a non-rounded trench isolation structure in the peripheral area, resulting in inefficiency. , Expensive and affecting yield and other issues. Another object of the present invention is to provide a shallow trench isolation structure, which solves the problem that the conventional shallow trench isolation structure cannot reach a small size in the memory cell area, and solves the problem of using a non-rounded trench isolation structure in the peripheral area to generate β. Problems such as inefficiency, cost, and impact on productivity. Another object of the present invention is to provide an integrated circuit,
9888twf.ptd 第11頁 1240362 五、發明說明（6) 記憶胞區淺溝渠隔離結構不能達到小尺寸的問題以及解決 習知在週邊區使用非圓角化溝渠隔離結構，而產生無效 率、昂貴且影響產率等問題。 本發明提出一種淺溝渠隔離結構的製造方法，包括： 提供一基底，基底具有一記憶胞區以及一週邊區，形成一 硬罩幕於基底上，以覆蓋部分記憶胞區以及部分週邊區， 於硬罩幕上方形成圖案化的一光阻層，光阻層在記憶胞區 曝露出一部份的硬罩幕以及在週邊區曝露出一部份的硬罩 幕，執行一第一姓刻過程，以移除在週邊區被光阻層曝露 的所有硬罩幕以及移除在記憶胞區被光阻層曝露的部份硬 罩幕，執行一第二蝕刻過程，以在週邊區形成具有多數個 圓角化頂角的一溝渠，以及移除更多在記憶胞區的硬罩 幕，執行一第三蝕刻過程，以加深在週邊區形成的溝渠且 保留些圓角化頂角以及在記憶胞區形成一溝渠，以及以一 絕緣物填入週邊區的溝渠以及記憶胞區的溝渠。 本發明提出一種形成淺溝渠隔離結構之溝渠的方法， 包括：在第一蝕刻過程期間，蝕刻週邊區的硬罩幕比記憶 胞區的硬罩幕深。之後，在第二蝕刻過程期間，進一步蝕 刻記憶胞區的硬罩幕，並蝕刻週邊區的基底以部份形成具 有圓角化頂角一溝渠，再之後第三蝕刻過程期間，蝕刻記 憶胞區的基底，以在記憶胞區形成一溝渠以及蝕刻在週邊 區中的基底，以便加深於週邊區所形成的溝渠。 本發明再提出一種形成淺溝渠隔離結構之溝渠的方 法，包括：在第一蝕刻過程期間，蝕刻一週邊區的一硬罩9888twf.ptd Page 11 1240362 V. Description of the invention (6) The problem that the shallow trench isolation structure in the memory cell area cannot reach a small size and solve the conventional use of non-rounded trench isolation structures in the surrounding area, resulting in inefficiency, expensive and Affect issues such as yield. The invention provides a method for manufacturing a shallow trench isolation structure, comprising: providing a substrate, the substrate having a memory cell region and a peripheral region, forming a hard mask on the substrate to cover a part of the memory cell region and a part of the peripheral region; A patterned photoresist layer is formed above the hard mask. The photoresist layer exposes a part of the hard mask in the memory cell area and a part of the hard mask in the peripheral area, and performs a first name engraving process. In order to remove all hard masks exposed by the photoresist layer in the peripheral area and remove some hard masks exposed by the photoresist layer in the memory cell area, a second etching process is performed to form a majority in the peripheral area. A ditch with rounded corners, and removing more hard masks in the memory cell area, performing a third etch process to deepen the trenches formed in the peripheral area and retain some rounded corners and memory The cell area forms a trench, and the trench in the surrounding area is filled with an insulator and the trench in the memory cell area. The invention provides a method for forming a trench of a shallow trench isolation structure, which includes: during a first etching process, a hard mask in a peripheral region is etched deeper than a hard mask in a memory cell region. After that, during the second etching process, the hard mask of the memory cell area is further etched, and the base of the peripheral area is etched to form a trench with rounded corners, and then the memory cell area is etched during the third etching process. To form a trench in the memory cell region and a substrate etched in the peripheral region to deepen the trench formed in the peripheral region. The present invention further provides a method for forming a trench with a shallow trench isolation structure, including: etching a hard mask of a peripheral region during a first etching process.
9888twf.ptd 第12頁 1240362 五、發明說明（7) 幕至一墊氧化層，以及蝕刻在記憶胞區的硬罩幕小於至墊 氧化層，以保留記憶胞區中部份被曝露的硬罩幕；在第二 蝕刻過程期間，蝕刻記憶胞區中保留部份被曝露的硬罩幕 至墊氧化層，以及蝕刻週邊區的基底，形成一溝渠具有圓 角化頂角。之後，在第三蝕刻過程期間，蝕刻在記憶胞區 中的基底以形成一溝渠，以及蝕刻週邊區中的基底，以便 加形成於週邊區的基底中的溝渠。 本發明又提出一種淺溝渠隔離結構，由本發明的製造 過程所形成。 本發明再提出一種積體電路，由本發明的製造過程所 形成。 φ 本發明又提出一種淺溝渠隔離結構，包括··一第一溝 渠，形成在基底的週邊區，且第一溝渠具有圓角化頂角； 以及第二溝渠^形成在基底的記憶胞區，且第二溝渠具有 圓角化頂角。 本發明再提出一種積體電路，包括：一基底，具有一 週邊區以及一記憶胞區，一第一溝渠，形成在基底的週邊 區中，第一溝渠具有圓角化頂角，以及第二溝渠，形成在 基底的記憶胞區中，第二溝渠具有不是圓角化的頂角。 本發明因採用一種同時製造具有圓角化頂角與不是圓 角化頂角之淺溝渠隔離結構，因此具有圓角化頂角與不是 圓角化頂角之淺溝渠隔離結構係解決習知技術溝渠隔離結 H 構，在記憶胞區淺溝渠隔離結構不能達到小尺寸，在週邊 區使用非圓角化溝渠隔離結構，產生無效率、昂貴且影響9888twf.ptd Page 12 1240362 V. Description of the invention (7) The curtain to a pad of oxide layer, and the hard cover etched in the memory cell area is smaller than the pad to protect the exposed hard cover in the memory cell area. During the second etching process, the exposed hard mask to the pad oxide layer remains partially etched in the memory cell area, and the substrate in the peripheral area is etched to form a trench with rounded corners. Thereafter, during the third etching process, the substrate in the memory cell region is etched to form a trench, and the substrate in the peripheral region is etched to add the trench formed in the substrate in the peripheral region. The invention also provides a shallow trench isolation structure formed by the manufacturing process of the invention. The present invention further proposes an integrated circuit formed by the manufacturing process of the present invention. φ The present invention also proposes a shallow trench isolation structure, including a first trench formed in a peripheral region of the substrate, and the first trench having a rounded corner; and a second trench formed in a memory cell region of the substrate, And the second trench has a rounded corner. The invention further provides an integrated circuit, including: a substrate having a peripheral region and a memory cell region, a first trench formed in the peripheral region of the substrate, the first trench having a rounded apex, and a second A trench is formed in the memory cell region of the base, and the second trench has an apex angle that is not rounded. Because the present invention adopts a shallow trench isolation structure with rounded corners and non-rounded corners, the conventional shallow trench isolation structure with rounded corners and non-rounded corners is a conventional solution. The trench isolation structure H structure, the shallow trench isolation structure in the memory cell area cannot reach a small size, and the non-rounded trench isolation structure is used in the peripheral area, which is inefficient, expensive and affects
9888twf.ptd 第13頁 1240362 五、發明說明（8) 產率等問題，進而提高產率與增加其價值。以及週邊區圓 角化頂角可以解決習知溝渠隔離區陡削邊角導致介電物質 填充於溝渠困難度，以及孔洞填入溝渠產生夾斷現象，且 可減低鄰接主動元件的I - V曲線雙峰特性。 為讓本發明之上述和其他目的，特徵和優點更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下。 【實施方式】 接下來以參考資料詳述本發明的實施例，實施例將以 附圖解釋。在儘可能的情況之下，圖解中相同或相似的參 考數字，用於描述相同或相似部份。應注意的是，描繪圖 是簡式形式，並非精確的尺吋大小。在此參考方向名稱， 如頂、底、左、右、上、下、在上面、在下面、向下及背 面和前面，是為了簡單明瞭的目的。這些方向專有名稱不 能用於限制發明之範圍。 雖然本發明已以較佳實施例揭露於此，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 在此的描述淺溝渠隔離結構製造流程，並不涵蓋整個 淺溝渠隔離結構所有製造流程。本發明可以與不同的積體 電路製造技術一起使用，只有一般熟練的製程步驟包含於 此，以提供對本發明的了解。本發明一般在半導體元件與 製造的領域上具有應用性。不過為了說明的目的，接下來9888twf.ptd Page 13 1240362 V. Description of the invention (8) Yield and other issues, which will increase yield and increase its value. And the rounded corners in the peripheral area can solve the difficulty of filling the trench with the dielectric material and the sharp edges of the trench isolation area, and the pinch-off phenomenon of the hole filling the trench, which can reduce the I-V curve of adjacent active components. Bimodal characteristics. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with reference to the accompanying drawings. [Embodiment] Next, the embodiments of the present invention will be described in detail with reference materials, and the embodiments will be explained with reference to the drawings. Wherever possible, the same or similar reference numbers are used in the illustrations to describe the same or similar parts. It should be noted that the drawing is a simplified form, not an exact size. Direction names are referred to here, such as top, bottom, left, right, up, down, above, below, down, and back and front, for simplicity and clarity. These direction proper names cannot be used to limit the scope of the invention. Although the present invention has been disclosed here with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. The description of the manufacturing process of the shallow trench isolation structure does not cover all the manufacturing processes of the entire shallow trench isolation structure. The invention can be used with different integrated circuit manufacturing techniques, and only generally skilled process steps are included here to provide an understanding of the invention. The present invention is generally applicable in the field of semiconductor elements and manufacturing. But for illustrative purposes, the next
9888twf.ptd 第14頁 1240362 五、發明說明（9) 的描述是有關於同時具有多種淺溝渠隔離結構製造方法， 就是有一些具有圓角化頂角的淺溝渠隔離結構和一些不是 圓角化頂角的淺溝渠隔離結構。 本發明提供一種形成淺溝渠隔離結構的方法，這方法 包括：同時在基底的記憶胞區形成不是圓角化頂角的溝 渠，及在基底的週邊區形成有圓角化頂角的溝渠。 本發明提出淺溝渠隔離結構的製造方法，包括：提供 一基底，基底具有一記憶胞區以及一週邊區，形成一硬罩 幕於基底上，以覆蓋部分記憶胞區以及部分週邊區，於硬 罩幕上方形成圖案化的一光阻層，光阻層在記憶胞區曝露 出一部份的硬罩幕以及在週邊區曝露出一部份的硬罩幕。 行一第一蝕刻過程，以移除在週邊區被光阻層曝露的 所有硬罩幕以及移除在記憶胞區被光阻層曝露的部份硬罩 幕。 接著，執行一第二蝕刻過程，以在週邊區形成具有多數個 圓角化頂角的一溝渠，以及移除更多在記憶胞區的硬罩 幕。 再接著，執行一第三蝕刻過程，以加深在週邊區形成 的溝渠且保留圓角化頂角以及在記憶胞區形成一溝渠。 之後，將絕緣物填入週邊區的溝渠以及記憶胞區的溝 渠，且其較佳為相同過程步驟。 完成第三蝕刻過程之後最好移除光阻。在絕緣物填充 於溝渠完成之後，最好移除硬罩幕。 硬罩幕形成於基底之前，最好於基底的上面形成一層9888twf.ptd Page 14 1240362 5. The description of invention description (9) is about the manufacturing method of multiple shallow trench isolation structures, that is, there are some shallow trench isolation structures with rounded corners and some are not rounded Corner shallow trench isolation structure. The present invention provides a method for forming a shallow trench isolation structure. The method includes simultaneously forming a trench that is not a rounded corner at a memory cell region of a substrate, and a trench having a rounded corner at a peripheral region of the substrate. The invention provides a method for manufacturing a shallow trench isolation structure, which includes: providing a substrate, the substrate having a memory cell region and a peripheral region, forming a hard mask on the substrate to cover part of the memory cell region and part of the peripheral region, and A patterned photoresist layer is formed above the mask. The photoresist layer exposes a part of the hard mask in the memory cell area and a part of the hard mask in the peripheral area. A first etching process is performed to remove all the hard masks exposed by the photoresist layer in the peripheral region and to remove a part of the hard masks exposed by the photoresist layer in the memory cell region. Next, a second etching process is performed to form a trench with a plurality of rounded corners in the peripheral region, and to remove more hard masks in the memory cell region. Then, a third etching process is performed to deepen the trench formed in the peripheral region while retaining the rounded corners and to form a trench in the memory cell region. Thereafter, the trenches in the peripheral area and the trenches in the memory cell area are filled with an insulator, and they are preferably the same process steps. It is best to remove the photoresist after completing the third etching process. After filling the trench with insulation, it is best to remove the hard mask. The hard cover is formed before the substrate, preferably a layer on top of the substrate
9888twf.ptd 第15頁 1240362 五、發明說明（ίο) 塾氧化層。移除光阻之後，再移除墊氧化層。 執行第一蝕刻過程，以移除在週邊區被光阻層曝露的所有 硬罩幕以及移除在記憶胞區被光阻層曝露的部份硬罩幕。 執行第二蝕刻過程，以在週邊區形成具有多數個圓角 化頂角的一溝渠，以及移除更多在記憶胞區的硬罩幕，在 記憶胞區形成的溝渠頂角最好是不是圓角。 第一蝕刻過程所使用的蝕刻氣体最好包括CF4/CH2F2或 cf4/chf3。之後，第二蝕刻過程所使用的蝕刻氣体最好包 括CF4/CHF3。第三蝕刻過程所使用的蝕刻氣体最好包括Cl2 /02。 週邊區的溝渠以及記憶胞區的溝渠所填入的物質最好 是相同。週邊區的溝渠以及記憶胞區的溝渠所填入的最好 是介電氧化物，例如是二氧化矽。其它的介電材料同樣也 適合填入溝渠中。 在週邊區形成之溝渠的圓角化頂角較佳係具有一半徑 介於大概3 0 n m及大概6 0 n m之間，且較佳係具有一半徑大概 為 6 0 nm 〇 週邊區的溝渠以及記憶胞區的溝渠最好被形成具有大 致相同的深度。但是，週邊區的溝渠以及記憶胞區的溝渠 也可選擇具有彼此不同的深度。 請參照第1 - 5圖所示，其繪示說明本發明一較佳實施 例，一種與具有非圓角化或方正的頂角或邊緣的絕緣淺溝 渠結構同時形成的具有圓角化的頂角或邊緣的絕緣淺溝渠 結構。9888twf.ptd Page 15 1240362 V. Description of the Invention (ί) The oxide layer. After the photoresist is removed, the pad oxide layer is removed. A first etching process is performed to remove all the hard masks exposed by the photoresist layer in the peripheral area and remove a part of the hard masks exposed by the photoresist layer in the memory cell area. The second etching process is performed to form a trench with a plurality of rounded apex angles in the peripheral area, and to remove more hard masks in the memory cell area. Is the top angle of the trench formed in the memory cell area better? Rounded corners. The etching gas used in the first etching process preferably includes CF4 / CH2F2 or cf4 / chf3. Thereafter, the etching gas used in the second etching process preferably includes CF4 / CHF3. The etching gas used in the third etching process preferably includes Cl 2/02. The trenches in the surrounding area and the trenches in the memory cell area are preferably filled with the same material. The trenches in the peripheral area and the trenches in the memory cell area are preferably filled with a dielectric oxide, such as silicon dioxide. Other dielectric materials are also suitable for filling trenches. The filleted apex of the trench formed in the peripheral area preferably has a radius between about 30 nm and about 60 nm, and preferably has a trench with a radius of about 60 nm. The trenches of the memory cell area are preferably formed to have approximately the same depth. However, the trenches in the peripheral area and the trenches in the memory cell area can also be selected to have different depths from each other. Please refer to Figs. 1-5, which illustrate a preferred embodiment of the present invention. A rounded top formed at the same time as an insulated shallow trench structure with non-rounded or squared corners or edges. Corner or edge insulation shallow trench structure.
9888twf.ptd 第16頁 1240362 五、發明說明（π) 熟習該項技術者應可理解雖然結構1 9描畫出頂角，事 實上，這些結構的邊緣是沿著溝渠上側。所以在此稱呼為 邊緣或者是角落，兩者名稱是可以替換。 請參照第1圖，一基底1 1包含一記憶胞區以及一週邊 區。基底1 1的材質例如是一石夕基底，這些一般地使用在如 記憶元件之積體電路的製造中。或者，基底1 1可以使用其 他材質。 一層墊氧化層12可被形成於基底11之上。墊氧化層12 可減低由於基底1 1與硬罩幕1 3間晶格結構不協調所產生應 力。 根據本發明之一較佳實施例，一硬罩幕1 3可被形成於 基底1 1上，以及墊氧化層1 2上面。硬罩幕1 3的材質例如是 氮化矽。硬罩幕1 3也可使用其他材質替代。而硬罩幕1 3與 之後提供的光阻層1 4共同作為決定哪一部份的基底將被蝕 刻或是將根據已知的原理被處理的罩幕之用，且有物質沉 積於基底上。 於硬罩幕13之上可形成一圖案化光阻層14。此圖案化 光阻層1 4有被圖案化而成的開口 1 5以及開口 1 6 ，以助於硬 罩幕1 3的相似的圖案化，隨後以助於根據已知的原理進行 蝕刻以及物質沉積於上。使用其他方法圖案化硬罩幕1 3同 樣適合。例如，採用雷射切割或者離子研磨。 在光阻層1 4中的一些開口 1 5，可被形成於基底的記憶 胞區之上，以助於頂角不是圓角化溝渠的形成。如前面所 述，有時要形成頂角不是圓角化溝渠，以便維持更好的關9888twf.ptd Page 16 1240362 V. Description of the invention (π) Those skilled in the art will understand that although the structures 19 depict the top corners, in fact, the edges of these structures are along the upper side of the trench. So here it is called edge or corner, and the two names can be replaced. Referring to FIG. 1, a substrate 11 includes a memory cell region and a peripheral region. The material of the substrate 11 is, for example, a stone substrate, and these are generally used in the manufacture of integrated circuits such as memory elements. Alternatively, the substrate 11 can be made of other materials. A pad oxide layer 12 may be formed on the substrate 11. The pad oxide layer 12 can reduce the stress caused by the lattice structure mismatch between the substrate 11 and the hard mask 13. According to a preferred embodiment of the present invention, a hard mask 13 may be formed on the substrate 11 and the pad oxide layer 12. The material of the hard cover 1 3 is, for example, silicon nitride. The hard cover 1 3 can also be replaced with other materials. The hard mask 13 and the photoresist layer 14 provided later are used as a mask to determine which part of the substrate is to be etched or processed according to known principles, and a substance is deposited on the substrate . A patterned photoresist layer 14 may be formed on the hard mask 13. The patterned photoresist layer 14 has patterned openings 15 and openings 16 to assist in the similar patterning of the hard mask 1 3, and subsequently to facilitate etching and materials according to known principles. Deposited on. Other methods of patterning a hard mask 1 3 are equally suitable. For example, laser cutting or ion milling is used. Some openings 15 in the photoresist layer 14 can be formed on the memory cell region of the substrate to help the formation of apex corners that are not rounded. As mentioned earlier, sometimes it is necessary to form culverts that are not rounded to maintain a better relationship.
9888twf.ptd 第17頁 1240362 五、發明說明（12) 鍵尺寸（critical dimension)。尤其，當形成的溝渠位於 半導體元件密集區時，必須維持溝渠的關鍵尺寸，以避免 鄰接半導體元件的物理干擾。 在光阻層1 4中的一些開口 1 6，同樣的可被形成於基底 的週邊區之上，以便促進圓角化頂角溝渠形成。如前面所 述，圓角化頂角溝渠的形成，有利降低鄰近半導體元件間 I - V曲線特有的雙峰性質。 請參照第1圖，在記憶胞區上的光阻1 4中之開口 1 5，小於 在週邊區上的光阻1 4中之開口 1 6。較小的開口 1 5有利於在 記憶胞區的淺溝渠隔離結構有較小的關鍵尺寸，較大的開 口 1 6有利於在週邊區的淺溝渠隔離結構有較大的關鍵尺 φ 寸。 值得注意的，本發明實施例，在化學氣相沉積製程中 (CVD)的一個晶片’許多的記憶胞區以及許多週邊區彼此 之間非常的接近。 請參照第2圖，執行一第一蝕刻過程，以移除在記憶胞 區曝露出的部分硬罩幕1 3，而形成一個被蝕刻部分1 7，及 移除在週邊區所有曝露出的硬罩幕13，而形成一個被蝕刻 部分1 8。因此，在週邊區的所有硬罩幕1 3較佳係被蝕刻至 墊氧化層1 2。 可以使用各種的方法除去物質，以達到要求的_.深_度。 例如，在記憶胞區的硬罩幕1 3可以處理的更厚，否則就要 ® 在週邊區的硬罩幕13上用更多的光阻蝕刻。 在#刻過程中，I虫刻微負載（m i c r 〇 - 1 〇 a d i n g )效應存在9888twf.ptd Page 17 1240362 V. Description of the invention (12) Key dimension (critical dimension). In particular, when the formed trenches are located in a dense area of semiconductor elements, the critical dimensions of the trenches must be maintained to avoid physical interference with adjacent semiconductor elements. Some of the openings 16 in the photoresist layer 14 can also be formed over the peripheral area of the substrate in order to promote the formation of rounded corner trenches. As mentioned earlier, the formation of rounded apex trenches is beneficial to reduce the unique bimodal nature of the I-V curve between adjacent semiconductor elements. Referring to FIG. 1, the opening 15 in the photoresist 14 in the memory cell area is smaller than the opening 16 in the photoresist 14 in the peripheral area. Smaller openings 15 are beneficial for shallow trench isolation structures in the memory cell area to have smaller critical dimensions, and larger openings 16 are beneficial for shallow trench isolation structures in the peripheral area to have larger critical dimensions φ inch. It is worth noting that in the embodiment of the present invention, a plurality of memory cell regions and many peripheral regions of one wafer in a chemical vapor deposition (CVD) process are very close to each other. Referring to FIG. 2, a first etching process is performed to remove a part of the hard mask 13 exposed in the memory cell area to form an etched part 17 and to remove all exposed hard parts in the peripheral area. The mask 13 forms an etched portion 18. Therefore, all the hard masks 13 in the peripheral area are preferably etched to the pad oxide layer 12. Various methods can be used to remove the material to achieve the required _.depth_ degree. For example, the hard mask 1 3 in the memory cell area can be processed thicker, otherwise it is necessary to etch the hard mask 13 in the peripheral area with more photoresist. In the # 刻 process, the micro-load (m i c r 〇-1 〇 a d i n g) effect exists
9888twf.ptd 第18頁 1240362 五、發明說明（13) 於不同的關鍵尺寸。通常硬罩幕技術用低聚合物氣體（例 如，cf4， cf4/o2)來降低這些效應。在本發明，可添加高聚 合物氣體（CHF3，CH2F2)用以選擇性地提高蝕刻微負載效 應。使用此技術，在記憶胞區可形成一較大的硬罩幕，同 時週邊區的硬罩幕也會被完全去除。 第一姓刻過程的蚀刻氣體，例如是C F 4 / C H 2 F 2或C F 4 / C H F 3。CF4與(：1132的比率較佳為2至5之間。CF4與0^3的比率較 佳為3至5之間。同樣地，可以使用其他比率的蝕刻氣體。 之後，請參照第3圖，執行一第二蝕刻過程，以移除在 記憶胞區剩餘的硬罩幕，以及在記憶胞區開始形成一溝 渠。在記憶胞區形成的溝渠一般是頂角不是圓角化或四方 形。同時，第二蝕刻過程會在週邊區開始形成一溝渠，在 週邊區的溝渠是有圓角化頂角19。 為在週邊區產生圓角化頂角，當溝渠開始形成時，例 如使用CF4/CHF3氣體，一重聚合物形成於溝渠的側壁。使 用側壁聚合物沉積法，能自然的形成頂部圓角化。 第二蝕刻過程之後，在記憶胞區中的被蝕刻部分1 7最 好延伸至墊氧化層1 3，以及在週邊區中的被蝕刻部分1 8會 好延伸蝕刻至進入基底1 1。 第二蝕刻過程的蝕刻氣體最好包括：CF4/CHF3。CF4與 C HF3比率最好大約4到6之間。同樣地可以使用其他比率的 蝕刻氣體。 請參照第4圖，執行一第三蝕刻過程，以在記憶胞區的 基底11中形成一溝渠17，以及完成在週邊區的基底11中的9888twf.ptd Page 18 1240362 V. Description of the invention (13) Different key dimensions. Generally, hard mask technology uses low polymer gas (for example, cf4, cf4 / o2) to reduce these effects. In the present invention, a high polymer gas (CHF3, CH2F2) may be added to selectively improve the etching microload effect. Using this technique, a large hard mask can be formed in the memory cell area, and the hard mask in the peripheral area will be completely removed. The etching gas in the first process is, for example, C F 4 / C H 2 F 2 or C F 4 / C H F 3. The ratio of CF4 and (: 1132 is preferably between 2 and 5. The ratio of CF4 and 0 ^ 3 is preferably between 3 and 5. Similarly, other ratios of etching gas can be used. After that, please refer to FIG. 3 A second etching process is performed to remove the remaining hard mask in the memory cell area and start to form a trench in the memory cell area. The trench formed in the memory cell area generally has a vertex that is not rounded or square. At the same time, the second etching process will start to form a trench in the peripheral area, and the trench in the peripheral area has rounded corners 19. In order to generate rounded corners in the peripheral area, for example, when a trench is formed, use CF4 / CHF3 gas, a heavy polymer is formed on the side wall of the trench. Using the sidewall polymer deposition method, the top fillet can be naturally formed. After the second etching process, the etched portion 17 in the memory cell area is preferably extended to the pad. The oxide layer 13 and the etched portion 18 in the peripheral area will extend to etch well into the substrate 11. The etching gas in the second etching process preferably includes: CF4 / CHF3. The CF4 to C HF3 ratio is preferably about 4 Up to 6. The same can be used Other ratios of etching gas. Please refer to FIG. 4 to perform a third etching process to form a trench 17 in the substrate 11 of the memory cell region, and to complete the formation of the trench 11 in the substrate 11 in the peripheral region.
9888twf.ptd 第19頁 1240362 五、發明說明（14) 溝渠1 8。在記憶胞區的溝渠1 7的頂角是非圓角化或四角 形，以及在週邊區的溝渠18的頂角是圓角化。 第三蝕刻過程的蝕刻氣體最好包括Cl2/02。Cl2與02比率 最好大約6到1 2，在本實施例，蝕刻電漿氣體包含 60-120sccm的Cl2以及5-12sccm 的02。同樣地，也可以使 用其他蝕刻電漿氣體。 請參照第5圖，移除光阻層1 4以及於溝渠1 7與1 8中沉積 絕緣物2 1 ，2 2如二氧化矽，以便形成淺溝渠隔離結構。 在絕緣物2 1 ，2 2沉積於溝渠1 7，1 8之後，最好移除硬 罩幕17以及墊氧化層12。 記憶胞區的淺溝渠隔離結構為四方角頂角或者頂角非 圓角化，以便保留關鍵尺寸（例如··淺溝渠隔離結構呈現 圓角化頂角時，有侵入鄰接的主動元件的傾向）。在週邊 區的淺溝渠隔離結構大體具有圓角化頂角1 9 ，此圓角化頂 角可減低鄰接主動元件的I - V曲線雙峰特性。 因此可同時形成記憶胞區的淺溝渠隔離結構是四方頂 角以及週邊區的淺溝渠隔離結構是圓角化頂角，以避免增 加其他減少產率及增加成本的過程步驟。 回顧前面所描述，本發明是形成具有圓角化頂角或頂 角非圓角化淺溝渠隔離結構的方法。雖然本發明已以較佳 實施例揭露如上，然其並非用以限定本發明，任何熟習此 技藝者，在不脫離本發明之精神和範圍内，當可作些許之 更動與潤飾，因此本發明之保護範圍當視後附之申請專利 範圍所界定者為準。9888twf.ptd Page 19 1240362 V. Description of the invention (14) Ditch 18. The apex of the trench 17 in the memory cell area is non-rounded or quadrangular, and the apex of the trench 18 in the peripheral area is rounded. The etching gas of the third etching process preferably includes Cl2 / 02. The ratio of Cl2 to 02 is preferably about 6 to 12. In this embodiment, the etching plasma gas contains Cl2 of 60-120 sccm and 02 of 5-12 sccm. Similarly, other etching plasma gases may be used. Please refer to FIG. 5, remove the photoresist layer 14 and deposit insulators 2 1, 2 2 such as silicon dioxide in the trenches 17 and 18 to form a shallow trench isolation structure. After the insulators 2 1, 2 2 are deposited in the trenches 17, 18, the hard mask 17 and the pad oxide layer 12 are preferably removed. The shallow trench isolation structure in the memory cell area is square corner apex or non-rounded corners in order to preserve key dimensions (for example, when a shallow trench isolation structure shows a rounded corner, there is a tendency to invade adjacent active components) . The shallow trench isolation structure in the surrounding area generally has a rounded corner angle of 19, which can reduce the double-peak characteristic of the I-V curve adjacent to the active element. Therefore, the shallow trench isolation structure that can form the memory cell area at the same time is a square apex and the shallow trench isolation structure in the surrounding area is a rounded apex to avoid adding other process steps that reduce productivity and increase costs. Reviewing the foregoing description, the present invention is a method of forming a shallow trench isolation structure with rounded corners or non-rounded corners. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
9888twf.ptd 第20頁 1240362 圖式簡單說明 第1圖是依照本發明一較佳實施例的剖面圖，其繪示在 一基底的記憶胞區以及週邊區上形成有一墊氧化層，一硬 罩幕，以及一光阻層。 第2圖是繪示移除在記憶胞區中暴露出之部份硬罩幕以 及移除在週邊區中暴露出的所有硬罩幕之剖面圖。 第3圖是繪示移除記憶胞區暴露出之剩餘硬罩幕與其下 的墊氧化層，以及移除在週邊區暴露出的基底，此時開始 形成一具有圓角化頂角的溝渠之剖面圖。 第4圖是繪示在基底的記憶胞區中形成一溝渠，以及完 成在週邊區的基底的一溝渠的形成之剖面圖。 第5圖是繪示記憶胞區的溝渠以及週邊區的溝渠兩者均 被填滿一絕緣物質之剖面圖。 【圖示標示說明】 11 :基 底 12 :墊 氧 化 層 13 :硬 罩 幕 14 :光 阻 層 15 、1 6 • 開 α 17 、1 8 • 溝 渠 19 :圓 角 化 頂 21 、22 • 絕 緣9888twf.ptd Page 20 1240362 Brief Description of Drawings Figure 1 is a cross-sectional view according to a preferred embodiment of the present invention, which shows an oxide layer formed on a memory cell region and a peripheral region of a substrate, and a hard cover. Screen, and a photoresist layer. Figure 2 is a cross-sectional view showing the removal of a part of the hard mask exposed in the memory cell region and the removal of all hard masks exposed in the peripheral region. Figure 3 shows the removal of the remaining hard mask exposed from the memory cell area and the pad oxide layer underneath, and the removal of the substrate exposed in the peripheral area. At this time, a trench with rounded corners began to form. Sectional view. Fig. 4 is a cross-sectional view showing the formation of a trench in the memory cell region of the substrate and the formation of a trench completed in the substrate of the peripheral region. Fig. 5 is a sectional view showing that the trenches in the memory cell area and the trenches in the peripheral area are filled with an insulating substance. [Icons] 11: Substrate 12: Oxidation layer 13: Hard cover 14: Photoresistive layer 15 and 16
9888twf.ptd 第21頁9888twf.ptd Page 21
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