1239570 玖、發明說明 【發明所屬之技術領域】 本發明係有關於一種半導體元件製造方法，特別是與 一種可降低溝渠式功率電晶體閘極電荷之製造方法有關。 【先前技術】 在傳統技術中’金氧半場效電晶體（M〇SFET)的發 展，已經逐漸取代了雙載子電晶體之應用。由於其能節省 電能及較快的元件切換速度之緣故，金氧半場效電晶體已 成為積體電路中最常被使用时導體元件。一般而言，溝 渠式功率電晶體（TRENCH POWER M0SFET)的基本操作 2任何的金氧半場效電晶體相同，但是其流通電流可達數 安坧。此外，溝渠式功率電晶體的優點是可以在耗費低功 率的狀況下，控制電壓進行元件的操作。 第一至四圖顯不傳統溝渠式功率型電晶體的製造流 程之剖面不意圖。在第一圖中，先提供一矽基材i 〇〇,其 中矽基材100作為功率電晶體的汲極。接著在矽基材1〇〇 上形成一磊晶層101，並作基底植入形成基體區域1〇5， 接著於其中形成複數個溝渠102。隨後在第二圖中，依序 於溝渠102的側壁形成閘氧化層1〇4，並且在溝渠1〇2中 填入複晶矽m然後蝕刻去除複晶…〇6及閘氧化 1239570 層104，並且曝露出石夕暮絲！ ηη ^ , 山材100的表面，其中殘留在溝渠 102中的複晶矽層106作為閘極。 接著在第二圖中，進杆料吾彡制和 逆仃U〜氟％，以於基體區域1 〇5 中定義源極圖案。然後進行煻簪賊舍j 丨夂％仃邋&驅入製程，以形成源極 1 08。最後在第四圖中，於开杜ρ β、一 #人 T於7^件&域沉積介電層110及金 屬内連線112，以形成溝渠式功率型電晶體。 隨著元件的縮小化，上沭之、售泪4丄古， 逆之溝渠式功率型電晶體的製 程必須使用較薄的閘氧化層1〇4，一 版而§厚度介於100 至1 000埃之間。然而由於底邱ρ弓备 田义低4閘氧化層i 04厚度越薄， 會造成閘極底部電容值越大，將合 种矿座生厭重的RC延遲， 降低電晶體的操作效能。因此如何 U戈1 J 0：善溝渠式功率型電晶 體的製程，降低電晶體的間托# & ▼-电曰日體的閘極底部電容值，以維持較佳的 電晶體操作速度，並且你亓杜… 使兀件小’已經成為目前半導體 業界亟需解決的課題。 【發明内容】 因= 本發明的主要目的即是在提供一種具有低間 =的溝渠式功率電晶體製造方法，藉由增加閘極底部 Κ «之厚度來降低此部分之閘極電容值。 本發明另一目的為福供—^ . ”、Α 種具有低閘極電容的溝 電晶體製造方法，於溝渠底部之氧化層的厚度大 “側壁之氧切層的厚度，形成不同厚度閉氧化層，: 1239570 降低閘極區域的電容值，提高電晶體的操作速度。 、本發明的再-目的在提供一種具有低間極電容的溝 渠式功率電晶體製造方法，可在原有 < 光罩數目下增加間 極底部氧化層之厚度，藉以降低此部分之閘極電容值。 本發明的又一目的在提供一具有低閘極電容的溝渠 式功率電晶體製造方法，根據此方法並不需使用額外之光 罩’因此可節省製程成本，同時增加生產效率。 根據上述之目的，本發明提出一種具有低閘極電容 的溝渠式功率電晶體製造方法，包含下列步驟：首先利用 一重摻雜之N型半導體基板作為汲極之用，再於此基板上 /儿積N型磊晶層，接著定義出主動區域，並對主動區域進 行植入步驟以形成基底區域，並於此基底區上形成第一氮 化矽層。接著利用一光阻層定義出閘極區域，並對半導體 曰曰圓進行蝕刻，以定義溝渠圖案於N型磊晶層上。接著形 、弟氣化石夕層於溝渠結構之表面上與第一氮化石夕層 上。執仃一非等向性蝕刻以暴露出溝渠結構之底部。進行 …、氧化製私’以於暴露出之底部上形成一氧化層。移除 第一與第二氮化矽層，再沿著該溝渠結構之表面形成閘極 氧化層’且形成摻雜多晶矽層以填充於溝渠結構中。接 著’形成摻雜區域於半導體底材中。其中摻雜區域鄰接於 邊溝渠結構作為源極。隨後，形成一介電層於該半導體底 表面 並進行接觸窗触刻，並填入金屬層。 1239570 【實施方式】 在不限制本發明之精神及應用範 -實把例，介紹本發明之實施；熟悉此領域技Μ下= 解本發明之精神後’當可應用本發明之不 同之功率電晶體中。根據本發明之功康士沄於各種不 〜β 士 "之力率電晶體製程方法， 可在原有之光罩數目下增加問極底部氧化層之厚度 降低閘極底部之閘極電容值，由於並 3 而要使用到額外之 先罩製程’因此可節省製程成本，同時增加生產效率。本 發明之製程方法可使用在多種之功率電晶體中不僅限於 以下所述之較佳實施例。 首先參考第五圖，提供一個Ν+型或是ρ+型的半導體 底材200 (substrate)，在其上面形成一層磊晶層2〇2，在 本發明的較佳實施例中以N型的磊晶矽為例，磊晶層2〇2 濃度約1013〜1015/cm3,以作為所欲形成的半導體元件之 汲極（dram)區域，其中磊晶矽層2〇2可以化學氣相沉積法 (Chemical Vapor Deposition，CVD)法加以形成之。形成磊 晶層202之後，於磊晶層202上形成一場氧化層（未圖 示），並以光罩定義出主動區，且去除一部你的場氧化層， 以於磊晶層202表面上形成前述之主動區。 接著對主動區域進行植入步驟，以於主動區中形成 基體區206。本發明較佳實施例中，植入步驟例如可為爐 管驅入製程或是離子佈植製程來形成基體區。而且基體區 1239570 206之摻質的電性與矽磊層202的電性相反，例如可為 或是P型摻質。以P型基體區206為例，可利用離子佈植及 高溫擴散法形成，其中高溫擴散法的溫度介於5〇〇至2〇〇〇 c之間，摻質例如可為硼，離子佈植的濃度介於丨χ 至 7xl017/cm3。 之後’參考第六圖，於磊晶層202上成長一層氮化石夕 層204，並在此氮化矽層2〇4上執行微影及蝕刻製程以形成 形成複數個溝渠結構208，其中溝渠用於定義功率電晶體 之閘極區域214。以較佳實施例而言，此蝕刻步驟可利用 非專向性反應離子餘刻製程（reactive i〇n etch ; RIE)來對p 型基體區206與磊晶層202進行蝕刻。 接著，參考第七圖所示，保留原先之氮化矽層2〇4， 先成長一層薄的氧化層，再形成一氮化矽層21〇於原本之 氮化矽層204與溝渠結構208中。一般而言，上述之氮化矽 204與210之形成，可使用任何適當之製程進行沈積，如同 熟悉該項技術者所熟知，可以使用低壓化學氣相沈積法 (LPC VD)，電漿增強化學氣相沈積法（PEcVD)等製程進行 沈積而得。在一較佳之具體實施例中，製造氮化矽層所用 的反應氣體為 SiH4，NH3，N2，N20 或是 SiH2Cl2，NH3， N2 ， N2〇 〇 參考第八圖所示，對氮化矽層210進行非等向性之乾 蝕刻程序，以於溝渠結構208之内壁形成氮化矽側壁212。 在一較佳實施例中，此乾蝕刻可使用反應離子蝕刻程序用 1239570 金或合金等來作為上述閘極之材料。 參照第十一圖所示，接著形成一圖案化光阻層（圖 中未展示出），此光阻層係用以形成源極區域。以此圖案 化光阻層為罩幕，對該基體區2〇6進行離子植入，以便形 成摻雜區域於基體區206中，作為所製造電晶體之源極區 域。其中該摻雜區域鄰接於閘極氧化層2丨6，亦即在該溝 渠結構208之側壁上方，形成源極區域22〇。源極區域22〇 佈植的濃度介於1χΐ〇ΐ8至7xl〇2〇/cm3。此外，源極區域22〇 · 離子佈植的電性與基體區2〇6的電性相反。 最後在第十二圖中，於源極區域220之間進行摻雜 222，提高源極區域22〇的接觸電性。接著進行接觸窗之 製作，首先形成一介電層224以覆蓋於摻雜多晶矽層2 j 8 與基體區206上。此介電層224例如可為麟石夕玻璃（psg) 或是侧磷矽玻璃（BPSG)，其中利用常壓化學氣相沉積 (Atmospheric Pressure Chemical Vapor Deposition, APCVD)法沉積磷矽玻璃（PSG)，而以電漿增強化學氣相 籲 沉積（Plasma-enhanced Chemical Vapor Deposition, PECVD)法沉積硼填矽玻璃（BPSG)。 接著形成一圖案化光阻層（圖中未展示出）於介電層 224上，並以此圖案化光阻層為罩幕進行介電層224之蝕 刻製程，以分別曝露源極區域220。最後於介電層224及 暴露出之源極區域220上形成金屬層226，即完成本發明 之具有低閘極電容的溝渠式功率電晶體。 11 1239570 知上所言’本發明利用於溝渠結構之内壁形成氮化石夕 側壁，、藉以抑制於第一次氧化製程時，僅在溝渠結構之底 部形成厚氧化層，接著於移除氣化石夕層後，再進行第二次 之氧化製程，以形成溝渠内壁之閘極氧化層。換言之，本 每明接由多次氧化製程，同時伴隨於溝渠結構内壁之氮化 石夕層來形成不同厚度的間氧化層，使間極區域底部的；氧 化層較厚’以減少電晶體的電容值。根據本發明之1239570 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for reducing the gate charge of a trench power transistor. [Previous Technology] In the traditional technology, the development of MOSFETs has gradually replaced the application of bipolar transistors. Due to its power saving and fast component switching speed, metal-oxide-semiconductor half-field-effect transistors have become the most commonly used conductor components in integrated circuits. Generally speaking, the basic operation of a TRENCH POWER M0SFET 2 is the same as any metal-oxygen half field-effect transistor, but its current can reach several amps. In addition, the advantage of the trench power transistor is that it can control the voltage to operate the component while consuming low power. The first to fourth figures show the unintended cross-section of the manufacturing process of the traditional trench power transistor. In the first figure, a silicon substrate i 00 is provided, in which the silicon substrate 100 is used as a drain of a power transistor. Next, an epitaxial layer 101 is formed on the silicon substrate 100, and the substrate is implanted to form a base region 105, and then a plurality of trenches 102 are formed therein. Subsequently, in the second figure, a gate oxide layer 104 is formed in sequence on the sidewall of the trench 102, and the polycrystalline silicon m is filled in the trench 102 and then the polycrystal is etched to remove the polycrystal ... And exposed Shi Xi Mu Si! ηη ^, the surface of the mountain material 100, in which the polycrystalline silicon layer 106 remaining in the trench 102 serves as a gate. Next, in the second figure, the material is made of aluminum and inversely U ~ fluorine%, so as to define the source pattern in the substrate region 105. Then, a driving process is performed to form a source electrode 108. Finally, in the fourth figure, a dielectric layer 110 and a metal interconnect 112 are deposited on a 7-piece & domain in Kaidu ρ β to form a trench-type power transistor. With the shrinking of the components, the manufacturing process of the upper and lower tears is 4 years old. The process of the inverse trench power transistor must use a thinner gate oxide layer 104, one version, and the thickness is between 100 and 1,000. Between Egypt. However, due to the thinner thickness of the oxide layer i 04 at the gate Qiu Bei Tian Yi low 4 gate, the larger the capacitance value at the bottom of the gate will delay the heavy RC of the hybrid mine and reduce the operating efficiency of the transistor. Therefore, how to reduce the capacitance of the bottom of the gate of the transistor to maintain a better operation speed of the transistor, And you don't want to ... make the small pieces' has become a problem that the semiconductor industry needs to solve at present. [Summary of the Invention] The main purpose of the present invention is to provide a trench-type power transistor manufacturing method with a low interval, by reducing the gate capacitance of this part by increasing the thickness of the gate bottom κ «. Another object of the present invention is to provide a method for manufacturing a trench transistor with low gate capacitance. The thickness of the oxide layer at the bottom of the trench is large, and the thickness of the oxygen cut layer on the side wall forms a closed oxide of different thickness. Layer: 1239570 Reduces the capacitance value in the gate area and increases the operating speed of the transistor. A further object of the present invention is to provide a trench-type power transistor manufacturing method with a low inter-electrode capacitance, which can increase the thickness of the bottom oxide layer of the inter-electrode under the original number of photomasks, thereby reducing the gate capacitance of this part. value. Another object of the present invention is to provide a trench-type power transistor manufacturing method with a low gate capacitance. According to this method, no additional photomask is needed, so that the process cost can be saved and the production efficiency can be increased. According to the above object, the present invention proposes a method for manufacturing a trench-type power transistor with a low gate capacitance, which includes the following steps: firstly, a heavily doped N-type semiconductor substrate is used as a drain, and then on the substrate / child An N-type epitaxial layer is deposited, then an active region is defined, and an implantation step is performed on the active region to form a base region, and a first silicon nitride layer is formed on the base region. Then, a photoresist layer is used to define the gate region, and the semiconductor circle is etched to define a trench pattern on the N-type epitaxial layer. Then, a layer of gaseous fossils is formed on the surface of the trench structure and the first nitrided layer. An anisotropic etch is performed to expose the bottom of the trench structure. Performing…, oxidizing to private ”to form an oxide layer on the exposed bottom. The first and second silicon nitride layers are removed, a gate oxide layer is formed along the surface of the trench structure, and a doped polycrystalline silicon layer is formed to fill the trench structure. Next, a doped region is formed in the semiconductor substrate. The doped region is adjacent to the side trench structure as a source. Subsequently, a dielectric layer is formed on the bottom surface of the semiconductor, a contact window is etched, and a metal layer is filled. 1239570 [Embodiment] Without restricting the spirit and application of the present invention-practical examples, introduce the implementation of the present invention; familiar with the technology in this field = after understanding the spirit of the present invention 'when different power sources of the present invention can be applied In the crystal. According to the invention, the power transistor process method can increase the thickness of the oxide layer at the bottom of the interrogator under the original number of masks, and reduce the gate capacitance at the bottom of the gate. And 3, an additional masking process is used, so it can save process costs and increase production efficiency. The method of the present invention can be used in a variety of power transistors and is not limited to the preferred embodiments described below. First, referring to the fifth figure, an N + -type or ρ + -type semiconductor substrate 200 (substrate) is provided, and an epitaxial layer 202 is formed thereon. In a preferred embodiment of the present invention, an N-type The epitaxial silicon layer is taken as an example. The concentration of the epitaxial layer 20 is about 1013 to 1015 / cm3, which is used as the drain region of the semiconductor device to be formed. The epitaxial silicon layer 20 can be chemical vapor deposited. (Chemical Vapor Deposition, CVD) method. After the epitaxial layer 202 is formed, an oxide layer (not shown) is formed on the epitaxial layer 202, and an active area is defined by a photomask, and a part of your field oxide layer is removed, so as to be on the surface of the epitaxial layer 202. The aforementioned active area is formed. An implantation step is then performed on the active area to form a base area 206 in the active area. In a preferred embodiment of the present invention, the implantation step may be, for example, a furnace tube driving process or an ion implantation process to form a substrate region. In addition, the electrical properties of the dopants in the base region 1239570 206 are opposite to those of the silicon oxide layer 202. For example, the electrical properties of the dopants may be P-type or P-type. Taking the P-type matrix region 206 as an example, it can be formed by ion implantation and high-temperature diffusion method. The temperature of the high-temperature diffusion method is between 500 and 2000c. The dopant can be boron, and ion implantation, for example. The concentration is between χ and 7xl017 / cm3. After that, referring to the sixth figure, a nitride nitride layer 204 is grown on the epitaxial layer 202, and a lithography and etching process is performed on the silicon nitride layer 204 to form a plurality of trench structures 208. Defines the gate region 214 of the power transistor. In a preferred embodiment, the etching step may use a non-specific reactive ion etch (RIE) process to etch the p-type substrate region 206 and the epitaxial layer 202. Next, referring to the seventh figure, the original silicon nitride layer 204 is retained. A thin oxide layer is grown first, and then a silicon nitride layer 21 is formed in the original silicon nitride layer 204 and the trench structure 208. . In general, the formation of the above-mentioned silicon nitrides 204 and 210 can be deposited using any suitable process. As is familiar to those skilled in the art, low pressure chemical vapor deposition (LPC VD) can be used to enhance the chemistry of the plasma. It is obtained by vapor deposition (PEcVD) and other processes. In a preferred embodiment, the reaction gas used to produce the silicon nitride layer is SiH4, NH3, N2, N20 or SiH2Cl2, NH3, N2, N2. Referring to the eighth figure, the silicon nitride layer 210 is shown in FIG. An anisotropic dry etching process is performed to form a silicon nitride sidewall 212 on the inner wall of the trench structure 208. In a preferred embodiment, the dry etching may use a reactive ion etching process using 1239570 gold or alloy as the material of the gate. Referring to FIG. 11, a patterned photoresist layer (not shown in the figure) is formed next, and the photoresist layer is used to form a source region. With the patterned photoresist layer as a mask, ion implantation is performed on the base region 206 to form a doped region in the base region 206 as a source region of the fabricated transistor. The doped region is adjacent to the gate oxide layer 216, that is, above the sidewall of the trench structure 208, a source region 22 is formed. The source region 22 was planted at a concentration between 1 × 10-8 and 7 × 1020 / cm3. In addition, the electrical property of the source region 22 ·· ion implantation is opposite to that of the base region 206. Finally, in the twelfth figure, doping 222 is performed between the source regions 220 to improve the contact electrical properties of the source regions 220. Next, the contact window is fabricated. First, a dielectric layer 224 is formed to cover the doped polycrystalline silicon layer 2 j 8 and the base region 206. The dielectric layer 224 may be, for example, Lin Shi Xi Glass (PSG) or Side Phosphor Silicate Glass (BPSG), wherein the Atmospheric Pressure Chemical Vapor Deposition (APCVD) method is used to deposit the phosphorous silicon glass (PSG). The plasma-enhanced chemical vapor deposition (PECVD) method was used to deposit boron-filled silica glass (BPSG). Then, a patterned photoresist layer (not shown) is formed on the dielectric layer 224, and the dielectric layer 224 is etched by using the patterned photoresist layer as a mask to expose the source regions 220 respectively. Finally, a metal layer 226 is formed on the dielectric layer 224 and the exposed source region 220 to complete the trench-type power transistor with low gate capacitance of the present invention. 11 1239570 Knowing the above, the present invention uses the inner wall of the trench structure to form a side wall of nitrided stone, so as to suppress the first oxidation process, a thick oxide layer is formed only at the bottom of the trench structure, and then the gasified stone is removed After the layer is formed, a second oxidation process is performed to form a gate oxide layer on the inner wall of the trench. In other words, Benming is formed by multiple oxidation processes, accompanied by a nitride layer on the inner wall of the trench structure to form inter-oxide layers of different thicknesses, so that the bottom of the inter-electrode region is thicker; to reduce the capacitance of the transistor value. According to the invention
並不需使用額外之光罩製程’因此不會增加製程:更 不會有額外之光罩成本。 ^ 、崎發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝 神和範圍内，當可作各種之更動鱼 發明之精 竣範圍當視後附之申請專利範圍所界定者為準。之保There is no need to use an extra mask process' so there is no added process: there is no additional mask cost. ^ The Saki invention has been disclosed as above with a preferred embodiment, but it is not intended to limit the present invention. Anyone who is familiar with this skill and scope, can be used as a variety of modified fish inventions. The patent scope shall prevail. Guarantee
12 1239570 【圖式簡單說明】 為讓本發明之上述和直他 “ ％曰扪特破、和優點能更明 顯易1¾ ’下文特舉 車交住音方存丨丨，人 _ 平又仏貝靶例並配合所附圖式，作詳 導體元件之製作流 第一圖至第四圖為傳統高功率半 程示意圖；以及 第五圖至第十二圖為依據本發明 法，製造一具低閘極電容的溝渠式功率 程示意圖。 的較佳實 電晶體製 施例的方 造方法流12 1239570 [Brief description of the figure] In order to make the above-mentioned and straightforward "% broken", and the advantages of the present invention more obvious and easy 1¾ 'The following special car handed over to the sound store 丨 丨, people _ flat and flat shell The target example and the accompanying drawings are used to make the detailed flow of the conductor element. The first to fourth diagrams are traditional high-power half-range diagrams; and the fifth to twelfth diagrams are used to make a low Schematic diagram of trench power path for gate capacitor.
【元件代表符號簡單說明】 100 紗基材 101 蠢晶層 102 溝渠 104 閘氧化層 105 基體區域 106 複晶秒層 108 源極 110 介電層 112 金屬内連線 200 矽基材 202 蟲晶層 204和210 氮化矽層 206 基底區 208 溝渠結構 212 氮化矽側壁 214 氧化層 216 閘極氧化層 218 複晶秒層 221 源極區域 222摻雜 224 介電層 226 金屬層 13[Simple description of element representative symbols] 100 yarn substrate 101 stupid crystal layer 102 trench 104 gate oxide layer 105 base region 106 polycrystalline second layer 108 source 110 dielectric layer 112 metal interconnect 200 silicon substrate 202 insect crystal layer 204 And 210 silicon nitride layer 206 base region 208 trench structure 212 silicon nitride sidewall 214 oxide layer 216 gate oxide layer 218 polycrystalline second layer 221 source region 222 doped 224 dielectric layer 226 metal layer 13