TWI239092B - MOSFET with electrostatic discharge protection structure and method of fabrication - Google Patents
MOSFET with electrostatic discharge protection structure and method of fabrication Download PDFInfo
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- TWI239092B TWI239092B TW093132980A TW93132980A TWI239092B TW I239092 B TWI239092 B TW I239092B TW 093132980 A TW093132980 A TW 093132980A TW 93132980 A TW93132980 A TW 93132980A TW I239092 B TWI239092 B TW I239092B
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- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 104
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 239000002019 doping agent Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 26
- 238000002955 isolation Methods 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 238000009941 weaving Methods 0.000 claims description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 2
- 230000028327 secretion Effects 0.000 claims 2
- HGUFODBRKLSHSI-UHFFFAOYSA-N 2,3,7,8-tetrachloro-dibenzo-p-dioxin Chemical compound O1C2=CC(Cl)=C(Cl)C=C2OC2=C1C=C(Cl)C(Cl)=C2 HGUFODBRKLSHSI-UHFFFAOYSA-N 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- 241000238631 Hexapoda Species 0.000 claims 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 235000006040 Prunus persica var persica Nutrition 0.000 claims 1
- 240000006413 Prunus persica var. persica Species 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 claims 1
- 210000004556 brain Anatomy 0.000 claims 1
- 239000000835 fiber Substances 0.000 claims 1
- 150000002259 gallium compounds Chemical class 0.000 claims 1
- 125000005842 heteroatom Chemical group 0.000 claims 1
- 239000007769 metal material Substances 0.000 claims 1
- APTZNLHMIGJTEW-UHFFFAOYSA-N pyraflufen-ethyl Chemical compound C1=C(Cl)C(OCC(=O)OCC)=CC(C=2C(=C(OC(F)F)N(C)N=2)Cl)=C1F APTZNLHMIGJTEW-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 24
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 239000000306 component Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 230000005669 field effect Effects 0.000 description 7
- 239000004575 stone Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- -1 button Chemical compound 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- RAHZWNYVWXNFOC-UHFFFAOYSA-N Sulphur dioxide Chemical compound O=S=O RAHZWNYVWXNFOC-UHFFFAOYSA-N 0.000 description 2
- 229910052769 Ytterbium Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000002041 carbon nanotube Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000008267 milk Substances 0.000 description 2
- 210000004080 milk Anatomy 0.000 description 2
- 235000013336 milk Nutrition 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- WSNMPAVSZJSIMT-UHFFFAOYSA-N COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 Chemical compound COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 WSNMPAVSZJSIMT-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 244000166124 Eucalyptus globulus Species 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 241001106041 Lycium Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 241000282320 Panthera leo Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- JUZTWRXHHZRLED-UHFFFAOYSA-N [Si].[Cu].[Cu].[Cu].[Cu].[Cu] Chemical compound [Si].[Cu].[Cu].[Cu].[Cu].[Cu] JUZTWRXHHZRLED-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910021360 copper silicide Inorganic materials 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 210000005069 ears Anatomy 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000004945 emulsification Methods 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002472 indium compounds Chemical class 0.000 description 1
- PSCMQHVBLHHWTO-UHFFFAOYSA-K indium(iii) chloride Chemical compound Cl[In](Cl)Cl PSCMQHVBLHHWTO-UHFFFAOYSA-K 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000009940 knitting Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021392 nanocarbon Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- RLBIQVVOMOPOHC-UHFFFAOYSA-N parathion-methyl Chemical compound COP(=S)(OC)OC1=CC=C([N+]([O-])=O)C=C1 RLBIQVVOMOPOHC-UHFFFAOYSA-N 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000004291 sulphur dioxide Substances 0.000 description 1
- 235000010269 sulphur dioxide Nutrition 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012549 training Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
1239092 九、發明說明: 、【發明所屬之技術領域】 本發明有關於一種半導體電路及其製作方法 電防護結構的半導體電路及其製作方法。 有關於一種具有靜 【先前技術 一個被連接至外接阜的半導體積體雷敗你办, 電的傷害,靜電放電通常是發生在當電荷快速二中靜電放 接腳以及-外界物體間轉移。隨著積體電路的縮^的-個或數個 造成傷害的齡也隨之增加。靜電放電防護電路可用來=2對私路 敏感的核心積體電路。 月靜電月匕^保護 然而 嶋度==-===^_徵 【發明内容】 本發明主要提供-半導體電路,其包含有—半導體基村、—半導體元 件具有錄區域設於半導縣材±,以及—減型摻雜_水平設置於 =極區域旁並與祕區域相接,其中相反型摻雜區域具有與汲極相反的捧 質類型,且其摻質濃度高辨導體基材,而減师籠域及汲極區域則 用來形成一 p-n接合區域。 本發明之另一實施例中則提供丁一種半導體電路,其包含有一具有隔 離特徵的半導體基材,以及複數個MOS電晶體形成於半導體基材上,各 MOS電晶體具有一閘極位於一源極區域與一汲極區域之間,其中汲極區域 係水平鄰接於一相反型摻雜區域,相反型摻雜區域之摻質類型與該汲極相 反’其备質濃度並高於半導體基材,相反型摻雜區域與該沒極間形成一 接合。
0503-A30589TWF 5 1239092 本發明之另一實施例中, 兩 、… 製作半導體電路的方法,首先如征_、一 ▲半導體電路的方法,-種 促么、一半導體晶片,並呈有一 & 以及一p型摻雜基材,其中各基材均具有複數烟極、,接著^紐 掺雜區域水平鄰接於—_電晶體的-i極:开t主、;
型==二_電晶體的汲極_相反型摻雜類型,且二 U貝之展度“於?型基材,p型相反型摻雜 P :酬間將形成一 p•區,再形成至少—n型相反一 ===驗_,射續目__«與 曰_的_區域_反型摻雜類型’且其n型摻f之濃度絲於 p型相反型麵_觸飾瓣__成—㈣接合區。 為使本發明之上述和其他目的、特徵、和優點能更明顯紐,下文特 舉-較佳f施例,並配合所關式,作詳細說明如下: 【實施方式】 #蒼考第la圖及第ib圖,第la圖係顯示本發明第—實施例中一靜電 放電防護結構之示意圖,第lb圖係顯示第仏圖中靜電放電防護結構 1〇〇之俯視圖。如第!圖所示,靜電放電防護結構勘包含有一半導體基材 110以及至4 - η型金屬氧化半導體場效電^_〇§ρΈΤ或舰〇^^ 形成於半導體基材110上,基材11〇可為一部分ρ型摻雜基材或一 η型^ 材中之ρ型井’ 史於半導體基枯no上以將各刪os電晶 肢115为。隔離結構120可由局部氧化(L〇c〇s)、淺溝隔離(sti)或是其 他適當的方法所構成。靜電放電防護結構1〇〇可再包含有p型摻雜區域13〇 以收集基材偏壓,各NM0S電晶體115可另包含有一源極區域(源極)14〇、 一 >及極區域(>及極)15〇以及一閘極堆疊(閘極)丨6〇設於源極區域丨4〇與汲極區 域150之間,閘極堆疊(閘極)160另包含有一閘極介電層以及一閘極電極。 此外’ NM0S電晶體115包含有一相反型摻雜區域17〇水平鄰接於汲極區 0503-A30589TWF 6 1239092 域150以及汲極插塞180。當NM〇s電晶體115作為一輸出/入界面元件的 一部分時,汲極150可再經由汲極插塞18〇耦接至一輸出/入墊。 為了強化靜電放電防護而言,麗0S電曰曰曰題L包含有p型換雜區域(相 150之間將會形成一 p-n接合,且相反型摻雜區域17〇具有較基材iiq高之 摻質濃2度,舉例來說,相反型摻雜區域m料位面積的推質濃度大抵為 10〗3cm_2而沒極區域150處單位面積的摻質濃度大抵為1〇1W2,相反型摻 雜區域170之上表面大致與沒極15〇之上表面共平&,相較於汲極⑽與 基材110間之p-n接合,形成於相反型摻雜17〇與汲極15〇間之接合則 可提供一較低之崩潰電壓,因此可強你靜電放電防護能力。 減型摻籠170可由-雜_,例如傳統的佈植製輯形成,且 可與其他的p型摻雜區同時製作,舉例來說,NM〇s電晶體lls中的相反 型摻雜區170可與源/沒極製程或是PM〇s電晶體的輕摻雜汲極使用相同的 -道離子佈植製糊時製作,因此,製作相反型摻雜17G將不會需要額 外的光罩與佈植步驟。 NMOS電s曰體115包含有源極140與汲極150形成於半導體基材内, 其中源極與汲極可直接形成於P型基材上、p型井結構中、石夕錯層上或是碳 石夕層或是在-突起結構内。源/汲極可藉由多到佈植製程來形成複雜的推雜 分佈而強化其電性表現,舉例來說,源級極可包含有由輕劑量佈植所形成 之輕摻雜祕(LDD)d域以及由箱量雜卿成之源/汲極區域。NM〇s 電晶體115可具有鰭式場效電晶體(FinFET)結構、雙閘極(a。.㈣結構 或是多指狀(multi-finger)結構。
口月參考第2圖’第2圖係顯示本發明第二實施例中一靜電放電防護結 構200之不意圖。如第2圖所示,靜電放電防護結構包含有一半導體 基材210、正型金屬氧化半導體場效電晶體(pM〇SFET或pM〇s)2i5形成於 基材210上,以及一隔離結構22〇。靜電放電防護結構2〇〇可進一步包含有 0503-A30589TWF 1239092 一 η型摻雜區23〇。各PM〇s電晶體215包含有一源極區域(源極)测、一 汲極區域(;及極)25〇以及一閘極堆疊(閘極)26〇設於源極區域mo與沒極區域 250之間,閘極堆疊(閘極)16〇 $包含有一閘極介電層以及一閑極電極。此 外,NMOS電晶體215包含有一相反型摻雜區域27〇,pM〇s電晶體115 亦可再包含有汲極插塞280。本發明之構造仍可包含有其他元件或堆疊結 構,但為說明方便起見,在此不予贅述。 弟2圖中之基材21〇可為一 n型桉雜基材之一部分或是一 p型基材上 之,η型井。此外,PM〇S電晶體215可由一 p型井或雙井(此結構 來‘ie農接製作於於半導體基材上或其内。在本實施例中,基#上具有 隔離區域220來將PM0S電晶體215與其他元件隔離,隔離區域22〇可採 用各種隔離技術,例如局部氧化法與淺溝隔離。基材可進一步包含有η型 摻雜區230以收集基材偏壓。 PMOS電晶體215可利用一輸出/入介面電路來強化靜電放電防護能 力PMOS電晶體215可具有鰭式場效電晶體結構以及淺通道來強化載子 移動能力。 在PMOS電晶體215中,源極240、汲極250以及設於源極240與没 極250間的閘極堆疊26〇,具有與前述_〇3電晶體結構115大致相同之 材1與結構,其差異僅在於其中之摻質種類相反。在一實施例中,係採用 不同於NMOS電晶體115的金屬矽化物,作為接觸區域,以最佳化工作效 能及元件表現。而在另一實施例中,當PM0S電晶體215作為一輸出/入界 面元件時,則可去除汲極區域的金屬矽化物層,當PMOS電晶體215作為 一輸出/入界面元件的一部分時,汲極250可直接經由汲極插塞28〇連接至 一輸出/入墊。 此外,根據本發明,η型摻雜區(相反型摻雜區)27〇係水平鄰接於PM〇s 電晶體215的汲極250,以在相反型摻雜區域270與汲極250之間形成一 P-n接合,且相反型摻雜區域27〇具有較基材21()高之摻質濃度。在另一實 °503-A30589TWF 〇 1239092 施例中’相反型摻雜區域270水平地位於二汲極區域之間,相反型摻雜區 域270的上表面大抵與汲極之上表面共平面。相較於汲極25〇與基材Μ。 間之p%接合’形成於相反型摻雜27〇與汲極25〇間之p_n接合則可提供一 較低之崩潰電壓,因此可強化靜電放電防護能力。相反型摻雜區270可由 一#雜製程,例如傳統的佈植製程所形成,且可與其他的n型摻雜區同時 製作,舉例來說,PM〇s電晶體215中的相反型摻雜區27〇可與源/汲極製 程或是NMOS電晶體的輕摻雜汲極使用相同的一道離子佈植製程同時製 作,因此,製作相反型摻雜區270將不會需要額外的光罩與佈植步驟。< 請參考第3目,第3圖係顯示本發明第三實施例中一靜電放電防護結 構300之示意圖。請參考第3圖,靜電放電防護結構3〇〇包含有一半導體 紐310、NM〇S電晶體奶形成於半導體基材31〇上,以及隔離結構32〇。 靜免放電防瘦結構300可再包含有p型摻雜區域33〇。電晶體3b 可另包§有源極區域(源極)34〇、一沒極區域(没極)35〇以及一閘極堆疊(閘 極)360設於源極區域340與汲極區域35〇之間。此外,電晶體Ms 匕έ有相反型备雜區域370,以及汲極插塞380。如同熟習該項技藝者所 熟知的,本發明之構造仍可包含有其他元件或堆疊結構,但為說明转起 見,在此不予贅述。 靜電放電防護結構3〇〇大致與第!圖中的靜電放電防護結構⑽相同, 但相反型摻雜區域370具有-多元件結構,複數個相反ρ型元件設置於η 型按雜絲’内以形成ρ_η接合,其中相反型摻雜區域37〇具有較基材 31〇高之摻質濃度。各相反ρ型摻雜元件係水平設置於二個η型摻雜祕 ^50之間,並與其相鄰。在一實施例中,在二近似間極堆疊之間,二相 反型摻雜區域370轉性地設置於三紙型換雜_35〇之間(如第3圖所 示)。此外,插塞特徵係設置於h型摻雜没極特徵之上,並連接到一輪出/ 入塾。 睛蒼考弟4圖’第4圖係顯示本發明第四實施例中一靜電放電防護結 0503-A30589TWF n 1239092 構400之示意圖。如第4圖所示,靜電放電防護結構·係包含有一半導 體基材410、複數個PMOS電晶體415設於半導體基材41〇上以及隔離結 構420 ^靜電放電防護結構400可再包含有;q型摻雜區域心〇。pM〇s電晶 體415可另包含有一源極區域(源極)440、一汲極區域(汲極)45〇以及一閘極 堆疊(閑極)460設於源極區域440與汲極區域450之間。此外,PM0S電晶 體415包含有一相反型摻雜區域470,以及;;及極插塞480。如同熟習該項技 藝者所熟知的,本發明之構造仍可包含有其他元件或堆疊結構,但為說明 方便起見,在此不予贅述。 靜電放電防濩結構400大致與第3圖中的靜電放電防護結構3〇〇相同, 但所有摻雜類型接相反。其具有複數個相反n型摻雜元件設置於p型摻雜 汲極450内以形成p-n接合,其中相反型摻雜區域47〇具有較基材41〇高之 掺質濃度。各減η讎雜元件係水平設置於二個p型摻雜錄45〇之間, 並與其相鄰。在一實施例中,在二近似閘極堆疊46〇之間,二相反型摻雜 區域470選擇性地設置於三個p型摻雜没極之間(如第4圖所示)。此外, 插塞結構係設置於各p型摻雜汲極特徵之上,並連接到一輸出/入墊。 本發明係揭露出一種新的積體電路結構,其中各汲極具有至少一相反 型摻雜區域水平鄰接於没極,以形成一押接合來強化靜電放電表現。而所 使用之7G件並不限於前述第丨圖之觀〇8電晶體、第2圖之電晶體、 第圖中具有多元件相反型摻雜區之NMOS電晶體,以及第4圖中具有多 ^牛相反型摻雜區之PM0S電晶體,而可為其他元件,例如高Mm〇sfe丁夕、 =狀場效電晶體(FinFRT)以及高分子場效電晶體。汲極可連接至一輪出从 每。由於相反雜雜區域可於其他摻雜製程巾同時製作,因此可降低製造 成本。 _
姓第5圖係顯示根據本發明一實施例中方法500來製作一靜電放電防護 結構之流程圖。第6至關鶴示根據第5圖中之方法來製作二靜L 放电防邊結構之不意圖。如第6圖所示,首紐行步驟训,提供—具有元 0503-A30589TWF 1239092 件610與620之半導體基材’元件61〇可包含有p型摻雜井或p型基材以 及一閑極堆疊㈣’而閘極堆疊6_包含有__介電層以及—閑及雷極。 閉極介電層可包含有-適合之介電#料,或可具有—多層結構㈣含 入複數種〃 $制’並《具料目對冑完紐與錢糕者雛,例如可包 s有二氧切、氮切、編_及高介電常數㈣k)材料。高介 數材料則包含有氧化銓(hafci—xide)、氧化物〇xi岭氧化链 ㈨馳麵祕e)、氧化㈣她_2.於金U賴歡組合。間 極介電層可錄氧化法、原子層沉積(ALD)、化學氣相沉積(⑽)或物理氣 相沉積(PVD)製程所形成。在製作閘極介電層之過程中,尚可包含有額外之 處理’:如對熱,化層進行氮氣處理,或對包含有二氧化賴高介電材料 ^閘極;丨⑨層堆g進行回火處理。_極電極則包含有—導電材料,並同 木八可具有一多層結構。 閘極電应可Q有石夕、錯、其他導電材料或上述材料之 =料可包输版㈣、如济价金射化物、金屬 =化物、.氧化物、奈米碳管或上述材料之組合。而金屬聽含有銅、 >鋁、鋁合金、鈀、鈦、鈕、鎳、鈷以及鉬。金屬矽化物包含有矽化銅、 ==1輪、梦餘、魏^脸、魏鎳、純似及魏麵。 1、^極了由化學乳相沉積、物理氣相沉積、金·化製程、電鍍或原子 二曰二二域問極%極可包合有兩種不同構造’例如在削⑽與丽08 刀別具有不同之間極電極高度,或是在pM〇s與跑 分別具有不同之材料。 如第^圖所示,在步驟52〇卜將藉由習知摻雜製程,如離子佈植及 =政’來^ N型輕摻雜没極(LDD)區域64〇,並形成元件⑽之源極及汲 f目同的製程中,-相反型摻雜區_同時形成於树㈣内之 府m,ldd摻祕64G與相反型摻籠㈣均可由離子佈植製程 所形成,而純可為子,軒佈植製程之參數,如舰與佈植能量可
0503-A30589TWF 1239092 8;1乍射读積體電路技術而定,舉例來說,佈植劑量可4 1*1013至 丄 u cin 〇 擴散如=所示,在步驟530中,將藉由習知捧雜製程,如離子佈植及
極如同准及極(LDD)區域650 ’並形成元件620之源極及没 ㈣^ 中’―相反师祕_將同時形成於元件610内之LDD 戶^ 捧雜區650與相反型摻雜區660均可由離子佈植製程 :岭冑可為獅子,鮮佈植製程之參數,如劑量I佈^旦可 -〇 540 "! 610 # 620 如氣切 間極堆疊630之兩侧,且可包含有一介電材料,例 可里有—二碳切、氮氧切或上述材料之組合。側壁子_ 硬或氮氧構耳並可由沉積多層介電材料(如氮切、二氧切、碳化 、 夕)後再以進行非等向性回蝕刻製程所形成。 佈植=1Q圖所示’在步驟550中,將進行一高劑量與高雜能I之離子 mtr源極無極深處部分形成―歸雜域,在進行多道不同 U域,將可於元件61G内形成N㈣摻雜區域㈣以及於元 695 ' 二二=K69G,而藉由_娜子饰植來形成㈣重摻雜區域晰,且 一者之I雜劑量均大抵為l〇i5至l〇】6CIrf2。 接觸2 可純含有—解賴程來製作連接刺極、源極及汲極之 墊。茈外’連接至汲極之接觸插塞可再經由金屬連線結構連接到輸出/入 610鱼620 Γ法5〇0亦可再包含有其他步驟來形成一應力層,覆蓋於元件 6Ug上’或形成多層之導通結構。 圖至第1〇圖所揭露的僅為本發明之一實施例,仍可藉由其他 " 來开滅第3圖與第4圖内之多元件相反型摻雜構造。在另-實
0503-A30589TWF 1239092 雜製程來製作,並與一重摻雜區域 施例中,相反型摻雜區域係藉由一重摻 一起形成。 第u圖係顯示本發明一實施例中一半導體基材上之積體雷路之叫 面示意圖。積體電路_係包含有第^财之動s u5,以及域 包含有弟2圖之PMOS電晶體215。舉例來說,積體電路9〇〇包含有複數 個雇os電晶體與PM0S電晶體91〇與92〇,類似於第!圖中之·§雪 晶體115及/或第2圖中之PM〇s電晶體215,而元件91〇可用來作為積體 電路之核心元件。 積體電路9〇〇另包含有連線結構93〇,經由介電層9錢伸至複數個雷 晶體9K)及中之-者。此外,電晶體92〇之汲極924可直接連接至 輸出/入墊,連線結構930可包含有接觸插塞/導孔啦,以及導線934,以 用來將MOS電晶體910及92〇中之一者連接至積體電路·上之其他元件 或積體電路9GG外之元件。縣做連線結構的材料包括有銅、紹、铭合金、 鎢、奈米㈣、已#狀多㈣、魏鈦、魏叙、其他導電材料或上述 封料之組合,而連線結構可藉由物理氣相沉積、化學氣相沉積、電鐘或原 子層沉積以及其他製程(例如化學機械研磨製程)所形成。 ,、介電層_可包含有二氧化石夕、氣石夕玻璃(FSG)、低介電常輝㈣姻 料以及/或其他材料,而可由化學氣相沉積、旋轉塗佈玻璃(s〇g)、物理氣 相沉積、原子層沉_及/或其他製程风學频研歸程所職。介電層 940之厚度大抵為至2_聰,_本發明之介電層_並不限: 定厚度。 、 根據本發騎_之内容,各電晶體可另包含有—相反型接雜區 域922 =紐極924,以形成一 p_n水平接合區,且相反型換雜區奶中 之择係高於周圍基材或井内之摻f濃度,電晶體㈣可為一刪〇s 電晶體或-PMOS電晶體,電晶體920可用來作為輪出/入電路之一部分, 以強化靜電放電表現。
0503-A30589TWF 13 1239092 k裡所述之NM〇s電晶體可包含有鰭形場效電晶體結構,並具有伸長 的迫返以強化載子移動能力,並可藉由p型井或雙井㈣__辑構來製作 NMOS 麵接製作於—半導體基材喊上。而此處所指之半導體 基材釭^有基本型半導體(eIemen_ ,如晶型、多晶型或 非晶型結構之矽或鍺或鑽石;化合型半導體(c〇卿_d §⑽^油叫,如 碳化石夕、石申化鎵、磷化鎵、碟化銦、石申化_録化麵;合金型半導體㈤㈣ s_〇ndUCt〇r) ’如鍺石夕化合物、磷碎鎵化合物、坤録減合物、坤麵嫁化 合:,銦聽合物與磷物觀合物;或上述材料之組合。在本發明之 貝也例中°金型半導體可為具有濃度梯度之發鍺結構,亦即在不同位 置上曰有不同之销鍺敍比。在另_實施例中,半導體基材包含有一晶 設於合金_結構上,在另_實施例中,—應力層設於電晶體上, ,、怎力層可包含有含氮材料,如氮切及氮氧切。此外,半導體基材 可為設於-絕緣體上之半導體,如赠絕緣(观)基材,或為__晶 « 〇 ^ ^ ν肢基才可具有一多層結構。 層可!==極堆疊可具有一 •介電層與-f刪極。間極介電 Iw田’电材料或為一多層結構而具有複數種介電材料,並以且 ====_電流者較佳’例如可包含有二氧切、氮化石夕、氮 乳化紹、乳化給-氧化銘合金或上述材料 石夕材料、含錯材料 2而閑極電極則包含有-含 材科可包含有摻雜之多晶石夕、多晶石夕錯、金屬、金十W 金屬氧化物、金魏錢、奈米碳管 化物、 銅、鎢、銘、銘合金、二而金屬則包含有 化銅、石夕化辑m ”、’ 乂及銦。金屬石夕化物包含有矽 石夕化麵。_堆疊可再包含有—織子構造,^:=倾、魏始以及 _ n 介電層與閘極電極
0503-A30589TWF 1239092 兩偵1J j則壁子可包含有_介電材料,例如氮化 Γ氮氧切或上述材料之組合。所要再次強調的是上述二1:化 用來說明本發明之各實施例,而非本發明之限制。 牛、 顯干為ΙΓ明域m第4 ®巾之部分元倾輪結構並未源t 用頁:此外’本發明中之相反型摻雜區並不限於 =泉 用來形成其他場效電晶體,如高壓電晶體。 版、,構,而可 隹;、、、:本鲞明已以較佳實施例揭露如上,麩1 何熟習此項技藝者,在不脫離本發明之精神和苑圍内發明,任 月之保細圍如_之申請專利劍所界定者為準。 【圖式簡單說明】 圖係顯示本發日實施例中—靜電放電防護結構之干 ί圖軸μ la®帽敎辦護結叙俯姻。〜 弟屬顯示本發明第二實施例 第3圖係!h 構之示意圖。 mu林發㈣三實施辦—靜電放電防護結構 二=顯示本發明第四實施例中—靜電放電防護結構之示^。 圖係頒不本發明一實施例來製作 ^ 第ό至1〇周杪日g - 4日处… 疗^敌包防口又蛣構之流程圖。 示意圖。^不根據弟5圖中之方法來製作—靜電放電防護結構之 意圖 第π圖係_本發明-實施辦—铸體紐上之紐電路之剖面示 【主要元件符號說明】 〜半導體基材; 120〜隔離結構; 140〜源極; 100〜靜電放電防護結構; 115〜NMOS電晶體; 130〜p型摻雜區;
0503-A30589TWF 1239092 15 0〜汲極; 170〜相反型摻雜區; 200〜靜電放電防護結構; 215〜PMOS電晶體; 230〜η型摻雜區; 250〜汲極; 270〜相反型摻雜區; 300〜靜電放電防護結構; 315〜NMOS電晶體; 330〜ρ型彳爹雜區, 3 50〜汲極; 370〜相反型摻雜區; 400〜靜電放電防護結構; 415〜PMOS電晶體; 430〜η型摻雜區; 450〜汲極; 470〜相反型摻雜區; 500〜方法; 510、520、530、540、550〜 640〜Ν型LDD區域; 660、670〜相反型摻雜區; 690〜重摻雜區域; 910〜MOS電晶體; 922〜相反型摻雜區; 930〜連線結構, 934〜導線;
0503-A30589TWF 160〜閘極堆疊; 180〜汲極插塞; 210〜半導體基材; 220〜隔離結構; 240〜源極; 260〜閘極堆疊; 280〜汲極插塞; 310〜半導體基材; 320〜隔離結構, 340〜源極; 360〜閘極堆疊; 3 80〜汲極插塞; 410〜半導體基材; 420〜隔離結構; 440〜源極; 460〜閘極堆疊; 480〜汲極插塞; 610、620〜元件; 驟; 630〜閘極堆疊; 650〜P型LDD區域; 680〜側壁子; 900〜積體電路; 920〜MOS電晶體; 924〜源/汲極; 932〜接觸插塞/導孔; 940〜介電層。
Claims (1)
1239092 十、申請專利範圍: 1. 一種半導體電路,其包含有: 一半導體基材; 半^脰元件具^>及極區域設於該基材上;以及 相反型摻雜區域水平設置於該汲極區域旁並與該汲極區域相接,其 中該相反型摻雜區域具有與該汲極相反的摻雜型態,且其摻質濃度高於該 半導體基材,而該相反型摻雜區域及該汲極區域則用來形成一 接合區 域。 2·如申請專利範圍第1項所述之半導體電路,另包含有一導電插塞耦 接於該汲極區域與一輸出/入墊(input/output pad)之間。 一 上3·如申請專利範圍第!項所述之半導體電路,其中該半導體基材包含 有選自石夕、錯、鑽石、碳化石夕、石申化錁、碟化銦、石申化鋼、録化嫁、錯化 石夕、織料合物、轉雜合物、鎵辦化合物賴紅鱗的材料。 4_如申%專利棚第1項所述之轉體電路,其巾該半導體基材包含 有一埋藏層。 丄5.如申請專利範圍第}項所述之半導體電路,其中該半導體基材包含 名蟲晶梦層設於一錯層上。 6_如申請專利範圍第1項所述之轉體電路,其巾該半導體元件包么 有一 NM0S電晶體。 。 7.如申請專利·第1項所述之半導體電路,其中該半導體轉包人 有一 PM0S電晶體。 Z 8_如申請專纖圍第1賴述之半導體,其巾辭導體元件 一輸出/入電路之一部分。 '' _ 9·如中請專利範®第1項所述之半導體電路,其巾辭導體元件另包 一源極區域;以及 0503-A30589TWF 17 1239092 -閘極設於該半導體基材上該源極區域與該祕區域之間。 極介^T 一導體電™極包含有-閘 料或上麵⑽_娜崎紐 12.如帽專利範_ u項所述之半導體電路,其中該高介電常數介 屯材料包含有氧化銓、氧化锆、氧化鋁、二氧化錘 dioxide-alumina)合金或上述材料之组合。 、·° 、. a nmm 有至猶項所述之半導體電路,其_極電極包含 U.如中請專利範圍第1G項所述之半導體電路,其中該閘極電極至少 匕含有石夕、鍺及金屬材辑中之一者。 丄15.如申請專利範圍第1〇項所述之半導體電路,其中該閑極雷極包么 傾化铪、氧傾、氧脑、二氧化錯训—We★咖^ 金或上述材料之組合。 口 丄、16.如申請專利範圍第9項所述之半導體電路,其中該源極及該沒極區 域包含有輕摻雜汲極(LDD)及重摻雜區域。 Π·如申請專利範圍第9項所述之半導體電路,其中該相反型接雜區域 與該輕推雜區域係使用同類型之接質。 18. 如申請專纖圍第9柄述之半導體電路,另包含有至少一額外的 相反型摻雜區域水平設置於至少一額外的汲極區域旁。 、 19. 如申請專利範圍第18項所述之半導體電路,其中該雜係為η型, 而該相反型摻雜區域為Ρ型。 20. 如申請專利範圍第18項所述之半導體電路,其中該汲減為ρ型, 而該相反型摻雜區域為η型。 0503-A30589TWF 18 1239092 21·如申請專利範圍第 耦接於一輸出/入墊。 18員所述之半導體電路,其巾各該&極區域係 22. —種製作半導體電路的方法,其包含有: 提供—半導體晶片,其具有_ η型摻雜基材以及1型摻雜基材,其 1各基材均具有複數個閘極; /、 形成至少-ρ型相反型摻雜域水平鄰接並接騎_ Ν型通道金屬氧 化半導體⑽S)電晶_-祕區域,其中該ρ型減域具有二 該_0S電晶體的該汲極區域的相反型摻雜類型,且其ρ型摻質之濃度係高 於該P型基封’該p »反型摻雜區域與該建t晶體的該_區^ = 形成一 p-n接合區;以及 形成至少-η型相反型摻雜區域水平鄰接並接觸於—p型通道金屬氧 化半導體(PMQS)«m極區域,其巾該η翻反型摻縣域具有與 該PM0S電晶體的該沒極區域的相反型摻雜類型,且其η型摻質之濃度係高 於該ri型基材,該ρ型相反型摻雜區域與該醒〇s f晶體的該沒極區域間將 形成一 ρ-η接合區。 23·如申4專她圍第22項所述之製作半導體電_方法,其中形成 至乂 Ρ抛反型摻雜區域包含有同時於η型基材内形成ρ型摻雜以製作 該PM0S電晶體之該汲極。 24·如申請專繼®第22項所述之製作半導體電路的方法,其中形成 至少- η型相反型摻雜區域包含有同時於ρ型基枋内形力η型接雀以製作 該NM0S電晶體之該;;及極。 25.如申請專利細第22項所述之製作半導體電路的方法,另包含有: 形成至少-ρ型相反型摻縫域包含有同時於η型基材_成ρ型推 雜’以製作PM0S電晶體中没極之輕摻雜没極;以及 形成至少一 η型相反型摻雜區域包含有同時於ρ型基材内形成η型摻 雜’以製作NM0S電晶體中汲極之輕摻雜沒極。 0503-A30589TWF 19 1239092 26.如申請專利範圍第25項所述之製作半導體電路的方法 型摻雜與p型摻雜之摻雜劑量大抵為2。 、 7战η 27·如申請專纖圍f 25顿述之製作铸體桃^綠,另包 於該閘極之兩側形成側壁子;以及 · 提供重源極摻雜及重汲極摻雜。 28. 、如申請專利範圍第27項所述之製作半導體電路的方法,其中 供之重源極摻雜及重汲極摻雜的摻雜劑量大抵為丨〇15现_2至1〇16咖_2。 29. 如申請專利範圍第22項所述之製作半導體電路的方法咖其 供之η型摻雜係藉由一離子佈植製程來進行磷摻雜。 30·如申轉她g第22項所述之製作半導體電路的方法,其中 供之P型摻雜係藉由一離子佈植製程來進行硼摻雜。 ’、 31·如申請專利範圍第22項所述之製作半導體電路的方法,其中該 型基材係為形成於該半導體晶片上之一 n型井。 μ n 32·如申請專利範圍第22項所述之製作半導體電路的方法,其中該 型基材係為形成於該半導體晶片上之一 ρ型井。 μ Ρ 33· —種半導體電路,包含有: 一半導體基材具有一隔離特徵;以及 曰複數個金屬氧化半導體⑽S)電晶體形成於半導體基材上,各該_電 晶體具有-閘極位於—源極區域與—汲極區域之間,其中該汲極區域係水 平鄰接並接觸於-減型摻雜域,該相反型摻雜區域之摻質類型與該沒 極相反’其摻質濃度並高於半導體基材,軸反型摻雜區域與紐極間形 成一 Ρ-η接合。 • 34.如申叫專利範圍第33項所述之半導體電路,其中該廳電晶體包 含有一 Ν型通道MOS電晶體。 35.如申請專利範圍第33項所述之半導體電路,其中該_電晶體包 含有一 Ρ型通道M0S電晶體。 〇5〇3-A30589TWF 20 1239092 36. 如申請專利範圍第33項所述之半導體電路,其中在三換雜 極區域内選擇性地於二近似閘極間設有二相反型摻雜區域。 37. 如申β月專利範圍第33項所述之半導體電路,其中該·電晶 體包含有70件結構具有複數個減型掺祕域元件設至於該沒極 内以形成ρ-η接合。 38·如申#專利圍第33項所述之半導體電路,另包含有導電特 徵耦接於該汲極區域與一輸出/入墊之間。 39.如申明專利範圍帛33項所述之半導體電路,其中該隔離特徵 包含有淺溝隔離(STI)結構。 40·如申π專利範圍第33項所述之半導體電路,其中該半導體基 材包含有矽。 41.如申明專利範圍帛33項所述之半導體電路,其中該間極包含 有一閘極介電層與一閘極電極。 42·如申明專利範圍第33項所述之半導體電路,其中該源極區域 與祕極(I域包含有輕摻雜祕域與重摻雜區域。 43·如申研專她圍第33項所述之半導體電路,另包含有推質類 型與基材相同但具有高摻雜濃度之重摻雜區域,其巾該重摻雜區域之 功能為與基材接觸之主體。 44· 士申明專利範㈣33項所述之半導體電路,另包含有複數個 由導電材料構成之連線結構,耦接至該職電晶體。 0503-A30589TWF 21
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