TWI237857B - Method of fabricating MOS transistor by millisecond anneal - Google Patents

Method of fabricating MOS transistor by millisecond anneal Download PDF

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Publication number
TWI237857B
TWI237857B TW093131965A TW93131965A TWI237857B TW I237857 B TWI237857 B TW I237857B TW 093131965 A TW093131965 A TW 093131965A TW 93131965 A TW93131965 A TW 93131965A TW I237857 B TWI237857 B TW I237857B
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semiconductor substrate
temperature
scope
millisecond
item
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TW093131965A
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Chinese (zh)
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TW200614387A (en
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Shian-Jyh Lin
Sheng-Tsung Chen
Neng-Tai Shih
Chien-Chang Huang
Chien-Jung Yang
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Nanya Technology Corp
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Priority to US11/174,750 priority patent/US7160804B2/en
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Publication of TW200614387A publication Critical patent/TW200614387A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Non-Volatile Memory (AREA)
  • Element Separation (AREA)

Abstract

A method of fabricating a MOS transistor by a millisecond anneal is provided. First, a semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of the semiconductor substrate is provided. Then, at least one implanting process is performed to form two doped regions in opposite sides of the gate electrode. Thereafter, a millisecond anneal is performed to activate the dopants in the doped regions. The millisecond anneal includes a rapid heating step and a rapid cooling step within 1 to 50 millisecond.

Description

1237857 五、發明說明α) 【發明所屬之技術領域】 本發明係有關於一電晶 用毫秒回火製程來活化摻質 【先前技術】 在半導體元件製程中， 適當的雜質來控制帶電載子 域’以構成所需之電路元件 摻雜（doping)，而所加入之 一般而言，在藉由各種摻雜 體沈積法、熱擴散法或是化 内形成摻雜區後，均需再進 子在植入半導體基底時對半 步使半導體基底内的摻質活 阻值。 體的製作方法，尤其是一種利 的電晶體製作方法。 常會藉由在半導體基底内加入 的數目’而形成不同的摻雜區 ’這種加入雜質的方法即稱為 4貝亦被稱為摻質（d〇p a n t )。 方，(例如離子佈值製程、液 學条鐘法等）來於半導體基底 行一熱製程，來修補各摻質粒 導體基底造成的傷害，並進一 化，而降低這些摻雜區域之電 在進行熱製程的時候，由於擦質濃度豈 子往往會由原本定義之摻雜區域向外擴散，=献制貝粒 的時間越長，戶If擴散的離也就越大 f 進灯 狀、位置與摻質濃度也會產生更大》、‘區域之形 半導體元件技術是利用這種方式二趨有許多 之深處或藉此擴大摻雜區域。 、、丁 V體基底 但隨著羊導體元件尺寸的給 一 昇，摻雜區域的控制要求也日趨而^及π件積集度的提 程時間均大幅縮減，由以往歷° 因此，目前的熱製 製程逐漸縮短成為歷時1分鐘 3 〇刀鐘的丨互溫爐管熱 鐘内的快速回火（raPld1237857 V. Description of the invention α) [Technical field to which the invention belongs] The present invention relates to the activation of dopants by a transistor using a millisecond tempering process. [Previous technology] In the semiconductor device process, appropriate impurities control the charged carrier domain 'Doping is used to form the required circuit elements. Generally speaking, after the dopant region is formed by various dopant deposition methods, thermal diffusion methods or in-situ methods, the sub-regions need to be re-entered. When implanting a semiconductor substrate, the active resistance value of the dopant in the semiconductor substrate is made in half steps. The manufacturing method of the body, especially a favorable transistor manufacturing method. Different doped regions are often formed by the number ′ added in the semiconductor substrate. This method of adding impurities is called 4 shells and is also called dopant. (For example, ionic cloth value process, liquid science clock method, etc.) to perform a thermal process on the semiconductor substrate to repair the damage caused by each doped plasmid conductor substrate, and further reduce the electricity in these doped regions. During the thermal process, as the rubbing concentration tends to diffuse outward from the originally defined doped region, = the longer the time it takes to make shellfish, the greater the diffusion distance of the If. F into the lamp shape, position and The dopant concentration will also produce greater "," the shape of the region of the semiconductor device technology is to use this method to have a lot of depth or to expand the doped region. However, as the size of the sheep conductor element is increased by one liter, the control requirements for the doped region are also increasing, and the lift time of the π-piece integration degree has been greatly reduced. Therefore, the current The heating process is gradually shortened to a rapid tempering (raPld) in the inter-temperature furnace tube heat clock which lasts for 1 minute 30 minutes.

1237857 五、發明說明（2) thermal annealing，RTA)製程或快速加熱製程（rapid thermal process，RTP)或是加熱時間僅數十nan〇 — sec〇nd 之雷射回火製程。在快速回 升溫速率快且熱處理的時間 散深度較習知熱處理的擴散 深度（junction depth)，並 散，而避免短通道效應或閘 生。 然而隨著半導體元件尺 的不斷提昇，快速回火製程 技術之需求，而雷射回火製 克服，因此，我們迫切需要 化方法，來改善摻質過度擴 【發明内容】 本發明的主要目的在於 體的製作方法以及活化摻質 質過度擴散的問題。 本發明的另一目的在於 改善習知技術中按質過度擴 為達上述與其他目的， 電晶體製作方法，首先提供 面並定義有一源極區域、_ 源極區域與没極區域之間， 域内進行一第一離子佈植製 火或快速加熱製程中，由於其 短，因此一方面可使摻質的擴 深度為淺，而可有效降低接面 可改善摻質在橫向上的過度擴 極起始電壓不穩定的狀況發 寸的持續縮小以及元件積集度 也逐漸無法滿足深次微米製程 程亦存在有相當多的問題無法 一種更快速及更有效的摻質活 散的問題。 提供一種金屬氧化半導體電晶 的方法，以改善習知技術中摻 提供一種活化摻質的方法，以 散的問題。 本發明之一種金屬氧化半導體 一半導體基底，半導體基底表 没極區域以及一通道區域位於 接著對半導體基底上之通道區 程’再於半導體基底之通道區1237857 V. Description of the invention (2) Thermal annealing (RTA) process or rapid thermal process (RTP) or laser tempering process with heating time of only tens of nano-sec. At the time of rapid temperature rise and heat treatment, the dispersion depth is longer than the diffusion depth of the conventional heat treatment, and diverges to avoid short channel effect or gate generation. However, with the continuous improvement of the size of semiconductor elements, the need for rapid tempering process technology, and the laser tempering process is overcome, therefore, we urgently need a method to improve the excessive expansion of dopant. [Abstract] The main purpose of the present invention is to And the problem of excessive diffusion of activated dopants. Another object of the present invention is to improve the conventional technology to excessively expand the quality to achieve the above and other objectives. The method of making a transistor first provides a surface and defines a source region, a region between the source region and the non-polar region. In a first ion implantation fire or rapid heating process, because of its short length, on the one hand, the depth of dopant expansion can be shallow, and the interface can be effectively reduced. The excessive expansion of the dopant in the lateral direction can be improved. The initial voltage is unstable, the size of the device continues to shrink, and the component accumulation is gradually unable to meet the deep sub-micron process. There are also quite a few problems. A faster and more effective dopant dispersion problem cannot be achieved. A method for metal oxide semiconductor transistor improvement is provided to improve the doping in the conventional art. A method for activating dopants is provided to solve the problem. According to the present invention, a metal oxide semiconductor, a semiconductor substrate, a semiconductor substrate surface electrode region, and a channel region are located next to the channel region on the semiconductor substrate, and then to the channel region of the semiconductor substrate.

1237857 五、發明說明（3) 一 ----- 或上依序形成一閘極絕緣層與一閘極，然後對半導體基底 進行第一離子佈植製程，以分別於源極區域與汲極區域 内开乂成一按雜區，作為該金屬氧化半導體電晶體之源極與 ;及極]再進行一毫秒回火製程’其中毫秒回火製程中包含 有 瞬間加熱步驟及一瞬間降温步驟，且瞬間加熱步驟係 以大於每毫秒50 °C之加熱速度來對半導體基底表面進行加 熱’而瞬間降溫步驟則以大於每毫秒20 t之降溫速度來冷 卻半導體基底表面。 依照本發明之另一目的，本發明係提供一種活化摻質 的方法’首先提供一半導體基底，半導體基底内設有至少 一接雜區域，接著進行一毫秒回火製程，該毫秒回火製程 係包含有一瞬間加熱步驟及一瞬間降温步驟，其中瞬間加 熱步驟係以大於每毫秒5 〇 t之加熱速度來對該半導體基底 表面進行加熱，而瞬間降溫步驟則以大於每毫秒2 0 t之降 溫速度來冷卻半導體基底表面。 為使本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下·· 【實施方式】 請參考第1圖至第2圖，第1圖至第2圖係顯示本發明中 一金屬氧化半導體電晶體的製作方法示意圖。如第1圖所 示’首先提供一半導體晶片1 〇，半導體晶片1 〇包含有一半 ‘體基底12，其上並定義有一源極區域30、一没極區域40 以及一通道預定區2 〇位於源極區域3 〇與没極區域4 0之間。1237857 V. Description of the invention (3) A ----- or sequentially forming a gate insulating layer and a gate, and then performing a first ion implantation process on the semiconductor substrate to separate the source region and the drain electrode The region is opened into a mixed region as the source of the metal oxide semiconductor transistor; and pole] and then a millisecond tempering process is performed, wherein the millisecond tempering process includes an instant heating step and an instant cooling step, and The instantaneous heating step heats the surface of the semiconductor substrate at a heating rate greater than 50 ° C per millisecond, and the instantaneous cooling step cools the surface of the semiconductor substrate at a temperature lower than 20 t per millisecond. According to another object of the present invention, the present invention provides a method for activating dopants. 'First, a semiconductor substrate is provided. The semiconductor substrate is provided with at least one doping region, and then a millisecond tempering process is performed. It includes an instantaneous heating step and an instantaneous cooling step. The instantaneous heating step heats the surface of the semiconductor substrate at a heating rate greater than 50 t per millisecond, and the instantaneous temperature lowering step is a cooling rate greater than 20 t per millisecond. To cool the surface of the semiconductor substrate. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following exemplifies a preferred embodiment, and in conjunction with the accompanying drawings, a detailed description is as follows: [Embodiment] Please refer to Section 1 FIG. 2 to FIG. 2 are diagrams showing a method for manufacturing a metal oxide semiconductor transistor in the present invention. As shown in FIG. 1, 'a semiconductor wafer 10 is provided first, and the semiconductor wafer 10 includes half of a body substrate 12 on which a source region 30, an electrodeless region 40, and a predetermined channel region 20 are defined. Between the source region 30 and the non-electrode region 40.

0548-A50172W(5.0) ; 93043 ； Ericwen.ptd 第9頁 1237857 發明說明（4) 接著可藉由適當的罩幕來對半 内進行-第一離子佈植製程，：：=12 =通道區域2。 調整所形成之金屬氧化半導 ；/成弟一袼雜區Η，用於 (threshold voltage)。接著/日日體的閘極起始電壓 區域20上依序形成_間極^緣體基底1 2之通道 成一閘極堆疊，在本發明之一閘極電極18，以構 二氧切層所構成，但並不以：極絕緣層16係由 電材料，如氮化石夕層或氮氧彳展艮，而可包含有其他介 材料所構成，並以多I:;:珍層，而間極1嶋由導電 接著如第2圖所示，於閘極丨8 子構造26，並對半導體基底 二 =成-:壁 以分別於源極區域30與汲極 子佈植製程’ 極。此外二Ϊ ΐ 半導體電晶體之源極與汲 在本务明之貫施例.中，亦可再啼休、隹一 μ 一· 離子佈植製程，以斜角佈植的 I仃一弟二 摻雜區24之内側靠近雜區22與第三 _舆-第五摻雜區32預二第°!離；；；- f:摻 離：布植製程中所使用之摻植粒子係具有不二：；性弟二 一麗〇S電晶體之製作為例，苴 电14以 換雜區22與第三接雜圖，而第 五摻雜㈣，以避免短四=2δ與-第 袋型離子佈植製程。二亦即所謂之口 田於上述弟一及罘二離子佈植製程之 0548-A50172T\Vf(5.0) ; 93043 ； Ericwen.ptd 第10頁 1237857 五、發明說明（5) 劑直與麥數皆為熟習該項技藝者所熟知，且盥太發明之p 徵並無直接關係，故在此不予贅述。 -本么明之〜 質，=半導體基底12内之各摻 步調整其閘極起^帝芦。ΐ ^脰之源極與汲極，並進一 圖ίΐΓ二 在㈣程中溫度與時間之關係示意 一初妒® 在時間t〇時’半導體基底12表面具有 時，達到一 】度逐漸上升，而在時間u 度τι 接者進行一毫秒回火製程，該毫 =^程&含# ―瞬間加熱製程以及—瞬 其中該宅秒回火製程之施行時間亦大抵為⑴。毫秒且 ==熱步驟係以大於每秒2〇〇 t之加熱速度來料導體 二，1J表面進行加熱，纟本發明之較佳實施例巾，更以大 =母毫秒50 t之加熱速度來對半導體基底12表面進行加 吏半導體晶片10之表面溫度於時m2時到達一第二溫 ΪΙ二：間降溫步驟則以大於每毫秒2〇°c之降溫速度來 ¥體基底12表面，使半導體晶片1〇之表面 連:降，而於時間t3時到達—第三溫度丁3，最後，可再進 J額外之降服步驟，使半導體基底1 2之表面溫度逐漸下 在本發明之一貫施例巾，初始溫度τ〇與第四溫度τ4皆 f室溫，而第一溫度T1大抵為5 0 0至80(TC，第二溫度丁2大 氏為1 0 0 0至1 5 0 0 C，第三溫度丁3大抵為5〇〇至8〇〇。而瞬0548-A50172W (5.0); 93043; Ericwen.ptd Page 9 1237857 Description of the invention (4) Then the inner half can be performed by a suitable mask-the first ion implantation process :: = 12 = channel area 2 . Adjust the metal oxide semiconducting formed; / into a mixed region, for (threshold voltage). Then, the gate starting voltage region 20 of the solar body is sequentially formed on the gate electrode voltage region 20, and the channels of the substrate 12 are formed into a gate stack. In one of the gate electrodes 18 of the present invention, a two-oxygen layer is formed. The structure, but not the following: The pole insulating layer 16 is made of an electrical material, such as a nitride layer or an oxynitride layer, and may include other dielectric materials. The electrode 1 嶋 is conductive and then as shown in FIG. 2, the gate electrode 8 and the substructure 26 are formed, and the semiconductor substrate 2 is formed into a-: wall to be implanted in the source region 30 and the drain electrode, respectively. In addition, the source of the semiconductor transistor and the source of the semiconductor transistor are described in the following examples. In addition, you can also use the micro-ion implantation process, and implant the oblique angle. The inner side of the doped region 24 is close to the doped region 22 and the third-fifth doped region 32, and is separated from the second and the second;-f: doped: the doped particle system used in the implantation process has the : As an example, the production of the sexually-friendly 21S transistor is performed. The electron source 14 is replaced with the impurity region 22 and the third dopant pattern, and the fifth element is doped with europium to avoid short four = 2δ and -th pocket type ions. Planting process. Second, the so-called Kou Tian Yu 1 and the above-mentioned two-ion implantation process of 0548-A50172T \ Vf (5.0); 93043; Ericwen.ptd Page 10 1237857 V. Description of the invention (5) The agent and the wheat number are both Those skilled in the art are well-known and the p-sign of the toilet invention is not directly related, so I will not repeat it here. -The quality of this material is equal to the quality of the semiconductor substrate 12, and the gate electrode of the semiconductor substrate 12 is adjusted.图 ^ 脰 The source and drain electrodes go one step further. ΐ 二 二 The relationship between temperature and time in the process indicates a preliminary jealousy® At time t0, 'the surface of the semiconductor substrate 12 has reached one, and the degree gradually rises, and At the time u degrees, the receiver performs a one-millisecond tempering process. The millisecond process includes the instantaneous heating process and the instantaneous execution time of the second-second tempering process. The millisecond and == thermal step is to feed the conductor 2 at a heating speed greater than 200 t per second, and the surface is heated at 1 J. According to the preferred embodiment of the present invention, the heating speed is 50 t at a large = female millisecond. The surface of the semiconductor substrate 12 is processed. The surface temperature of the semiconductor wafer 10 reaches a second temperature at time m2: the step of indirect cooling reduces the temperature of the substrate 12 surface at a temperature greater than 20 ° c per millisecond, so that the semiconductor The surface of the wafer 10 is connected, and it is reached at time t3-the third temperature D3, and finally, an additional step of lowering may be performed to gradually reduce the surface temperature of the semiconductor substrate 12 in one embodiment of the present invention. The initial temperature τ〇 and the fourth temperature τ4 are both room temperature, and the first temperature T1 is approximately 500 to 80 (TC, and the second temperature Ding 2 is 100 to 150 C. The third temperature D3 is approximately 500 to 800. And the instant

0548 A50172TWf(5.0) ； 93043 i Ericwen.ptd 第11頁 1237857 五、發明說明（6) 間加熱步驟之施行時間（12 - 11)大抵為1至5 0毫秒，瞬間降 溫步驟之施行時間（t3 —ΐ2)亦大抵為1至5〇毫秒。 以下將進一步說明本發明之熱處理流程及所採用之熱 處理裝置與方法。請參考第4圖，第4圖係顯示本發明一實 施例中所使用的熱處理裝置丨〇 〇之示意圖。如第4圖所示， 熱處理裝置1 0 0包含一第一加熱源丨丨〇及一第二加熱源丨2 〇 分別設於熱處理裝置1 〇 〇之上下兩側，其中並設有一可放 置半導體晶片之載座。在本發實施例中，第一加熱源丨i 〇 與第二加熱源120均為電弧燈（arc ，而第二加熱源 120更包含有一氬氣燈（argon lamp)或氙（Xen〇n)氣燈，以 產生短波長之輻射光線（相較於矽之可吸收波長12〇〇nm)。 當半導體晶片1 0置入熱處理裝置丨〇 〇時，將先利兩第 一加熱源1 1 〇由半導體晶片1 〇下表面1 〇 b之一侧對整個半導 體晶片1 0進行加前述預加熱步驟，使半導體晶片工〇之溫度 逐漸上升至第一溫度T 1。 值得注意的是在進行預加熱步驟時，位於半導體晶片 1 0上表面1 〇 a —側之第二加熱源丨2 〇並不會開啟，直到要進 行毫秒回火製程時，方會開啟第二加熱源12〇，並藉由第 二加熱源120對半導體晶片1〇之上表面1〇a(亦即含^摻雜 區之半導體基底12表面）進行瞬間加熱，使上表面1〇a之溫 度到達前述第二溫度T2。隨後再迅速關閉第二加熱源丨 ’使半導體晶片1 〇上表面1 0 a的溫度再瞬間下降到第三温 度T3，並藉由此瞬間的高溫度梯度來達到前述活化捧—質/J^ 目的。之後可再關閉第一加熱源丨1 〇或逐漸降低其輪出、功0548 A50172TWf (5.0); 93043 i Ericwen.ptd Page 11 1237857 V. Description of the invention (6) The execution time of the heating step (12-11) is probably 1 to 50 milliseconds. The execution time of the instant cooling step (t3 — ΐ2) It is probably 1 to 50 milliseconds. The heat treatment process of the present invention and the heat treatment apparatus and method used in the present invention will be further described below. Please refer to FIG. 4. FIG. 4 is a schematic diagram showing a heat treatment apparatus used in an embodiment of the present invention. As shown in FIG. 4, the heat treatment apparatus 100 includes a first heating source 丨 and a second heating source 丨 2, which are respectively disposed on the upper and lower sides of the heat treatment apparatus 100, and a semiconductor can be placed therein. Wafer carrier. In the embodiment of the present invention, the first heating source 丨 i 〇 and the second heating source 120 are both arc lamps (arc, and the second heating source 120 further includes an argon lamp or xenon). Gas lamp to generate short-wavelength radiant light (compared to the absorbable wavelength of 12000nm of silicon). When the semiconductor wafer 10 is placed in the heat treatment device, it will first benefit the two first heating sources 1 1 〇 The entire pre-heating step of the entire semiconductor wafer 10 is performed from one side of the lower surface 10 b of the semiconductor wafer 10, so that the temperature of the semiconductor wafer process gradually rises to the first temperature T 1. It is worth noting that the pre-heating is performed During the step, the second heating source 丨 2 〇 located on the upper surface 10a of the semiconductor wafer 10 will not be turned on, and the second heating source 12 will be turned on until the millisecond tempering process is performed. The second heating source 120 instantaneously heats the upper surface 10a of the semiconductor wafer 10 (that is, the surface of the semiconductor substrate 12 including the doped region), so that the temperature of the upper surface 10a reaches the aforementioned second temperature T2. Quickly turn off the second heating source again to make the semiconductor crystal 1 〇 The temperature of the upper surface 10 a is instantly lowered to the third temperature T3, and the aforementioned high temperature gradient is used to achieve the aforementioned activation target—quality / J ^. After that, the first heating source may be turned off again 丨 1 〇 Or gradually reduce its rotation, work

1237857 五、發明說明（7) 率’使半導體晶片1 〇逐漸冷卻至第四溫度T4，以完成前述 之熱處理製程。 ^ 第5圖則為熱處理過程中半導體晶片丨〇的溫度與深度 關係示意圖。如第5圖所示，在毫秒回火製程中，雖然^ 將半導體晶片1 0之上表面1 〇 a瞬間加熱到第二溫度τ 2，作 這僅限於極接近上表面10a之部分區域，大部分=半導; 晶片1 0仍係維持在第一溫度丁 1。 、 ，相較於習知技術，本發明之主要特徵在於藉由毫秒回 火製程來活化摻質，而由於毫秒回火製程歷時僅數毫种至 數十毫秒，因此將可有效防止摻質粒子在半導體某y 擴散。此外，在摻質的活化過程中，所提供之溫度 大，往往越能促進摻質的活化，亦即可使摻雜區=^ 之片。電阻值（sh^eet resistance)，因此本發明之毫秒二， 製粒所具有之咼溫度梯度（大於每秒丨〇4它）將可大幅提升二 質的活化效果，因此可在降低摻質佈值劑量的炉、兄下传^ 導體基底12内料摻雜區具有相同甚至更佳 ”= 了之，在摻雜過程中不但可以形成更淺的接雜區^ 、 降低半導體基底12在摻雜過程中所受到之金 ^ 半導體元件之穩定性與可靠度。切。，進而楗升 —，然本發明已以較佳實施例揭露如上，铁 限疋本發明，任何熟習此技蓺 …、，、亚非用以 和範圍内，當可作更動盥潤^圖此太心肖本發明之精神 視後附之申請專利範圍所；；者；J本發明之保護範圍當1237857 V. Description of the invention (7) The rate ′ gradually cools the semiconductor wafer 10 to a fourth temperature T4 to complete the aforementioned heat treatment process. ^ Figure 5 is a schematic diagram of the relationship between temperature and depth of a semiconductor wafer during heat treatment. As shown in Fig. 5, in the millisecond tempering process, although ^ heats the upper surface 10a of the semiconductor wafer 10 to the second temperature τ2 instantly, this is limited to a part of the area very close to the upper surface 10a. Part = semiconducting; wafer 10 is still maintained at the first temperature D1. Compared with the conventional technology, the main feature of the present invention is that the dopant is activated by the millisecond tempering process, and because the millisecond tempering process lasts only a few milliseconds to tens of milliseconds, it will effectively prevent the inclusion of particles. Some y diffusion in the semiconductor. In addition, in the process of dopant activation, the higher the temperature provided, the more often the dopant activation can be promoted, that is, the doped region = ^. The resistance value (sh ^ eet resistance), so the millisecond of the present invention, the temperature gradient of granulation (greater than 〇 04) per second will greatly improve the activation effect of the second quality, so it can reduce the doped fabric Value dosing furnace, brother ^ The material doped regions in the conductor substrate 12 have the same or even better "= In addition, during the doping process, not only can the shallower doped regions be formed ^, the semiconductor substrate 12 is reduced in doping. The stability and reliability of the gold semiconductor components received in the process. Cut, and then improve-but the present invention has been disclosed in the preferred embodiment as above, the iron is limited to the present invention, anyone familiar with this technology ... ,, Within the scope and scope of Asia and Africa, it can be used to make changes ^ Figure this is too heart-shaking The spirit of the present invention is attached to the scope of patent application;

1237857 圖式簡單說明 第1圖至第2圖係顯示本發明中一金屬氧化半導體電晶 體的製作方法示意圖。 第3圖係顯示本發明之熱處理製程中溫度與時間之關 係不意圖。 第4圖係顯示本發明之一實施例中兩來進行熱處理製 程之裝置示意圖。 第5圖係顯示本發明之熱處理製程中溫度與深度之關 係不意圖。 【主要元件符號說明】 1 0〜半導體晶片； 10a〜上表面； 1 Ob〜下表面； 1 2〜半導體基底； 1 4〜第一摻雜區； 1 6〜閘極介電層； 1 8〜閘極； 2 0〜通道區域； 22〜第二摻雜區； 2 4〜第二掺雜區； 2 β〜侧壁子； 2 8〜第二摻雜區； 3 0〜源極區域， 3 2〜第二摻雜區；1237857 Brief Description of Drawings Figures 1 to 2 are schematic views showing a method for manufacturing a metal oxide semiconductor electric crystal in the present invention. Figure 3 shows the relationship between temperature and time in the heat treatment process of the present invention is not intended. Fig. 4 is a schematic diagram showing an apparatus for performing a heat treatment process in accordance with one embodiment of the present invention. Figure 5 shows the relationship between temperature and depth in the heat treatment process of the present invention is not intended. [Description of main component symbols] 10 ~ semiconductor wafer; 10a ~ upper surface; 1 Ob ~ lower surface; 12 ~ semiconductor substrate; 1 ~ 4 ~ first doped region; 16 ~ gate dielectric layer; 1 ~ 8 ~ Gate; 2 0 ~ channel region; 22 ~ second doped region; 2 4 ~ second doped region; 2 β ~ sidewall; 2 8 ~ second doped region; 3 0 ~ source region, 3 2 ~ second doped region;

0548-A50172TWf(5.0) ； 93043 ； Ericwen.ptd 第14頁 1237857 圖式簡單說明 4 0〜汲極區域； 100〜熱處理裝置； 11 0〜第一加熱源； 1 2 0〜第二加熱源； t0 、tl 、ΐ2 、t3 、t4〜時間； 丁 0〜初始溫度； T1〜第一溫度； 丁2〜第二溫度； 丁 3〜第三溫度； T4〜第四溫度。0548-A50172TWf (5.0); 93043; Ericwen.ptd page 14 1237857 The diagram briefly explains 40 ~ drain region; 100 ~ heat treatment device; 110 ~ first heating source; 120 ~ second heating source; t0 , T1, ΐ2, t3, t4 ~ time; D0 ~ initial temperature; T1 ~ first temperature; D2 ~ second temperature; D3 ~ third temperature; T4 ~ fourth temperature.

0548-A50172TWf(5.0) ； 93043 ； Ericwen.ptd 第15頁0548-A50172TWf (5.0); 93043; Ericwen.ptd page 15

Claims (1)

1237857 六、申請專利範圍 1. 一種金屬氧化半導體電晶體製作方法，其包含有： 提供一半導體基底，該半導體基底表面設有一通道預 定區， 對該半導體基底上之該通道預定區内進行一第一離子 佈植製程，以將複數第一摻質植入半導體基底； 於該半導體基底之該通道預定區上形成一閘極堆疊， 該閘極堆疊包含有一閘極絕緣層以及一閘極電極； 對該半導體基底進行一第二離子佈植製程，以於該閘 極堆疊之兩侧的該半導體基底植入第二摻質，而分別形成 一摻雜區，作為該金屬氧化半導體電晶體之源極與汲極； 以及 進行一毫秒回火製程，該毫秒回火製程係包含有一瞬 間加熱步驟及一瞬間降溫步驟，其中該瞬間加熱步驟及該 瞬間降溫步驟之進行時間均大抵為1至5 0毫秒。 2. 如申請專利範圍第1項所述之金屬氧化半導體電晶 體製作方法，其中該毫秒回火製程係用來修補該半導體基 底於該第一及第二離子佈植製程中受到的傷害及並活化該 第一摻質與該第二摻質。 3. 如申請專利範圍第1項所述之金屬氧化半導體電晶 體製作方法，其中該瞬間加熱步驟係以大於每毫秒50 °C之 加熱速度來對該半導體基底表面進行加熱。 4. 如申請專利範圍第1項所述之金屬氧化半導體電晶 體製作方法，其中該瞬間降溫步驟則以大於每毫秒2 0 °C之 降溫速度來冷卻該半導體基底表面。1237857 VI. Scope of patent application 1. A method for manufacturing a metal oxide semiconductor transistor, comprising: providing a semiconductor substrate, a surface of the semiconductor substrate is provided with a predetermined channel area, and a first channel area is performed on the semiconductor substrate; An ion implantation process to implant a plurality of first dopants into a semiconductor substrate; forming a gate stack on a predetermined region of the channel of the semiconductor substrate, the gate stack including a gate insulating layer and a gate electrode; A second ion implantation process is performed on the semiconductor substrate, a second dopant is implanted on the semiconductor substrate on both sides of the gate stack, and a doped region is formed respectively as a source of the metal oxide semiconductor transistor Electrode and drain electrode; and a one millisecond tempering process, the millisecond tempering process includes an instant heating step and an instant cooling step, wherein the duration of the instant heating step and the instant cooling step are approximately 1 to 50 millisecond. 2. The method for manufacturing a metal oxide semiconductor transistor as described in item 1 of the scope of the patent application, wherein the millisecond tempering process is used to repair the damage and damage to the semiconductor substrate during the first and second ion implantation processes. The first dopant and the second dopant are activated. 3. The method for manufacturing a metal oxide semiconductor electric crystal as described in item 1 of the scope of the patent application, wherein the instant heating step is to heat the surface of the semiconductor substrate at a heating rate greater than 50 ° C per millisecond. 4. The method for fabricating a metal oxide semiconductor electric crystal as described in item 1 of the scope of the patent application, wherein the instant cooling step cools the surface of the semiconductor substrate at a cooling rate greater than 20 ° C per millisecond. 0548-A50172TWf(5.0) i 93043 i Ericwen.ptd 第16頁 1237857 六、申請專利範圍 ------ 5.如申請專利範圍第w M , x ^ ^ . 1項所述之金屬氧化半導體電晶 .^ X, ^ ^ ^ 口袋型離子佈值製程，以製作該 源極及該汲極。 製作方法，其中該毫秒 6 ·如申請專利範圍筻！ 了5 y丄 ^ ^ ^ 1項所述之金屬氧化半導體電晶 回火製程所進行之時間大抵為1 至5 0毫秒。 7 ·如申請專利範圍第！ TS ^丄 乳固系1項所述之金屬氧化半導體電晶 體製作方法，另包含有〜予g j < — _ , 預加熱製程，實行於該宅秒回火 製程之\ f預先將該半導體基底加熱至-第-溫度。 8 ·如％專利耗圍第7項所述之金屬氧化半導體電晶 體製作方法，纟中該第―溫度大抵為5〇〇至8〇(rc。 9·如申睛專利範圍第7項所述之金屬氧化半導體電晶 體製作方法/其中該毫秒回火製程係先藉由該瞬間加熱步 驟來將該半導體基底表面加熱至一第二溫度，之後再藉由 該瞬間降溫步驟來將該半導體基底表面冷卻至一第三溫 度。 I 0 ·如申請專利範圍第9項所述之金屬氧化半導體電晶 體製作方法，其中該第二溫度大抵為8 〇 〇至丨5 〇 〇 t。 II ·如申請專利範圍第9項所述之金屬氧化半導體電晶 體製作方法，其中該第三溫度大抵為500至800 °C。 1 2 · —種活化摻質的方法包含有： 提供一半導體基底，該半導體基底内設有至少一摻雜 區域；以及 進行一毫秒回火製程，該毫秒回火製程係包含有一瞬0548-A50172TWf (5.0) i 93043 i Ericwen.ptd Page 16 1237857 VI. Application scope of patent ------ 5. As described in the scope of application for patent scope w M, x ^ ^. 1 Crystal. ^ X, ^ ^ ^ pocket-type ion-distribution process to make the source and the drain. Production method, in which the milliseconds The 5 y 丄 ^ ^ ^ 1 metal oxide semiconductor transistor tempering process takes about 1 to 50 milliseconds. 7 · If the scope of patent application is the first! The method for making a metal oxide semiconductor transistor described in TS ^ 丄 Milk Solid System 1 further includes ~~ gj < — _, a pre-heating process, which is performed in the home-tempering process, and the semiconductor substrate is preliminarily used. Heated to -S-temperature. 8 · The method for manufacturing a metal oxide semiconductor transistor according to item 7 of the% Patent Consumption, in which the-temperature is generally between 500 and 80 (rc. 9) as described in item 7 of Shenjing's patent scope Manufacturing method of metal oxide semiconductor transistor / wherein the millisecond tempering process firstly heats the surface of the semiconductor substrate to a second temperature by the instantaneous heating step, and then uses the instantaneous temperature lowering step to surface the semiconductor substrate Cool to a third temperature. I 0 · The method for manufacturing a metal oxide semiconductor transistor as described in item 9 of the scope of patent application, wherein the second temperature is approximately 800 to 5,000 t. II. The method for manufacturing a metal oxide semiconductor transistor according to item 9 in the scope, wherein the third temperature is approximately 500 to 800 ° C. 1 2 · A method for activating dopants includes: providing a semiconductor substrate, the semiconductor substrate Providing at least one doped region; and performing a millisecond tempering process, the millisecond tempering process includes a transient 0548-A50172TWf(5.0) ； 93043 ； Ericwen.ptd 第17頁 1237857 六、申請專利範圍 --- *-- ^ 間加熱步驟及一瞬間降溫步驟，其中該瞬間加熱步驟及該 瞬間降溫步驟之進行 1 丁日間均大抵為1至5 0笔；秒。 1 3 .如申睛專利範圍第1 2項所述之活化摻質的方法， 另包含有一預加熱步驟，施行於該毫秒回火製程之前，該 預加熱步驟係利用一第一加熱源將該半導體基底加熱到一 第一溫度。 1 4 ·>如申明專利範圍第1 3項所述之活化摻質的方法， 其中該*秒回火製程係先進行該瞬間加熱步驟，利用一第 二加熱源對該半導體基底表面進行瞬間加熱，使該半導體 基底表面之溫度瞬間上升到一第二溫度，接著再進行該瞬 間降blL步弥’以將該半導體基底表面之溫度由該第二溫度 快速下降至一第三溫度。土 — 1 5 ·如申請專利範圍第i 4項所述之活化摻質的方法， 其中該第一溫度大抵為500至800 °C。 1 6 ·如申請專利範圍第1 4項所述之活化摻質的方法’ 其中該第二溫度大抵為8 0 0至1 5 0 〇 °C ° 1 7 ·如申請專利範圍第1 4項所述之活化摻質的方法’ 其中該第三溫度大抵為5 0 0至8 0 0 °C ° 1 8 ·如申請專利範圍第1 2項所述之活化換質的方法’ 其中該瞬間加熱步驟係以大於每毫秒5 0 °C之加熱速度來對 該半導體基底表面進行加熱。 1 9 ·如申請專利範圍第1 2項所述之活化摻質的方法’ 其中該瞬間降溫步驟則以大於每毫秒2 0 C之降溫速度來冷 卻該半導體基底表面。0548-A50172TWf (5.0); 93043; Ericwen.ptd Page 17 1237857 VI. Patent Application Scope --- *-^ Intermediate heating step and instant cooling step, among which the instant heating step and the instant cooling step are performed 1 Ding averaged between 1 and 50 strokes during the day; seconds. 1 3. The method for activating dopants as described in item 12 of Shenyan's patent scope, further comprising a pre-heating step, which is performed before the millisecond tempering process. The pre-heating step uses a first heating source to The semiconductor substrate is heated to a first temperature. 1 4 > The method for activating dopants as described in Item 13 of the declared patent scope, wherein the * second tempering process first performs the instant heating step and uses a second heating source to instantaneously perform surface treatment on the semiconductor substrate. The heating causes the temperature of the surface of the semiconductor substrate to instantly rise to a second temperature, and then the instantaneous step blL step is performed to rapidly decrease the temperature of the surface of the semiconductor substrate from the second temperature to a third temperature. Soil — 1 5. The method for activating dopants as described in item i 4 of the scope of patent application, wherein the first temperature is approximately 500 to 800 ° C. 1 6 · The method for activating dopants as described in item 14 of the scope of patent application ', wherein the second temperature is approximately 800 to 150 ° C ° 1 7 The method for activating dopant as described above, wherein the third temperature is approximately 500 to 800 ° C ° 1 8 · The method for activating and changing quality as described in item 12 of the patent application scope ', wherein the instant heating step The surface of the semiconductor substrate is heated at a heating rate greater than 50 ° C per millisecond. [19] The method of activating dopants as described in item 12 of the scope of patent application ', wherein the instant cooling step cools the surface of the semiconductor substrate at a cooling rate greater than 20 C per millisecond. 0548-A50172TWf(5.0) ； 93043 ； Ericwen.ptd 第18頁 1237857_ 六、申請專利範圍 2 〇.如申請專利範圍第1 2項所述之活化摻質的方法， 另包含有^一第-一降溫步驟，以將該半導體基底由該弟二溫 度下降至室溫。 2 1 .如申請專利範圍第1 2項所述之活化摻質的方法， 其中該毫秒回火製程所進行之時間均大抵為1至5 0毫秒。0548-A50172TWf (5.0); 93043; Ericwen.ptd, page 18, 1237857_ 6. Application for patent scope 2 〇. The method for activating dopants as described in item 12 of the scope of patent application, including the first-first cooling Step to lower the semiconductor substrate from the second temperature to room temperature. 2 1. The method for activating dopants as described in item 12 of the scope of patent application, wherein the time during which the millisecond tempering process is performed is approximately 1 to 50 milliseconds. 0548-A50172TWf(5.0) ； 93043 ； Ericwen.ptd 第19頁0548-A50172TWf (5.0); 93043; Ericwen.ptd page 19
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