TWI237444B - Low jitter input buffer with small input signal swing - Google Patents

Abstract

A particular input buffer receiver includes a buffer input portion for receiving an input signal SIGNAL_IN, a large capacitance CHC between the PMOS bias node and the VSS source voltage, and a buffer output portion for producing an output signal SIGNAL_OUT1. The circuit works to remove ground noise by charge coupling the VB11 bias voltage to the VSS source voltage of the input device.

Description

面電路，特別是指一種低 1237444 五、發明說明（1) 【發明所屬之技術領域】 本發明通常是有關於一個 輸入信號波動之輸入缓衝器。 【先前技術】 本發明主要係應用於儲存裝置的輸入 已有大量的解決方案也被提出，如： 美國專利權號5,978,3 1 〇(Bae et al) 動態隨機存取記憶體（DRAM)儲存裝置的一 其可以除去來自於（接收機解碼器識別用 的噪音。該裝置有一個可被延遲一預定時 力，而且也能夠產生一個輸出的控制信號 器根據此控制信號產生無噪音輸入的緩衝 美國專利權號6,002,618Uomaak et 用於唯讀記憶體的一個N通道金屬氧化半 接收器電路。它包括一個控制磁滯現象的 於接收器的一個第二階段和附加的輸出， 的轉變噪音是被隔離的，而且不能夠回饋 衫響電晶體-電晶體邏輯（電路）Τ τ l的電 =長，場效應電晶體FET被用來將接收器 隻化量最少化。 一個輸入緩衝器起作用於地線噪音之 J機械裝置，特定的電容量能被用來減少 路這種噪音。 【發明内容】 電路上，在之前 描述了一種用於 種輸入緩衝器， )列位址濾波器 間的資料輸出能 。同時也具有一 輸出。 a 1)揭示了一種 導體（NMOS)輸人 回饋迴路，有用 來自記憶體内部 於接收器電路去 壓水平。尺寸寬 轉變水平的加工 前’仍然需要_ 一個儲存輸入電Surface circuit, especially a low 1237444 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention generally relates to an input buffer with an input signal fluctuation. [Previous Technology] The present invention is mainly applied to the input of storage devices. A large number of solutions have also been proposed, such as: US Patent No. 5,978,3 1 0 (Bae et al) Dynamic Random Access Memory (DRAM) Storage One of the devices can remove the noise from the (receiver decoder identification). The device has a control signal that can be delayed for a predetermined time and can also produce an output. A noise-free input buffer is generated based on this control signal. U.S. Patent No. 6,002,618 Uomaak et al. An N-channel metal-oxide half-receiver circuit for read-only memory. It includes a second stage of the receiver that controls hysteresis and additional output. The transition noise is Isolated, and can not give back to the transistor-transistor logic (circuit) T τ l = long, field effect transistor FET is used to minimize the amount of receiver only. An input buffer acts on The mechanical mechanism of the ground wire noise, a specific capacitance can be used to reduce the noise of the road. [Summary of the Invention] On the circuit, a kind of use is described before. Types of input buffer) can output data between the column address filter. It also has an output. a 1) Reveals a conductor (NMOS) input feedback loop, useful from the internal memory to the receiver circuit to depressurize the level. Wide size before level conversion processing ’still need _ a storage input power

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本發明之主要目的是為一 接收器提供一種有效率的電路 音。 特定的儲存裝置之輸入緩衝 設計技術，以過濾其地線噪 降 通 量 本發明的進一步的目的 低“號波動的方法。這種方 道金屬氧化半導體（PM0S)的 的電容。 係提供一種在輸入緩衝器中 法係於輪入緩衝接收器的p 偏壓節點上附著的一個大容 這些目的均由輸入緩衝接收器所完成 接收一個輪入信號SIGNAL IN =元成，，、匕έ :為- ν / / +導體（觸S)的偏壓節點和—個電源電壓 ----—工屮JI η u 出信號SIGNAL—0UT1的緩衝器輪出部分 vss之間的-個大電容量通道控制器chc，為了產生一個· 此外，、在輸入緩衝接收器中，電晶體PU和電晶體P12 的閘極電壓信號VB11連接負荷電源電壓Vss，這將導致輸出信 號SIGNAL— OUT 1有較快的反應時間。 藉由以下對本發明的一個較佳具體實施例的各項詳細 的描述，丽述的和其他的目的，各方面和優點都將比較容 易理解。 【實施方式】 第1圖是依先前技術之一輸入緩·衝接收器電路圖，該 輸入緩衝接收器包括··用來接收輸入信號SIGNAL JN的緩 衝器輸入部分1〇〇 ，及用來產生輸出信號SIGNAL__0UT的 緩衝器輸出部分2 0 0 。 缓衝器輸入部分1〇〇包含有··二N通道金屬氧化半導The main object of the present invention is to provide an efficient circuit tone for a receiver. The input buffer design technology of a specific storage device to filter its ground line noise reduction flux. A further object of the present invention is to reduce the number of fluctuations. This type of metal oxide semiconductor (PM0S) capacitor is provided. The input buffer method is a large capacity attached to the p-bias node of the round buffer receiver. These purposes are accomplished by the input buffer receiver to receive a round signal. SIGNAL IN = Yuan Cheng ,, -ν / / + the bias node of the conductor (touch S) and a power supply voltage --- industrial JI η u output signal SIGNAL — OUT1 buffer buffer part vss-a large capacity channel The controller chc, in order to produce a · In addition, in the input buffer receiver, the gate voltage signal VB11 of the transistor PU and the transistor P12 is connected to the load power voltage Vss, which will cause the output signal SIGNAL_ OUT 1 to have a faster Response time. With the following detailed description of a preferred embodiment of the present invention, all aspects and advantages of the present invention and other objects will be relatively easy to understand. [Embodiment] Figure 1 is According to one of the prior art input buffer receiver circuit diagrams, the input buffer receiver includes a buffer input section 100 for receiving an input signal SIGNAL JN, and a buffer output section 2 for generating an output signal SIGNAL__0UT 0 0. The buffer input section 100 includes two N-channel metal oxide semiconductors.

第6頁 1237444 五、發明說明（3) 的電晶體1^1、N2，在此，-個較低的電源電壓V 被靶加於該電晶體N1、N2之 二 v被施λ ^電日日體、P2，在此，一個較高的供應電壓 vDD破化加於其源極節點， 祜磕垃认中 於電晶體/ΪΓ點’在先前技術中，一參考電壓被施加 的閘極，而、1極，輸入信被連接於電晶體… „ .. 且信號VB1被施加於電晶體N1和電晶體p 1的汲極， 二儉f 用於電晶體P1和電晶體1"2的p通道金屬氧化半導體 乂二輸出邛分20 0由電晶體⑽汲極和電晶體P2汲極的一個 :二：=所組成，其適合作為對一個反向器π的輸入，反向 口口 π的輸出係輸出信號SIGNAL_〇UT 〇 第P圖是本發明之一輸入緩衝接收器較佳實施例電路 ，i t該圖所示，本發明包含有：一緩衝器輸入部分1 ο 1 緩衝器輸出部分201，該緩衝輸入部分1〇1包含有：二 ^通道金屬氧化半導體的電晶體Nl 1和電晶體N12，在此， *低的電源電壓Vss被施加於電晶體Nil和電晶體N12的 源極節點，二P通道金屬氧化半導體的電晶體PI 1和電晶體 在此 較南的供應電壓VDD被施加於源極節點，以 了個信號vB11銜接於電晶體PU和電晶體P12的閘極節點， 以一參考電壓VREF銜接於該電晶體N 1 1的閘極，輸入信號 N AL — I N被施加於電晶體n 1 2的閘極，而且信號vbii被銜接 於電晶體N11和電晶體ρ π的汲極。在本發明中，一個大的電 谷星通道控制器CHC在PMOS金屬氧化物半導體的偏壓節點信Page 61237444 V. Description of the invention (3) Transistor 1 ^ 1, N2, Here, a lower power supply voltage V is applied to the transistor N1, N2 bis v is applied λ ^ electric day Sun body, P2. Here, a higher supply voltage vDD is added to its source node, which is considered to be at the transistor / ΪΓ point. In the prior art, a reference voltage was applied to the gate, And, 1 pole, the input signal is connected to the transistor ...… and the signal VB1 is applied to the transistor N1 and the drain of the transistor p 1, and the second voltage f is used for the transistor P1 and the transistor 1 " 2 p The channel metal oxide semiconductor has two output points of 20 0, which is composed of one of the transistor's drain and the transistor P2's drain: two: =, which is suitable as an input to an inverter π. The output is the output signal SIGNAL_〇UT 〇 Figure P is a circuit of a preferred embodiment of the input buffer receiver of the present invention, as shown in the figure, the present invention includes: a buffer input section 1 ο 1 buffer output section 201. The buffer input section 101 includes: a transistor N11 and a transistor N12 of a two-channel metal oxide semiconductor. Here, the * low power supply voltage Vss is applied to the source node of transistor Nil and transistor N12, the transistor P1 of the two P-channel metal oxide semiconductor and the transistor are applied to the source at the souther supply voltage VDD The node of the transistor is connected to the gate of transistor PU and transistor P12 with a signal vB11, and the gate of transistor N 1 1 is connected with a reference voltage VREF. The input signal N AL — IN is applied to the transistor n 1 2 gate, and the signal vbii is connected to the transistor N11 and the drain of the transistor ρ π. In the present invention, a large electric valley star channel controller CHC is at the bias node of the PMOS metal oxide semiconductor letter

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號v:和電源電麼Vss之間，緩衝器 晶體N12的汲極和雷曰驊pi9从u 係由電 ，其適合作為J ΛτΛ 個公共節點所組成 ^個反向态111的輸入，反向器π 1的於屮 疋本發明的輪出信號SIGNAL — 0UT1。 ° 、刖 一個大電容量通道控制器CHC是與輸入緩衝 置電晶體Nil、P11和P12的寄生電容相串聯的，由於^ 聯結比率，該大電容量通道控制器CHC基本上加枰充ς 了 Ρ通道金屬氧化物半導體偏壓節點的U閘.極電壓°，而; 於電晶體Nil和電晶體N12的電壓電源Vss，則 SIGNAL —0UT1信號有一個比較快的回應時間。 +第3Α、3Β圖是本發明之輸入緩衝接收器中波動提升、 回落的定義時間向量圖，由該二圖可知本發明的輸入信號 SIGNAL—IN、電壓電源vss 、以及輸出信號SIGNAL —〇UT1的 時控運行方式，當輸入信號SIGNAL —IN被定義為vih = vref + 350mv和V1L - VREF - 350mv ’電源電壓Vss為200mv。於輸入信號 SIGNAL 一 IN增加時，輸出信號SIGNAL 一 0UT1係藉由延遲的 DELTA1或DELTA2所定義，而輸入信號SIGNAL—IN下降時 ，則該輸出信號SIGNAL一0UT1被延遲的DELTA3或DELTA4 所定義。當電源電壓Vss = 200mv時，該DELTA1被定義為從 輸入信號SIGNAL一IN的上升邊緣到輸出信號SIGNAL_OUT的 上升邊緣的延遲，當電晶體N1 2經歷電源電壓yss之噪音， 而且微弱地打開的時候，它是輸出信號SIGNAL_0UT1上的 延遲，當電壓電源Vss = 〇v時，DELTA2被定義為從輸入信號 SIGNAL—IN的上升邊緣到輸出信號SIGNAL_0UT1的上升邊緣No. v: Between the power supply and the power supply Vss, the drain of the buffer crystal N12 and the thunder pi9 are powered from the u system, which is suitable as an input of the reverse state 111 composed of J ΛτΛ common nodes, reverse The signal SIGNAL — OUT1 of the invention according to the invention π 1. °, a large-capacity channel controller CHC is connected in series with the parasitic capacitance of the input buffer transistor Nil, P11, and P12. Due to the ^ connection ratio, the large-capacity channel controller CHC is basically filled. The U-gate pole voltage of the P-channel metal-oxide-semiconductor bias node, and the voltage supply Vss of transistor Nil and transistor N12, the SIGNAL — OUT1 signal has a faster response time. + Figures 3A and 3B are defined time vector diagrams of the wave rise and fall in the input buffer receiver of the present invention. From these two figures, the input signal SIGNAL_IN, voltage power supply vss, and output signal SIGNAL —〇UT1 of the present invention can be known When the input signal SIGNAL —IN is defined as vih = vref + 350mv and V1L-VREF-350mv, the power supply voltage Vss is 200mv. When the input signal SIGNAL_IN increases, the output signal SIGNAL_0UT1 is defined by the delayed DELTA1 or DELTA2, and when the input signal SIGNAL_IN falls, the output signal SIGNAL_OUT1 is defined by the delayed DELTA3 or DELTA4. When the power supply voltage Vss = 200mv, the DELTA1 is defined as the delay from the rising edge of the input signal SIGNAL_IN to the rising edge of the output signal SIGNAL_OUT. When the transistor N1 2 experiences the noise of the power supply voltage yss and is weakly turned on , Which is the delay on the output signal SIGNAL_0UT1. When the voltage source Vss = 0v, DELTA2 is defined as the rising edge from the input signal SIGNAL_IN to the rising edge of the output signal SIGNAL_0UT1

1237444 五、發明說明（5) 的延遲’當電晶體N12沒有經歷電源電壓vss嚼音，而且 強烈地打開的時候，它是輸出信號SIGNAL — 0UT1上的延遲 ’而當電壓電源Vss = Ov時，DELTA3被定義為從SIGNAL—IN 的下降邊緣到輸出信號SIGNAL_OUT 1的下降邊緣的延遲， 當電晶體N1 2沒有經歷電源電壓vss噪音，而且微弱地被關 閉的時候，它是輸出信號SIGNAL一0UT1上的延遲。當電源1237444 V. Description of the invention (5) Delay 'When the transistor N12 has not experienced the power supply voltage vss chewing and is turned on strongly, it is a delay on the output signal SIGNAL — 0UT1' and when the voltage power supply Vss = Ov, DELTA3 is defined as the delay from the falling edge of SIGNAL_IN to the falling edge of the output signal SIGNAL_OUT 1. When transistor N1 2 does not experience the power supply voltage vss noise and is weakly turned off, it is on the output signal SIGNAL_OUT1 Delay. When the power

電壓Vss = 200mv時，DELTA4被定義為從輸入信號signal—IN 的下降邊緣到輸出信號SIGNAL-0UT1的下降邊緣的延遲， 當電晶體N1 2經歷電源電壓Vss噪音，而且激烈地被打開的 時候，它是輸出信號SIGNAL — 0UT1上的延遲；根據上述定 義，DELTA2或DELTA4係小於DELTA1或DELTA3，當輸入信號 SIGNAL—IN上升時，在DELTA1或DELTA2之間的波動提升 JITTER —RISE是不同的，而當輸入信號SIGNAL—IN下降的 日守候，在DELTA3或DELTA4之間的波動回落jitter FALL·是 不同的。在本發明中電容量通道控制器CHC主要係地利用 有電晶體P12和電晶體N12之裝置，以減少幾乎同時存在或 不存在地線噪音中之波動提升JITTER —RISE和波動回落 JITTER—FALL 。 第4A圖是本發明以電容量通道控制器CHC減少波動之 等效電路圖，由其參照第4B圖之以電容量通道控制器CHC 減少波動之工作示意圖，可知該電容量通道控制器CH(：以 大士量聯結比率加倍充電二PM〇s金屬氧化半導體的偏壓節 點化號VB11，來自於輸入緩衝接收器之電源電壓，這將 致輸出信號SIGNAL 0UT1作歌右 ^ ^ ^ -^ u l琥有一較快的回應時間。When the voltage Vss = 200mv, DELTA4 is defined as the delay from the falling edge of the input signal signal_IN to the falling edge of the output signal SIGNAL-0UT1. When the transistor N1 2 experiences the noise of the power supply voltage Vss and is turned on violently, It is the delay on the output signal SIGNAL — 0UT1. According to the above definition, DELTA2 or DELTA4 is smaller than DELTA1 or DELTA3. When the input signal SIGNAL_IN rises, the fluctuation between DELTA1 or DELTA2 is increased. JITTER —RISE is different, and When the input signal SIGNAL_IN drops and waits for the day, the fluctuation between DELTA3 or DELTA4 drops back jitter FALL · is different. In the present invention, the capacitor channel controller CHC mainly uses a device with a transistor P12 and a transistor N12 to reduce fluctuations in the presence or absence of ground wire noise at the same time. Improve JITTER-RISE and fluctuation fall-back JITTER-FALL. FIG. 4A is an equivalent circuit diagram of the present invention using the capacitance channel controller CHC to reduce fluctuations. Referring to FIG. 4B, the capacitance channel controller CHC is used to reduce fluctuations, and the capacitance channel controller CH (: Doubles the bias node number VB11 of the two PM0s metal oxide semiconductors at the connection ratio of tuas. It comes from the input buffer receiver's power supply voltage, which will cause the output signal SIGNAL 0UT1 to sing right ^ ^ ^-^ ul Faster response time.

第9頁 1237444 五、發明說明（6) 以上所述，僅係本發明的一較佳實施例，並非用來限 定本發明實施的範圍。即凡依本發明權利要求範圍所作的 均等變化與修飾，皆為本發明專利範圍所涵蓋。Page 9 1237444 V. Description of the invention (6) The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of implementation of the present invention. That is, all equivalent changes and modifications made according to the claims of the present invention are covered by the patent scope of the present invention.

第10頁 1237444 圖式簡單說明 【圖式簡單說明】 電路 定義 定義 動！ 動之 第1圖是依先前技術之一輸入緩衝接收器電路圖 第2圖是本發明之一輸入缓衝接收器較佳實施例 第3A圖是本發明之輸入緩衝接收器中波動提升的 間向量圖。 第3B圖是本發明之輸入緩衝接收器中波動回落的 間向量圖。 第4A圖是本發明以電容量通道控制器減少波 效電路圖。 第4B圖是本發明以電容量通道控制器CHC減少波 作示意圖。 【圖示中元件與編號對照說明】 100、101 ......緩衝器輸入部分 200、201 ......緩衝器輸出部分 N1、N2、N11、N12...... N通道金屬氧化半導體Page 10 1237444 Schematic description [Schematic description] Circuit definition Definition Move! Figure 1 is a circuit diagram of an input buffer receiver according to one of the prior art. Figure 2 is a preferred embodiment of an input buffer receiver of the present invention. Figure 3A is a vector of fluctuations in the input buffer receiver of the present invention. Illustration. Fig. 3B is a vector diagram of fluctuations in the input buffer receiver of the present invention. Fig. 4A is a circuit diagram of a capacitor channel controller for reducing wave efficiency in the present invention. Fig. 4B is a schematic diagram of reducing the wave by the capacitance channel controller CHC according to the present invention. [Comparison of components and numbers in the illustration] 100, 101 ... buffer input sections 200, 201 ... buffer output sections N1, N2, N11, N12 ... N Channel metal oxide semiconductor

Vss......電源電壓 PI、P2、PI 1、P12...... P通道金屬氧化半導體 VDD......供應電壓 · νΒ1、νΒ11 ......信號 11、111 ......反向器 CHC......電容量通道控制器Vss ... Power supply voltage PI, P2, PI 1, P12 ... P-channel metal oxide semiconductor VDD ... Supply voltage νΒ1, νΒ11 ... Signal 11, 111 ... inverter CHC ... capacity channel controller

Claims (1)

12374441237444 1 · 一種低輸入信號波動之輸入緩衝接收器，其至少包含· 一為了接收輸入信號SIGNAL—IN緩衝器輸入部分；· 一大電容，其在一個PM0S金屬氧化半導體的偏壓節 和一個電源電壓vss之間； 一為了產生輸出信號SIGNAL一0UT1緩衝器輸出部分。 2·如申請專利範圍第χ項所述的低輸入信號波動之輸入緩 衝接收器，其中該緩衝器輸入部分包含： 、一第一電晶體Nil ，具有一源極節點連接到電源電壓 源vss ’一閘極節點連接到一參考電壓Vref，和一汲極節 點連接到一信號％11 ; 一第二電晶體P11 ，具有一個汲極節點，連接到第一 電晶體Nil的一個汲極節點，及一閘極連接到信號Vbii ’一源極連接到一供應電壓VDD ; 一第二電晶體P1 2 ，具有一·個汲極節點，連接到下述 第四電日a體N1 2的汲極節點，及一閘極節點連接到信號 VB11 ’ 一源極節點連接到一供應電壓％ ; 一第四電晶體N12·，具有一源極節點連接到電源電壓 Vss ’ 閘極卽點連接到輸入信號S IG N A L — I N，及一連接 到緩衝器輸出部分的輸入汲極節點。 3·如申請專利範圍第2項所述的低輸入信號波動之輸入緩 衝接收器，其中該第一電晶體Nil和第四電晶體ni2皆係 NMOS金屬氧化半導體的電晶體，而第二電晶體pi 1和第 二電晶體P1 2都是PMOS金屬氧化半導體的電晶體。 4·如申請專利範圍第i項所述的低輸入信號波動之輸入緩1 · An input buffer receiver with low input signal fluctuation, which contains at least · a SIGNAL-IN buffer input section for receiving input signals; · a large capacitor, which is in a PM0S metal oxide semiconductor bias section and a power supply voltage vss; one in order to generate the output signal SIGNAL a OUT1 buffer output section. 2. The input buffer receiver with low input signal fluctuation as described in item χ of the patent application scope, wherein the buffer input part includes: a first transistor Nil having a source node connected to the power supply voltage source vss' A gate node connected to a reference voltage Vref, and a drain node connected to a signal% 11; a second transistor P11 having a drain node connected to a drain node of the first transistor Nil, and A gate is connected to the signal Vbii 'a source is connected to a supply voltage VDD; a second transistor P1 2 has a drain node connected to the drain node of the body N1 2 of the fourth electric circuit described below And a gate node is connected to the signal VB11 'a source node is connected to a supply voltage%; a fourth transistor N12 · has a source node connected to the power supply voltage Vss' and a gate point is connected to the input signal S IG NAL — IN, and an input drain node connected to the output section of the buffer. 3. The input buffer receiver with low input signal fluctuation as described in item 2 of the scope of patent application, wherein the first transistor Nil and the fourth transistor ni2 are both NMOS metal oxide semiconductor transistors, and the second transistor Both pi 1 and the second transistor P1 2 are transistors of a PMOS metal oxide semiconductor. 4. The input buffer with low input signal fluctuation as described in item i of the patent application 1237444 六、申請專利範圍 衝接收器，其中該大電容在緩衝器輸入部分的第一電晶 體Nil和第四電晶體N12的源極，以及緩衝器輸入部分$ 第二電晶體P11的閘極之間被連接。 5 ·=申明專利範圍第1項所述的低輸入信號波動之輸入緩 衝接收器’其中該第二電晶體？n的閘極被連接到其没 才虽° 6 · ^申明專利範圍第1項所述的低輸入信號波動之輸入緩 衝接收器’其中該第二電晶體？11的閘極被連接到第一 電晶體N11的·沒極。 7 ·如申請專利範圍第1項所述的低輸入信號波動之輸入緩 衝接收器，其中該第二電晶體p丨1的閘極被連接到第三 電晶體P12的閘極。 8·如申請專利範圍第i項所述的低輸入信號波動之輸入緩 衝接收器，其中該緩衝器輸出部分包含··一連接到第三 電晶體P1 2汲極和第四電晶體N1 2汲極的反向器π 1。 9 ·如申請專利範圍第1項所述的低輸入信號波動之輸入緩 衝接收器，其中該第三電晶體p丨2和第四電晶體N丨2幾乎 同時的被激發。 10·如申請專利範圍第1項所述的低輸入信號波動之輸入 缓衝接收器’其中其包括一個大容量聯結比率，加倍 控制輸入緩衝接收器的PMOS金屬氧化半導體的偏壓節 點，到輸入缓衝接收器的電壓電源Vss。 11·如申請專利範圍第1項所述的低輸入信號波動之輸人 緩衝接收器，其中該大電容包括一大容量聯結比率，1237444 6. The scope of the patent application is for the receiver, where the large capacitor is at the source of the first transistor Nil and the fourth transistor N12 of the buffer input section, and at the gate of the buffer input section of the second transistor P11. Were connected. 5 · = Declares the input buffer receiver with low input signal fluctuation as described in item 1 of the patent scope. 'Where is the second transistor? The gate of n is connected to it. Although the second transistor is the input buffer receiver with low input signal fluctuation as described in item 1 of the claimed patent range? The gate of 11 is connected to the terminal of the first transistor N11. 7. The input buffer receiver with low input signal fluctuation as described in item 1 of the patent application range, wherein the gate of the second transistor p1 is connected to the gate of the third transistor P12. 8. The input buffer receiver with low input signal fluctuation as described in item i of the patent application scope, wherein the buffer output part includes a connection to the third transistor P1 2 drain and the fourth transistor N1 2 drain Pole inverter π 1. 9 · The input buffer receiver with low input signal fluctuation as described in item 1 of the patent application range, wherein the third transistor p 丨 2 and the fourth transistor N 丨 2 are excited almost simultaneously. 10. The input buffer receiver with low input signal fluctuation as described in item 1 of the patent application scope, which includes a large-capacity connection ratio, which doubles the bias node of the PMOS metal oxide semiconductor that controls the input buffer receiver to the input Buffer receiver voltage supply Vss. 11. The input buffer receiver with low input signal fluctuation as described in item 1 of the scope of patent application, wherein the large capacitor includes a large capacity connection ratio, 第13頁 1237444Page 13 1237444 第14頁Page 14