TWI236748B - Flip chip on lead package and process thereof - Google Patents
Flip chip on lead package and process thereof Download PDFInfo
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- TWI236748B TWI236748B TW093110064A TW93110064A TWI236748B TW I236748 B TWI236748 B TW I236748B TW 093110064 A TW093110064 A TW 093110064A TW 93110064 A TW93110064 A TW 93110064A TW I236748 B TWI236748 B TW I236748B
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- chip
- frame
- nail
- flip
- bumps
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- 238000000034 method Methods 0.000 title claims description 24
- 229910000679 solder Inorganic materials 0.000 claims description 25
- 239000000565 sealant Substances 0.000 claims description 19
- 238000012858 packaging process Methods 0.000 claims description 13
- 238000005476 soldering Methods 0.000 claims description 8
- 239000002313 adhesive film Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 238000005553 drilling Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000005538 encapsulation Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 39
- 238000010586 diagram Methods 0.000 description 9
- 238000004806 packaging method and process Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 239000003292 glue Substances 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 238000003466 welding Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000979 O alloy Inorganic materials 0.000 description 1
- WGCOQYDRMPFAMN-ZDUSSCGKSA-N [(3S)-3-[4-(aminomethyl)-6-(trifluoromethyl)pyridin-2-yl]oxypiperidin-1-yl]-pyrimidin-5-ylmethanone Chemical compound NCC1=CC(=NC(=C1)C(F)(F)F)O[C@@H]1CN(CCC1)C(=O)C=1C=NC=NC=1 WGCOQYDRMPFAMN-ZDUSSCGKSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical compound [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000009916 joint effect Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
1236748 五、發明說明（1) 發明所屬之技術領域 本發明是有關於一種晶片 是有關於一種可有效防止凸塊 覆晶封裝結構及其製程。 先前技術 半導體工業是近年來發展 一，隨著電子技術的日新月異 世，使得更人性化、功能更佳 新，並朝向輕、薄、短、小的 程當中，導線架（lead frame 之一’而應用導線架作為承載 frame type package )更涵蓋 Hole, PTH)以及表面黏著型 Technology，SMT)等兩大類 封裝結構及其製程，且特別 接合時之坍塌問題的釘架型 速度最快之高科技工業之 ，高科技電子產業的相繼問 的電子產品不斷地推陳出 趨勢設計。目前在半導體製 )是經常使用的構裝承載器 器之釘架型封裝結構（lead 引腳***型（Pin Through (Surface Mount ，其中較常見的例如有雙邊1236748 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a wafer and a chip-on-chip packaging structure and a process for effectively preventing bumps. The previous technology semiconductor industry has been developed in recent years. With the rapid development of electronic technology, it has become more humane and has better functions. It is also leading to light, thin, short, and small processes. The lead frame is used as the load-bearing frame type package. It also covers the two major types of packaging structures such as Hole, PTH) and Surface Mount Technology (SMT) and their processes, and it is the fastest high-tech industry in the nail rack type when it has the problem of collapse during bonding. In short, the high-tech electronics industry has successively asked about the trending design of electronic products. Currently made in semiconductors) is a pin-type package structure (lead through (Surface Mount), which is often used to form a carrier.
引腳型封裝結構（Dual In-Line Package, DIP 在 曰曰Lead type package structure (Dual In-Line Package, DIP in
片上搭載導線架（Lead On Chip Package， L0C)之封裝 結構，以及四方扁平封裝結構（Quad Flat Package, QFP )等。 請參考圖1 ，其繪示習知之一種四方扁平封裝結構的 局部剖面圖。四方扁平封裝結構1 0 0包括一晶片1 1 0、一晶 片座1 2 0、多個導線1 3 0、多個接腳1 4 0以及一封膠1 5 0。其 中，晶片1 1 0具有一主動表面1 1 2以及對應之一背面1 1 4， 而晶片1 1 0之主動表面1 1 2具有多個銲墊1 1 6 ，且晶片1 1 0之 背面1 1 4例如藉由一銀膠（s i 1 v e r e p〇X y ) 1 1 8而固定於晶The chip is equipped with a lead frame (L0C) package structure, and a quad flat package (QFP) structure. Please refer to FIG. 1, which illustrates a partial cross-sectional view of a conventional rectangular flat package structure. The square flat package structure 100 includes a chip 110, a chip holder 120, a plurality of wires 130, a plurality of pins 140, and a glue 150. Among them, the wafer 1 1 0 has an active surface 1 12 and a corresponding back surface 1 1 4, and the active surface 1 1 2 of the wafer 1 10 has a plurality of pads 1 1 6, and the back surface 1 of the wafer 1 1 0 1 4 is fixed to the crystal by, for example, a silver glue (si 1 verep〇X y) 1 1 8
12633twf.ptd 第6頁 1236748 五、發明說明（2) 片座1 2 0之上表面。此外，晶片1 1 0之銲墊1 1 6則藉由導線 1 3 0而電性連接至其所對應之接腳1 4 0 ，而封膠1 5 0係包覆 晶片1 1 0、導線1 3 0、晶片座1 2 0之上表面以及接腳1 4 0之上 表面，用以保護晶片1 1 0以及導線1 3 0 。 值得注意的是，不論是上述之四方扁平封裝結構或其 他以打線接合之釘架型封裝結構，其因為藉由導線電性連 接晶片與接腳，而通常具有導線本身之電性不佳，以及在 填充封膠時可能發生導線偏移（w i r e s w e e p )等問題。因 此，習知為解決上述問題，更提出以覆晶方式接合晶片與 接腳之一種釘架型覆晶（Flip Chip on Lead, FOL)封裝 結構。 請參考圖2 A及2 B，其分別繪示習知之一種覆晶型態之 四方扁平封裝結構的局部剖面圖。如圖2 A所示，覆晶型態 之四方扁平封裝結構200包括一晶片210、多個凸塊2 3 0、 多個接腳240以及一封膠250。其中，晶片210之主動表面 2 1 2具有多個銲墊2 1 6，且晶片2 1 0之銲墊2 1 6係藉由凸塊 2 3 0而電性與機械性連接至其所對應之接腳2 4 0，而封膠 2 5 0係包覆晶片2 1 0、凸塊2 3 0、以及接腳2 4 0之上表面，用 以保護晶片2 1 0以及凸塊2 3 0。然而，由於接腳2 4 0之材質 為銅，而凸塊2 3 0之材質多為錫鉛合金，因此當凸塊2 3 0被 加熱為融熔狀態而與接腳2 4 0接合時，便可能因凸塊2 3 0在 接腳2 4 0上溢流而導致姆塌（c ο 1 1 a p s e )的現象，使得晶 片2 1 0無法有效地與接腳2 4 0接合，且晶片2 1 0與接腳2 4 0之 間亦無法維持固定之間隙。12633twf.ptd Page 6 1236748 V. Description of the invention (2) The upper surface of the film holder 1 2 0. In addition, the solder pads 1 1 6 of the chip 1 10 are electrically connected to the corresponding pins 1 4 0 through the wires 1 3 0, and the sealing compound 1 50 is the chip 1 1 0 and the wire 1 30. The upper surface of the chip holder 120 and the upper surface of the pins 140 are used to protect the chip 110 and the wires 130. It is worth noting that, whether it is the above-mentioned quadrangular flat package structure or other nail-frame-type package structures that are connected by wire bonding, it usually has poor electrical properties of the wires themselves because they are electrically connected to the chip and the pins by wires, and Problems such as wiresweep may occur when filling the sealant. Therefore, in order to solve the above problems, a flip-chip-on-chip (FOL) package structure in which a chip and a pin are bonded in a flip-chip manner has been proposed. Please refer to Figs. 2A and 2B, which respectively show partial cross-sectional views of a conventional flip-chip flat package structure of a flip-chip type. As shown in FIG. 2A, the flip-chip tetragonal flat package structure 200 includes a chip 210, a plurality of bumps 230, a plurality of pins 240, and a piece of glue 250. Among them, the active surface 2 1 2 of the chip 210 has a plurality of bonding pads 2 1 6, and the bonding pads 2 1 6 of the chip 2 10 are electrically and mechanically connected to the corresponding ones through the bumps 2 3 0. The pins 2 4 0, and the sealant 2 50 cover the upper surface of the chip 2 1 0, the bumps 2 3 0, and the pins 2 4 0 to protect the chips 2 1 0 and the bumps 2 3 0. However, since the material of the pin 2 40 is copper, and the material of the bump 2 3 0 is mostly a tin-lead alloy, when the bump 2 3 0 is heated to a molten state and is bonded to the pin 2 4 0, Then, the phenomenon that the bump 2 3 0 overflows on the pin 2 4 0 may cause the phenomenon of collapse (c ο 1 1 apse), so that the chip 2 1 0 cannot effectively join the pin 2 4 0, and the chip 2 A fixed gap cannot be maintained between 1 0 and pins 2 4 0.
12633 twf.ptd 第7頁 1236748 五、發明說明（3) 發明内容 因此， 結構，其中 防止凸塊接 接合效果。 本發明 程，其係於 解決凸塊接 率。 基於上 構，其例如 膠。其中導 貫孔，而晶 以及多個銲 上。此夕卜， 對應之貫孔 凸塊。 依照本 裝結構例如 與接腳之間 局告P表面 。 成之族群其 依照本 裝結構例如 本發明的目的就是在提供一種釘架型覆晶封裝 導線架之接腳上具有可容納凸塊之貫孔，用以 合時之坍塌的情形，進而改善晶片與導線架之 的另一目的是在提供一種釘架型覆晶封裝製 導線架之接腳上形成可容納凸塊之貫孔，用以 合時之坍塌的問題，進而提高封裝製程之良 述目的，本發明提出一種釘架型覆晶封裝結 包括一導線架、一晶片、多數個凸塊以及一封 線架具有多個接腳，其中每一接腳具有至少一 片係配置於導線架上，且晶片具有一主動表面 墊，其中銲墊係對應於貫孔而配置於主動表面 凸塊係分別配置於銲墊與接腳之間並部分嵌入 内，而封膠係配置於導線架上並包覆晶片以及 發明的較佳實施例所述，上述之釘架型覆晶封 更包括一沾附層，此沾附層係對應配置於凸塊 ，並覆蓋貫孔之内壁以及接腳之鄰接於貫孔的 此外，沾附層之材質例如係選自於錄、金所組 中之一。 發明的較佳實施例所述，上述之釘架型覆晶封 更包括一銲罩層，此銲罩層係覆蓋接腳，並暴12633 twf.ptd Page 7 1236748 V. Description of the invention (3) Summary of the invention Therefore, the structure in which the bumps are prevented from joining the joint effect. The invention is to solve the bump rate. Based on the structure, it is for example gum. Among them are through-holes, and crystals and multiple are soldered. In the future, the corresponding via bumps. According to this assembly structure, for example, the P surface is connected between the pins. According to the present structure, the purpose of the Chengzu group is to provide a nail-frame flip-chip package lead frame with pins that can accommodate bumps in the pins for timely collapse, thereby improving the chip. Another purpose of the lead frame is to provide a pin-hole type flip-chip packaged lead frame to form a through hole capable of accommodating a bump, so as to solve the problem of timely collapse, thereby improving the good description of the packaging process. Aim, the present invention provides a nail-frame flip-chip package junction including a lead frame, a chip, a plurality of bumps, and a wire frame with a plurality of pins, wherein each pin has at least one piece arranged on the lead frame. And the chip has an active surface pad, wherein the pads are arranged corresponding to the through holes and the active surface bumps are respectively arranged between the pads and the pins and partially embedded therein, and the sealant is arranged on the lead frame and According to the preferred embodiment of the coated wafer and the invention, the above-mentioned nail-frame flip-chip package further includes an adhesion layer, which is disposed correspondingly to the bump and covers the inner wall of the through hole and the abutment of the pin. to Further holes, buildup of the material layer is selected from, for example, to record, one of the gold group. According to a preferred embodiment of the present invention, the aforementioned nail-frame type flip-chip package further includes a solder mask layer, which covers the pins and exposes
12633 twf.ptd 第8頁 1236748 五、發明說明（4) 露出貫孔以及接腳之鄰 值得一提的是，本 一四方爲平封裝結構’ 片的一側，並暴露出貫 外，上述之接腳亦可切 平無接腳（Quad Flat 承上述，此四方扁 印刷電路板接合，其中 離晶片之另一側，並具 接點係藉由位於貫孔内 接。此外，凸塊與印刷 層，以使凸塊與接點相 基於上述之釘架型 釘架型覆晶封裝製程。 其中導線架例如具有多 面以及多個銲墊，且每 於接腳之對應於凸塊的 孔之方法例如包括機械 然後，結合晶片與導線 後，形成一封膠，並使 依照本發明的較佳 程，其中在結合晶片與 膜（t a p e )於導線架之 片與導線架之後，更例 接於貫孔 發明之釘 其中封膠 孔以及凸 齊於封膠 No- 1 ead， 的局 架型 係位 塊於 之側 QFN 型態 板例 貫孔 而與 接點 平無接腳 印刷電路 有對應於 之凸塊， 電路板之 互橋接。 覆晶封裝結構， 首先，提供一導 部表 覆晶 於導 導線 緣， )型 之封 如係 之多 晶片 間更 面。 封裝 線架 架之 而形 態之 裝結 配置 個接 上之 例如 結構更 之配置 另 成 側 四 本發明 線架以 個接腳，而晶片例如具 一銲塾上係形成有一凸 位置分別 鑽孔、雷 架，並令 封膠包覆 實施例所 導線架之 退離晶片 如包括移 形成一 射鑽孔 凸塊對 晶片以 述之釘 前，更 的表面 除此膠 貫孔， 以及化 應嵌入 及凸塊 架型覆 例如包 。此外 膜0 封裝結 構更可 於導線 點，且 銲墊電 可S己置 更提出 及一晶 有一主 塊。接 其中形 學I虫刻 貫孔内 可為 有晶 。此 方扁 構。 與一 架遠 這些 性連 錫膏 一種 片， 動表 著， 成貫 等。 1=7 。 取 晶封裝製 括貼覆一膠 ，在結合晶12633 twf.ptd Page 8 1236748 V. Description of the invention (4) Exposing the vias and the neighbors of the pins It is worth mentioning that this box is a flat package structure's side and exposes the outer side. The pins can also be cut flat without the pins (Quad Flat supports the above, this square flat printed circuit board is bonded, which is on the other side of the chip, and has contacts that are connected through the through holes. In addition, the bumps and Print the layer so that the bumps and contacts are based on the above-mentioned nail-frame-type nail-frame flip-chip packaging process. The lead frame, for example, has multiple sides and multiple pads, and each pin corresponds to the hole of the bump. The method includes, for example, mechanically combining a wafer and a wire to form an adhesive, and performing a preferred process according to the present invention, wherein after combining the wafer and the tape to the sheet of the lead frame and the lead frame, it is more preferably connected to The nail of the through-hole invention includes a sealing hole and a local frame type block protruding to the sealing No-1 ead. The side of the QFN type plate is a through hole, which corresponds to the contact level without a pin printed circuit. Bumps, bridges between circuit boards. Chips package, first, a sheet guide portion to the guide wire flip-chip edge) of the type such as the sealing surface between lines much more wafer. The package of the wire rack is configured with a knotting configuration, such as a structural configuration, and another side. The wire rack of the present invention has pins, and the chip has a convex position formed on the welding pad, respectively. If the encapsulation covers the lead wafer of the lead frame in the embodiment, if the ejection wafer includes moving a drilled bump into the wafer to nail the wafer, the surface should be cut in addition to the glue through hole, and A bump-frame type cover such as a bag. In addition, the film 0 package structure can be more at the wire point, and the pads can be set up and there is a main block. Following the morphology I, the through hole can be crystalline. This square is flat. A piece of solder paste with a distant shelf, moving, showing, etc. 1 = 7. Take a crystal package, including sticking a glue,
12633twf.ptd 第9頁 1236748 五、發明說明（5) 依照本 程，其中在 依照本 程 預 程， 以及 程 銲 之鄰 程係 使凸 表面 發生 合效 顯易 說明 實施 其中在 銲層（ 依照本 其中在 接腳之 依照本 其中在 罩層， 接於貫 基於上 於接腳 塊於融内，以 坍塌的 果’並 為讓本 懂，下 如下。 方式 發明的 結合晶 發明的 結合晶 p r e - s 〇 發明的 結合晶 鄰接於 發明的 結合晶 此銲罩 孔的局 述，本 之對應 熔狀態 避免在 現象。 且提高 發明之 文特舉 較佳實 片與導 較佳實 片與導 1 d e r ) 較佳實 片與導 貫？L的 較佳實 片與導 層係覆 部表面 發明之 於凸塊 時可集 接合晶 如疢匕一 封裝製 上述和 較佳實 釘架 包括 釘架 更包 層係 釘架 更包 成一 施例所述之 線架時，更 施例所述之 線架之前， ，且此預銲 施例所述之 線架之前， 局部表面形 施例所述之釘架 線架之前，更包 蓋接腳，並暴露 型覆晶 回鲜凸 型覆晶 括於接 配置於 型覆晶 括於貫 沾附層 型覆晶 括於接 出貫孔 釘架型覆晶封裝結構及 的位置上形成貫孔，其 中於貫孔及其周圍之接 片與導線架時，凸塊於 來，將可改善晶片與導 程之良率。 其他目的、特徵、和優 施例，並配合所附圖式 封裝製 塊。 封裝製 腳上形成 貫孔上。 封裝製 孔之内壁 〇 封裝製 腳上形成 以及接腳 其封裝製 目的在於 腳的局部 接腳表面 線架之接 點能更明 ，作詳細 第一實施例 請依序參考圖3A〜3D，其依序繪示本發明之第一實施12633twf.ptd Page 9 1236748 V. Description of the invention (5) According to this process, which is in accordance with this process, and the adjacent process of welding is to make the convex surface synergistic, it is easy to explain the implementation of the welding layer (according to this In accordance with the present, the pin is in the cover layer, connected to the pin block in the melt, to collapse the fruit, and for the sake of understanding, the following is the method of the combined crystal of the invention. The combined crystal of the invention is pre-s. The invention of the bonding crystal is adjacent to the invention of the bonding mask. The corresponding molten state avoids the phenomenon of the molten state. And the invention of the invention is better. Jiashi film and guide? The better solid piece of L and the surface of the guide layer system are invented. The bumps can be assembled together when the bumps are assembled. The above and preferred nail holders include nail holders and more clad nail holders. In the case of the wire rack, before the wire rack described in this embodiment, and before the wire rack described in this pre-welding example, before the nail rack wire frame described in the partial surface shape, the pins are further covered, The exposed flip-chip flip-convex flip-chip is placed in a connection configuration. The flip-chip is attached to a through-attachment layer. The flip-chip is connected to a through-hole nail-frame flip-chip package structure and a through-hole is formed. When the vias and the surrounding tabs and lead frames, the bumps come in, will improve the yield of the chip and the lead. Other purposes, features, and preferred embodiments, in conjunction with the accompanying drawings, encapsulate the blocks. Through holes are formed on the package feet. The inner wall of the package hole is formed on the package foot and the purpose of the package is to make the contact of the wire surface of the partial pin surface of the pin clearer. For a detailed first embodiment, please refer to FIGS. 3A to 3D in sequence. Sequentially shows the first implementation of the present invention
12633twf.ptd 第10頁 1236748 五、發明說明（6) 例之一種釘架型覆晶封裝製程的示意圖。 首先，如圖3 A所示，提供一導線架3 1 0以及一晶片 3 2 0 ，其中導線架3 1 0例如具有多個接腳3 1 2，其中每一接 腳3 1 2係具有一上表面3 1 2 a與對應之一下表面3 1 2 b，而晶 片320之主動表面322上例如具有多個銲墊324，且每一銲 墊3 2 4上例如形成有一凸塊3 3 0。值得一提的是，本發明之 凸塊3 3 0可為圖中所繪示之柱狀凸塊，或再經成球步驟而 形成之球狀凸塊。 接著，如圖3 B所示，藉由例如機械鑽孔、雷射鑽孔以 及化學蝕刻等方式，而於接腳3 1 2之對應於凸塊3 3 0的位置 分別形成一貫穿接腳312之上表面312a與下表面312b的貫 孔 3 1 4 〇 然後，如圖3 C所示，結合晶片3 2 0與導線架3 1 0。其 中，例如先使凸塊3 3 0對應嵌入貫孔3 1 4内，並對凸塊3 3 0 進行回銲，以使晶片3 2 0藉由凸塊3 3 0而與接腳3 1 2緊密接 合。 最後，如圖3 D所示，於導線架3 1 0上形成一封膠3 4 0， 並完成本發明之釘架型覆晶封裝結構3 0 0。其中，封膠3 4 0 係包覆晶片3 2 0、凸塊3 3 0以及部分之接腳3 1 2，以防止外 界之濕氣或雜塵進入釘架型覆晶封裝結構3 0 0内，進而維 持晶片3 2 0之正常運作。 值得一提的是，在上述之本發明之釘架型覆晶封裝製 程中，其中在結合晶片與導線架（如圖3 C所示）之前，更 可如圖4所示，先行貼覆一膠膜3 5 0於導線架3 1 0之背面 ipillll12633twf.ptd Page 10 1236748 V. Description of the invention (6) An example of a nail-frame flip-chip packaging process. First, as shown in FIG. 3A, a lead frame 3 1 0 and a chip 3 2 0 are provided. The lead frame 3 1 0 has, for example, a plurality of pins 3 1 2, and each of the pins 3 1 2 has a The upper surface 3 1 2 a and the corresponding one of the lower surfaces 3 1 2 b. The active surface 322 of the wafer 320 has, for example, a plurality of solder pads 324, and each solder pad 3 2 4 has a bump 3 3 0 formed thereon, for example. It is worth mentioning that the bump 330 of the present invention can be a columnar bump as shown in the figure, or a spherical bump formed by a ball forming step. Next, as shown in FIG. 3B, through-hole pins 312 are respectively formed at positions corresponding to the bumps 3 3 0 of the pins 3 1 2 by mechanical drilling, laser drilling, and chemical etching. The through holes 3 1 4 of the upper surface 312a and the lower surface 312b are then combined with the wafer 3 2 0 and the lead frame 3 1 0 as shown in FIG. 3C. For example, firstly, the bump 3 3 0 is correspondingly embedded in the through hole 3 1 4, and the bump 3 3 0 is re-soldered, so that the wafer 3 2 0 and the pin 3 1 2 pass through the bump 3 3 0. Tightly joined. Finally, as shown in FIG. 3D, an adhesive 3 4 0 is formed on the lead frame 3 10 and the nail frame type flip-chip package structure 3 0 0 of the present invention is completed. Among them, the sealant 3 4 0 covers the wafer 3 2 0, the bump 3 3 0, and some of the pins 3 1 2 to prevent external moisture or dust from entering the nail-frame flip-chip packaging structure 3 0 0. In order to maintain the normal operation of the chip 3 2 0. It is worth mentioning that, in the above nail frame type flip chip packaging process of the present invention, before the chip and the lead frame are combined (as shown in FIG. 3C), as shown in FIG. 4, a first Adhesive film 3 5 0 on the back of the lead frame 3 1 0
12633 twf.ptd 第11頁 1236748 五、發明說明（7) (即接腳312之下表面312b)，以防止凸塊330在嵌入貫孔 3 1 4時，自貫孔3 1 4的另一側掉落。此夕卜，若所進行者為一 Q F P製程，則在回銲凸塊3 3 0之後，便可將膠膜3 5 0自導線 架3 1 0上移除，以進行後續之封膠的動作◦另外，若所進 行者為一 Q F N製程，則可待封膠的動作完成之後，再將膠 膜3 5 0自導線架3 1 0上移除。 此外，本發明之釘架型覆晶封裝製程在結合晶片3 2 0 與導線架3 1 0之前，更可如圖5所示，於接腳3 1 2之貫孔3 1 4 上預先形成一預鮮層（pre-solder) 360 ，以助於晶片320 與導線架3 1 0之接合，而此預銲層3 6 0在回銲後將與凸塊 330 —起融入貫孔中。 承上述，本發明之釘架型覆晶封裝結構3 0 0係於接腳 3 1 2之對應於凸塊3 3 0的位置上配置有貫孔3 1 4，藉由此貫 孔可以使得凸塊3 3 0在回銲成為融熔狀態後，得以集中於 貫孔3 1 4及其周圍之區域内，而不至於發生坍塌之問題。 第二實施例 雖然上述之本發明的釘架型覆晶封裝結構已能有效防 止凸塊之坍塌，但為使凸塊在接合時更集中於貫孔其及周 邊區域，本發明更提出下列之釘架型覆晶封裝結構。 請參考圖6，其繪示本發明之第二實施例之第一種釘 架型覆晶封裝結構的示意圖。其中，釘架型覆晶封裝結構 4 0 0之導線架4 1 0上例如可藉由電鍍形成一沾附層4 5 0 ，其 材質例如可為鎳、金或其他適於沾附凸塊4 3 0之合金，且 沾附層4 5 0係覆蓋貫孔4 1 4之内壁4 1 4 a以及接腳4 1 2之鄰接12633 twf.ptd Page 11 1236748 V. Description of the invention (7) (ie, the lower surface 312b of the pin 312) to prevent the bump 330 from being inserted into the through hole 3 1 4 on the other side of the through hole 3 1 4 Drop. In addition, if the process is a QFP process, after the solder bumps 3 3 0, the adhesive film 3 5 0 can be removed from the lead frame 3 1 0 for subsequent sealing operations. ◦ In addition, if the process is a QFN process, after the sealing operation is completed, the adhesive film 3 50 can be removed from the lead frame 3 1 0. In addition, in the nail-frame flip-chip packaging process of the present invention, before the wafer 3 2 0 and the lead frame 3 1 0 are combined, as shown in FIG. 5, a through hole 3 1 4 of the pin 3 1 2 is formed in advance. A pre-solder layer 360 is used to facilitate the bonding of the wafer 320 to the lead frame 3 10, and this pre-solder layer 3 60 will be integrated into the through hole with the bump 330 after re-soldering. According to the above, the nail frame type flip-chip packaging structure 3 0 0 of the present invention is provided with a through hole 3 1 4 at a position corresponding to the bump 3 3 0 of the pin 3 1 2. By this, the through hole can make the convex After the block 3 3 0 is reflowed into a molten state, it can be concentrated in the through hole 3 1 4 and the surrounding area without causing the problem of collapse. Second Embodiment Although the above-mentioned nail-frame flip-chip package structure of the present invention has been able to effectively prevent the collapse of the bumps, in order to make the bumps more concentrated in the through-holes and their surrounding areas when joining, the present invention further proposes the following Nail-frame flip-chip package structure. Please refer to FIG. 6, which illustrates a schematic diagram of a first pin-frame flip-chip package structure according to a second embodiment of the present invention. The lead frame 4 1 0 of the nail-frame flip-chip packaging structure 4 0 0 can be formed with an adhesion layer 4 5 0 by electroplating, for example, the material can be nickel, gold, or other suitable for attaching the bump 4. 3 0 alloy, and the adhesion layer 4 5 0 covers the inner wall 4 1 4 a of the through hole 4 1 4 and the abutment of the pin 4 1 2
12633twf.ptd 第12頁 1236748 五、發明說明（8) 於貫孔4 1 4的局部表面，使得凸塊4 3 0在回銲時可沾附並侷 限於此沾附層4 5 0上，以增進凸塊4 3 0與貫孔4 1 4的接著效 果，並可控制凸塊4 3 0回銲後之高度。 請參考圖7，其繪示本發明之第二實施例之第二種釘 架型覆晶封裝結構的示意圖。其中’銲罩層5 5 0係配置於 接腳512之上表面512a，並暴露出貫孔514以及接腳512之 鄰接於貫孔5 1 4的局部上表面5 1 2 a。藉由此銲罩層5 5 0可有 效隔絕凸塊5 3 0與接腳5 1 2之上表面5 1 2 a，進而更加確保凸 塊5 3 0不會因溢流至接腳5 1 2上而導致坍塌。 此外，在合理的範圍内，本發明之釘架型覆晶封裝結 構的導線架上更可同時配置有上述之沾附層及銲罩層，而 其相關元件及配置因與上述實施例類似，在此不再重複贅 述。 第三實施例 請參考圖8，其繪示應用本發明之一種四方扁平無接 腳（Q u a d F 1 a t N 〇 - 1 e a d， Q F N )型態之覆晶封裝結構（以 下簡稱QFN覆晶封裝結構）的示意圖。QFN覆晶封裝結構 6 0 0例如包括由多個接腳6 1 2所構成之一導線架6 1 0，其中 每一接腳6 1 2係具有一上表面6 1 2 a與對應之一下表面 6 1 2 b ，而晶片6 2 0係配置於導線架6 1 0上。此外，晶片6 2 0 之主動表面6 2 2上的多個凸塊6 3 0係對應嵌入接腳6 1 2之貫 孔6 1 4内，以使晶片6 2 0透過凸塊6 3 0而與接腳6 1 2電性連 接。另外，封膠6 4 0係包覆晶片6 2 0、凸塊6 3 0以及接腳6 1 2 之上表面612a，而接腳612之下表面612b係暴露於封膠64012633twf.ptd Page 12 1236748 V. Description of the invention (8) The local surface of the through hole 4 1 4 makes the bump 4 3 0 adhere to and is limited to the adhesion layer 4 5 0 during reflow. Improve the bonding effect between the bump 4 3 0 and the through hole 4 1 4, and control the height of the bump 4 30 after re-soldering. Please refer to FIG. 7, which illustrates a schematic diagram of a second pin-frame flip-chip package structure according to a second embodiment of the present invention. The 'solder mask layer 5 50' is disposed on the upper surface 512a of the pin 512, and exposes the through hole 514 and a partial upper surface 5 1 2 a of the pin 512 adjacent to the through hole 5 1 4. With this solder mask layer 5 5 0, the bump 5 3 0 can be effectively isolated from the upper surface 5 1 2 a of the pin 5 1 2 to further ensure that the bump 5 3 0 will not overflow to the pin 5 1 2 Collapsed. In addition, within a reasonable range, the lead frame of the nail-frame flip-chip package structure of the present invention can be further provided with the above-mentioned adhesion layer and solder mask layer, and its related components and configurations are similar to the above embodiments, I will not repeat them here. For a third embodiment, please refer to FIG. 8, which illustrates a flip-chip package structure (hereinafter referred to as a QFN flip-chip package) of a square flat no-pin (Q uad F 1 at N 〇-1 ead, QFN) type to which the present invention is applied. Structure). The QFN flip-chip package structure 6 0 0 includes, for example, a lead frame 6 1 0 composed of a plurality of pins 6 1 2, wherein each pin 6 1 2 has an upper surface 6 1 2 a and a corresponding lower surface. 6 1 2 b, and the wafer 6 2 0 is arranged on the lead frame 6 1 0. In addition, the plurality of bumps 6 3 0 on the active surface 6 2 2 of the wafer 6 2 0 are correspondingly embedded in the through holes 6 1 4 of the pins 6 1 2 so that the wafer 6 2 0 passes through the bumps 6 3 0 and It is electrically connected to pin 6 1 2. In addition, the sealant 6 4 0 covers the upper surface 612 a of the wafer 6 2 0, the bump 6 3 0 and the pin 6 1 2, and the lower surface 612 b of the pin 612 is exposed to the sealant 640.
12633 twf. pui 第13頁 1236748 五、發明說明（9) 之外，且接腳6 1 2之外端係切齊於封膠6 4 0之四邊的側緣， 以作為Q F N覆晶封裝結構6 0 0對外之I / 0接點。 請再參考圖8，Q F N覆晶封裝結構6 0 0係配置於一印刷 電路板6 5 0上，其中由於晶片6 2 0上之凸塊6 3 0可藉由貫孔 6 1 4暴露於導線架6 1 0下方，因此在印刷電路板6 5 0上之接 點652形成錫膏（solder paste) 654之後，便可使印刷電 路板6 5 0之接點6 5 2藉由錫膏6 5 4，而與晶片6 2 0上之凸塊 6 3 0相互接合。基於上述，本發明之Q F N覆晶封裝結構6 0 0 不需於導線架6 1 0與印刷電路板6 5 0之間形成銲球（s ο 1 d e r ball)，且由於晶片6 2 0與印刷電路板6 5 0之間係直接透過 凸塊6 3 0進行橋接，因此可具有較佳之電性表現 (electrically performance )，並可達到減少製程步 驟，增加生產效率之目的。 第四實施例 除上述之單晶片的QF N覆晶封裝結構之外，本發明亦 適用於堆疊式（s t a c k e d )的雙晶片封裝結構。請同時參 考圖9 A及9 B，其分別繪示本發明之第一種堆疊式的釘架型 覆晶封裝結構的剖面圖，及此釘架型覆晶封裝結構之導線 架的俯視圖。釘架型覆晶封裝結構7 0 0例如包括一導線架 710 ，而導線架710之上下兩面分別配置一第一晶片720a及 一第二晶片7 2 0 b 。然而，由於第一晶片7 2 0 a與第二晶片 7 2 0 b係共用導線架7 1 0 ，因此，導線架7 1 0之多個接腳7 1 2 例如可分為穿插配置之第一接腳組7 1 2 a及第二接腳組7 1 2 b (以斜線區域表示），其中第一晶片7 2 0 a上之凸塊7 3 0 a係12633 twf. Pui Page 13 1236748 V. Description of the invention (9) and the outer ends of the pins 6 1 2 are cut to the side edges of the four sides of the sealant 6 4 0 as a QFN flip-chip package structure 6 0 0 External I / 0 contact. Please refer to FIG. 8 again. The QFN flip-chip package structure 60 0 is arranged on a printed circuit board 6 50. The bump 6 3 0 on the wafer 6 2 0 can be exposed to the wires through the through hole 6 1 4. Under the frame 6 1 0, after the solder paste 654 is formed at the contact 652 on the printed circuit board 6 50, the contact 6 5 2 of the printed circuit board 6 5 0 can be passed through the solder paste 6 5 4, and the bumps 6 3 0 on the wafer 6 2 0 are bonded to each other. Based on the above, the QFN flip-chip packaging structure 6 0 0 of the present invention does not need to form a solder ball (s ο 1 der ball) between the lead frame 6 1 0 and the printed circuit board 6 50 0, and because the wafer 6 2 0 and printing The circuit boards 650 are bridged directly through the bumps 630, so they can have better electrical performance, and can reduce the number of process steps and increase production efficiency. Fourth Embodiment In addition to the single-chip QF N flip-chip package structure described above, the present invention is also applicable to a stacked (sta c k e d) dual-chip package structure. Please also refer to Figs. 9A and 9B, which respectively show a cross-sectional view of the first stacked pin-frame type flip-chip package structure of the present invention, and a top view of a lead frame of the pin-frame type flip-chip package structure. The nail-frame flip-chip package structure 700 includes, for example, a lead frame 710, and a first chip 720a and a second chip 720b are arranged on the upper and lower surfaces of the lead frame 710, respectively. However, since the first chip 7 2 0 a and the second chip 7 2 0 b share the lead frame 7 1 0, the plurality of pins 7 1 2 of the lead frame 7 1 0 can be divided into, for example, the first interposed configuration. The pin group 7 1 2 a and the second pin group 7 1 2 b (indicated by the hatched area), wherein the bump 7 3 0 a on the first wafer 7 2 0 a is
12633twf.ptd 第14頁 1236748 五、發明說明（ίο) 對應嵌入第一接腳組7 1 2 a上之第一貫孔7 1 4 a，而第二晶片 7 2 0 b上之凸塊7 3 0 b係對應嵌入第二接腳組7 1 2 b上之第二貫 孔7 1 4 b 。此外，封膠7 4 0係包覆第一晶片7 2 0 a 、第二晶片 7 2 0 b、凸塊7 3 0 a、凸塊7 3 0 b以及部分之導線架7 1 0，而第 一接腳組7 1 2 a與第二接腳組7 1 2 b係分別穿出封膠7 4 0而水 平延伸至外界，以作為第一晶片7 2 0 a與第二晶片7 2 0 b對外 之I /〇接點。 請參考圖1 0，其繪示本發明之第二種堆疊式的釘架型 覆晶封裝結構的剖面圖。與上述之第一種堆疊式的釘架型 覆晶封裝結構相較之下，本發明之第二種堆疊式的釘架型 覆晶封裝結構8 0 0之第一晶片8 2 0 a與第二晶片8 2 0 b係為共 用接腳8 1 2之型態，然而依照本發明之特徵，本發明在配 置第一晶片8 2 0 a於導線架8 1 0上時，便可使凸塊8 3 0穿過貫 孑L而延伸突出於導線架8 1 0之另一側。此外，第二晶片 820b上可不需再另外形成凸塊’而弟一晶片820a與弟》—晶 片820b可共用同一凸塊830而與接腳812電性連接，如此一 來，同樣可達到縮短製程時間，並提高生產效率之目的。 綜上所述，本發明之釘架型覆晶封裝結構及其封裝製 程係於接腳之對應於凸塊的位置上形成貫孔，使得凸塊可 直接嵌入此貫孔中，以避免凸塊在接合時發生坍塌的現 象，進而改善晶片與導線架之接合效果，並且提高封裝製 程之良率。此外，在一較佳實施例中，本發明之凸塊例如 可以是高鉛凸塊、銅凸塊、金凸塊等高熔點之凸塊，且其 係可藉由預銲層而與導線架接合在一起，以控制晶片和導12633twf.ptd Page 14 1236748 V. Description of the invention (1) Corresponding to the first through hole 7 1 4 a embedded in the first pin group 7 1 2 a, and the bump 7 3 on the second wafer 7 2 0 b 0 b corresponds to the second through hole 7 1 4 b embedded in the second pin group 7 1 2 b. In addition, the sealant 7 4 0 covers the first wafer 7 2 0 a, the second wafer 7 2 0 b, the bump 7 3 0 a, the bump 7 3 0 b, and a part of the lead frame 7 1 0. The first pin group 7 1 2 a and the second pin group 7 1 2 b respectively penetrate the sealant 7 4 0 and extend horizontally to the outside, as the first chip 7 2 0 a and the second chip 7 2 0 b External I / 〇 contact. Please refer to FIG. 10, which illustrates a cross-sectional view of a second stacked pin-frame flip-chip package structure of the present invention. Compared with the first stacked nail-frame type flip-chip package structure described above, the second stacked nail-frame type flip-chip package structure 8 0 0 of the first wafer 8 2 0 a and the first The two chips 8 2 0 b are in the form of shared pins 8 12. However, according to the features of the present invention, when the first chip 8 2 0 a is arranged on the lead frame 8 10, the bumps can be made. 8 3 0 extends through the 孑 L and protrudes from the other side of the lead frame 8 1 0. In addition, the second wafer 820b does not need to form additional bumps, and the first wafer 820a and the second wafer—the wafer 820b can share the same bump 830 and be electrically connected to the pin 812. In this way, the process can also be shortened. Time and the purpose of improving production efficiency. In summary, the nail-frame flip-chip package structure and the packaging process of the present invention form a through hole at the position of the pin corresponding to the bump, so that the bump can be directly embedded in the through hole to avoid the bump. Collapse occurs during bonding, which improves the bonding effect between the chip and the lead frame, and improves the yield of the packaging process. In addition, in a preferred embodiment, the bumps of the present invention can be, for example, high-melt bumps such as high-lead bumps, copper bumps, and gold bumps, and they can be connected to the lead frame through a pre-soldering layer. Bonded together to control the wafer and guide
iipiriipir
12633 twf.ptd 第15頁 1236748 五、發明說明（11) 線架之間距。另外，本發明之第一實施例及第二實施例中 所提及之膠膜、預銲層、沾附層以及銲罩層等並非為必要 之元件，其可視製程上之設計以及成本上之考量等因素選 擇性地配置，以求得最佳化之封裝結構與製程。 由於本發明之釘架型覆晶封裝結構的接腳上設計有貫 孔，因此在與外界之印刷電路板進行接合時，可直接藉由 晶片上之凸塊與印刷電路板接合，而當應用於晶片之堆疊 時，亦可使導線架兩側之晶片共用同一凸塊。換言之，藉 由本發明之釘架型覆晶封裝結構不僅可簡化與外界之接合 步驟，更有利於進行晶片之堆疊，而在製作成本降低與製 程步驟簡化之後，將可大幅提高產品之生產效率。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。12633 twf.ptd Page 15 1236748 V. Description of the invention (11) The distance between the wire racks. In addition, the adhesive film, pre-soldering layer, adhesion layer, and solder mask layer mentioned in the first and second embodiments of the present invention are not necessary components. The design and cost of the process can be visualized. Selectively consider factors such as configuration to obtain an optimized package structure and manufacturing process. Because the pins of the nail-frame flip-chip package structure of the present invention are designed with through holes, when bonding with the external printed circuit board, it can be directly bonded to the printed circuit board by the bump on the wafer, and when applied When the chips are stacked, the chips on both sides of the lead frame can also share the same bump. In other words, the nail-frame flip-chip package structure of the present invention not only simplifies the bonding steps with the outside world, but also facilitates the stacking of wafers. After reducing the manufacturing cost and simplifying the process steps, the production efficiency of the product can be greatly improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.
12633 twf.ptd 第16頁 1236748 圖式簡單說明 圖1繪示為習知之一種釘架型封裝結構的局部剖面 圖。 圖2 A及2 B分別繪示為習知之一種釘架型覆晶封裝結構 的局部剖面圖。 圖3 A〜3 D繪示為本發明之第一實施例之一種釘架型覆 晶封裝製程的示意圖。 圖4繪示為本發明之第一實施例之另一種釘架型覆晶 封裝製程的示意圖。 圖5繪示為本發明之第一實施例之另一種釘架型覆晶 封裝製程的示意圖。 圖6繪示為本發明之第二實施例之第一種釘架型覆晶 封裝結構的示意圖。 圖7繪示為本發明之第二實施例之第二種釘架型覆晶 封裝結構的示意圖。 圖8繪示為應用本發明之一種QFN覆晶封裝結構的示意 圖。 圖9 A繪示為本發明之第一種堆疊式的釘架型覆晶封裝 結構的剖面圖。 圖9 B繪示為圖9 A之導線架的俯視圖。 圖1 0繪示為本發明之第二種堆疊式的釘架型覆晶封裝 結構的剖面圖。 【圖式標示說明】 1 0 0 :釘架型封裝結構 1 1 0 :晶片 112633 twf.ptd Page 16 1236748 Brief Description of Drawings Figure 1 shows a partial cross-sectional view of a conventional nail rack type packaging structure. 2A and 2B are partial cross-sectional views of a conventional nail-frame flip-chip package structure, respectively. 3A to 3D are schematic diagrams showing a nail frame type flip chip packaging process according to the first embodiment of the present invention. FIG. 4 is a schematic diagram of another nail frame type flip chip packaging process according to the first embodiment of the present invention. FIG. 5 is a schematic diagram of another nail frame type flip chip packaging process according to the first embodiment of the present invention. FIG. 6 is a schematic diagram of a first nail-frame flip-chip package structure according to a second embodiment of the present invention. FIG. 7 is a schematic diagram of a second nail-frame flip-chip package structure according to a second embodiment of the present invention. FIG. 8 is a schematic diagram showing a QFN flip-chip package structure to which the present invention is applied. FIG. 9A is a cross-sectional view of the first stacked pin-frame flip-chip package structure of the present invention. FIG. 9B is a top view of the lead frame of FIG. 9A. FIG. 10 is a cross-sectional view of a second stacked pin-frame flip-chip package structure according to the present invention. [Schematic description] 1 0 0: Nail-frame package structure 1 1 0: Chip 1
I 12633iwΓ.ptd 第17頁 1236748 圖式簡單說明 112 主動表面 114 背面 116 銲墊 1 18 銀膠 1 20 晶片座 1 30 導線 1 40 接腳 1 50 封膠 200 釘架型覆晶封裝結構 2 1 0晶片 212 主動表面 216 銲墊 230 凸塊 240 接腳 250 封膠 300 釘架型覆晶封裝結構 310 導線架 312 接腳 312a 二上表面 3 12b :下表面 3 14 貫孔 320 晶片 322 主動表面 324 銲墊I 12633iwΓ.ptd Page 17 1236748 Brief description of the diagram 112 Active surface 114 Back 116 Solder pad 1 18 Silver glue 1 20 Chip holder 1 30 Wire 1 40 Pin 1 50 Sealant 200 Nail-frame flip-chip package structure 2 1 0 Chip 212 Active surface 216 Solder pad 230 Bump 240 Pin 250 Sealant 300 Pin holder flip-chip package structure 310 Lead frame 312 Pin 312a Two upper surface 3 12b: Lower surface 3 14 Through hole 320 Wafer 322 Active surface 324 Solder pad
12633twf.ptd 第18頁 1236748 圖式簡單說明 330 凸塊 340 封膠 350 膠膜 360 預銲層 400 釘架型覆晶封裝結構 4 10 導線架 4 12 接腳 414 貫孔 414a :内壁 430 凸塊 450 沾附層 5 12 接腳 5 12a : 上表面 5 14 貫孔 530 凸塊 550 銲罩層 600 Q F N覆晶封裝結構 6 10 導線架 6 12 接腳 6 12a : 上表面 6 12b :下表面 6 14 貫孔 620 晶片 622 主動表面12633twf.ptd Page 18 1236748 Brief description of the drawings 330 Bump 340 Sealant 350 Adhesive film 360 Pre-soldering layer 400 Nail-frame flip-chip package structure 4 10 Lead frame 4 12 Pin 414 Through hole 414a: Inner wall 430 Bump 450 Adhesion layer 5 12 pin 5 12a: upper surface 5 14 through hole 530 bump 550 solder mask layer 600 QFN flip chip package structure 6 10 lead frame 6 12 pin 6 12a: upper surface 6 12b: lower surface 6 14 through Hole 620 chip 622 active surface
12633 twf.ptd 第19頁 1236748 圖式簡單說明 630 凸 塊 640 封 膠 650 印 刷 電 路 板 652 接 點 654 錫 膏 700 釘 架 型 覆 晶封裝結構 7 10 導 線 架 7 12 接 腳 7 1 2 a :第一接腳組 7 1 2 b :第二接腳組 714a:第一貫孔 _ 7 1 4 b :第二貫孔 7 2 0 a :第一晶片 7 2 0 b :第二晶片 730a :凸塊 730b :凸塊 7 4 0 :封膠 8 0 0 :釘架型覆晶封裝結構 8 1 0 :導線架 8 1 2 :接腳 8 2 0 a :第一晶片 8 2 0 b :第二晶片 ® 8 3 0 :凸*塊12633 twf.ptd Page 19 1236748 Schematic description 630 bump 640 sealant 650 printed circuit board 652 contact 654 solder paste 700 pin-frame flip chip package structure 7 10 lead frame 7 12 pin 7 1 2 a: One pin group 7 1 2 b: second pin group 714a: first through hole _ 7 1 4 b: second through hole 7 2 0 a: first wafer 7 2 0 b: second wafer 730a: bump 730b: bump 7 4 0: sealant 8 0 0: nail-frame flip-chip package structure 8 1 0: lead frame 8 1 2: pin 8 2 0 a: first chip 8 2 0 b: second chip® 8 3 0: convex * block
12633twf.ptd 第20頁12633twf.ptd Page 20
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| TW093110064A TWI236748B (en) | 2004-04-12 | 2004-04-12 | Flip chip on lead package and process thereof |
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