TWI236228B - Coordinating frequency synthesizer device - Google Patents
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1236228 _案號 92114887_年月日__ 五、發明說明（1) 發明所屬之技術領域 本發明是有關於一種綜頻器鎖頻電路（C ο 〇 r d i n a t 1 n g F r e q u e n c y S y n t h e s i z e r )，且特別是關於一種複合式綜頻 鎖頻電路，每個迴路皆具有定/跳頻功能，在定頻時可選 其中一組使用，在使用跳頻時，可交替變頻使用。 先前技術 綜頻器鎖頻電路是提供給接收機或是發射機本地振盪 之用，傳統的技術，一般都是使用單迴路式（S i n g 1 e Phase L o c k L ο o p )鎖頻電路，然而其缺點在於頻率鎖頻速 度快時，也就是在高頻時，會伴隨較大之雜訊，且鎖頻速 度慢，因此無法符合在目前通信裝置之所要求的快速變換 頻率之要求。除此之外，傳統的綜頻器鎖頻電路，其壓控 振盪器必透過除頻器、參考頻率、迴路濾波器進行鎖頻， 在單一迴路時，因頻率波道數密集（除數值大）時鎖頻迴路 速度慢，無法使用於快速跳頻通信機。 發明内容 有鑑於此，本發明之目的是提供一種複合式綜頻器 (Coordinating Frequency Synthesizer)鎖頻電路，每個 迴路皆具有定/跳頻功能，在定頻時可選其中一組使用， 在使用跳頻時，可交替變頻使用。 在本發明之一實施例之複合式綜頻器鎖頻電路中，具 有複數組之鎖頻迴路，每個迴路皆具有定/跳頻功能，配 合壓控振盪器（Voltage Control Oscillator，底下稱 為” V C 0 π )頻率之適當分配，並考量鎖頻速度與伴隨之雜1236228 _ Case number 92114887_ 年月 日 __ V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a frequency synthesizer frequency lock circuit (C ο 〇rdinat 1 ng F requency S ynthesizer), and particularly It is a composite integrated frequency locking circuit. Each loop has a fixed / frequency-hopping function. When a fixed frequency is selected, one of them can be used. When frequency-hopping is used, it can be used by alternating frequency conversion. In the prior art, the frequency lock circuit of the synthesizer was provided to the receiver or the transmitter for local oscillation. The traditional technology generally uses a single loop (Singing 1 e Phase Lock L ο op) frequency lock circuit. However, The disadvantage is that when the frequency is locked at a high frequency, that is, at high frequencies, it will be accompanied by large noise and the frequency is slow, so it cannot meet the requirements of fast frequency conversion required by current communication devices. In addition, in the traditional frequency synthesizer frequency-locked circuit, its voltage-controlled oscillator must be frequency-locked through the frequency divider, reference frequency, and loop filter. ) When the frequency lock loop is slow, it cannot be used for fast frequency hopping communication. SUMMARY OF THE INVENTION In view of this, the object of the present invention is to provide a composite frequency synthesizer (Coordinating Frequency Synthesizer) frequency locking circuit, each loop has a fixed frequency / frequency hopping function, when the fixed frequency is selected, one group can be used. When frequency hopping is used, frequency conversion can be used alternately. In a composite synthesizer frequency-locking circuit according to an embodiment of the present invention, there is a frequency-locked loop of a complex array, and each loop has a fixed / frequency-hopping function, and cooperates with a voltage-controlled oscillator (Voltage Control Oscillator, hereinafter referred to as ”VC 0 π) Proper frequency allocation, taking into account the frequency lock speed and the concomitant miscellaneous
11371twfl.ptc 第8頁 1236228 _案號92114887_年月曰 修正_ 五、發明說明（2) 訊，以取得最佳化之分配，並輔以射頻信號快速切換電路 之設計配合電腦控制，在不同波段電路間快速切換，以達 成低雜訊與快速鎖頻之功能。 在本發明之一實施例之複合式綜頻器鎖頻電路中，係 利用兩組鎖頻迴路，當使用定頻操作模式時，第一組迴路 進入工作模式，而第二組則處於關機狀態，可節省電流。 如迴路有不良之情形時，可更換另外一組繼續使用，不至 於影響通信之品質。當使用跳頻操作模式時，其中一組綜 頻器鎖頻電路開始動作，而另外一組綜頻器鎖頻電路便處 於準備妥善之狀態。當變換頻率時，兩組綜頻器鎖頻電路 交換運用，而後經由射頻快速轉換電路提供給接收機或是 發射機本地振盪之用。 為達上述之目的，本發明提供一種複合式綜頻器鎖頻 電路。此電路包括一第一鎖相迴路、一第二鎖相迴路與一 切換電路。此第一鎖相迴路係用以接收從一參考頻率信號 以及一第一命令信號，並據以產生一第一頻率通道信號。 而第二鎖相迴路用以接收參考頻率信號以及第二命令信 號，並據以產生第二頻率通道信號。而切換電路係用以接 收第一頻率通道信號與第二頻率通道信號，以及一第三命 令信號，並根據此第三命令信號選擇輸出一輸出頻率通道 信號。 上述之複合式綜頻器鎖頻電路，其中參考頻率信號係 由一石英振盪裝置所產生。而此石英振盪裝置產生之參考 頻率信號範圍在數個Κ Η z到數百個ΜΗ z之間，並達到變化頻11371twfl.ptc Page 8 1236228 _Case No. 92114887_ Revised Year of the Month _5. Description of the invention (2) to obtain the optimal distribution, supplemented by the design of the RF signal fast switching circuit and computer control, in different Quickly switch between band circuits to achieve low noise and fast frequency locking. In the composite synthesizer frequency-locking circuit of one embodiment of the present invention, two sets of frequency-locked circuits are used. When the fixed-frequency operation mode is used, the first group of circuits enters the working mode, and the second group is in the off state , Can save current. If the circuit is bad, you can change another group and continue to use it without affecting the quality of communication. When the frequency-hopping operation mode is used, one of the synthesizer frequency-locked circuits starts to operate, while the other set of synthesizer frequency-locked circuits is in a ready state. When the frequency is changed, the two sets of synthesizer frequency-locked circuits are used interchangeably, and then provided to the receiver or transmitter for local oscillation through the RF fast conversion circuit. To achieve the above object, the present invention provides a composite frequency synthesizer frequency locking circuit. The circuit includes a first phase locked loop, a second phase locked loop and a switching circuit. The first phase-locked loop is used to receive a reference frequency signal and a first command signal, and generate a first frequency channel signal accordingly. The second phase locked loop is used to receive the reference frequency signal and the second command signal, and generate a second frequency channel signal accordingly. The switching circuit is configured to receive the first frequency channel signal, the second frequency channel signal, and a third command signal, and select and output an output frequency channel signal according to the third command signal. In the above-mentioned composite synthesizer frequency-locking circuit, the reference frequency signal is generated by a quartz oscillation device. The reference frequency signal generated by this quartz oscillation device ranges from several 数 Κ z to several hundred Η Η z, and reaches a varying frequency.
11371twfl.ptc 第9頁 1236228 _案號 92114887_年月日__ 五、發明說明（3) 率對於溫度之變化比約為1到2個ppm/ °C。 上述之複合式綜頻器鎖頻電路，其中當切換電路所輸 出之輸出頻率通道信號係第一頻率通道信號，而若所接收 到的第三命令信號要求切換時，第二頻率通道信號已由第 二鎖相迴路之完成在一預定頻率之第二頻率通道信號。 上述之複合式綜頻器鎖頻電路，其中第一鎖相迴路包 括一相位檢知器、一迴路遽波器、一電壓控制振盈器 (V C 0 )、一緩衝電路、以及兩個除頻器。此相位檢知器用 以比較一經由除頻之回授V C 0頻率控制信號與將參考頻率 信號除頻後之信號，並產生一相位差異信號。迴路濾波器 係連接到相位檢知器，用以接收相位差異信號，過濾其雜 訊後輸出一控制電壓信號。電壓控制振盪器（V C 0 )連接到 迴路濾波器，用以接收控制電壓信號，並據以輸出一 V C 0 頻率信號。緩衝電路連接到電壓控制振盪器，用以根據電 壓控制振盪器所輸出之VCO頻率信號，輸出回授VCO頻率控 制信號。第一除頻器連接到緩衝電路，用以對回授VCO頻 率控制信號進行除頻後輸出至相位檢知器。第二除頻器用 以接收參考頻率信號，並進行除頻後輸出至相位檢知器。 在一選擇實施例中，控制電壓信號之電壓位準係根據所需 要的頻帶而設定。 上述之複合式綜頻器鎖頻電路，其中迴路淚波器包 括一頻帶選擇裝置、一寬頻帶濾波器、一窄頻帶濾波器、 以及一輸出選擇切換裝置。頻帶選擇裝置用以根據迴路濾 波器所接收到的相位差異信號，選擇由寬頻帶濾波器或是11371twfl.ptc Page 9 1236228 _Case No. 92114887_Year Month Day__ 5. Description of the invention (3) The ratio of the change of the rate to the temperature is about 1 to 2 ppm / ° C. In the above-mentioned composite synthesizer frequency locking circuit, when the output frequency channel signal output by the switching circuit is the first frequency channel signal, and if the received third command signal requires switching, the second frequency channel signal has been changed by The completion of the second phase locked loop is a second frequency channel signal at a predetermined frequency. In the above-mentioned composite frequency synthesizer frequency-locking circuit, the first phase-locked loop includes a phase detector, a loop oscillator, a voltage-controlled oscillator (VC 0), a buffer circuit, and two frequency dividers. Device. This phase detector is used to compare a frequency-divided feedback V C 0 frequency control signal with a frequency-divided reference frequency signal and generate a phase difference signal. The loop filter is connected to the phase detector and is used to receive the phase difference signal, and output a control voltage signal after filtering the noise. The voltage-controlled oscillator (V C 0) is connected to the loop filter to receive the control voltage signal and output a V C 0 frequency signal accordingly. The buffer circuit is connected to the voltage-controlled oscillator and is used to output a feedback VCO frequency control signal according to the VCO frequency signal output by the voltage-controlled oscillator. The first frequency divider is connected to the buffer circuit and is used to divide the frequency of the feedback VCO frequency control signal and output it to the phase detector. The second frequency divider is used to receive the reference frequency signal, and divide the frequency and output it to the phase detector. In an alternative embodiment, the voltage level of the control voltage signal is set according to the required frequency band. In the above-mentioned composite synthesizer frequency-locking circuit, the loop tear wave device includes a band selection device, a wide band filter, a narrow band filter, and an output selection switching device. The band selection device is used to select a wide band filter or a phase difference signal according to the phase difference signal received by the loop filter.
11371twfl.ptc 第10頁 1236228 _案號92114887_年月日_^_ 五、發明說明（4) 窄頻帶濾波器過濾其雜訊後輸出控制電壓信號。輸出選擇 切換裝置係用以選擇連接到寬頻帶濾波器之一輸出端或是 窄頻帶濾波器之一輸出端，並據以輸出控制電壓信號。 上述之複合式綜頻器鎖頻電路，其中切換電路包括一第一 開關、一第二開關、一第三傳送開關、以及一第四接收開 關。第三傳送開關與第四接收開關係用以選擇性地將第一 頻率通道信號或是第二頻率通道信號輸出，以作為複合式 綜頻器鎖頻電路之輸出頻率通道信號。而經由第三傳送開 關輸出之信號，係用以作為一發射機本地振盪之用，而由 第四接收開關輸出之信號，係用以作為一接收機本地振盪 之用。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 實施方式 請參照第1圖，係顯示根據本發明一較佳實施例之複 合式綜頻器（Coordinating Frequency Synthesizer) 鎖 頻電路。如第1圖所示，此複合式綜頻器鎖頻電路1 0 0包括 一第一鎖相迴路1200、一第二鎖相迴路1300、一切換電路 1400與兩個命令串接介面1500與1502。此第一鎖相迴路 1 2 0 0用以接收從外部而來的一參考頻率信號（R e f e r e n c e Frequency Signal)以及一從命令串接介面1500傳來的一 第一命令信號（Commend Signal)1501 。而此第二鎖相迴路 1 3 0 0用以接收從此參考頻率信號以及一從命令串接介面11371twfl.ptc Page 10 1236228 _Case No. 92114887_Year_Month_ ^ V. Description of the invention (4) The narrow-band filter outputs the control voltage signal after filtering its noise. The output selection switching device is used to select an output terminal connected to a wideband filter or an output terminal of a narrowband filter, and output a control voltage signal accordingly. In the above-mentioned composite synthesizer frequency-locking circuit, the switching circuit includes a first switch, a second switch, a third transmission switch, and a fourth receiving switch. The third transmission switch and the fourth reception switch are used to selectively output the first frequency channel signal or the second frequency channel signal as the output frequency channel signal of the frequency synthesizer of the composite synthesizer. The signal output through the third transmission switch is used as a transmitter for local oscillation, and the signal output from the fourth reception switch is used for a receiver for local oscillation. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in conjunction with the accompanying drawings, and are described in detail as follows: For implementation, please refer to FIG. A compound frequency synthesizer (Coordinating Frequency Synthesizer) frequency locking circuit according to a preferred embodiment of the present invention. As shown in Fig. 1, the frequency synthesizer circuit of the composite synthesizer 100 includes a first phase-locked loop 1200, a second phase-locked loop 1300, a switching circuit 1400, and two command serial interfaces 1500 and 1502. . The first phase locked loop 1 2 0 0 is used to receive a reference frequency signal (R e f e r n c e Frequency Signal) from the outside and a first command signal (Commend Signal) 1501 transmitted from the command serial interface 1500. The second phase locked loop 1 3 0 0 is used to receive the reference frequency signal and a slave command serial interface.
11371twf1.pt c 第11頁 1236228 ___ 案號92114887_年月日 修正 _ 五、發明說明（5) * 1 5 0 0傳來的一第二命令信號1 5 0 3。 基於上述所接收到的信號，此第一鎖相迴路1 2 0 0與第 二鎖相迴路1 3 0 0可分別用以產生一第一頻率通道信號 (First Frequency Channel Signal)1202與一第二頻率通 道信號（Second Frequency Channel Signal)1302 〇 而上 述的切換電路1 4 0 0，則用以接收上述之第一頻率通道信號 1202與第二頻率通道信號1302，以及由命令串接介面1502 所傳來的第三命令信號1505。基於由命令串接介面1502傳 來之第三命令信號1505，此切換電路1400可選擇並且輸出 一輸出頻率通道信號（Output Frequency Channel Signal) 〇 如上所述，第一鎖相迴路1 2 0 0與第二鎖相迴路1 3 0 0都 會接收到所收到的參考頻率信號，而此參考頻路信號在一 較佳實施例中可由溫度所影響的石英振盪裝置。此石英振 盪裝置具有一非常穩定的輸出特性，並且能夠產生非常廣 頻帶範圍可供選擇。因此，此石英振盪裝置可用在輸出一 具有非常良好且正確穩定之頻率信號。而一般而言，可使 用石英振盪裝置產生範圍在數個Κ Η z到數十個Μ Η z之頻率， 以達到餐化頻率對於溫度之變化比約為1到2個p p m / 。 在本發明之操作方法中，例如若是在第1圖中的第一 鎖相迴路1 2 0 0接收到此參考頻率信號時，根據從命令串接 介面1 5 0 0傳來的一第一命令信號丨5 〇 1 ，產生此第一頻率通 道信號1 2 0 2，並輸出至切換電路1 4 〇 〇。因此，此切換電路 1 4 0 0可據此輸出頻率通道信號。然而，當切換電路丨4 〇 〇在11371twf1.pt c Page 11 1236228 ___ Case No. 92114887_Year Month Day Amendment _ V. Description of the invention (5) * A second command signal 1 5 0 3 from 1 5 0 0. Based on the received signals, the first phase-locked loop 1 2 0 and the second phase-locked loop 1 3 0 0 can be used to generate a first frequency channel signal 1202 and a second The frequency channel signal (Second Frequency Channel Signal) 1302 〇 and the above-mentioned switching circuit 14 0 0 is used to receive the above-mentioned first frequency channel signal 1202 and the second frequency channel signal 1302, and transmitted by the command serial interface 1502来 的 thirdCommand 信号 1505. Based on the third command signal 1505 transmitted from the command serial interface 1502, the switching circuit 1400 can select and output an output frequency channel signal. As described above, the first phase-locked loop 1 2 0 0 and The second phase-locked loop 130 will receive the received reference frequency signal, and the reference frequency signal is a quartz oscillator that can be affected by temperature in a preferred embodiment. This quartz oscillator has a very stable output characteristic and can produce a very wide frequency band to choose from. Therefore, this quartz oscillator can be used to output a frequency signal with very good and accurate stability. In general, a quartz oscillation device can be used to generate frequencies ranging from several K Η z to several tens of M Η z, so as to achieve a change ratio of meal frequency to temperature of about 1 to 2 p p m /. In the operating method of the present invention, for example, if the first phase-locked loop 1 2 0 0 in FIG. 1 receives the reference frequency signal, a first command transmitted from the command serial interface 15 0 0 is received. The signal 丨 5 〇 1 generates the first frequency channel signal 1 2 0 2 and outputs it to the switching circuit 1 4 〇 0. Therefore, the switching circuit 140 can output a frequency channel signal accordingly. However, when the switching circuit 丨 4 〇 〇
11371twf1.ptc 第12頁 1236228 _案號 92114887_年月日_ifi_ 五、發明說明（6) 輸出此第一頻率通道信號1 2 0 2時，此第二鎖相迴路1 3 0 0可 基於由命令串接介面1 5 0 0傳來的第二命令信號1 5 0 3，開始 產生穩定的第二頻率通道信號1 3 0 2， 在此方法中，當切換電路1 4 0 0完成輸出此第一頻率通 道信號1 2 0 2時，且接收到從命令串接介面1 5 0 2傳來的第三 命令信號1 5 0 5，要求切換並且開始使用第二頻率通道信號 1 3 0 2時，第二鎖相迴路1 3 0 0已經完成並產生穩定的第二頻 率通道信號1 3 0 2。因此，可避免第二鎖相迴路1 3 0 0之浪費 時間與延遲，而可產生具有穩定且在一預定頻率之第二頻 率通道信號1 3 0 2。 依照上述之方法，此頻率綜頻器（C ο 〇 r d i n a t i n g Frequency Synthesizer)可再操作一次。當切換電路1400 正在輸出第二頻率通道信號1 3 0 2時，且接收到從命令串接 介面1 5 0 2傳來的第三命令信號1 5 0 5，要求切換並且開始使 用第一頻率通道信號1 2 0 2時，由第一鎖相迴路1 2 0 0根據從 命令串接介面1500傳來的第一命令信號1501 ，再次產生具 有固定頻率或是其他頻率之第一頻率通道信號1 2 0 2，以便 輸出。 由上述方法可知，此第一鎖相迴路1 2 0 0與第二鎖相迴 路1300係在一複合方式（Coordinating Manner)，可避免 因為鎖相迴路為了獲得穩定的振盪頻率所造成的時間延 遲。因此，此複合式的頻率綜頻器速度將會被切換電路 1 4 0 0的切換速度所影響，而非由鎖相迴路為了獲得穩定的 振盪頻率所造成的時間延遲所影響。除此之外，具有兩個11371twf1.ptc Page 12 1236228 _ Case No. 92114887_year month_ifi_ V. Description of the invention (6) When the first frequency channel signal 1 2 0 2 is output, the second phase locked loop 1 3 0 0 can be based on The second command signal 15 0 3 from the command serial interface 15 0 0 starts to generate a stable second frequency channel signal 1 3 0 2. In this method, when the switching circuit 1 4 0 0 finishes outputting the first When a frequency channel signal is 1 2 0 2 and a third command signal 1 5 0 5 is received from the command serial interface 15 0 2 and a switching is required and the second frequency channel signal 1 3 0 2 is used, The second phase locked loop 1 3 0 0 has been completed and generates a stable second frequency channel signal 1 3 2. Therefore, the waste of time and delay of the second phase-locked loop 1 300 can be avoided, and a second frequency channel signal 1 3 2 having a stable and a predetermined frequency can be generated. According to the above method, the frequency synthesizer (C ο ο r d i n a t i n g Frequency Synthesizer) can be operated again. When the switching circuit 1400 is outputting the second frequency channel signal 1 3 0 2 and receives a third command signal 1 5 0 5 from the command serial interface 1 5 0 2, it is required to switch and start using the first frequency channel When the signal 1 2 0 2 is generated, the first phase-locked loop 1 2 0 0 again generates a first frequency channel signal having a fixed frequency or another frequency according to the first command signal 1501 transmitted from the command serial interface 1500. 2 0 for output. It can be known from the above method that the first phase locked loop 1220 and the second phase locked loop 1300 are in a composite mode (Coordinating Manner), which can avoid the time delay caused by the phase locked loop in order to obtain a stable oscillation frequency. Therefore, the speed of this composite frequency synthesizer will be affected by the switching speed of the switching circuit 140, rather than the time delay caused by the phase-locked loop in order to obtain a stable oscillation frequency. In addition, there are two
1 1371twfl.ptc 第13頁 12362281 1371twfl.ptc Page 13 1236228
案號 92114887 五、發明說明（7) 以上的鎖相迴路有其特別之優點，例如，在其中一個鎖相 迴路失敗或是錯誤後，另外一個鎖相迴路可以取代作為備 用，以維持系統之正常運作。 請參照第2圖，係顯示在第1圖中的第一鎖相迴路丨2 〇 〇 之一較佳實施例之電路方塊圖。此第一鎖相迴路1 2 〇 〇包括 一相位檢知器1 2 1 0、一迴路濾波器1 2 2 0、一電壓控制振堡 器（Voltage Control Oscillator ，底下簡稱nVCOn) 1230、一緩衝電路（Buffer Circuit)1240、以及兩個除頻 器（Frequency Divider)1250與1260。而其連接關係如下 所述。迴路濾波器1 2 2 0係連接到電壓控制振盪器（VC0 ) 1 2 3 0及相位檢知器1 2 1 0。緩衝電路1 2 4 0係連接到電壓控制 振盪器（V C 0 ) 1 2 3 0及除頻器1 2 5 0。而除頻器1 2 5 0與1 2 6 0亦 皆連接到相位檢知器1 2 1 0。 此第一鎖相迴路1 2 0 0之操作係眾所皆知。例如，使用 相位檢知器1 2 1 0之目的即在於使第一鎖相迴路1 2 0 0能產生 所需要的第一頻率通道信號1 2 0 2。此相位檢知器1 2 1 0比較 了分別由除頻器1 2 5 0與1 2 6 0所除頻之一回授V C 0頻率控制 信號1 2 5 2與參考頻率信號，並產生一相位差異信號（p h a s eCase No. 92114887 V. Description of the invention (7) The phase-locked loop above has its special advantages. For example, after one phase-locked loop fails or is faulty, the other phase-locked loop can be replaced as a backup to maintain the normality of the system. Operation. Please refer to FIG. 2, which is a circuit block diagram of a preferred embodiment of the first phase-locked loop shown in FIG. 2. The first phase-locked loop 1 2 00 includes a phase detector 12 1 0, a loop filter 1 2 2 0, a voltage control oscillator (Voltage Control Oscillator, abbreviated as nVCOn below) 1230, and a buffer circuit. (Buffer Circuit) 1240, and two frequency dividers (Frequency Divider) 1250 and 1260. The connection relationship is as follows. The loop filter 1 2 2 0 is connected to a voltage controlled oscillator (VC0) 1 2 3 0 and a phase detector 1 2 1 0. The buffer circuit 1 2 4 0 is connected to a voltage controlled oscillator (V C 0) 1 2 3 0 and a frequency divider 1 2 5 0. The frequency divider 1 2 5 0 and 1 2 6 0 are also connected to the phase detector 1 2 1 0. The operation of this first phase-locked loop 1 2 0 0 is well known. For example, the purpose of using the phase detector 1 2 1 0 is to enable the first phase locked loop 1 2 0 0 to generate the required first frequency channel signal 1 2 0 2. This phase detector 1 2 1 0 compares VC 0 frequency control signal 1 2 5 2 with a reference frequency signal and returns a phase by dividing one of the frequency dividers 1 2 5 0 and 1 2 6 0. Difference signal
Difference Signal)1212。而此除頻器1250係接收由電壓 控制振盪器（V C 0 ) 1 2 3 0所輸出之V C 0頻率信號1 2 3 2，並經由 緩衝電路1 2 4 0緩衝輸出之回授V C 0頻率控制信號（底下簡 稱n F v c ο n ) 1 2 4 2，並據此輸出除頻之回授v C 0頻率控制信號 1 2 5 2 〇 迴路濾波器1 2 2 0接收上述之相位差異信號1 2 1 2，並過Difference Signal) 1212. The frequency divider 1250 receives the VC 0 frequency signal 1 2 3 2 output by the voltage controlled oscillator (VC 0) 1 2 3 0 and feedbacks the VC 0 frequency control through the buffer circuit 1 2 4 0 buffer output. Signal (hereinafter abbreviated as n F vc ο n) 1 2 4 2 and outputs the frequency-divided feedback v C 0 frequency control signal 1 2 5 2 〇 loop filter 1 2 2 0 receives the above-mentioned phase difference signal 1 2 1 2 and over
WmMWmM
11371twf1.ptc 第14頁 1236228 __案號 92114887_年 月_9____修正___ 五、發明說明（8) * 濾其雜訊，接著輸出一適當的控制電壓信號1 2 2 2給電壓控 制振盡器（V C 0 ) 1 2 3 0。而此適當的控制電壓信號1 2 2 2係由 所需要的頻帶而設定。例如在一較佳實施例中，此迴路渡 波器1220可包括一寬頻帶與一窄頻帶之操作模式選擇。當 電壓控制振盈器（V C 0 ) 1 2 3 0接收到此控制電壓信號1 2 2 2 時，會根據此信號發出上述之V C 0頻率信號丨2 3 2到緩衝電 路1 2 4 0中，如第2圖所示。而此緩衝電路丨2 4 〇則輸出一回 授V C 0頻率控制信號（底下簡稱n F v c 〇 ”）1 2 4 2到除頻器 1 2 5 0。除此之外，此緩衝電路1 2 4 0亦輪出上述的第一頻率 通道信號1 2 0 2到切換電路1 4 0 0中。 ' 根據第1圖所示，第二鎖相迴路1 3 〇 〇之操作方式係與 第一鎖相迴路1 2 0 0之操作方式相同，而且包括相同之元 件’在此不在冗述。而在此操作方法中，當切換電路1 4 〇 〇 完成輸出此第一頻率通道信號1 2 0 2時，且接收到從命令串 接介面1 5 0 2傳來的第三命令信號1 5 0 5，要求切換並且開始 使用弟一頻率通道信號1 3 0 2時’第二鎖相迴路1 3 0 0已經完 成並產生穩定的第二頻率通道信號1 3 0 2。因此，可避免第 二鎖相迴路1 3 0 0之浪費時間與延遲，而可產生具有穩定且 在一預定頻率之第二頻率通道信號1 3 0 2。 請參照第3圖，係顯示在本發明較佳實施例中之第2圖 所示之迴路濾波器1 2 2 0之一具體實施例。此迴路濾波器 1220 包括一頻帶選擇裝置（Band Selector Switch)1310 、 一見頻帶濾波器（Broad Band Filter)1320、一窄頻帶濾、 波器（Narrow Band Filter) 1 3 3 0以及一輸出選擇切換裝置11371twf1.ptc Page 14 1236228 __Case No. 92114887_ Year_9____ Amendment ___ V. Description of the invention (8) * Filter the noise, and then output an appropriate control voltage signal 1 2 2 2 to the voltage control oscillator (VC 0) 1 2 3 0. The appropriate control voltage signal 1 2 2 2 is set by the required frequency band. For example, in a preferred embodiment, the loop wave transformer 1220 may include a wide-band and a narrow-band operation mode selection. When the voltage control oscillator (VC 0) 1 2 3 0 receives the control voltage signal 1 2 2 2, it will send out the above-mentioned VC 0 frequency signal according to this signal 2 2 2 to the buffer circuit 1 2 4 0. As shown in Figure 2. The buffer circuit 丨 2 4 〇 outputs a feedback VC 0 frequency control signal (hereinafter referred to as n F vc 〇 ") 1 2 4 2 to the frequency divider 1 2 5 0. In addition, the buffer circuit 1 2 4 0 also turns out the above-mentioned first frequency channel signal 1 2 0 2 to the switching circuit 1 4 0 0. 'According to the first figure, the operation mode of the second phase locked loop 1 3 00 is the same as that of the first lock. The operation mode of the phase loop 1 2 0 0 is the same, and includes the same components. It is not described in detail here. In this operation method, when the switching circuit 1 4 0 0 completes outputting the first frequency channel signal 1 2 0 2 When receiving the third command signal 1 5 0 5 from the command serial interface 15 0 2, it is required to switch and start to use the frequency signal of the first frequency channel 1 3 0 2 'the second phase locked loop 1 3 0 0 A stable second frequency channel signal 1 3 0 2 has been completed and generated. Therefore, a waste of time and delay of the second phase locked loop 1 3 0 0 can be avoided, and a second frequency channel having a stable and at a predetermined frequency can be generated Signal 1 3 0 2. Please refer to Figure 3, which is shown in Figure 2 in the preferred embodiment of the present invention. A specific embodiment of the loop filter 1 2 2 0. The loop filter 1220 includes a band selector 1310, a broad band filter 1320, a narrow band filter, and a narrow wave filter (narrow Band Filter) 1 3 3 0 and an output selection switching device
1 1371twfl. 第15頁 1236228 _案號 92114887_年月日__ 五、發明說明（9) 1 3 4 0。此頻帶選擇裝置1 3 1 0用以選擇連接到寬頻帶濾波器 1320之一輸入端或是窄頻帶濾·波器1330之一輸入端。而輸 出選擇切換裝置1 3 4 0則係選擇連接到寬頻帶濾波器1 3 2 0之 一輸出端或是窄頻帶濾波器1 3 3 0之一輸出端。如此，可根 據設計上的需要，選擇寬頻帶或是窄頻帶過濾輸出。 請參照第4圖，係顯示在本發明較佳實施例中之第1圖 所示之複合式綜頻器鎖頻電路1 0 0，其包括元件切換電路 1 4 0 0之具體實施例。此切換電路1 4 0 0包括一第一開關 1 4 1 0 、一第二開關1 4 2 0 、一第三傳送開關1 4 3 0 、以及一第 四接收開關1 4 4 0 。第三傳送開關1 4 3 0與第四接收開關1 4 4 0 係用以選擇性地將第一頻率通道信號1 2 0 2或是第二頻率通 道信號1 3 0 2輸出，以作為此複合式綜頻器鎖頻電路1 0 0之 輸出頻率通道信號。而經由第三傳送開關1 4 3 0輸出，係用 以作為發射機本地振盪之用。而經由第四接收開關1 4 4 0輸 出，係用以作為接收機本地振盪之用。 本發明之複合式綜頻器鎖頻電路，具有複數組之鎖頻 迴路，每個迴路皆具有定/跳頻功能，配合壓控振盪器 (V C 0 )頻率之適當分配，並考量鎖頻速度與伴隨之雜訊， 以取得最佳化之分配，並輔以射頻信號快速切換電路之設 計配合電腦控制，在不同波段電路間快速切換，以達成低 雜訊與快速鎖頻之功能。 從上述之實施例中可知，係利用兩組鎖頻迴路作為本 發明之複合式綜頻器鎖頻電路。當使用定頻操作模式時， 例如第一鎖相迴路1 2 0 0工作模式時，而第二鎖相迴路1 3 0 01 1371twfl. Page 15 1236228 _Case No. 92114887 _ Month and Day __ V. Description of the invention (9) 1 3 4 0. The band selection device 1 3 1 0 is used to select an input terminal connected to a wideband filter 1320 or an input terminal of a narrowband filter 1330. The output selection switching device 1340 is selected to be connected to one output end of the wideband filter 1320 or one output end of the narrowband filter 1330. In this way, you can choose a wideband or narrowband filtered output according to your design needs. Please refer to FIG. 4, which is a composite frequency synthesizer frequency locking circuit 100 shown in FIG. 1 in a preferred embodiment of the present invention, which includes a specific embodiment of a component switching circuit 1 400. The switching circuit 1 4 0 0 includes a first switch 1 4 1 0, a second switch 1 4 2 0, a third transmitting switch 1 4 3 0, and a fourth receiving switch 1 4 4 0. The third transmission switch 1 4 3 0 and the fourth reception switch 1 4 4 0 are used to selectively output the first frequency channel signal 1 2 0 2 or the second frequency channel signal 1 3 0 2 as the composite. The output frequency channel signal of the integrated synthesizer frequency lock circuit 100. The output through the third transmission switch 1430 is used for local oscillation of the transmitter. The output through the fourth receiving switch 1440 is used for local oscillation of the receiver. The frequency synthesizer circuit of the composite synthesizer of the present invention has a frequency-locked loop of a complex array, and each loop has a function of frequency setting / frequency hopping. It cooperates with the proper allocation of the frequency of the voltage-controlled oscillator (VC 0) and considers the frequency of the frequency-locked With the accompanying noise, to obtain the optimal distribution, supplemented by the design of the RF signal fast switching circuit and computer control, fast switching between different band circuits to achieve the function of low noise and fast frequency lock. It can be known from the above embodiments that two sets of frequency-locked loops are used as the frequency synthesizer circuit of the composite synthesizer of the present invention. When using the fixed frequency operation mode, for example, the first phase locked loop 1 2 0 0 working mode, and the second phase locked loop 1 3 0 0
11371twf1.pt c 第16頁 1236228 _案號 92114887_年月日__ 五、發明說明（10) 則處於關機狀態，可節省電流，避免功率之消耗。而若是 在第一鎖相迴路1 2 0 0有不良或是損壞之情形時，可更換另 外一組繼續使用，不至於影響通信之品質。當使用跳頻操 作模式時，其中一組綜頻器鎖頻電路開始動作，而另外一 組綜頻器鎖頻電路便處於準備妥善之狀態。當變換頻率 時，兩組綜頻器鎖頻電路交換運用，而後經由射頻快速轉 換電路提供給接收機或是發射機本地振盪之用。 在本發明中可知，可將全頻道依頻率比率分為數組頻 道，並可與微電腦結合加強跳頻之速度。另外，再跳頻變 換頻率時，綜頻器可由兩組鎖頻迴路交替使用，跳頻之速 度僅需射頻轉換電路之時間。除此之外，定/跳頻鎖頻迴 路因為係各自獨立，因此，可依照所需要的設計而更換。 因此，本發明所可得到的效用，除了提供一種複合式綜頻 器鎖頻電路，每個迴路皆具有定/跳頻功能，在定頻時可 選其中一組使用，在使用跳頻時，可交替變頻使用，並可 兼顧雜訊之去除。另外，因為定頻與跳頻獨立使用，因 此，不受模式更動之影響。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。11371twf1.pt c page 16 1236228 _ case number 92114887_ year month day __ 5. Description of the invention (10) is in the shutdown state, which can save current and avoid power consumption. However, if the first phase-locked circuit 1 2 0 is defective or damaged, another group can be replaced and continued to be used without affecting the quality of the communication. When the frequency hopping operation mode is used, one of the synthesizer frequency-locked circuits starts to operate, and the other group of synthesizers frequency-locked circuits are in a ready state. When the frequency is changed, the two sets of synthesizer frequency-locked circuits are used interchangeably, and then provided to the receiver or transmitter for local oscillation through the RF fast conversion circuit. It can be known in the present invention that the full channel can be divided into array channels according to the frequency ratio, and can be combined with a microcomputer to enhance the speed of frequency hopping. In addition, when frequency hopping is used to change the frequency, the synthesizer can be used alternately by two sets of frequency-locked loops. The frequency hopping speed only needs the time of the RF conversion circuit. In addition, the fixed / frequency-hopping frequency-locked circuits are independent, so they can be replaced according to the required design. Therefore, in addition to the utility provided by the present invention, in addition to providing a composite synthesizer frequency-locking circuit, each loop has a fixed / frequency-hopping function, and one of them can be selected when the frequency is fixed. When using frequency-hopping, Can be used alternately with frequency conversion, and can take care of noise removal. In addition, since fixed frequency and frequency hopping are used independently, they are not affected by mode changes. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
11371twfl.ptc 第17頁 1236228 _案號 92114887_年月日_ifi__ 圖式簡單說明 第1圖是顯示根據本發明一較佳實施例之複合式綜頻器 (Coordinating Frequency Synthesizer)鎖頻電路方塊 圖。 第2圖係顯示在第1圖中的鎖相迴路之一較佳實施例之電 路方塊圖。 第3圖係顯示在本發明較佳實施例中之第2圖所示之迴路 濾波器之一具體實施例。 第4圖係顯示在本發明較佳實施例中之第1圖所示之複合 式綜頻器鎖頻電路，其所包括元件切換電路之具體實施 例。 圖式標號說明 1 0 0 :複合式綜頻器鎖頻電路 1 2 0 0、1 3 0 0 鎖相迴路 1 4 0 0 :切換電路 1500、1502 :命令串接介面 1 2 1 0 :相位檢知器 1 2 2 0 :迴路濾波器 1 2 3 0 :電壓控制振盪器（V C 0 ) 1 2 4 0 :緩衝電路 1250 、 1260 :除頻器 1 3 1 0 :頻帶選擇裝置 1 3 2 0 :寬頻帶濾波器 1 3 3 0 :窄頻帶濾波器 1340 :輸出選擇切換裝置11371twfl.ptc Page 17 1236228 _ Case No. 92114887_ Year Month _ifi__ Brief Description of the Drawings Figure 1 is a block diagram showing a frequency lock circuit of a Coordinating Frequency Synthesizer according to a preferred embodiment of the present invention . Fig. 2 is a block diagram showing a preferred embodiment of the phase locked loop shown in Fig. 1. Fig. 3 shows a specific embodiment of the loop filter shown in Fig. 2 in the preferred embodiment of the present invention. Fig. 4 shows a specific embodiment of the component synthesizer frequency-locking circuit shown in Fig. 1 of the preferred embodiment of the present invention, including the component switching circuit. Explanation of figure labels 1 0 0: composite synthesizer frequency lock circuit 1 2 0 0, 1 3 0 0 phase locked loop 1 4 0 0: switching circuit 1500, 1502: command serial interface 1 2 1 0: phase detection 1 2 2 0: loop filter 1 2 3 0: voltage controlled oscillator (VC 0) 1 2 4 0: buffer circuits 1250, 1260: frequency divider 1 3 1 0: frequency band selection device 1 3 2 0: Broadband filter 1 3 3 0: Narrowband filter 1340: Output selection switching device
11371twfl.ptc 第18頁 123622811371twfl.ptc Page 18 1236228
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