TWI234002B - Adapter for testing one or more conductor assemblies - Google Patents
Adapter for testing one or more conductor assemblies Download PDFInfo
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- TWI234002B TWI234002B TW092132186A TW92132186A TWI234002B TW I234002 B TWI234002 B TW I234002B TW 092132186 A TW092132186 A TW 092132186A TW 92132186 A TW92132186 A TW 92132186A TW I234002 B TWI234002 B TW I234002B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
- G01R31/2808—Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2805—Bare printed circuit boards
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- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measuring Leads Or Probes (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
1234002 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一用於測試一或 一 個導體組件之轉去 器❶尤其本發明係關於一用於測試電路 轉去 年反及其他大致g 士 狀非元件式之導體組件的轉接器。 具有一晶片側之每 體組件（如晶片載體）係具有數個接 " 碉點以連接至一積體t 路，且該導體組件上之一連接侧具 、另平又大的接觸點以連去 至另外的導體組件。此等該連接側 莰側上的接觸點可以規律&1234002 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a transfer device for testing one or a conductor assembly. In particular, the present invention relates to a transfer circuit used for testing a circuit and other general g-like conditions. Adapters for non-elemental conductor assemblies. Each body component having a chip side (such as a wafer carrier) has a plurality of connection points to connect to an integrated circuit, and one of the conductor components is connected to the side with a flat and large contact point to Connect to another conductor assembly. The contact points on the 侧 side of the connection side can be regular &
格狀作配置。 【先前技術】The grid is configured. [Prior art]
已知用於測試非元件式之電路板装置原則上可劃分 為兩個群組。第一個群組包括具有數個轉接器的裝置，稱 之為平行測試器（paraiiel testers)，其中一電路板的所有接 觸點可使用一轉接器同步作接觸。第二個群組包括所謂的 指狀測試器（finger testers)。此等裝置可依序以兩個或更多 的測試指狀物檢閱各個接觸點。 該荨具有轉接器之測試器係揭示於下列專利案中，例 如· DE 42 37 591 A1、DE 44 06 538 A1、DE 43 23 276 A、 EP 215 146 B1 以及 DE 3 8 38 41 3 A1。 上述該等轉接器基本上係用於將欲測試電路板之該 等接觸點的不對稱配置匹配至該電子測試器之預設基本格 子。在欲測試之現今電路板中，該等接觸點不再配置成均 勻的格子狀，因此該轉接器中於該接觸格子及該接觸點之 3 1234002 間進行連接的該等接觸針係配置成一傾斜或偏斜狀，或配 置一所谓的轉換器（translator),用以將該均勻的接觸格子 轉換」成不對稱配置的接觸點。此等轉接器也因而稱作 格子匹配式轉接器。 不論裝置的種類為何，非元件式之電路板的各個導體 路徑都會進行該等導體路徑（開路電路測試）中的電路中斷 測试以及至其他導體路徑（短路電路測試）的電性連接測 试。該短路測試可包括低阻抗及高阻抗連接的檢測。 不同的量測技術已熟知於開路電路測試及短路電路 測試中。此包含測試每一導體路徑以檢視是否短路以及測 試每一導體路徑的分支以檢視電路是否中斷，故對具多重 導體路徑的現今電路板而言，必須執行相應大量的各個量 測操作。 由歐洲EP 〇 508 062 B1之專利安士 〇 Λ 号刊案中已知一測試電路 板的方法中，欲測試之電路板係受 ^ db _ & 一非均勻電場的影響 〜非均勻電場具有一由於一量測 ^ 針於一接觸點接通之非 句勻電場所形成之電位，且該電位 喷丨# 係與一參考值及/或其他 / J忒點的電位作比較❹此方法稱為 电場量測。 此電場量測之進一步改良係抵 號盡 T矿田述於EP 0 772 054 A; &辱利案中。於此電場量測的進一 一 t v改良中，於測試一第 €路板時，該各個導體路徑係藉 精電場量測以測試是否短 ’並藉電阻量測以檢視電路是否6份 計I 中斷。由所得的量測值 °界導納（admittances)以作為測蛣 納。 另一電路板的參考導 相'由利用此4參考導納來測古史s ^乃一電路板時，便可能 Ϊ234002 #由電場量測來測試各個導體路徑是否短路及電路中斷。 美國專利案US 5，2 68,645及US 5,903,1 60(其係分別 對應歐洲專利案EP 0 508 062 B1及EP 0 772 054 A2)，該 $專利案之揭示内容係合併於本申請案以作為參考。 德國專利案DE 1 97 00 505 A1係揭示一用以測試電 路把 双之方法，其中一電路板的許多電源網路以及/或接地網 咏至短路，且具有高測試電壓的信號網路係對照此等網 路的結合以測試是否短路。此包含首先施予該等結合網路 向電位，並接著對照此結合測試各個信號網路U藉由此 方式將可明顯減少測試的數量，也由於該等信號網路不需 對照每一電源及/或接地網路作測試，故會因包含高電壓而 非常節省時間。 於該所謂晶片載體的測試中，該測試裝置需具有特別 需求。晶片載體一侧有小的電路板或導體組件，該晶片側 及該等接觸點可不需罩體而直接與一或多個積體電路連 接，且藉由結合而電性連接至該晶片載體的接觸點。於該 晶片側之每一該等接觸點係藉導體路徑而電性連接至該晶 片載體相對側上的接觸點，即該連接側。該晶片載體可為 三維結構（參照US 5,006,093號專利案）。 於該晶片側之該等接觸點一般較小且彼此配置緊 密。以技術名詞來說稱為「高強度（high-pitch)」。在該連 接側上之該等接觸點通常較多且一般係配置呈格子狀。一 般係呈球閘陣列（ball grid array，BGA)狀之格子。上述晶片 載體係示範性描述於 MC2M®BGA Type Multi-Chip 1234002Known circuit board devices for testing non-components can in principle be divided into two groups. The first group includes devices with several adapters, called parallel testers, in which all contacts of a circuit board can be contacted simultaneously using one adapter. The second group includes so-called finger testers. These devices can sequentially review each contact point with two or more test fingers. This tester with an adapter is disclosed in the following patents, for example: DE 42 37 591 A1, DE 44 06 538 A1, DE 43 23 276 A, EP 215 146 B1 and DE 3 8 38 41 3 A1. The aforementioned adapters are basically used to match the asymmetrical configuration of the contact points of the circuit board to be tested to the preset basic cell of the electronic tester. In the current circuit boards to be tested, the contact points are no longer arranged in a uniform grid pattern, so the contact pins in the adapter that are connected between the contact grid and 3 1234002 of the contact points are configured into one It is inclined or skewed, or a so-called translator is provided to transform the uniform contact grid into asymmetrically arranged contact points. These adapters are therefore also called grid-matched adapters. Regardless of the type of device, each conductor path of a non-component circuit board is subjected to a circuit interruption test in these conductor paths (open circuit test) and an electrical connection test to other conductor paths (short circuit test). The short-circuit test may include detection of low-impedance and high-impedance connections. Different measurement techniques are well known in open circuit and short circuit tests. This involves testing each conductor path to see if it is short-circuited and testing each branch of the conductor path to see if the circuit is interrupted, so for today's circuit boards with multiple conductor paths, a correspondingly large number of individual measurement operations must be performed. A method for testing a circuit board is known from the European EP 0508 062 B1 patent Anshi No. 0Λ. The circuit board to be tested is affected by ^ db _ & a non-uniform electric field. Because the potential formed by a measuring pin at a non-sentence uniform electric field connected at a contact point, and the potential spraying # is compared with a reference value and / or other potential at the J 忒 point, this method is called For electric field measurement. The further improvement of this electric field measurement was achieved as far as possible. The T ore field is described in the EP 0 772 054 A; & In the further improvement of this electric field measurement, when testing a first circuit board, each conductor path is measured by a precise electric field measurement to test whether it is short ', and a resistance measurement is used to check whether the circuit is 6 parts. Break. From the obtained measured values, admittances are used as the measured admittances. The reference phase of another circuit board is used to measure the ancient history by using this 4 reference admittance. ^ When the circuit board is a circuit board, it is possible to measure 234002 #Electric field measurement to test whether each conductor path is short-circuited and the circuit is interrupted. US patents US 5,2 68,645 and US 5,903,1 60 (which correspond to European patents EP 0 508 062 B1 and EP 0 772 054 A2, respectively), the disclosure of this $ patent case is incorporated in this application as reference. The German patent case DE 1 97 00 505 A1 discloses a method for testing circuit pairs. Many power networks and / or ground networks on a circuit board are short-circuited, and a signal network with a high test voltage is compared. These networks are combined to test for short circuits. This includes first applying the combined network to the potential, and then testing each signal network against this combination. In this way, the number of tests can be significantly reduced, and because these signal networks do not need to check each power source and / Or a grounded network for testing, so it can save time by including high voltages. In the so-called wafer carrier test, the test device needs to have special requirements. There is a small circuit board or conductor component on one side of the chip carrier, and the chip side and the contact points can be directly connected to one or more integrated circuits without a cover, and electrically connected to the chip carrier by bonding. Contact point. Each of these contact points on the wafer side is electrically connected to a contact point on the opposite side of the wafer carrier by a conductor path, that is, the connection side. The wafer carrier may have a three-dimensional structure (refer to US Pat. No. 5,006,093). The contact points on the wafer side are generally small and closely arranged with each other. In technical terms, it is called "high-pitch". The contact points on the connection side are usually many and are generally arranged in a grid pattern. It is generally a grid in the shape of a ball grid array (BGA). The above wafer carrier is exemplarily described in MC2M®BGA Type Multi-Chip 1234002
Modul s之文中。此篇可由網址w w· v a 11rο ni c · c h取得。該 等曰曰片載體係進一步揭示於美國專利案us 5,〇66,963中。 月J述4晶片載體之晶片側上的該些接觸點係經精密 建置且彼此緊靠，故無法與普通轉接器接觸。且該等晶片 載體係大批量生產的，因此無法以_平行測試器去測試該 等曰曰片載體。若以傳統的指狀測試器來測試，雖然該晶片 側之該等接觸點亦可作接觸，但由於依序檢閱測試該晶片 載體的所有接觸點需耗費大量時間，&不符合經濟效益。 因此，為测試該等晶片載體，業界已著手發展具有一設有 數個接觸元件（用以接觸該連接側）之轉接器的特殊測試裝 置"亥等接觸元件係經配置以與該連接側上該晶片載體的 接觸點相對應。通常轉接器之該些接觸元件係以預定格狀 進行配置，尤其係以BGA型式的格狀。另一方面，該晶片 載體的曰曰片側係藉大量可來回移動的接觸指來作連接。該 等用於測试晶片載體的裝置因此可結合平行/指狀測試 益。利用此裝置，便可以相當高的處理量來測試該等晶片 載體。然而此等特別的裝置非常昂貴，因此不但需提供適 ° 平行測試器之電子評估單元，也需提供適合一指狀測 试器之電子評估單元，同時該測試裝置僅可用於各種特殊 的導體組件，亦即該些晶片載體。 由美國US 2 001/013783 A1之專利案中已知一用以 /貝J試非元件式之電路板的裝置，此裝置即所謂的探針段， 其可娘美一具有多個探針之轉接器，欲進行測試之一電路 板係置於此探針段上，該欲作測試之電路板上設有一絕緣 6 Ϊ234002 薄膜 試頭 針係 段、 測試 電子 之電 (bed· 有該 該感 進行 之該 板之 以一 狀測 及非 供一 之一 ’該等測試頭之探針尖端係在該該絕緣薄膜上，該測 可移動以接觸各個電路板測試點。該探針段之該等探 經由轉換裝置連接至一電子評估單元，再由該探針 轉換電子元件以及評估單元組成之該單元形成一平行 器。 由德國DE 44 1 7 580 C2之專利案中已知一用以測試 電路板的裝置。此測試裝置係用以測試具有電子元件 路板。此處所述之該測試裝置具有一針床 •〇f-nails)型式之轉接器，於其上置有欲測試之板。含 專電子元件之該板的上表面係以一感應陣列作接觸， 應陣列具有一可於該板上移動之接觸針。並對此裝置 該各個電子元件的功能測試，其係類似於前文所描述 結合之平行/指狀測試器。 由德國DE 3838413A1之專利案中已知一用於電路 轉接器或一電子測試器，該電路板上之接觸區域具有 導電性彈簧體製成的墊狀插塞。 歐洲專利案EP 0 772 054 A2係關於一用於連接一指 試器的方法，但轉接器的用途並未揭示於此文中。 本發明係以前述問題為基礎，利用一習知測試裝置以 元件式之導體組件（為晶片載體或類似晶片載體）以提 簡易、測試成本低且快速的測試方法。 前述所提之該等問題可藉申請專利範圍第1項所述 轉接器來解決，其他優點將於該等附屬項中提出。 7 1234002 【發明内容】 依據本發明之一轉接器係用於測試一或多個具有數 個導體路徑於一指狀測試器中之導體組件，其中該導體組 件之一側設有數個接觸點，其與最近之鄰近接觸點相距至 少一預定距離，以便此側之該導體組件可藉由一轉接器進 行接觸，該轉接器至少包含： 具一組接觸元件之至少一接觸區，其中該接觸區之該 等接觸元件係配置成一佈局，而與該導體組件之該等接觸 點相對應’其中該接觸區之每一該等接觸元件係以一方式 電性連接至另一接觸元件，而該方式係指將該導體組件/ 組件群之導體路徑結合以形成一測試網路，該測試網路於 該導體組件/組件群之該側或該等側上具有一或多個未與 该轉接器接觸之接觸點。 本發明因而創作一轉接器，其可用於接觸於一側上之 導體組件’其中該等導體組件之該等導體路徑係電性連接 至此或另一導體組件之一或多個導體路徑。該等測試網路 因而於該導體組件（其非以該轉接器作接觸）之談側上形成 至^ 一接觸點，以讓此等測試網路可藉一指狀測試器之測 試心作接觸。所有欲作測試之導體路徑皆為無法以該轉接 器進行接觸之該導體組件的該側上一可接觸測試網路的一 部份。 ， 此轉接器系統以及一或多個導體組件可固設於一指 狀測忒器中’且該等測試網路可被檢閱。由於經由該轉接 **午多導體路徑可結合成數個測試網路，各個測量操作 8 1234002 都可同步測試數條導體路徑，也就是說，與習知指狀測試 器中的測试相較下，在測試速率上有相當大的提昇。 由於轉接器本身並不直接連接至電子評估單元，故在 與習知平行測試器相較時，它可以簡易且成本低的方式製 造。若該導體組件的接觸點是以一預定的標準格子作配置 時前述方式特別適用。對上述導體組件而言，在某些情況 下甚至可用於標準化的轉接器，而不必特別為某些導體組 件作設計。Modul s article. This article can be obtained from the website w w · v a 11rο ni c · c h. Such tablet carriers are further disclosed in U.S. Patent No. 5,066,963. These contact points on the wafer side of the 4-chip carrier are precisely built and are close to each other, so they cannot be contacted with ordinary adapters. And these wafer carriers are produced in large quantities, so it is impossible to test these wafer carriers with a parallel tester. If a conventional finger tester is used for testing, although the contact points on the wafer side can also be contacted, it takes a lot of time to sequentially inspect and test all the contact points of the wafer carrier, which is not economical. Therefore, in order to test such chip carriers, the industry has started to develop a special test device with an adapter provided with several contact elements (to contact the connection side). The contact elements such as "Hai" are configured to connect with the The contact points of this wafer carrier on the side correspond. Usually, the contact elements of the adapter are arranged in a predetermined grid shape, especially a BGA type grid shape. On the other hand, the wafer side of the wafer carrier is connected by a large number of contact fingers which can be moved back and forth. Such devices for testing wafer carriers can therefore combine the benefits of parallel / finger testing. With this device, the wafer carriers can be tested at a relatively high throughput. However, these special devices are very expensive, so it is not only necessary to provide an electronic evaluation unit for a suitable parallel tester, but also an electronic evaluation unit suitable for a finger tester. At the same time, the test device can only be used for various special conductor components. , That is, the wafer carriers. A device for testing non-component circuit boards is known from the patent of US 2 001/013783 A1. This device is a so-called probe section. Adapter, one of the circuit boards to be tested is placed on this probe section, and the circuit board to be tested is provided with an insulating 6Ϊ234002 thin film test probe needle section, and the test of electronic electricity (bed The test probe's probe tip is attached to the insulating film, and the test can be moved to contact the test points of each circuit board. The probes are connected to an electronic evaluation unit through a conversion device, and the unit consisting of the probe conversion electronic component and the evaluation unit forms a parallelizer. It is known from German patent DE 44 1 7 580 C2 for a Device for testing circuit board. This test device is used to test circuit boards with electronic components. The test device described here has a needle bed type 〇f-nails) type adapter on which it is intended to test The board. The upper surface of the board containing specialized electronic components is contacted by an inductive array, and the array should have a contact pin that can be moved on the board. The functional test of each electronic component of the device is similar to the parallel / finger tester combined as described above. From German patent DE 3838413 A1, a circuit adapter or an electronic tester is known. The contact area of the circuit board has a pad-shaped plug made of a conductive spring body. European patent EP 0 772 054 A2 relates to a method for connecting a tester, but the purpose of the adapter is not disclosed here. The present invention is based on the foregoing problems, and uses a conventional test device with a component-type conductor assembly (which is a wafer carrier or a similar wafer carrier) to improve a simple, low-cost, and fast test method. These problems mentioned above can be solved by the adapter described in item 1 of the scope of patent application, and other advantages will be raised in these subsidiary items. 7 1234002 [Summary of the invention] An adapter according to the present invention is used to test one or more conductor assemblies having a plurality of conductor paths in a finger tester, wherein one side of the conductor assembly is provided with a plurality of contact points. , Which is at least a predetermined distance from the nearest adjacent contact point, so that the conductor component on this side can be contacted by an adapter, the adapter at least comprising: at least one contact area with a set of contact elements, wherein The contact elements of the contact area are arranged in a layout corresponding to the contact points of the conductor component. 'Each of the contact elements of the contact area is electrically connected to another contact element in a manner, The method refers to combining the conductor paths of the conductor component / component group to form a test network, and the test network has one or more on the side or the sides of the conductor component / component group that are not connected with the side. Contact point for adapter contact. The invention thus creates an adapter that can be used to contact a conductor component on one side ', wherein the conductor paths of the conductor components are electrically connected to one or more conductor paths of this or another conductor component. The test networks thus form a contact point on the side of the conductor assembly (which is not in contact with the adapter), so that these test networks can borrow the test heart of a finger tester contact. All conductor paths to be tested are part of a contactable test network on the side of the conductor assembly that cannot be accessed with the adapter. This adapter system and one or more conductor components can be fixed in a finger tester 'and the test networks can be inspected. Since the multi-conductor path can be combined into several test networks via this transfer **, each measurement operation 8 1234002 can simultaneously test several conductor paths, that is, compared with the test in the conventional finger tester There is a considerable improvement in the test rate. Since the adapter itself is not directly connected to the electronic evaluation unit, it can be manufactured in a simple and cost-effective manner when compared to conventional parallel testers. The foregoing method is particularly applicable if the contact points of the conductor assembly are arranged in a predetermined standard grid. For the above-mentioned conductor assemblies, in some cases it can even be used for standardized adapters without having to specifically design certain conductor assemblies.
依據本發明之一較佳實施例，該導體組件/組件群之 導體路徑係經由轉接器作電性連接，該測試網路於該導體 組件/組件群（未與該轉接器接觸）之該側或該等側上具有 至少兩個接觸點。在一測試網路中供應至少兩個接觸點可 允許以一電阻量測的方式進行測試網路的開路測試。由於 許多導體組件的製造商認為在高阻抗電路中斷的情況下電 阻量測是最可靠的方式，因此會要求該些導體組件的導體 路徑能以一電阻量測的方式進行電路中斷測試。According to a preferred embodiment of the present invention, the conductor path of the conductor component / component group is electrically connected via an adapter, and the test network is in the conductor component / component group (not in contact with the adapter). There are at least two contact points on the side or sides. Supplying at least two contact points in a test network allows an open circuit test of the test network by means of a resistance measurement. Since many manufacturers of conductor assemblies consider resistance measurement to be the most reliable method in the event of a high-impedance circuit interruption, the conductor paths of these conductor assemblies are required to be able to perform circuit interruption tests in a resistance measurement manner.
轉接器若以上述方式設計，在一指狀測試器中該導 組件之該等導體路徑將可快速且容易的利用電阻量測進 電路中斷測試。在此處並非指該等轉接器本身連接至該 子評估單元，而是只有料測試指去連接。因此依據本 明之轉接器可以較低成本去製造並延伸指狀測試器的使 領域，也因為大幅降低測試時間，相較於某些僅以平行 試器或特定設計之測試^的測試特定導體組件的轉接 而言，前述使用指狀測試器測試特定導體組件之轉接器 9 1234002 進行測試是較經濟的方式。 依據本發明之轉接器亦允許兩側具有接觸點之導體 組件以其單邊的指狀測試器來作測試。因此依據本發明之 轉接器，習知單邊指狀測試器的應用範圍可擴大至兩邊具 有接觸點的導體組件。使用本發明之轉接器，不同導體組 件之導體路徑可電性連接至一單一測試網路。本發明之轉If the adapter is designed in the manner described above, the conductor paths of the conducting element in a finger tester can quickly and easily use the resistance measurement into the circuit to interrupt the test. This does not mean that the adapters themselves are connected to the sub-evaluation unit, but only the test materials are meant to be connected. Therefore, the adapter according to the present invention can manufacture and extend the field of the finger tester at a lower cost, and because the test time is greatly reduced, compared to the test of certain conductors with only parallel testers or specific design tests ^ In terms of component transfer, the aforementioned test of the adapter 9 1234002 using a finger tester for a specific conductor component is a more economical way. The adapter according to the present invention also allows a conductor assembly having contact points on both sides to be tested with a single-sided finger tester. Therefore, according to the adapter of the present invention, the application range of the conventional single-sided finger tester can be extended to a conductor assembly having contact points on both sides. With the adapter of the present invention, the conductor paths of different conductor components can be electrically connected to a single test network. Turn of the invention
體組件之導體路徑可經由該轉接器彼此電性連接，而不同 導體組件之導體路徑亦可藉該轉接器作連接以形成一測試 網路。 較佳而言，許多導體路徑亦可藉該轉接器彼此電性連 接以形成幾個測試網路，較理想者係僅形成兩個測試網 路。這裡便可將所謂的鄰近屏蔽準則（Shielded Adjacency Criterion)列入考量，亦即，由於該些導體路徑在導體組件 中的位置，僅有不會與其他相關測試網路的導體路徑形成 短路之導體路徑可藉轉接器彼此連接，這是因非此測試網 路一部份的另一導體路徑是配置在它們之間、或者於該導 體組件中另一位置形成邊界層。該等導體路徑與一些測試 、周路的連結即可僅利用該等獨立測試網路（於上述情況下 需彼此對照測量）而使測試短路的量測減少到僅有幾個測 量操作。 提供最；數目的測試網路亦容許高測試電壓的使用 而不會造成時間上的損失，同時也因為測試網路的限制數 目，必須建立的增加電壓僅有幾倍。此原理已描述於德國 10 1234002 專利案DE 197 00 505 A1中，其全文係合併於此作參考。 若特別使用電場量測的方法，該等測試網路可以一單 一測試樣品作短路的測試，且若可得到適合的參考導納， 它們甚至可用於測試電路中斷。 此等測試量測法可以已知的指狀測試器進行，且處理 量並不會比特別設計用於測試晶片載體的測試裝置低。在 用於電場量測時，處理量甚至會增加。 【實施方式】 依據本發明之一轉接器1係用於測試四個晶片載韻 2,如第3圖所示之概要透視圖。該轉接器具有一轉接器本 體3，於此實施例中其係一非導電性之塑膠薄板材料。於 §亥轉接器本體3中有數個通孔4，每一通孔皆可容納一接 觸針5 ^該等通孔係以兩陣列的方式作配置，每一陣列異 有1 〇 X 1 0個通孔數目《於任何情況下兩鄰近通孔4其中心 至中心的距離皆為〇 · 5 -1 mm。該等通孔4係按規律設置诗 矩形格狀以與一球閘陣列（BGA)相對應。該等接觸針5之 兩端各具有一探針尖端6,7，為簡化圖式，示於第3圖_ 之該等接觸針5係以某些方式凸出該通孔4。於一具體, $ ·中該等接觸針5之探針尖端6,7僅由該轉接器本毙 之上表面8或下表面9延伸出十分之一亳米。該等接角 針5較佳係所謂以一 ^ , 彈黃疋件製成之彈簧接觸針，以讓言 等接觸針5可以彈筈古斗^ 方式進行按壓。該等接觸針較佳係^ 兵縱向中心區域上氧古 、有一抗摩擦劑（anti-fricti〇I1 agent) 1234002 以確保該等接觸針5不會由該通孔4掉出。 該轉接器本體3的兩矣而0 , 表面8及9之每一區域中該等接 十5陣列之該等探針尖 jr . 〇 入’刀別形成一接觸區17 及18以接觸一晶片載體2。 於本發明之—實施例中，上述之晶片載體2係為一具 /曰片側1〇及—連接側11的小電路板（參照第U 2圖）。 ’:的接觸腳12(contact pad)係形成於該晶""〇之上形 平面呈四個彎曲分段丨3的環形。此等接觸腳12係用 於結合積體電路(未示出)。數個導體路徑Μ由此等接觸腳 U的若干者通到該導電孔15。通常所有或至少接觸腳12 係藉一導體路徑14連接至一導電孔ls。於第i至4圖中， 僅簡化示出部分導體路徑14以便於說明。此等導電孔Η 係以球閘陣列的格狀形成在該晶片載體2上，且每一者係 由該晶片側1 0延伸至該連接側丨丨。於該連接側丨丨上，該 等導電孔15每一者皆形成一接觸點16。該等導電孔15係 具有一直徑（例如小於0 · 1 mm)之通孔，其皆以一導電性材 料作元全塗覆或填充。於該接觸點1 6之區域中，該導電性 材料形成一接觸腳1 6 ^該接觸點1 6之直徑明顯大於該晶 片側1 〇上之該接觸腳12的長度或寬度（例如約大於 0.5mm)。該等接觸點16係以前述規則格狀（BGA格子）方 式配置，因此與該晶片側丨〇之該等接觸腳1 2相比間隔較 寬，故較易於與一轉接器接觸。 因為在晶片側上的接觸點密度較高，該些晶片載體一 般係以一多層電路板的方式形成。也因如此，上述型式之 12 1234002 载體中該等 體。笛n 斧寬孔並不總是延伸通過所有的晶片載 昂1至4圖p…， 匕从此態樣概要式作簡化。 該痒晶片葡 體路# 體之一典型特徵係所有或至少的主要導 二’、由該晶片也 中，益丄 彳】導引至該連接側。於本發明之實施例 τ 耨由這些導 接。# & — 零孔可影響該該晶片側至該連接側的連 牧 右為複雜晶片番ω 片伽卜& 1 戰體的情況下，該等導體路徑僅由該晶 A W上兩接觸點 路徑的數目較心 會導引至該連接側，故該等導體 為測試上述At由曰晶^則導引至連接側者為少。 點16置於一组探I载體2，—晶片載體2係以其接觸 17。將另一晶片栽f ^ 、 探針尖端形成一接觸區 上形成另-接觸區！以其接觸點16置於該探針尖端7 經由該接觸針5彼办 ~接觸區17，18之探針尖端6,7係 做此成對作電性連接， 之接觸點16彼此成^ M讓兩晶片載體2 战辦作電性連接（如 於本發明之〜 第4圖所示）。 I施例中’轉接器 載體2，並以相對晶μ + 1上可固設兩對晶片 日曰片戴體2之接觸駐t 連接。 觸·，έ 1 6彼此成對作電性 為了進行測試，轉 得接器1及晶片恭 測試器20中（如第7画 取體2係設於一指狀 圖所示）。上述— 數個測試指2 1，每〜 *日狀測試器20具有 測武指係集成一測H α 試電極22係連接至〜 j減電極22。該等測 電子評估單元。妗纷、 座2 3 (平行於該晶片截辦 〜專測試指2 1在滑 體2之表面）的暂丄 之上表面及下表面作伞>μ 助下可於該轉接器 订移動，以讓哕 載體2之接觸腳12作挺細 喊巧等電極可藉該晶片The conductor paths of the body components can be electrically connected to each other through the adapter, and the conductor paths of different conductor components can also be connected by the adapter to form a test network. Preferably, many conductor paths can also be electrically connected to each other through the adapter to form several test networks. Ideally, only two test networks are formed. Here, the so-called Shielded Adjacency Criterion can be taken into consideration, that is, due to the position of these conductor paths in the conductor assembly, only the conductors that do not form a short circuit with the conductor paths of other related test networks The paths can be connected to each other by an adapter, because another conductor path that is not part of the test network is arranged between them or forms a boundary layer at another location in the conductor assembly. The connection of these conductor paths with some tests and circuits can only use these independent test networks (in the above case, they need to be measured against each other) to reduce the test short circuit measurement to only a few measurement operations. Provide the most; the number of test networks also allows the use of high test voltages without loss of time. At the same time, because of the limited number of test networks, the increased voltage must be established only a few times. This principle has been described in German Patent No. 10 1234002 DE 197 00 505 A1, which is incorporated herein by reference in its entirety. If the method of electric field measurement is used in particular, these test networks can be used for short-circuit tests on a single test sample, and if suitable reference admittances are available, they can even be used to test circuit interruptions. These test measurements can be performed with a known finger tester and the throughput is not lower than a test device specifically designed for testing wafer carriers. When used for electric field measurement, the throughput can even increase. [Embodiment] An adapter 1 according to the present invention is used to test four wafers carrying rhyme 2, and is a schematic perspective view shown in FIG. The adapter has an adapter body 3, which is a non-conductive plastic sheet material in this embodiment. There are several through holes 4 in the body of the adapter adapter 3, each through hole can accommodate a contact pin 5 ^ These through holes are configured in two arrays, each array has 10 × 10 The number of through holes "In any case, the distance from the center to the center of two adjacent through holes 4 is 0.5-1 mm. The through-holes 4 are arranged in a regular rectangular grid pattern to correspond to a ball grid array (BGA). Each of the contact pins 5 has a probe tip 6, 7 at both ends. In order to simplify the drawing, the contact pins 5 shown in FIG. 3 are protruded from the through hole 4 in some ways. In a specific example, the probe tips 6, 7 of the contact pins 5 in this case extend only one tenth of a meter from the upper surface 8 or the lower surface 9 of the adapter itself. The angle pin 5 is preferably a so-called spring contact pin made of a piece of yellow ,, so that the contact pin 5 can be pressed in the manner of popping the ancient bucket ^. The contact pins are preferably an anti-frictiIl agent 1234002 on the longitudinal center region of the soldier to ensure that the contact pins 5 do not fall out of the through hole 4. The two sides of the adapter body 3 and 0, the surfaces 8 and 9 are connected to the probe tips jr of the ten-fifth array in the area of the adapter body. Wafer carrier 2. In the embodiment of the present invention, the above-mentioned wafer carrier 2 is a small circuit board with a chip side 10 and a connection side 11 (refer to FIG. 2). The contact pad 12 is formed on the surface of the crystal " ". The plane has a ring shape with four curved sections. These contact pins 12 are used to integrate an integrated circuit (not shown). A plurality of conductor paths M lead to the conductive hole 15 from several of the contact pins U. Usually all or at least the contact pins 12 are connected to a conductive hole 1s via a conductor path 14. In figures i to 4, only a part of the conductor path 14 is shown in simplified form for ease of explanation. These conductive holes Η are formed on the wafer carrier 2 in a grid shape of a ball brake array, and each of them extends from the wafer side 10 to the connection side 丨 丨. Each of the conductive holes 15 forms a contact point 16 on the connection side. The conductive holes 15 are through holes having a diameter (for example, less than 0.1 mm), which are all fully coated or filled with a conductive material. In the region of the contact point 16, the conductive material forms a contact pin 16 ^ The diameter of the contact point 16 is significantly larger than the length or width of the contact pin 12 on the wafer side 10 (for example, about 0.5 mm). The contact points 16 are arranged in a regular grid pattern (BGA grid), so they are wider than the contact pins 12 on the chip side, so they are easier to contact with an adapter. Because of the high density of contact points on the wafer side, these wafer carriers are generally formed as a multilayer circuit board. Because of this, these bodies are in the 12 1234002 carrier of the above type. The wide hole of the axe axe does not always extend through all the wafers. Angular figures 1 to 4 p ..., the dagger is simplified from this aspect. One of the typical features of the itchy chip glucose body is all or at least the main guide. It is guided by the chip to the connection side. In the embodiment τ of the present invention, these are connected. # & — Zero hole can affect the right side of the wafer to the connection side of Lian Mu is a complex wafer Fan ω Gabbana & 1 war, these conductor paths are only made by the two contact points on the crystal AW The number of paths is more guided to the connection side, so the conductors are less guided to the connection side for testing the above At. Point 16 is placed on a set of probe carriers 2-the wafer carrier 2 is in contact 17. Place another wafer f ^, and the probe tip forms a contact area to form another contact area! The contact point 16 is placed on the probe tip 7 via the contact pin 5 ~ the probe points 6, 7 of the contact areas 17, 18 are electrically connected in pairs, and the contact points 16 form each other ^ M Let the two chip carriers 2 be electrically connected (as shown in Figure 4 of the present invention). In the embodiment, the adapter 2 is connected to the carrier 2 with two pairs of wafers on the opposite crystal μ + 1. Touch, έ 1 and 6 are paired with each other for electrical testing. For the test, the connector 1 and the wafer tester 20 are transferred (as shown in Figure 7). Above — several test fingers 21, each ~ * Sun shape tester 20 has a test finger integrated with a test H α test electrode 22 connected to ~ j minus electrode 22. The measurement electronics evaluation unit.妗, seat 2 3 (parallel to the chip cut-off ~ special test finger 2 1 on the surface of the slider 2) temporary upper and lower surfaces as umbrellas > μ can be ordered to move on the adapter In order to make the contact pin 12 of the carrier 2 make a very thin call, the electrode can be borrowed from the chip.
接觸。上述一相壯、日I &測試器具有數個（例 13 1234002 指 器 至 之 旋 置 於 接 包 述 片 常 電 量 由 路 測 載 因 接 該 如1 6個）測試指2 1，在該轉接器1上可以例如八個測試 於上方，八個測試指於下方的方式作配置，以讓該轉接 1兩側上的晶片載體2可作連接。每一測試指21係固定 一滑座23，該滑座23可滑動於一平行該轉接器1表面 平面上。每一該等滑座23具有一垂直校準作動汽缸24 該等測試指 21可藉由該作動汽缸24而繞著該垂直軸 轉。該等測試指21亦可結合一活動裝置，以藉該活動裝 使該接觸腳12可以一正確角度移至該晶片載體2之表S 以讓該等接觸腳1 2可與該測試電極22作接觸。 該接觸點1 6之成對連接係藉轉接器1流通，例如 各情況下該兩晶片載體2之兩導體路徑2 5係彼此電性連 並與該連接器（於本實施例中（即第3及4圖所示者）至少 含該等接觸針5之一者）形成一測試網路。每一情況下上 一測試網路之該些端點係以一接觸腳1 2成形。由於該晶 載體之該些導體路徑2 5並未分支，故上述一測試網路通 僅有兩端點。此兩端點及對應之接觸腳1 2可藉該等測試 極22之一者作同步接觸。若藉由該測試電極22可將一 測電流施予該測試網路以判定該測試網路之電阻，則可 此量測結果斷定兩晶片載體2之兩導體路徑25是否有電 中斷，此相當於習知用以測試是否電路中斷之電阻量 法。因此，藉由轉接器耦合兩晶片載體，將可在兩晶片 體上以一單一量測去測試導體路徑2 5是否電路中斷，並 此也可同時在兩導體路徑25上測試是否電路中斷。該轉 器本身並不連接至該電子評估單元，於測試操作期間， 14 4〇〇2 螂試網路僅經由該等測試指21連接至該電子評估單元。 電在以電阻量測測試短路時，任何情況下都可藉一測$ 電栈22接觸鄰近之測試網路，並量測兩鄰近測試網路間^ 陡，此處兩對導體路徑25係於同時間進行測試。 兩使用本發明之該轉接胃i將可以一測試操作中至+ ^片載體係同步進行測試的方式於習知指狀測試器^ 磚等晶片載體。該欲作測試< ^ _ Μ & % & 騎 曰曰片載體的處理量可與先 厅述該具有轉接器及測試指之牿抹^ ^ 辕 < 将殊測试裝置相匹配。依 來發明另一實施例之一轉接弩伤-认够< η , 镇 器係不於第5及6圖。此轉 雜1具有其轉接器本體3，复在炎 .a ^ 轉抵^ /、係為一多層電路板。於該 崎器本體3之表面，不同於铪 係u 於剛述之該等探針尖端6,7， 乂導電性橡膠材質製成的拯網1 * 件^ 接觸凸部26,27作為接觸元 此等接觸凸部26,27依次报士、上^ 啷區 ^成兩接觸區17，18，且一接 &内之該等接觸凸部26,27传α μ * 片動 贷乂一對應一欲作測試之晶 趙2之接觸點1 6的陣列推并 26抵A 』進仃定位，以使每一接觸凸部 ’觸一接觸點1 6。於本發明夕 區1 7 一具體實施例中，兩接觸 ，1 8之該等接觸凸點2 6 2 5己复。 /係从一對應BGA之矩陣作 該接觸區17之該箄接自 2δ成似 觸凸4 26係經由電導體路徑 战辦的連接至該接觸區1 8 盤；5说丨也 < 钱觸凸部27，亦即相同行 數及列數的矩陣。通常該等接 17 18 , 觸凸部較佳係設於各接觸區 17，18中之相同位置彼此作 备鉼+ L ., 建接，例如在第6圖左下 ，、。上述該接觸區17，18 同晶片恭雜IV知m X對接觸元件的聯繫對兩相 同曰曰片载體以相同排列被置於診 ^ ί要觸區1 7，1 8上時有相當 15 1234002 影響，該等晶片載體同類型的導體路徑14係彼此電性連 接。由於相同類型的導體路徑1 4係一起作測試（亦即接觸 該晶片載體2之對應接觸腳12以執行一開路剌試），故此 將可大幅簡化測試演算法。 除了以成對方式連接該等接觸區17,18之接觸元件 的導體路徑28外，該轉接器具有一或多個導體路徑29(如 第ό圖所示）以作為電場量測步驟之架空線路（aeriai)。該 電場量測步驟係詳述於歐洲專利案Ep 508 〇62 B1以及Ep 7 2 0 5 4 A 2。藉由該架空線路2 9可开少成一非均勻電場，且 在測試網路中所得的電位可接著由該測試指2ι接通。經由 與另一測試網路及/或一參考值作比較，將可判定該測試網 路是否短路。此電場量測便可僅由相關之測試網路的量測 試樣進行短路測試。 。 右可和用各個測试網路的通道作為參考，在符合依击 歐洲2利EP 〇 772 〇54 A2之方法不，僅以所需測試網s 申的單一測試樣品亦可藉此電場量測方法來判定是否電S 中斷。 I既然每一情況下該等測試網路包含兩晶片載體2之 至^兩導體路徑，便可以一單一量測同步測試至少兩導體 路徑。也由於 、 琢s測方法僅需一單一測試網路去測試電 路是否中斷及/或祐 及紐路，亦可以每一測試樣品同步測試多個 導體路徑。此矣- 、 不欲測試晶片載體2的處理量與習知用於 、式曰曰片載體的特別裝置相比有相當明顯的增加。 據刖文本發明及其實施例所描述之轉接器，於任何 16 1234002contact. The above-mentioned one-phase strong and Japanese I & tester has several (for example, 13 1234002, the finger is placed on the package, and the constant power is connected by the road test load, such as 16). The connector 1 can be configured with, for example, eight tests on the top and eight test fingers on the bottom, so that the chip carriers 2 on both sides of the adapter 1 can be connected. Each test finger 21 is fixed to a sliding base 23, and the sliding base 23 can slide on a plane parallel to the surface of the adapter 1. Each of these slides 23 has a vertically aligned actuating cylinder 24. The test fingers 21 can be rotated about the vertical axis by the actuating cylinder 24. The test fingers 21 can also be combined with a movable device, so that the contact pin 12 can be moved to the table S of the wafer carrier 2 at a correct angle by the movable device, so that the contact pins 12 can work with the test electrode 22 contact. The paired connection of the contact point 16 is circulated by the adapter 1. For example, in each case, the two conductor paths 25 of the two chip carriers 2 are electrically connected to each other and to the connector (in this embodiment (that is, The ones shown in Figures 3 and 4) including at least one of the contact pins 5) form a test network. In each case, the endpoints of the previous test network are formed with a contact pin 12. Since the conductor paths 25 of the crystal carrier are not branched, the above-mentioned test network has only two ends. The two ends and the corresponding contact pins 12 can be synchronized for contact by one of the test electrodes 22. If a test current can be applied to the test network by the test electrode 22 to determine the resistance of the test network, the measurement result can be used to determine whether the two conductor paths 25 of the two chip carriers 2 are electrically interrupted, which is equivalent. The resistance method is used to test whether the circuit is interrupted. Therefore, by coupling the two chip carriers with the adapter, a single measurement can be used to test whether the conductor path 25 is interrupted on the two chip bodies, and it is also possible to test whether the circuit is interrupted on both conductor paths 25 at the same time. The converter itself is not connected to the electronic evaluation unit. During the test operation, the 144002 test network was only connected to the electronic evaluation unit via the test fingers 21. When measuring the short circuit by resistance measurement, in any case, you can borrow a test. The electric stack 22 contacts the adjacent test network and measures the steepness between two adjacent test networks. Here, the two pairs of conductor paths 25 are at Test at the same time. Two use of the transfer stomach i of the present invention will be able to perform a test in a test operation up to + ^ carrier simultaneously, in a conventional finger carrier such as a brick carrier. The test amount < ^ Μ &% & The processing capacity of the carrier can be matched with the test device described above with the adapter and the test finger ^ ^ 辕 < Match the special test device . According to another embodiment of the invention, the crossbow injury is recognized-<η, the ballast is not shown in Figs. 5 and 6. This adapter 1 has its adapter body 3, which is located in Yan.a ^ transferred to ^ /, is a multilayer circuit board. On the surface of the oscillating body 3, it is different from the 铪 system 刚 the probe tips 6, 7 just described, 乂 a life-saving net made of conductive rubber material 1 * pieces ^ contact protrusions 26, 27 as contact elements These contact protrusions 26, 27 are reported in order, and the upper ^ 啷 area ^ is formed into two contact areas 17, 18, and the contact protrusions 26, 27 in one & pass α μ * corresponding to each of the moving loans. An array of contact points 16 of the crystal Zhao 2 to be tested is pushed and positioned 26 to A ′, so that each contact protrusion ′ touches a contact point 16. In a specific embodiment of the invention zone 17 of the present invention, the two contact contacts 18 and the contact bumps 2 6 2 5 are restored. / It is from a matrix corresponding to BGA that the contact area 17 is connected from 2δ into a contact-like convexity. 4 26 is connected to the contact area via an electrical conductor path. 1 8 disks; 5 said also <money touch The convex portion 27 is a matrix having the same number of rows and columns. Usually, these contacts 17 18, the contact protrusions are preferably provided at the same position in each contact area 17, 18 to prepare each other 鉼 + L., For example, in the lower left of FIG. 6. The above-mentioned contact areas 17, 18 are similar to the wafer, and the contact relationship between the contact element and the two identical wafer carriers is placed in the same arrangement in the same arrangement. ^ It is quite 15 when the contact areas 17 and 18 are to be touched. 1234002, the conductor paths 14 of the same type of the chip carriers are electrically connected to each other. Since the same type of conductor paths 14 and 4 are tested together (that is, the corresponding contact pins 12 of the wafer carrier 2 are contacted to perform an open circuit test), the test algorithm can be greatly simplified. In addition to the conductor paths 28 connecting the contact elements of the contact areas 17, 18 in pairs, the adapter has one or more conductor paths 29 (as shown in the figure) as an overhead line for the electric field measurement step. (Aeriai). The electric field measurement procedure is described in detail in European Patent Ep 508 〇62 B1 and Ep 7 2 0 5 4 A 2. The overhead line 29 can be turned into a non-uniform electric field, and the potential obtained in the test network can then be turned on by the test finger 2m. By comparing with another test network and / or a reference value, it can be determined whether the test network is short-circuited. This electric field measurement can be short-circuited only by the measurement samples of the relevant test network. . You can use the channels of each test network as a reference. In accordance with the method of conforming to the European 2nd EP 〇772 〇54 A2, only a single test sample applied for the required test network s can also be measured by this electric field Method to determine if the power S is interrupted. Since each of these test networks includes two chip carriers 2 to two conductor paths in each case, a single measurement can simultaneously test at least two conductor paths. Also, since the test method only requires a single test network to test whether the circuit is interrupted and / or new circuit, it is also possible to test multiple conductor paths simultaneously for each test sample. The processing capacity of the wafer carrier 2 which is not intended to be tested has a considerable increase compared with the special device conventionally used for the wafer carrier. According to the invention described in the invention and its embodiments, the adapter is described in any 16 1234002
情況下’該等接觸區17，18的接觸元件係成對彼此連接。 在以晶片載體形成電路板時，在生產的習慣上係於一電路 板上提供數個晶片載體，其即表示一所謂的形式，例如可 於-電路板上提供五或十個這樣的形式。於這樣的情況下 可方便提供一轉接器，其每一形式係指定於-接觸區，且 各個接觸區相肖m之接^件係'以前述方式&此電性連 接。由於電路板製造商通常會要求作電阻量測以測試是否 電路中斷’在實務上該方法較佳會包含-電阻量測法以及 -電場量測法以測試電路是否中斷或短路。為測試電路是 否中斷，該些測試網路的所有端點必須至少接觸一次而 測試短路時每-測試網路必須；則試一：欠，以同步於各個# 式上或晶片載體上測試該些導體路徑多樣性的可能性。乂 第8圖係表示另一轉接器，與示於第5及6圖之轉接 器有類似設計。此轉接H丨具有—作為轉接器本趙3之電 路板上。轉接器本體3之表面配置成接觸元件者係數個接 觸凸部30’其係以導電性橡膠材料製成。此等接觸凸部形 成-單-接職31，該等㈣凸部每一者係經定In this case, the contact elements of the contact regions 17, 18 are connected to each other in pairs. When forming a circuit board from a wafer carrier, it is customary to provide a plurality of wafer carriers on a circuit board in the production practice, which means a so-called form, for example, five or ten such forms can be provided on a circuit board. In such a case, it is convenient to provide an adapter, each form of which is designated in the contact area, and the contact parts of each contact area are similar to each other in the aforementioned manner. Because circuit board manufacturers usually require resistance measurement to test whether the circuit is interrupted. In practice, the method preferably includes-resistance measurement and-electric field measurement to test whether the circuit is interrupted or shorted. In order to test whether the circuit is interrupted, all the endpoints of these test networks must be contacted at least once and every test network must be tested when the short circuit is tested; then try one: ow, test these in synchronization with each # mode or on the chip carrier Possibility of conductor path diversity.乂 Figure 8 shows another adapter with a similar design to the adapter shown in Figures 5 and 6. This switch H 丨 has-as a switch board of the main board. The surface of the adapter body 3 is configured such that the number of contact protrusions 30 'of the contact elements is made of a conductive rubber material. These contact protrusions form -Single-takeover 31, each of these protrusions is determined
欲測試晶片U 2之該等接觸點的配置，以使一接觸點= 於任何情況下接可以各接觸凸部3〇作接觸。於本發明之 施例中該等接觸凸部30係對應一驗排列成1〇“ 列。 早 於此實施例中，於該陣列之各個列中，該等接觸 30係藉該等導趙路徑32彼此連接。此處於各情況下 體路徑32係連接一該等列之每一第二接觸凸部。提供 17 1234002 體路徑3 2以用於該等接觸凸部之一 此目的可不以多層電路板的形式直接形導體組件為 之表面上。 飞罝接心成於-樣品電路板 於本發明之實施例中，五個接觸 連接，此表示該晶月載體2的五 30彼此係電性 路徑"連接之所有接觸點16都可彼導:雷路：及欲以-導體 1 J後此電性連接。 上述轉接器可用於測試具有數個 11(其係以椤進捻佑A你s * 接觸點16於連接侧 I丹你以帖準格狀佈局作配置）上的晶片 :接器可用於不同晶片載體2’且該等接觸點16之格：： 要佈局相符。此…則…需 =心轉接器以使之可測試於-指狀 測“中，只要該晶片載體2之該等接觸點 狀 標準化並盥唁轉接4 局係為 可。 轉…之該等接觸凸部3〇之佈局相符即 當然也可能以不同方式去互連該等接觸凸部3 如不同列的接觸凸部可彼此電性連接，或彼此電性連 接觸凸部的數目可較多或較少。 於一轉接器上提供數個接觸區31也相當有利，於一 接觸區中該等接觸幻牛（此處係指接觸凸部3())係彼此電： 連接且不同接觸區之各個接觸元件亦可彼此電性連接。 例如於第8圖中所示之轉接器中，各個導體路徑32可於另 一對應之接觸區中電性連接至對應之導體路徑。 第9圖係概要且非常簡化的表示-晶片載體2之該些 導體路徑，其中每—者係由該晶片側指向該連接側。藉由 18 1234002 第8圖中之該轉接器，該等導體路徑之一 _ 第~導體 徑係電性連接，因此兩測試網路33,34係带成於 中，因而於一測試網路之兩鄰近導體路徑間形成其 網路之另一導體路徑。藉此將可確保一測試 二他剛 、 、』崎 < 兩鄰 導體路徑不會形成短路’另一測試網路（配 且於此兩導體 徑之間）之另一導體路徑也不會形成短路。此 辦马鄰近 蔽準則（Shielded Adjacency Criterion)，# 9 丄 ’心疋由於各個導 路徑之各者係以一鄰接之導體路徑屏蔽相同測試網路最 近之導體路徑。以此方式形成之測試網路可確保嗲曰 體中該等導體路徑間的任何短路都可藉由於相關測試= 間（其每一者包含多個的導體路徑）之短路測試檢測出。 外，由於前述許多導體路徑之内連接可顯著減少測試網 的數目，也藉此減少了測量操作步驟。於依據第8圖之 轉接器中，五個導體路徑係彼此連接，其當然亦可讓更 的導體路徑彼此連接，以使之形成至少5〇個導體路徑。 理想係連接所有導體路徑以僅形成兩測試網路，故僅需 行單一量測以測試該晶片載體是否短路。 於一較簡易之實施例中，若目的係為於該晶片載體 供較長、分支的導體路徑（例如電源或接地導體路徑）以 此等較長之導體路徑彼此連接，而得到相對於其他導體 徑為較大的測試網路以作獨立測試時，則可例如將一高 試電壓施於此測試網路一次，並在短時間内對照此高電 施於其他所有欲測試之導體路徑。於此相關之參考請參 德國專利案DE 197 00 505 A1。 路 列 δ式 近 路 屏 體 接 載 路 此 路 該 多 較 進 提 將 路 測 壓 閱 19 1234002 第 片 每 線 作 板 且 線 架 具 該 内 該 有 適 校 之士 第1〇圖係表示依據本發明之另一轉接器，其類似於 3圖所示之設計，相同部分則給予同樣的參考號。The configuration of the contact points of the chip U 2 is to be tested so that a contact point = in any case can be contacted by each of the contact convex portions 30. In the embodiment of the present invention, the contact protrusions 30 are arranged in a 10 "row corresponding to a test. Earlier in this embodiment, in each column of the array, the contacts 30 are borrowed by the guide paths. 32 are connected to each other. Here in each case, the body path 32 is connected to each of the second contact protrusions of one such row. The 17 1234002 body path 32 is provided for one of the contact protrusions. This purpose may not be a multilayer circuit board. The form of the direct-shaped conductor assembly is on the surface. The flying maggot is formed in the sample circuit board in the embodiment of the present invention. The five contacts are connected, which indicates that the five to thirty of the crystal moon carrier 2 are electrical paths. ; All contact points 16 can be connected: Lei Lu: and the electrical connection after -J 1 conductor. The above adapter can be used to test with a number of 11 * The contact point 16 is on the connection side (you use a standard grid layout for the configuration). The chip: the connector can be used for different wafer carriers 2 'and the contact point 16 grid: To match the layout. This ... then ... Need = heart adapter to make it testable in -finger test, as long as the wafer carrier 2 Such a contact point and the gray condolence standardized adapter to be 4 based Board. The layout of the contact protrusions 30 conforming to the turning means that it is of course possible to interconnect the contact protrusions 3 in different ways. For example, the contact protrusions of different columns may be electrically connected to each other, or the contact protrusions may be electrically connected to each other. The number can be more or less. It is also quite advantageous to provide several contact areas 31 on an adapter. In such a contact area, the contacts (herein referred to as the contact protrusions 3 ()) are electrically connected to each other: each contact of the different contact areas The components can also be electrically connected to each other. For example, in the adapter shown in Fig. 8, each conductor path 32 may be electrically connected to the corresponding conductor path in another corresponding contact area. Figure 9 is a schematic and very simplified representation of the conductor paths of the wafer carrier 2, each of which is directed from the wafer side to the connection side. With the adapter in Figure 8 of 12 12002002, one of the conductor paths is electrically connected, so the two test networks 33,34 are integrated in the middle, and therefore in a test network Between two adjacent conductor paths forms another conductor path of its network. This will ensure that one test will not form a short circuit between two adjacent conductor paths, and another conductor path will not form another test network (matched between the two conductor diameters). Short circuit. This Shielded Adjacency Criterion, # 9 丄 ′ heart, because each of the conductive paths shields the nearest conductive path of the same test network with an adjacent conductive path. The test network formed in this way can ensure that any short circuit between these conductor paths in the antenna can be detected by the short circuit test of the relevant test = interval (each of which contains multiple conductor paths). In addition, the internal connection of many of the aforementioned conductor paths can significantly reduce the number of test nets, thereby reducing the number of measurement operations. In the adapter according to Fig. 8, the five conductor paths are connected to each other. Of course, it is also possible to connect more conductor paths to each other so as to form at least 50 conductor paths. Ideally, all conductor paths are connected to form only two test networks, so only a single measurement is required to test whether the chip carrier is shorted. In a simpler embodiment, if the purpose is to provide a longer, branched conductor path (such as a power or ground conductor path) to the chip carrier to connect these longer conductor paths to each other, to obtain relative to other conductors. When the test network with a larger diameter is used for independent testing, for example, a high test voltage can be applied to the test network once, and this high power can be applied to all other conductor paths to be tested in a short time. Reference is made in this respect to German patent application DE 197 00 505 A1. The δ-type short-circuit screen body of the road can take the road. This road should be more advanced than the road test. 19 1234002 The first piece of each line is used as a board and the line frame should have a suitable person. Figure 10 shows the basis. Another adapter of the present invention has a design similar to that shown in FIG. 3, and the same parts are given the same reference numbers.
該轉接器1為一具有四個1 〇 X 10通孔4之陣列，每 者支撐一接觸針5，因此形成八個接觸區以支撐八個晶 載體2。鄰接每一轉接器本體3者係架空線路板35，於 架空線路板上設一電纜3 6以將電位應用用於該架空 路板上的架空線路。該架空線路板35上具有數個通孔以 為該等接觸針5的通道。該架空線路可形成於架空線路 35中作為一垂直延伸出所有架空線路板35之接觸層， 僅於該通孔區域絕緣以容納該等接觸針5。然而該架空 路亦可呈複雜結構。 第圖所示之轉接器同樣具有與該轉接器本體3 空線路板35㈣外徑之兩校準板37。此等校準 有四個…，其較欲量測之晶片載體2之二板略3:、 等孔检3 8下部略為縮減，以於每-孔徑3 8處形成一 突出之連續邊界板39,晶片載體可***每一孔徑38, 晶片載體之端部係相適於該邊界板39。The adapter 1 is an array with four 10 × 10 through-holes 4, each supporting a contact pin 5, thus forming eight contact areas to support eight crystal carriers 2. Adjacent to each adapter body 3 is an overhead wiring board 35, and a cable 36 is provided on the overhead wiring board to apply a potential to the overhead wiring on the overhead wiring board. The overhead wiring board 35 has a plurality of through holes for the passages of the contact pins 5. The overhead line can be formed in the overhead line 35 as a contact layer extending vertically out of all the overhead line boards 35, and is insulated only in the through-hole area to accommodate the contact pins 5. However, the overhead road can also have a complex structure. The adapter shown in the figure also has two calibration plates 37 with the outer diameter of the adapter body 3 empty circuit board 35 本体. There are four of these calibrations, which are slightly smaller than the two plates of the wafer carrier 2 to be measured :, the lower part of the isopore inspection 3 8 is slightly reduced to form a protruding continuous boundary plate 39 at each aperture 38, The wafer carrier can be inserted into each aperture 38, and the end of the wafer carrier is adapted to the boundary plate 39.
:广準板37、該架空線路板35以及轉接器本體3 相對應之孔洞40，該孔洞中為螺 =或螺帽…螺狀連接裝置可使裝:於： >反7及連接器本體及架空線路板^ 、 W 一 极3 5彼此鉗緊以彬 早疋，同時各個晶片載趙係藉該校準板37按遷：: Guangzhun board 37, the overhead circuit board 35, and the hole 40 corresponding to the adapter body 3, the hole is a screw = or nut ... The screw-shaped connection device can be installed in: > anti 7 and connector The main body and the overhead circuit board ^ and W pole 3 5 are clamped to each other so that they can be moved to each other at the same time. At the same time, each chip containing Zhao is relocated by the calibration plate 37:
隆觸區。 +板37按壓於該對J 該螺狀連接裝置 41代表一夾甜裝置 ’此等夾鉗裝置 20 1234002 係均勻分散於該轉接器1之表面’因此該轉接器1係承受 均勻負載。 於轉接器上藉校準板37钳緊該等晶片載體之轉接器 可安裝成一指狀測試器之單元並作測試。在該指狀測試器 中本身並不需要其他的固定裝置去支撐該轉接器以及該等 晶片載體。 便捷的夾钳元件也可使用而不需使用前述之螺.狀連 接装置41。Long touch area. The + plate 37 is pressed against the pair of J. The screw-shaped connection device 41 represents a clamp device ‘these clamp devices 20 1234002 are evenly distributed on the surface of the adapter 1’, so the adapter 1 is subjected to a uniform load. The adapter of the wafer carrier is clamped on the adapter by the calibration plate 37. The adapter can be installed as a finger tester and tested. No other fixtures are needed in the finger tester to support the adapter and the wafer carriers. Convenient clamp elements can also be used without using the aforementioned screw-like connection means 41.
當然亦有可能不需使用以校準板37以及螺狀連接裝 置41組成的定位裝置（其係直接形成在該轉接器上），而是 設一具按壓形式的固定裝置，其在該指狀測試器中具有對 應的壓力板。 既然是將導體組件鉗緊至該轉接器，在力量上就必須 有所考量，較有利的是於該欲作測試之導體組件的一部份 設一欲鉗緊及校準之轉接器，接著再設欲鉗緊及測試之其 他導體組件組^由於同步鉗緊全部的形式會導致高應力形 成的物理問題’此方法會特別適用於多個導體組·件形成在 電路板的測試，即所謂的形式。在測試有多Of course, it is also not necessary to use a positioning device (which is directly formed on the adapter) composed of a calibration plate 37 and a screw-like connection device 41, but a fixing device with a pressing form is provided, which is in the shape of a finger The tester has a corresponding pressure plate. Since the conductor assembly is clamped to the adapter, strength must be considered. It is more advantageous to set an adapter to be clamped and calibrated on a part of the conductor assembly to be tested. Then set other conductor component groups to be clamped and tested ^ because of the simultaneous clamping of all forms will cause physical problems of high stress formation 'This method will be particularly suitable for the test of multiple conductor groups and components formed on the circuit board, that is, The so-called form. How much is tested
路板時，僅將一列形式鉗緊至轉接器會較為有利，在未 有兩爽鉗橫桿之校進把昧，生 _ 早板時母一者經配置以鄰近該電路 上該列形式的兩側並甜緊 I甜冢主該轉接器本體。 測試有許多形式之電& ^^路板的另外方法係提供一可 於測試僅一個或彼少形式的 右 轉接态，亦即，此轉接器僅 有—個或少數的接觸區。 W接器藉適當的機構按壓至 21 1234002 電路板之一側（為該轉接器可觸及者），並進行相關的量測 操作。在完成量測操作後，藉機構移開該轉接器使之與電 路板相距一短距離，並對照所按壓者移動至另一形式，接 著可執行其他的量測操作。該轉接器因此可步進於各個形 式間或少數形式群組間。 本發明之範圍内當然亦包括僅以架空線路來取代須 特定設於轉接器（晶片載體上具導體路徑）中的架空線路。 此可特別應用在當晶片載體具有較大且較多分支的導體路 徑時，例如用於電源供應或接地的導體路徑。 依據本發明之轉接器已詳細解釋於前文以及測試晶 片載體的實施例中。然而依據本發明之轉接器也不僅可用 於測試晶片载體，也可用於測試於一側有接觸點之任何類 型導體組件（指一側之接觸點彼此非配置非常緊密以及例 如有至少0.5mm之間隔者）。且另一側之接觸點可以所欲 之任何方式形成。由於上述接觸點可毫無困難以測試指作 接觸，故該些接觸點可非f小且彼此緊密。依據本發明之 轉接器及指狀測試器亦可測試晶片側區域具有三維外形之 晶片載體。 本發明可簡略摘要如下： 本發明係關於一用於測試一導體組件之轉接器，其特 别用於測4曰曰片載體。上述之導體組件一側具有接觸元 件’其配置非呈高密度且具有約〇 5mm之最小間距，該轉 接器至少具有兩接觸區，每一接觸區有一組接觸元件，其 中轉接器接觸區之該等接觸元件可與接觸點非配置緊密之 22 1234002 導體組件相接觸。接觸區之每一接觸元件係電性連接至另 一接觸區的接觸元件，以讓兩導體組件之導體路徑可彼此 電性連接並可同步進行測試。 【圖式簡單說明】 本發明係以示範例及附加的圖示進行詳述，其中： 第1圖為兩晶片載體之透視圖，分別為該晶片側與該 連接側的側視方向。In the case of a circuit board, it is more advantageous to clamp only one row of the form to the adapter. When there is no alignment of the two clamps, the mother one is configured to be adjacent to the row form on the circuit. The two sides of the adapter are sweet and tight. An alternative method of testing electrical & electrical boards in many forms is to provide a right transition state that can test only one or a few forms, that is, the adaptor has only one or a few contact areas. The W connector is pressed to one side of the 21 1234002 circuit board by the appropriate mechanism (which is accessible to the adapter), and relevant measurement operations are performed. After the measurement operation is completed, the adapter is removed from the circuit board to make it a short distance from the circuit board, and it is moved to another form according to the pressed person, and then other measurement operations can be performed. The adapter can thus be stepped between various forms or groups of minor forms. It is a matter of course that the scope of the present invention also includes only the overhead lines to replace the overhead lines which have to be specially provided in the adapter (the conductor path on the wafer carrier). This is particularly applicable when the wafer carrier has a larger and more branched conductor path, such as a conductor path for power supply or ground. The adapter according to the present invention has been explained in detail in the foregoing and the embodiments of the test wafer carrier. However, the adapter according to the present invention can also be used not only for testing the wafer carrier, but also for testing any type of conductor assembly having contact points on one side (referring to the fact that the contact points on one side are not closely arranged with each other and have at least 0.5 mm Interval). And the contact point on the other side can be formed in any way desired. Since the above-mentioned contact points can be contacted without any difficulty by the test fingers, the contact points may not be small and close to each other. The adapter and the finger tester according to the present invention can also test a wafer carrier having a three-dimensional shape in a wafer-side region. The present invention can be briefly summarized as follows: The present invention relates to an adapter for testing a conductor assembly, and is particularly used for testing a 4-chip carrier. The above-mentioned conductor assembly has contact elements on one side. Its configuration is not high-density and has a minimum pitch of about 0.5mm. The adapter has at least two contact areas, and each contact area has a set of contact elements. These contact elements can be in contact with 22 1234002 conductor components with non-close contact points. Each contact element in the contact area is electrically connected to a contact element in another contact area, so that the conductor paths of the two conductor assemblies can be electrically connected to each other and can be tested simultaneously. [Brief description of the drawings] The present invention is described in detail with an exemplary example and additional drawings, in which: Figure 1 is a perspective view of two wafer carriers, which are the side view directions of the wafer side and the connection side, respectively.
第2圖為第1圖之晶片載體僅有接觸點、導體路徑、 導電孔以及該邊緣邊界的圖示。 第3圖為依據本發明之一具有第1及2圖之晶片載體 的轉接器。 第4圖為第3圖之該轉接器的接觸針陣列以及該等晶 片載體。 第5圖係依據本發明之另一種轉接器的透視圖。Figure 2 is an illustration of the wafer carrier of Figure 1 with only contact points, conductor paths, conductive holes, and the edge boundary. Fig. 3 is an adapter having a wafer carrier according to Figs. 1 and 2 according to the present invention. Figure 4 is the contact pin array of the adapter and the wafer carrier of Figure 3. Figure 5 is a perspective view of another adapter according to the present invention.
第6圖係第5圖之轉接器，顯示該轉接器之各個導體 路徑（以平面圖形式）。 第7圖係一指狀測試器，其中使用一依據本發明之轉 接器。 第8圖係依據本發明之另一轉接器的平面圖。 第 9圖係以較簡化的形式說明一晶片載體互連之導 體路徑的配置。 第1 0圖係一轉接器的透視圖，其上固設有該些晶片 載體。 23 1234002 【元件代表符號簡單說明】 1 轉接器 2 晶片載體 3 轉接器本體 4 通孔 5 接觸針 6、7 探針尖端 8、9 表面 10晶片側 11連接側 1 2接觸腳 1 3彎曲分段 1 4導體路徑 1 5孔洞 1 6接觸點 1 7、1 8 接觸區 20指狀測試器 21測試指 22測試電極 23滑座 24作動汽缸 2 5導體路徑 26、27、30 接觸凸部 24 1234002 28、32 導體路徑 29架空線路 3 1接觸區 33 ' 34 測試網路 3 5架空線路板 36電纜 37校準板 3 8孔徑 3 9邊界板 40通孔 4 1螺狀連接裝置Figure 6 is the adapter of Figure 5, showing the conductor paths (in plan view) of the adapter. Fig. 7 is a finger tester in which an adapter according to the present invention is used. Figure 8 is a plan view of another adapter according to the present invention. Figure 9 illustrates the configuration of the conductor paths of a wafer carrier interconnect in a more simplified form. Fig. 10 is a perspective view of an adapter on which the wafer carriers are fixed. 23 1234002 [Simple description of component symbols] 1 Adapter 2 Wafer carrier 3 Adapter body 4 Through hole 5 Contact pin 6, 7 Probe tip 8, 9 Surface 10 Wafer side 11 Connection side 1 2 Contact pin 1 3 Bend Segment 1 4 Conductor path 1 5 Hole 1 6 Contact point 1 7, 1 8 Contact area 20 Finger tester 21 Test finger 22 Test electrode 23 Slide 24 Actuating cylinder 2 5 Conductor path 26, 27, 30 Contact protrusion 24 1234002 28, 32 Conductor path 29 Overhead line 3 1 Contact area 33 '34 Test network 3 5 Overhead line board 36 Cable 37 Calibration plate 3 8 Aperture 3 9 Boundary plate 40 Through hole 4 1 Screw connection device
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10260238A DE10260238B4 (en) | 2002-12-20 | 2002-12-20 | Adapter for testing one or more ladder arrangements and methods |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200413740A TW200413740A (en) | 2004-08-01 |
| TWI234002B true TWI234002B (en) | 2005-06-11 |
Family
ID=32519240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092132186A TWI234002B (en) | 2002-12-20 | 2003-11-17 | Adapter for testing one or more conductor assemblies |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2006510026A (en) |
| KR (1) | KR100638330B1 (en) |
| CN (1) | CN1714294A (en) |
| AU (1) | AU2003292115A1 (en) |
| DE (1) | DE10260238B4 (en) |
| TW (1) | TWI234002B (en) |
| WO (1) | WO2004059329A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI413777B (en) * | 2010-09-01 | 2013-11-01 | Multi - power circuit board and its application probe card |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4845031B2 (en) | 2006-11-10 | 2011-12-28 | 株式会社ヨコオ | Relay connector |
| KR101396604B1 (en) * | 2006-11-27 | 2014-05-16 | 엘지디스플레이 주식회사 | Apparatus for Testing Liquid Crystal Display Device |
| CN102721835B (en) * | 2012-07-03 | 2014-06-04 | 航天科工防御技术研究试验中心 | Test adapter |
| CN104031823B (en) * | 2014-06-27 | 2016-08-24 | 江苏卓微生物科技有限公司 | cell detection chip and adapter thereof |
| CN104073426B (en) * | 2014-06-27 | 2016-03-30 | 江苏卓微生物科技有限公司 | Cell detection adaptor chip mount pad |
| CN104073427B (en) * | 2014-06-27 | 2016-03-30 | 江苏卓微生物科技有限公司 | Cell detection adaptor chip |
| DE102015113046A1 (en) * | 2015-08-07 | 2017-02-09 | Xcerra Corp. | Positioning device for a parallel tester for testing printed circuit boards and parallel testers for PCB testing |
| CN105044402A (en) * | 2015-08-25 | 2015-11-11 | 贵州航天计量测试技术研究所 | Encapsulated micro-wave voltage-controlled oscillator test device |
| DE102018120337B3 (en) * | 2018-08-21 | 2020-02-27 | Preh Gmbh | TOUCH-SENSITIVE CONTROL FOR A MOTOR VEHICLE |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3838413A1 (en) * | 1988-11-12 | 1990-05-17 | Mania Gmbh | ADAPTER FOR ELECTRONIC TEST DEVICES FOR PCBS AND THE LIKE |
| US5469064A (en) * | 1992-01-14 | 1995-11-21 | Hewlett-Packard Company | Electrical assembly testing using robotic positioning of probes |
| DE19541307C2 (en) * | 1995-11-06 | 2001-09-27 | Atg Test Systems Gmbh | Method for testing electrical conductor arrangements and device for carrying out the method |
| DE19718637A1 (en) | 1997-05-02 | 1998-11-05 | Atg Test Systems Gmbh | Device and method for testing printed circuit boards |
| DE19644725C1 (en) * | 1996-10-28 | 1998-04-02 | Atg Test Systems Gmbh | System for testing electric printed circuit board |
| TW360790B (en) * | 1996-10-28 | 1999-06-11 | Atg Test Systems Gmbh | Printed circuit board test apparatus and method |
| JP3214415B2 (en) * | 1997-10-30 | 2001-10-02 | 日本電産リード株式会社 | Substrate inspection device and substrate inspection method |
| JP2000009755A (en) * | 1998-06-23 | 2000-01-14 | Jsr Corp | Printed wiring board testing jig substrate and printed wiring board testing method |
| DE10024875B4 (en) * | 2000-05-16 | 2004-07-01 | Infineon Technologies Ag | Component holder system for use with test devices for testing electronic components |
-
2002
- 2002-12-20 DE DE10260238A patent/DE10260238B4/en not_active Expired - Fee Related
-
2003
- 2003-11-17 TW TW092132186A patent/TWI234002B/en not_active IP Right Cessation
- 2003-11-25 AU AU2003292115A patent/AU2003292115A1/en not_active Abandoned
- 2003-11-25 KR KR1020057011514A patent/KR100638330B1/en not_active IP Right Cessation
- 2003-11-25 JP JP2004562651A patent/JP2006510026A/en not_active Withdrawn
- 2003-11-25 WO PCT/EP2003/013253 patent/WO2004059329A1/en active Application Filing
- 2003-11-25 CN CNA200380103923XA patent/CN1714294A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI413777B (en) * | 2010-09-01 | 2013-11-01 | Multi - power circuit board and its application probe card |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2004059329A1 (en) | 2004-07-15 |
| JP2006510026A (en) | 2006-03-23 |
| KR100638330B1 (en) | 2006-10-25 |
| DE10260238B4 (en) | 2007-04-05 |
| CN1714294A (en) | 2005-12-28 |
| TW200413740A (en) | 2004-08-01 |
| KR20050091013A (en) | 2005-09-14 |
| DE10260238A1 (en) | 2004-07-22 |
| AU2003292115A1 (en) | 2004-07-22 |
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