TWI233196B - Stackable IC package structure and the method of automatically manufacturing the IC module - Google Patents
Stackable IC package structure and the method of automatically manufacturing the IC module Download PDFInfo
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- TWI233196B TWI233196B TW92133240A TW92133240A TWI233196B TW I233196 B TWI233196 B TW I233196B TW 92133240 A TW92133240 A TW 92133240A TW 92133240 A TW92133240 A TW 92133240A TW I233196 B TWI233196 B TW I233196B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
1233196 五、發明說明（1) 【發明所屬之技術領域】 本案係關於一種積體電路模組及其製造方法，尤指一 種易於堆疊之積體電路模組（S t a c k e d I C Μ〇d u 1 e )及其自 動化之製造方法。 【先前技術】 隨著半導體產業的高度發展，電子產品在積體電路元 件的設計上亦朝向小型化、高速化與高積集度等方向發 展。舉例而言，在電腦或其他電子產品中，影響整體運作 效率之因素除了中央處理器的處理速度外，記憶體的容量 及運作時脈亦是一項相當重要的要素，因此記憶體的製作 亦朝向高容量與小體積的設計方向發展。然而在眾多的結 構與方法中，最有效且最節省製作成本的方式則是將複數 個記憶體晶片以堆疊的型態相互電連接以形成一堆疊之積 體電路模組(S t a c k e d I C Μ 〇 d u 1 e )。 請參閱第一圖，其係顯示一習知以堆疊方式組裝之積 體電路模組結構示意圖。如第一圖所示，該積體電路模組 1 (integrated circuit module)主要是由第一積體電路封 裝單元11 (integrated circuit package unit)與第二積 體電路封裝單元12(integrated circuit package unit) 所堆疊而成，其中每一積體電路封裝單元1 1 、1 2具有一晶 片、一導線架、一封裝材料以及複數個接腳。第一積體電 路封裝單元1 1.係位於下方，而第二積體電路封裝單元1 2則 位於上方，且堆疊後第一積體電路封裝單元1 1及第二積體1233196 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to an integrated circuit module and a manufacturing method thereof, particularly an integrated circuit module (S tacked IC MUdu 1 e) that is easy to stack. And its automated manufacturing method. [Previous technology] With the rapid development of the semiconductor industry, the design of integrated circuit components for electronic products is also moving toward miniaturization, high speed, and high integration. For example, in a computer or other electronic products, in addition to the processing speed of the central processing unit, the factors that affect the overall operating efficiency are also a very important factor in memory capacity and operating clock. Moving towards high-volume and small-volume designs. However, among many structures and methods, the most effective and cost-effective way is to electrically connect a plurality of memory chips in a stacked form to form a stacked integrated circuit module (S tacked IC Μ 〇 〇 du 1 e). Please refer to the first figure, which is a schematic diagram showing the structure of a conventional integrated circuit module assembled in a stacked manner. As shown in the first figure, the integrated circuit module 1 is mainly composed of a first integrated circuit package unit 11 and a second integrated circuit package unit 12 ), Each of the integrated circuit packaging units 1 1, 12 has a chip, a lead frame, a packaging material and a plurality of pins. The first integrated circuit packaging unit 1 1. is located below, and the second integrated circuit packaging unit 12 is located above, and the first integrated circuit packaging unit 11 and the second integrated circuit are stacked.
第8頁 1233196 五、發明說明（2) 電路封裝單元I 2兩側的接腳1 1 1 、1 2 1會彼此相互接觸。此 積體電路模組之堆疊方式簡單敘述如下：首先，將第二積 體電路封裝單元1 2之接腳1 2丨彎折，並利用人工的方式在 第一與第二積體電路封裝單元1 1 、1 2之接腳1 1 1 、1 2 1上點 上錫膠，以使得接腳1 1丨、1 2 i相互連接而電導通。 雖然此種堆疊方式的製作成本較低，但由於須將第二 積體電路封裝單元12之接腳12 1彎折使其與第一積體電路 封裝單元1 1之接腳1 1 1接觸，因此不只破壞了第二積體電 路封裝單元1 2的結構，且堆疊過程仍須採人工作業方式進 行，因而無法達到自動4匕生產之目的。 請參閱第二圖，其係顯示另一習知以堆疊方式組裝之 積體電路模組結構不意圖。如第二圖所不^該積體電路模 組2主要是由第一積體電路封裝單元21 (integrated circuit package unit)、第二積體電路封裝單元22 (integrated circuit package u n i t )與介電材料 2 3 所堆 疊而成，其中每一積體電路封裝單元2 1 、2 2具有一晶片、 一導線架、一封裝材料以及複數個接腳。該結構之堆疊方 法係使第二積體電路封裝單元2 2的接腳2 2丨先利用錫膠黏 固在介電材料2 3上，然後再利用複數個一端事先包覆在介 電材料2 3内而製作成一體的折腳2 3 1 ，由介面材料2 3的邊 緣以錫膠與第一積體電路封裝單元2 1對應的接腳2 1 1連 接。 此種堆疊方式由於須將介面材料2 3上的折腳2 3 1彎 折，再以人工方式上錫膠固定，因此製作成本較高，且無Page 8 1233196 V. Description of the invention (2) The pins 1 1 1 and 1 2 1 on both sides of the circuit packaging unit I 2 will contact each other. The stacking method of this integrated circuit module is briefly described as follows: First, the pins 12 of the second integrated circuit packaging unit 12 are folded, and the first and second integrated circuit packaging units are manually folded. Pins 1 1 1 and 1 2 of 1 1 and 1 2 are soldered with tin glue so that the pins 1 1 丨 and 1 2 i are connected to each other and electrically conductive. Although the manufacturing cost of this stacking method is low, since the pin 12 1 of the second integrated circuit packaging unit 12 must be bent to make contact with the pin 1 1 1 of the first integrated circuit packaging unit 11, Therefore, not only the structure of the second integrated circuit packaging unit 12 is destroyed, but the stacking process still needs to be performed manually, so the purpose of automatic 4k production cannot be achieved. Please refer to the second figure, which shows another conventional integrated circuit module structure assembled in a stacking manner. As shown in the second figure, the integrated circuit module 2 is mainly composed of a first integrated circuit package unit 21, an integrated circuit package unit 22, and a dielectric material. 2 3 is stacked, wherein each integrated circuit packaging unit 2 1, 2 2 has a chip, a lead frame, a packaging material, and a plurality of pins. The stacking method of the structure is that the pins 2 2 of the second integrated circuit packaging unit 2 2 are first fixed to the dielectric material 2 3 with tin glue, and then a plurality of ends are used to cover the dielectric material 2 in advance. 3 are integrated into the folded foot 2 3 1, and the edge of the interface material 2 3 is connected to the corresponding pin 2 1 1 of the first integrated circuit packaging unit 2 1 with tin glue. In this stacking method, the folding feet 2 3 1 on the interface material 2 3 must be bent and then manually fixed with tin glue, so the production cost is high, and there is no
第9頁 1233196 五、發明說明（3) 法以自動化方式大量生產。 請參閱第三圖，其係顯示另一習知以堆疊方式組裝之 積體電路模組結構示意圖。如第三圖所示，該積體電路模 組3主要是由第一積體電路封裝單元31 (integrated c i r c u i t p a c k a g e u n i t )、第二積體電路封裝單元3 2 (integrated circuit package u n i t)與導電體 3 3 、3 4 所 堆疊而成，其中每一積體電路封裝單元3 1 、3 2具有一晶 片、一導線架、一封裝材料以及複數個接腳。該結構之設 計在於利用第一積體電路封裝單元3 1的接腳3 1 1及第二積 體電路封裝單元3 2的接腳3 2 1上分別設一導電體3 3、3 4， 藉對應的導電體3 3 、3 4在上下方向相互搭接以構成電性連 接。該結構之堆疊方式須先將各積體電路封裝單元3 1 、3 2 分別與導電體3 3、3 4對位與完成電性導接，然後再將各導 電體3 3、3 4相互搭接以完成電性連接。然而這樣的設計不 只結構複雜，且其堆疊步驟又十分繁瑣，須將接腳3 1 1 、 3 2 1與導電體3 3、3 4進行二次加工，雖然沒有使用介面材 料，但其製作成本仍然偏高，且須以人工方式進行，亦無 法以自動化方式大量產製。 因此，如何提供一種結構簡單、成本低、易於堆疊且 可自動化生產之積體電路模組（s t a c k e d I C Μ 〇 d u 1 e )結構 及堆疊方法，實為目前迫切需要解決之問題。 【發明内容】 本案之主要目的係提供一種積體電路模組（s t a c k e dPage 9 1233196 V. Description of the invention (3) The method is mass-produced in an automated manner. Please refer to the third figure, which is a schematic diagram showing the structure of another conventional integrated circuit module assembled by stacking. As shown in the third figure, the integrated circuit module 3 is mainly composed of a first integrated circuit package unit 31 (integrated circuit package unit), a second integrated circuit package unit 3 2 (integrated circuit package unit), and a conductor 3 3 , 3 4, wherein each integrated circuit packaging unit 3 1, 3 2 has a chip, a lead frame, a packaging material and a plurality of pins. The design of the structure consists in using a conductor 3 3 1 of the first integrated circuit packaging unit 3 1 and a pin 3 2 1 of the second integrated circuit packaging unit 3 2 to provide a conductor 3 3, 3 4 respectively. The corresponding conductors 3 3 and 3 4 are overlapped with each other in the vertical direction to form an electrical connection. The stacking method of this structure must first align each of the integrated circuit packaging units 3 1 and 3 2 with the conductors 3 3 and 3 4 and complete the electrical connection, and then lap each of the conductors 3 3 and 3 4 with each other. Connect to complete the electrical connection. However, this design is not only complicated in structure, but also the stacking steps are very tedious. The pins 3 1 1, 3 2 1 and the conductors 3 3 and 3 4 must be processed twice. Although no interface material is used, the production cost It is still high, and it must be performed manually, and it cannot be mass-produced by automation. Therefore, how to provide a structure and a stacking method of a integrated circuit module (s t a c k e d I C MU d u 1 e) with a simple structure, low cost, easy stacking, and automatic production is an urgent problem to be solved at present. [Summary] The main purpose of this case is to provide an integrated circuit module (s t a c k e d
1233196 五、發明說明（4) I C Μ〇d u 1 e )結構，該積 於堆疊。 本案之另一目的係 (stacked IC Module) 路封裝單元，俾達到體 本案之另一目的為 法，其可藉由自動化方 為達上述目的，本案提 Module)，其至少包含 二積體電路封裝單元與 單元包括一積體電路晶 實施例中，該導線架具 與該積體電路晶片電連 電路晶片與部分該導線 裝材料之上表面上或外 材料之側邊延伸出接腳 根據本案之構想， 裝單元與該第二積體電 表面及一第二表面與該 接，俾使該第一與第二 該介面層以該第一表面 封裝單元各接腳之第一 複數個焊墊與該第二積 部連接。 易 且 低 本 成 Λ 口彐一 簡 構 結 組 模 路 電 體 供構 提士口 么，\' 堆 vtg一 種 體堆 積i 之需 疊依 可 其 電 疊 路 組 電 體 積 模種 各 方本 造成 製程 之製 。組省 的模節 目路能 之電且 量體， 容積產 高種生 且一量 小供大 積提式 組 模 路 電 體 積 種 I 供 元 單 裝 封 路 電 體 積1 第 第 裝該 封於 路。 電料 體材 積裝 一封 每一 中與 其架 ，線 層導 面一 介、 一片 端體 一積 之該 腳覆 接包 一料 每材 且裝 ，封 腳該 接， 個外 數另 複 。 有接 封裝 該封 於該 腳於 接且 一 ? 每部 的接 架焊 線一 導第 該一 使露 ，暴 架側 封 。路 部電 接體 焊積 二一 第第 一該 成於 形介 並係 端層 一面 另介 之該 第連 一元 以單 別裝 分封 且路 ’ 電 間體 之積 元二 單第 裝與 封一 路第 ，路 中電 其體 〇 積 通一 導第 電該 元與 單塾 裝焊 封個 路數 電複 體之 積上 之接 上焊面二 表第 二之 第卿 該接 以各 且元 ，單 接裝 連封 部路 接電 焊體 Ιϋ_Ι1233196 V. Description of the invention (4) I C Mod u 1 e) structure, which is stacked. Another purpose of this case is (stacked IC Module) circuit packaging unit, which can achieve the other purpose of this case. It can be automated to achieve the above purpose. This case refers to Module. It contains at least two integrated circuit package. The unit and the unit include an integrated circuit crystal. In the embodiment, the lead frame is electrically connected to the integrated circuit chip and a portion of the wire mounting material on the upper surface or a side of the outer material is extended with pins. It is conceived that the mounting unit is connected to the second integrated electrical surface and a second surface is connected to the first, so that the first and second interface layers are connected with the first plurality of pads of each pin of the first surface packaging unit and This second product is connected. Is it easy to reduce the cost of Λ? A simple structure group circuit electrical supply for the construction of the Tieskou, \ 'heap vtg a volume stacking i need to be stacked according to its electrical stack circuit volume model System of processes. The province's modular programs can be powered by electricity and measured in volume, with high volume and high yield, and a small amount for large accumulations. Types of modular circuit electricity volume I supply unit, sealed circuit electricity volume 1 . A piece of electrical material is assembled with each frame, a wire layer guide is introduced, and a piece of end body is covered with the foot. One piece of each material is installed, and the foot is connected. The number is extra. There is a connection package, the seal is connected to the pin and the connection frame of each frame is to be exposed first, and the frame side seal is exposed. The electrical connection body of the road section is welded together. The first one is formed in the shape medium and is connected to the end layer. The first connected yuan is packaged in a separate package and the road 'electrical unit is assembled and sealed in a single unit. First, Lu Zhongdian's body, one product, one product, one yuan, one yuan, one yuan, and one unit, and the number of electrical complexes should be welded to the welding surface. The second one, the second one in the table, should be connected to each yuan. Connecting and sealing parts connected to welding body Ιϋ_Ι
第1丨頁 1233196 五、發明說明（5) 為達上述目的，本案另提供一種積體電路裝置，其至 少包括：一電路板，具有一上表面與一下表面；以及複數 個積體電路模組，排列於該電路板之該上表面與下表面， 且每一積體電路模組包括一第一積體電路封裝單元、一第 二積體電路封裝單元與一介面層。 於該實施例中，每一積體電路封裝單元包括：一積體 電路晶片；一導線架，具有複數個接腳，其中每一接腳之 一端與該積體電路晶片電連接；以及一封裝材料，包覆該 積體電路晶片與部分該導線架，使該導線架的每一接腳於 該封裝材料之上表面上或外側暴露一第一焊接部，且於該 封裝材料之惻邊延伸出接腳之另一端並形成一第二焊接 部。 根據本案之構想，該介電層係介於該第一積體電路封 裝單元與該第二積體電路封裝單元之間，且分別以一第一 表面及一第二表面與該第一與第二積體電路封裝單元連 接，俾使該第一與第二積體電路封裝單元電導通。其中， 該介電層以該第一表面上之複數個焊墊與該第一積體電路 封裝單元各接腳之第一焊接部連接，且以該第二表面上之 複數個焊墊與該第二積體電路封裝單元各接腳之第二焊接 部連接。 為達上述目的，本案提供一種積體電路模組之自動化 堆疊方法，其至少包括步驟：首先，提供一第一與第二積 體電路封裝單元，其中該第一與該第二積體電路封裝單元 包括：一積體電路晶片：一導線架，具有複數個接腳，其Page 1 of 1233196 V. Description of the invention (5) In order to achieve the above purpose, the present invention further provides an integrated circuit device, which at least includes: a circuit board having an upper surface and a lower surface; and a plurality of integrated circuit modules Are arranged on the upper surface and the lower surface of the circuit board, and each integrated circuit module includes a first integrated circuit packaging unit, a second integrated circuit packaging unit and an interface layer. In this embodiment, each integrated circuit package unit includes: an integrated circuit chip; a lead frame having a plurality of pins, wherein one end of each pin is electrically connected to the integrated circuit chip; and a package Material, covering the integrated circuit chip and part of the lead frame, so that each pin of the lead frame exposes a first soldering portion on the upper surface or outside of the packaging material, and extends on the edge of the packaging material A second soldering portion is formed at the other end of the pin. According to the concept of the present case, the dielectric layer is interposed between the first integrated circuit packaging unit and the second integrated circuit packaging unit, and a first surface and a second surface and the first and The two integrated circuit packaging units are connected to electrically conduct the first and second integrated circuit packaging units. Wherein, the dielectric layer is connected to the first soldering portion of each pin of the first integrated circuit packaging unit by a plurality of pads on the first surface, and the plurality of pads on the second surface is connected to the first pad The second soldering portions of the pins of the second integrated circuit packaging unit are connected. In order to achieve the above purpose, the present invention provides an automated stacking method for integrated circuit modules, which at least includes the steps: first, providing a first and a second integrated circuit packaging unit, wherein the first and the second integrated circuit packaging are provided; The unit includes: an integrated circuit chip: a lead frame with a plurality of pins, and
1233196 五、發明說明（G) 中每一接腳之一端與該積體電路晶片電連接；以及一封裝 材料，包覆該積體電路晶片與部分該導線架，使該導線架 的每一接腳於該封裝材料之上表面上或外側暴露一第一焊 接部，且於該封裝材料之側邊延伸出接腳之另一端並形成 一第二焊接部。接著，提供一介面層，其中該介面層具有 一第一表面與一第二表面。然後，利用表面接著法將該第 一積體電路單元每一接腳之第一焊接部與該介面層第一表 面上之複數個焊墊連接。最後，利用表面接接著法將該第 二積體電路單元每一接腳之第二焊接部與該介面層第二表 面上之複數個焊墊連接。 本案得由下列圖示與實施例說明，俾得一更深入之了 解。 【實施方式】 本案係為一種可堆疊式積體電路模組及其自動化積體 電路模組製造方法，其係適用於各種積體電路封裝，例如 記憶體（包括[)R A Μ 、D D R DRAM > RAMBUS DRAM 、F L A S H 或 S R A M )、特殊應用積體電路A S I C或液晶顯示器驅動積體電 路等，利用堆疊同一積體電路封裝單元或不同之積體電路 封裝單元，以提供結構簡單、成本低、電氣特性佳、高容 量、體積小、易於堆疊且可以自動化方式大量產製之積體 電路模組。 請參閱第四圖，其係顯示本案一較佳實施例之積體電 路模組結構示意圖。如第四圖所不^本案之積體電路模組1233196 V. One end of each pin in the description of the invention (G) is electrically connected to the integrated circuit chip; and a packaging material covering the integrated circuit chip and a part of the lead frame, so that each lead frame is connected. The foot exposes a first welding portion on the upper surface or outside of the packaging material, and the other end of the pin extends from the side of the packaging material to form a second welding portion. Next, an interface layer is provided, wherein the interface layer has a first surface and a second surface. Then, a first bonding portion of each pin of the first integrated circuit unit is connected to a plurality of bonding pads on the first surface of the interface layer by a surface bonding method. Finally, a second bonding portion of each pin of the second integrated circuit unit is connected to a plurality of bonding pads on the second surface of the interface layer by a surface bonding method. This case can be illustrated by the following illustrations and examples, which will give a deeper understanding. [Embodiment] This case is a stackable integrated circuit module and an automated integrated circuit module manufacturing method, which is suitable for various integrated circuit packages, such as memory (including [) RA Μ, DDR DRAM & gt RAMBUS DRAM, FLASH or SRAM), special application integrated circuit ASIC or liquid crystal display driver integrated circuit, etc., use the same integrated circuit packaging unit or different integrated circuit packaging units to provide a simple structure, low cost, electrical Integrated circuit module with good characteristics, high capacity, small size, easy stacking, and mass production in an automated manner. Please refer to the fourth figure, which is a schematic diagram showing the structure of the integrated circuit module of a preferred embodiment of the present invention. As shown in the fourth figure, the integrated circuit module of this case
第13頁 1233196 五、發明說明m 至少包括一第一積體電路封裝單元4 1 、一第二積體電路封 裝單元4 2與一介面層4 3 。該第一積體電路封裝f元4 1係位 於下方，而該第二積體電路封裝單元4 2係位於上方，介面 層4 3則設置於第一積體電路封裝單元4 1與第二積體電路封 裝單元4 2之間，且分別與該第一積體電路封裝單元4 1與該 第二積體電路方裝單元4 2連接，以使該第一積體電路封裝 單元4 1與第二積體電路封裝單元4 2電性導通。 請參閱第五圖，其係顯示第四圖所示積體電路模組中 每一積體電路封裝單元之結構示意圖。如第五圖所示，每 一積體電路封裝單元4 1 、4 2係包含導線架4 1 1 、積體電路 晶片4 1 2與封裝材料4 1 3 。積體電路晶片4 1 2具有一第一表 面4 121與一與第一表面相對之第二表面4122 ，其中積體電 路晶片4 1 2之第一表面4 1 2 1上並設有複數個電性接點（未圖 示）。 導線架4 1 1係具有複數個接腳4 Π 1 ，各接腳4 1 1 1均具 有一第一端4 1 1 1 1及一第二端4 1 1 1 2，第一端4 1 1 1 1係對應 地電性連接於積體電路晶片4 1 2之第一面4 1 2 1上所設之接 點，第二端4 1 1 1 2則分布於積體電路晶片4 1 2之一側。於本 實施例中，複數個接腳4 1 1 1之第二端4 1 1 1 2係被區分為兩 列而分別在積體電路晶片4 1 2的兩側（請參閱苐六圖）。另 外，以一絕緣之封裝材料4 1 3可將積體電路晶片4丨2之第一 表面4121及第二表面41 22包覆並對應地構成一上表面4 131 及一下表面4 1 3 2。於本實施例中，封裝材料4 1 3在封裝後 係形成一長矩形體，使得接腳4 1 1 1之第二端4 1 1 1 2分布在Page 13 1233196 V. Description of the invention m includes at least a first integrated circuit packaging unit 4 1, a second integrated circuit packaging unit 4 2 and an interface layer 4 3. The first integrated circuit package f element 41 is located below, and the second integrated circuit package unit 4 2 is located above, and the interface layer 43 is disposed on the first integrated circuit package unit 41 and the second product. Between the body circuit packaging unit 41 and the first integrated circuit packaging unit 41 and the second integrated circuit square mounting unit 42 respectively, so that the first integrated circuit packaging unit 41 and the first integrated circuit packaging unit 41 The two integrated circuit packaging unit 42 is electrically conductive. Please refer to the fifth figure, which is a schematic diagram showing the structure of each integrated circuit packaging unit in the integrated circuit module shown in the fourth figure. As shown in the fifth figure, each of the integrated circuit packaging units 4 1 and 4 2 includes a lead frame 4 1 1, an integrated circuit chip 4 1 2, and a packaging material 4 1 3. The integrated circuit wafer 4 1 2 has a first surface 4 121 and a second surface 4122 opposite to the first surface. The first surface 4 1 2 1 of the integrated circuit wafer 4 1 2 is provided with a plurality of electrical circuits. Sexual contact (not shown). The lead frame 4 1 1 has a plurality of pins 4 Π 1, and each of the pins 4 1 1 1 has a first end 4 1 1 1 1 and a second end 4 1 1 1 2 and a first end 4 1 1 1 1 is correspondingly electrically connected to the contact provided on the first surface 4 1 2 1 of the integrated circuit chip 4 1 2, and the second end 4 1 1 1 2 is distributed on the integrated circuit chip 4 1 2 One side. In this embodiment, the second ends 4 1 1 1 2 of the plurality of pins 4 1 1 1 are divided into two columns and are respectively on two sides of the integrated circuit chip 4 1 2 (see FIG. 26). In addition, the first surface 4121 and the second surface 41 22 of the integrated circuit chip 4 丨 2 can be covered with an insulating packaging material 4 1 3 and correspondingly constitute an upper surface 4 131 and a lower surface 4 1 3 2. In this embodiment, the packaging material 4 1 3 is formed into a long rectangular body after packaging, so that the second ends 4 1 1 1 2 of the pins 4 1 1 1 are distributed at
第14頁 1233196 五、發明說明（8) 封裝材料4 1 3長度的相反兩側。 請參閱第五圖，導線架4 Π之接腳4 1 1 1的第一端4 1 1 1 1 與積體電路晶片4 1 2之第一面4 1 2 1的接點連接後係向上延 伸至封裝材料4 I ;]的上表面4 1 3 1位置，再彎折呈水平地向 遠離積體電路晶片4 1 2的方向延伸以形成一顯露在封裝材 料4 1 3的上表面4 1 3 1之第一焊接部4 1 1 1 3 ，並接著由第一焊 接部4 1 1 1 3向下彎折而與封裝材料4 1 3的下表面4 1 3 2的方向 同向延伸，而在略超出下表面4132所在平面之位置轉而向 遠離封裝材料4 1 3之方向呈水平狀而構成一第二焊接部 41114° 請再參閱第四圖，該介面層4 3係介於第一積體電路封 裝單元4 1與第二積體電路封裝單元4 2之間，且分別以第一 表面431及第二表面432與該第一與第二積體電路封裝單元 4 1 、4 2連接，以使該第一與第二積體電路封裝單元電4 1 、 4 2電導通。於此實施例中，該介面層4 3以第一表面4 3 1上 之複數個焊墊（未圖示）與第一積體電路封裝單元4 1各接腳 4 1 1 1之第一焊接部利用焊劑材料4 4，例如錫膠，連接，且 以該第二表面432上之複數個焊墊（未圖示）與第二積體電 路封裝單元4 2各接腳4 1 1 1之第二焊接部4 1 1 1 4利用焊劑材 料4 4 ，例如錫膠，連接。另外，該介面層4 3可為硬質介電 材料層或軟質介電材料層。 由於本案所提供之積體電路封裝單元4 1 、4 2可利用其 第一焊接部4 U 1 3以及第二焊接部4 1 1 1 4直接進行堆疊，因 此使整個製程十分簡易且可以自動化方式大量生產。以下Page 14 1233196 V. Description of the invention (8) Packaging material 4 1 3 Opposite sides of length. Referring to the fifth figure, the first end 4 1 1 1 of the lead 4 of the lead frame 4 Π 4 1 1 1 1 is connected to the contact of the first surface 4 1 2 1 of the integrated circuit chip 4 1 2 and extends upward. To the upper surface 4 1 3 1 of the packaging material 4], and then bend to extend horizontally away from the integrated circuit wafer 4 1 2 to form an upper surface 4 1 3 exposed on the packaging material 4 1 3 The first soldering portion 4 1 1 1 3 of 1 is then bent downward from the first soldering portion 4 1 1 1 3 to extend in the same direction as the lower surface 4 1 3 2 of the packaging material 4 1 3, and The position slightly beyond the plane where the lower surface 4132 is located is turned horizontally away from the packaging material 4 1 3 to form a second soldering portion 41114 °. Please refer to the fourth figure again, the interface layer 4 3 is between the first product The bulk circuit packaging unit 41 and the second integrated circuit packaging unit 42 are connected to the first and second integrated circuit packaging units 4 1 and 4 2 through a first surface 431 and a second surface 432, respectively. In this way, the first and second integrated circuit packaging units are electrically conductive. In this embodiment, the interface layer 43 is first soldered with a plurality of solder pads (not shown) on the first surface 4 3 1 to each pin 4 1 1 of the first integrated circuit packaging unit 4 1. The portion is connected with a flux material 4 4 such as a tin paste, and a plurality of solder pads (not shown) on the second surface 432 and the second integrated circuit packaging unit 4 2 each of the pins 4 1 1 1 are connected. The two soldering portions 4 1 1 1 4 are connected using a flux material 4 4 such as a tin paste. In addition, the interface layer 43 may be a hard dielectric material layer or a soft dielectric material layer. Since the integrated circuit packaging units 4 1 and 4 2 provided in this case can be directly stacked using the first soldering portion 4 U 1 3 and the second soldering portion 4 1 1 1 4, the entire process is very simple and can be automated. Mass production. the following
第15頁 439 1233196 五、發明說明（9) 簡述本案積體電路模組之製造方法：首先，提供一第一積 體電路封裝單元4 1與一第二積體電路封裝單元4 2 ，其中該 第一積體電路封裝單元4 1與第二積體電路封裝單元4 2之結 構如前所述，於此不再贅述。接著，利用一上下兩面均設 有焊墊之介面層4 3 ，以表面接著法將第一積體電路單元4 1 每一接腳4 1 1 1之第一焊接部4 1 1 1 3與該介面層4 3第一表面 4 3 1上之複數個焊墊連接，於過錫爐後即可完成電性導 接。然後，利用表面接接著法將第二積體電路單元4 2每一 接腳41 1 1之第二焊接部41 1 14與該介面層43第二表面4 3 2上 之複數個焊墊連接，於過錫爐後即可完成電性導接。因 此，藉由介面層4 3可將積體電路封裝單元4 1 、4 2以堆疊的 方式直接進行連接。 另一方面，為使堆疊後之積體電路模組高度更為縮 小，於第七圖所示之另一實施例中，積體電路封裝單元 4 1 、4 2亦可為封裝材料4 1 3只封裝部分導線架4 1 1與積體電 路晶片412之上表面4121 ’而使積體電路晶片412之下表面 4 1 2 2裸露，藉此可減少封裝材料之使用以及使積體電路封 裝單元4〗、4 2高度縮小。因此，於利用與第四圖所示實施 例相同之堆疊方式後，所堆疊之積體電路模組的高度便可 進一步縮小。 此外，積體電路封裝單元4 1 、4 2之第一焊接部4 1 1 1 3 亦不限定於只暴露於封裝材料4 1 3之上表面4 1 3 1上。請參 閱第八圖，於另一實施例中，導線架4 1 1之接腳4 1 1 1的第 一端4 1 1 1 1與積體電路晶片4 1 2之第一面4 1 2 1的接點連接後Page 15 439 1233196 V. Description of the invention (9) Briefly describe the manufacturing method of the integrated circuit module in this case: First, provide a first integrated circuit packaging unit 41 and a second integrated circuit packaging unit 4 2, of which The structures of the first integrated circuit packaging unit 41 and the second integrated circuit packaging unit 42 are as described above, and are not repeated here. Then, using an interface layer 4 3 provided with solder pads on the upper and lower surfaces, the first soldering portion 4 1 1 1 3 of each pin 4 1 1 1 of the first integrated circuit unit 4 1 and the A plurality of solder pads are connected on the first surface 4 3 1 of the interface layer 4 3, and the electrical conduction can be completed after passing through the tin furnace. Then, the second soldering portions 41 1 14 of each of the pins 41 1 1 of the second integrated circuit unit 4 2 are connected to a plurality of solder pads on the second surface 4 3 2 of the interface layer 43 by a surface bonding method. Electrical connection can be completed after passing through the tin furnace. Therefore, the integrated circuit packaging units 4 1 and 4 2 can be directly connected in a stacked manner through the interface layer 4 3. On the other hand, in order to further reduce the height of the stacked integrated circuit module, in another embodiment shown in FIG. 7, the integrated circuit packaging units 4 1 and 4 2 may also be packaging materials 4 1 3 Only a part of the lead frame 4 1 1 and the upper surface 4121 ′ of the integrated circuit chip 412 are exposed, so that the lower surface 4 1 2 2 of the integrated circuit chip 412 is exposed, thereby reducing the use of packaging materials and enabling the integrated circuit packaging unit. 4〗, 4 2 The height is reduced. Therefore, after using the same stacking method as the embodiment shown in the fourth figure, the height of the stacked integrated circuit modules can be further reduced. In addition, the first soldering portions 4 1 1 1 3 of the integrated circuit packaging units 4 1, 4 2 are not limited to being exposed only on the surface 4 1 3 1 above the packaging material 4 1 3. Please refer to the eighth figure. In another embodiment, the first end 4 1 1 1 of the lead 4 4 1 of the lead frame 4 1 1 1 and the first surface 4 1 2 of the integrated circuit chip 4 1 2 1 After the contacts are connected
1233196 五、發明說明（10) 係向平行積體電路晶片4 1 2方向延伸至鄰近封裝材料4 1 3侧 邊，再漸彎折向上至封裝材料4 1 3上表面邊緣後水平地向 遠離封裝材料4 1 3的方向延伸以形成一顯露在封裝材料4 1 3 的上表面4 1 3 1外側之第一焊接部4 1 1 1 3 ，並接著由第一焊 接部41113向下彎折而與封裝材料413的下表面4132的方向 同向延伸，而在略超出下表面4 1 3 2所在平面之位置轉而向 遠離封裝材料4 1 3之方向呈水平狀而構成一第二焊接部 4 1 1 Μ。藉此，使第二焊接部4 1 1 1 3暴露於封裝材料4 1 3上 表面4 1 3 1之外惻。這樣的結構同樣地有利於堆疊出本案之 積體電路封裝模組。 請再參閱第九圖，本案另提供一種積體電路裝置5 ， 其至少包括一電路板5丨以及複數個積體電路模組5 2，其中 電路板51具有一上表面與一下表面，而複數個積體電路模 組5 2係排列於該電路板5 1之上表面與下表面。於此實施例 中’母一積體電路模組5 2之結構與第四圖所示之積體電路 模組結構相同，於此不再贅述。 綜上所述，本案之積體電路模組主要是由第一積體電 路封裝單元4 1 、第二積體電路封裝單元4 2與介面層4 3所堆 疊而成。由於本案之積體電路封裝單元4 1 、4 2具有可直接 向上連接之第一焊接部4 1 1 1 3 ，以及可直接向下連接之第 二焊接部4 1 1 1 4 ，因此使整個堆疊製程更為簡易且有利於 以自動化方式製造。再則，介面層4 3之焊墊位置係利用印 刷電路板的製程可相當容易在事前製作定位完成，再加上 本創作之積體電路封裝單元4 1 、4 2具有利於堆疊連接之第1233196 V. Description of the invention (10) It extends in the direction of the parallel integrated circuit chip 4 1 2 to the side of the packaging material 4 1 3, and then bends upward to the edge of the packaging material 4 1 3 horizontally away from the package. The material 4 1 3 extends in a direction to form a first soldering portion 4 1 1 1 3 exposed on the upper surface 4 1 3 1 of the packaging material 4 1 3 1, and then is bent downward by the first soldering portion 41113 to communicate with The direction of the lower surface 4132 of the packaging material 413 extends in the same direction, and at a position slightly beyond the plane where the lower surface 4 1 3 2 is located, it is horizontal to the direction away from the packaging material 4 1 3 to form a second welding portion 4 1 1 M. Thereby, the second solder portion 4 1 1 1 3 is exposed to the upper surface 4 1 3 1 of the packaging material 4 1 3. Such a structure is also conducive to stacking the integrated circuit package module of the present case. Please refer to the ninth figure again. This case also provides an integrated circuit device 5, which includes at least a circuit board 5 丨 and a plurality of integrated circuit modules 52, wherein the circuit board 51 has an upper surface and a lower surface, and a plurality of Each integrated circuit module 5 2 is arranged on the upper surface and the lower surface of the circuit board 51. In this embodiment, the structure of the 'mother-integrated circuit module 52' is the same as the structure of the integrated circuit module shown in the fourth figure, and will not be repeated here. In summary, the integrated circuit module of this case is mainly formed by stacking the first integrated circuit packaging unit 41, the second integrated circuit packaging unit 42, and the interface layer 43. Since the integrated circuit packaging units 4 1 and 4 2 of the present case have a first soldering portion 4 1 1 1 3 that can be directly connected upward and a second soldering portion 4 1 1 1 4 that can be directly connected downward, the entire stack is stacked The manufacturing process is simpler and facilitates automated manufacturing. Furthermore, the position of the pads of the interface layer 43 is based on the printed circuit board manufacturing process, which can be easily made and positioned in advance. In addition, the integrated circuit packaging units 4 1 and 4 2 of this creation have the advantages of stacking connections.
第17頁 1233196 五、發明說明αι) 一焊接部4 1 11 3與第二焊接部4 1 1 1 4的設計，使得以本案之 積體電路封裝單元4 1 、4 2可輕易地以堆疊的方式加以連 接，無須如習知方式進行二次加工，同時利用表面黏著法 之成熟技術可以自動化方式大幅降低整體堆疊連接之成 本，並達到結構簡單、成本低、電氣特性佳、高容量、體 積小、易於堆疊且可以自動化方式大量產製之目的。 本案得由熟悉此技術之人士任施匠思而為諸般修飾， 然皆不脫如附申請專利範圍所欲保護者。Page 17 1233196 V. Description of the invention αι) The design of a soldering part 4 1 11 3 and a second soldering part 4 1 1 1 4 makes the integrated circuit packaging units 4 1 and 4 2 of this case easily stackable. It can be connected in a way that does not require secondary processing as is known. At the same time, the mature technology of surface adhesion method can greatly reduce the cost of the overall stacking connection in an automated manner, and achieve simple structure, low cost, good electrical characteristics, high capacity, and small size. , Easy to stack and can be automated for mass production purposes. This case may be modified by anyone familiar with this technology, but none of them can be protected by the scope of the patent application.
第18頁 1233196 圖式簡單說明 第一圖：其係顯示一習知以堆疊方式組裝之積體電路模組 結構示意圖。 第二圖：其係顯示另一習知以堆疊方式組裝之積體電路模 組結構示意圖。 第三圖：其係顯示另一習知以堆疊方式組裝之積體電路模 組結構示意圖。 第四圖：其係顯示本案較佳實施例之積體電路模組結構示 意圖。 第五圖：其係顯示第四圖中每一積體電路封裝單元之結構 示意圖。 第六圖：其係顯示第五圖所示積體電路封裝單元之立體 圖。 第七圖：其係顯示另一較佳積體電路封裝單元之結構示意 圖。 第八圖：其係顯示又一較佳積體電路封裝單元之結構示意 圖。 第九圖：其係顯示本案較佳實施例之積體電路裝置結構示 意圖。 圖示符號說明 I 、2、3 :積體電路模組 II 、21 、31 :第一積體電路封裝單元 12、22、32 ·弟二積體電路封裝早元 1 1 1 、1 2 1 、2 1 1 、2 2 1 、3 1 1 、3 2 1 ··接腳Page 18 1233196 Schematic description of the first diagram: It shows the structure of a conventional integrated circuit module assembled in a stack. The second figure: it is a schematic diagram showing the structure of another conventional integrated circuit module assembled in a stacked manner. The third figure: it is a schematic diagram showing the structure of another conventional integrated circuit module assembled in a stacked manner. The fourth figure: it shows the structure of the integrated circuit module of the preferred embodiment of the present invention. Fifth figure: It is a schematic diagram showing the structure of each integrated circuit packaging unit in the fourth figure. Figure 6: It is a perspective view showing the integrated circuit packaging unit shown in Figure 5. Figure 7: A schematic diagram showing the structure of another preferred integrated circuit packaging unit. Figure 8: A schematic diagram showing the structure of another preferred integrated circuit packaging unit. Ninth figure: It shows the structure of the integrated circuit device of the preferred embodiment of this case. Symbols I, 2, 3: Integrated circuit module II, 21, 31: First integrated circuit packaging unit 12, 22, 32 · First integrated circuit package early element 1 1 1, 1 2 1, 2 1 1 2 2 1 3 1 1 3 2 1
第19頁 1233196 圖式簡單說明 2 3 :介電材料 2 3 1 :折腳 4 1 :第一積體電路封裝單元 4 1 1 1 :接腳 4 1 1 1 2 :第二端 4 1 1 1 4 :第二焊接部 4 1 2 1 :第一表面 4 1 3 :封裝材料 4 1 3 2 :下表面 4 3 :介面層 4 3 2 ·•第二表面 3 3、3 4 :導電體 4 1 1 :導線架 4 1 1 1 1 :第一端 4 Π 1 3 :第一焊接部 4 1 2 :積體電路晶片 4 1 22 :第二表面 4 13 1 ： 上表面 4 2 :第二積體電路封裝單元 4 3 1 : 第一表面 4 4 :焊劑材料Page 19 1233196 Brief description of the drawing 2 3: Dielectric material 2 3 1: Folding pin 4 1: First integrated circuit packaging unit 4 1 1 1: Pin 4 1 1 1 2: Second end 4 1 1 1 4: Second soldering part 4 1 2 1: First surface 4 1 3: Packaging material 4 1 3 2: Lower surface 4 3: Interface layer 4 3 2 · Second surface 3 3, 3 4: Conductor 4 1 1: lead frame 4 1 1 1 1: first end 4 Π 1 3: first soldering portion 4 1 2: integrated circuit wafer 4 1 22: second surface 4 13 1: upper surface 4 2: second integrated body Circuit packaging unit 4 3 1: first surface 4 4: solder material
第20頁 444Page 444
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| TW92133240A TWI233196B (en) | 2003-11-26 | 2003-11-26 | Stackable IC package structure and the method of automatically manufacturing the IC module |
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| TW92133240A TWI233196B (en) | 2003-11-26 | 2003-11-26 | Stackable IC package structure and the method of automatically manufacturing the IC module |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7821122B2 (en) | 2005-12-22 | 2010-10-26 | Atmel Corporation | Method and system for increasing circuitry interconnection and component capacity in a multi-component package |
| US8237266B2 (en) | 2005-12-20 | 2012-08-07 | Atmel Corporation | Component stacking for integrated circuit electronic package |
| CN108288484A (en) * | 2017-01-10 | 2018-07-17 | 爱思开海力士有限公司 | Include the nonvolatile semiconductor memory member of multiple planes |
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2003
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8237266B2 (en) | 2005-12-20 | 2012-08-07 | Atmel Corporation | Component stacking for integrated circuit electronic package |
| US8525329B2 (en) | 2005-12-20 | 2013-09-03 | Atmel Corporation | Component stacking for integrated circuit electronic package |
| US7821122B2 (en) | 2005-12-22 | 2010-10-26 | Atmel Corporation | Method and system for increasing circuitry interconnection and component capacity in a multi-component package |
| CN108288484A (en) * | 2017-01-10 | 2018-07-17 | 爱思开海力士有限公司 | Include the nonvolatile semiconductor memory member of multiple planes |
| CN108288484B (en) * | 2017-01-10 | 2021-05-25 | 爱思开海力士有限公司 | Nonvolatile memory device including multiple planes |
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