1231571 玖、發明說明 【發明所屬之技術領域】 本發明係有關於一種半導體元件的結構及其製造方 法，特別是有關於一種具低閘極阻值之功率電晶體結構及 其製造方法。 【先前技術】 雙載子連接電晶體（BJT)為現今最重要的半導體元件 之一，這種元件雖然可作為高功率元件及高速邏輯電路之 用，但是在操作的過程之中，其最大的缺點為會消耗大量 的能量。目前，金氧半場效電晶體（MOSFET)的發展，已 經逐漸取代了雙載子電晶體之應用。由於其能節省電能的 緣故，金氧半場效電晶體已成為積體電路中最常被使用的 半導體元件。 在一般技術之中，所稱的功率金氧半場效電晶體 (POWER MOSFET)基本操作和任何的金氧半場效電晶體 相同，但是其電流處理能力可達數安培，且其汲極至源極 所可耐受的阻隔電壓可高達約20V〜1200V或是更高。功 率金氧半場效電晶體的優點是可以使用小控制電壓於耗 費低功率的狀況下來操作元件。 請參閱第1圖，其顯示一般常見之功率電晶體結構。 1231571 I主=構包合重摻雜N型（或P型）半導體基材100 與一層N型石夕蠢晶石夕層110。在N型石夕蠢晶石夕層110之上 具有閘層氧化層140與複晶石夕閘極150。㈣型蠢晶石夕層 中"、有一輕摻雜P井區120，作為功率金氧半場 效電晶體的通道區（BGdy)。而在輕摻雜p井區12G之中， 尚包含兩個重摻雜N井區130,作為功率半導體元件的源 極’二間以一重摻雜P井區180做為金屬I 170與輕摻雜 P井區1.20之接觸連接點。在複晶石夕間極⑼的上方具有 一層硼磷矽玻璃 160 ( B⑽ph〇sph〇silicate Gl:s， BPSG)’作為複晶矽閘極ι5〇的絕緣層。此外，在硼磷矽 玻璃160之上’具有—金屬層m用以接觸重摻雜n井 區1 3〇，作為源極導線。 依照第1圖的元件設計，整個元件的操作是以重摻雜 N井區130作為源極，而基底區域12〇是作為通道區。然 後再以重摻雜N型矽基材1〇〇作為元件的汲極，電子進 入源極區，並橫向通過閘極下反轉層而到N型摻雜磊晶 矽層110，電子將垂直流經^^型摻雜磊晶矽層110到達汲 極〇 ” 一般而言，半導體元件之切換是藉由於閘極上施加電 壓，以在源極與汲極間形成通道達成導通目的，並藉由移 除閘極上之施加電壓以關閉電晶體，因此元件之切換速度 與閘極之電阻值大小息息相關，太大之閘極電阻會影響元 件之開關速度。 1231571 發明内容】 鑒於上述之發明背景所述，閘極電阻值之大 響功率電晶體開關速度的-項重要因素，本發明的= =即為提供—種具有低閘極電阻之高功率半 之製造方法。 卞 ▲本發明的另—目的係為提供_種具.有低閘極電阻之 间功率半導體元件之製造方法，於部分閘極處填入金屬 層’利用低電阻值之金屬來降低閘極之電阻 閉電極之切換速度。 I曰強 本發明的次—目的係提供—種具有低閘極電阻 =半導體元件之結構，以低電阻值之金屬來形成部分間 極結構，來降低閘極電阻增強閘電極之切換速度。 本t明係揭路-種具低閘極阻值之功率電晶體 及其製造方法，根據本發明之結構，其中包含一半導體基 材’-蟲晶梦層位於此半導體基材上，—閘極位於此^ 矽層上，基底區域則位於㈣兩側之磊晶矽層内，於此基 底區域内形成有功率電晶體之源極區，其中於此閘極中且 有一填入耗鶴金屬之溝渠結構，用以降低整體閘 電 阻值。 根據本發明功率電晶體之製程，首先係於一半導體 基材上形成與其相同電性之-蟲晶矽層，接著於蟲晶矽層 1231571 之上分別形成氧化矽層與複晶矽層，作為閘極結構。並進 行基體區域植入和形成源極區域。接著形成一氧化層於複 晶矽、源極區域和基體區域之上方，並於氧化層上形成圖 案化光阻層後，蝕刻氧化層與複晶矽層，以使每個閘極區 域中具有溝渠結構，並於此溝渠結構中填入矽化鎢。最 後，進行後續之接觸窗與金屬内連線等製程，以形成本發 明具有地閘極電阻值功率電晶體元件。 【實施方式】 在不限制本發明之精神及應用範圍之下，以下即以 一實施例，介紹本發明之實施；熟悉此領域技藝者，在瞭 解本發明之精神後，當可應用本發明之製程方法與元件結 構於各種不同之功率電晶體中。根據本發明之功率電晶體 結構及其製造方法，係以低電阻值之金屬來形成部分閑極 結構，藉以降低閘極電阻增強閘電極之切換速度。本發明 之製程方法可使用在多種之功率電晶體中不僅限於以下 所述之較佳實施例。 本發明揭露一種高功率半導體元件的製造方法，藉 由改變元件内閘極結構’以克服傳統閉極電阻值過高，以 至於不能提升切換速度的問題。自第二圖至第九圖繪示為 使用本發明於高功率半導體元件架構上的具體實施例。 如第二圖所述，提供一適當阻值之矽基材200,此基 I23l57l 材可以是N+型或是P+型的半導體基材，以本發明之一較 佳實施例中此基材為N型半導體基材200，以作為所欲形 成的半導體元件之汲極區域。此外，並在此N型半導體基 材200上形成一層適當阻值之輕摻雜n型磊晶矽層21〇，於 本發明之實施例中該濃度為1〇i4〜1〇i5 cm-2。 其次’如第二圖所描述，於蟲晶石夕層21〇之上成長一 層閘層氧化層220，舉例來說，閘層氧化層22〇可以由加熱 氧化法的製程生成。之後，於該閘層氧化層22〇上方沉積 一層複晶矽，作為閘極導電層。揍著，於複晶矽層上使用 光罩（未圖示）之曝光、顯影等步驟，形成一光阻圖案層， 以定義出閘極230。 接著請參閱第三圖，於磊晶矽層21〇上形成閘極23〇 之後，利用此閘極230作為幕罩，針對閘極兩側裸露之磊 晶矽層210表面，進行一基底區域之離子植入步驟，植入 的離子係為與磊晶矽層21〇具有相反電性的離子。於本發 明之實施射，係、植入含棚之離子，植入的料換雜濃度 約為1〇17 cm-2,且於植入基底區域離子後，再以熱驅入 方式形成基底區域240。接著形成一圖案化光阻層（圖中 未展示出），此光阻層係用以形成源極區域。以此圖案化 光阻層為罩幕，㈣基體區域24G進行離子植人，以便形 成摻雜區域於基體區域24时，作為所製造電晶體之源極 區域242。其中該源極區域242離子佈植的電性與基體區域 240的電性相反。 1231571 接著，請參閱第四圖所示，於部分磊晶矽層210之上 與閘極230上沉積一層氧化層250，該氧化層250係以化學 氣相沉積法沉積，厚度約為2000埃。 請參閱第五圖所示，於氧化層250上形成另一光阻圖 案層246，並暴露出各獨立的複晶閘極230上方之部分區 域。接著，使用光阻圖案層246作為蝕刻罩冪，分別對氧 化層250和閘極230進行蝕刻程序，以形成溝渠結構248於 閘極230中，並暴露出部分之複晶矽層。此蝕刻方法。例 如可利用非等向性反應離子餘刻製程（reactive ion etch ; RIE)來對閘極230進行蝕刻以形成如第六圖所示之溝渠結 構248，接著移除光阻圖案層246。 接著於氧化層250與溝渠結構248上沈積一矽化鎢 層，由於矽化鎢具有不容易附著於氧化層上，卻易於形成 於複晶矽層上之特性，因此將只有溝渠結構248所暴露之 複晶石夕層上會形成石夕化鐫2 6 0之沈積，如第七圖所示。 接著在第八圖中，進行接觸窗之製作，首先形成一絕 緣護層270以覆蓋於矽化鎢260與氧化層250上。此絕緣 護層 270例如可為磷矽玻璃（PSG)或是硼磷矽玻璃 (BPSG)，其中利用常壓化學氣相沉積（Atmospheric Pressure Chemical Vapor Deposition，APCVD)法沉積石粦石夕 玻璃（PSG)，而以電漿增強化學氣相沉積（Plasma-enhanced Chemical Vapor Deposition，PECVD)法沉積石朋鱗石夕玻璃 (BPSG)。 1231571 接著形成一圖案化光阻層（圖中未展示出）於絕緣護 層270上，姐以此圖案化光阻層為罩幕進行介電層之蝕刻 製程，以分別曝露源極區域242及基體區域240,由於所 形成之絕緣護層270亦為一種氧化層，因此在移除部分絕 . 緣護層270之同時，亦會移除氧化層25〇。接著於絕緣護 層270及暴露出之源極區域242和基體區域24〇上形成金 屬層280，如第九圖所示。 綜上所言，本發明所揭露之高功率電晶體，其閘極結 φ 構中具有部分低電阻值之金屬，因此可降低閘極電阻，並 增強閘電極之切換速度。 ^雖然本發明已以一較佳實施例揭露如上，然其並非用 从限$本發明，任何熟習此技藝者，在不脫離本發明之精 靶圍内，當可作各種之更動與潤飾，因此本發明之保 遵範圍當視後附之申請專利範圍所界定者為準。1231571 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to a structure of a semiconductor element and a manufacturing method thereof, and more particularly to a power transistor structure with a low gate resistance value and a manufacturing method thereof. [Previous technology] BJT is one of the most important semiconductor components today. Although this component can be used as high-power components and high-speed logic circuits, its largest The disadvantage is that it consumes a lot of energy. At present, the development of metal oxide half field effect transistors (MOSFETs) has gradually replaced the application of bipolar transistors. Because of its ability to save electricity, metal-oxide-semiconductor MOSFETs have become the most commonly used semiconductor components in integrated circuits. In general technology, the basic operation of the so-called power MOSFET is the same as that of any MOSFET, but its current handling capacity can reach several amps, and its drain to source The tolerable blocking voltage can be as high as about 20V ~ 1200V or higher. The advantage of the power metal-oxide half field effect transistor is that it can use a small control voltage to operate the element under the condition of low power consumption. Please refer to FIG. 1, which shows a common power transistor structure. 1231571 I main = contains a heavily doped N-type (or P-type) semiconductor substrate 100 and a layer of N-type stupid stone layer 110. A gate oxide layer 140 and a polycrystalline spar gate 150 are provided on the N-type spar patina spar layer 110. There is a lightly doped P-well region 120 in the ytterbium-type stupid slab layer, which serves as the channel region (BGdy) of the power metal-oxygen half field effect transistor. In the lightly doped p-well region 12G, there are still two heavily-doped N-well regions 130, which serve as the source of the power semiconductor device. A heavily-doped P-well region 180 is used as the metal I 170 and lightly doped. The contact connection point of the mixed P well area 1.20. A layer of borophosphosilicate glass 160 (Bpthosposilicate Gl: s, BPSG) 'is used as the insulating layer of the polycrystalline silicon gate electrode 50 above the polycrystalline stone. In addition, on the borophosphosilicate glass 160 'there is a-metal layer m for contacting the heavily doped n-well region 130 as a source wiring. According to the element design of FIG. 1, the operation of the entire element is to use the heavily doped N-well region 130 as the source, and the base region 120 as the channel region. Then the heavily doped N-type silicon substrate 100 is used as the drain of the device. The electrons enter the source region and pass through the gate inversion layer laterally to the N-type doped epitaxial silicon layer 110. The electrons will be vertical. Flow through the ^^-type doped epitaxial silicon layer 110 to reach the drain 0 ”In general, the switching of semiconductor devices is achieved by applying a voltage on the gate to form a channel between the source and the drain, and by Remove the applied voltage on the gate to turn off the transistor, so the switching speed of the device is closely related to the resistance value of the gate. A too large gate resistance will affect the switching speed of the device. 1231571 Summary of the Invention In view of the above background of the invention The gate resistance value is an important factor in the switching speed of a large power transistor. The == of the present invention is to provide a method of manufacturing a high power half with a low gate resistance. 卞 ▲ Another purpose of the present invention It is to provide a kind of manufacturing method for power semiconductor components with low gate resistance. A metal layer is filled in part of the gate. 'Using a metal with a low resistance value to reduce the switching speed of the closed electrode of the gate. The purpose of the present invention is to provide a structure with a low gate resistance = semiconductor element, and a partial resistance structure is formed by a metal with a low resistance value to reduce the gate resistance and enhance the switching speed of the gate electrode. Ming Ming Jie Lu-a power transistor with a low gate resistance value and a method for manufacturing the same, according to the structure of the present invention, which includes a semiconductor substrate-the insect crystal dream layer is located on the semiconductor substrate, the gate It is located on the silicon layer, and the base area is located in the epitaxial silicon layer on both sides of the gallium. In this base area, the source region of the power transistor is formed. Among these gates, there is a metal filled with crane metal. The trench structure is used to reduce the overall gate resistance value. According to the process of the power transistor of the present invention, first, a worm-crystal silicon layer having the same electrical property is formed on a semiconductor substrate, and then on the worm-crystal silicon layer 1231571, respectively. A silicon oxide layer and a polycrystalline silicon layer are formed as a gate structure. A base region is implanted and a source region is formed. Then, an oxide layer is formed over the polycrystalline silicon, the source region, and the base region, and is oxidized. After the patterned photoresist layer is formed thereon, the oxide layer and the polycrystalline silicon layer are etched so as to have a trench structure in each gate region, and tungsten silicide is filled in the trench structure. Finally, subsequent contact windows and metal are performed. Processes such as interconnections to form the power transistor device with ground gate resistance of the present invention. [Embodiment] Without limiting the spirit and scope of the present invention, the following is an example to introduce the implementation of the present invention. ; Those skilled in this field, after understanding the spirit of the present invention, can apply the process method and element structure of the present invention to various different power transistors. The power transistor structure and its manufacturing method according to the present invention are based on The metal with a low resistance value forms part of the idle electrode structure, thereby reducing the gate resistance and enhancing the switching speed of the gate electrode. The manufacturing method of the present invention can be used in a variety of power transistors, not limited to the preferred embodiments described below. The present invention discloses a method for manufacturing a high-power semiconductor element. By changing the gate structure within the element, the conventional closed-pole resistance value is too high, so that the switching speed cannot be improved. The second to ninth figures show specific embodiments using the present invention on a high-power semiconductor device architecture. As shown in the second figure, a silicon substrate 200 with appropriate resistance is provided. The I23l57l material can be an N + or P + semiconductor substrate. In a preferred embodiment of the present invention, the substrate is N. A semiconductor substrate 200 is used as a drain region of a semiconductor element to be formed. In addition, a lightly doped n-type epitaxial silicon layer 21 with an appropriate resistance is formed on the N-type semiconductor substrate 200. In the embodiment of the present invention, the concentration is 10i4 to 10i5 cm-2. . Secondly, as described in the second figure, a gate oxide layer 220 is grown on the worm crystal layer 21o. For example, the gate oxide layer 22o can be generated by a heating oxidation process. Thereafter, a layer of polycrystalline silicon is deposited over the gate oxide layer 22 as a gate conductive layer. Coincidentally, a photoresist pattern layer is formed on the polycrystalline silicon layer by using a photomask (not shown) and other steps to define a gate electrode 230. Referring to the third figure, after the gate 23 is formed on the epitaxial silicon layer 21o, the gate 230 is used as a screen cover to perform a substrate area on the surface of the epitaxial silicon layer 210 exposed on both sides of the gate. In the ion implantation step, the implanted ions are ions having opposite electrical properties to the epitaxial silicon layer 21. In the practice of the present invention, ions containing sheds are implanted and implanted, and the impurity concentration of the implanted material is about 1017 cm-2. After implanting ions in the basal area, the basal area is formed by thermal driving. 240. A patterned photoresist layer (not shown) is then formed. The photoresist layer is used to form a source region. With this patterned photoresist layer as a mask, the implanted base region 24G is implanted with ions to form a doped region in the base region 24 as the source region 242 of the fabricated transistor. The electrical properties of the ion implantation in the source region 242 are opposite to the electrical properties of the base region 240. 1231571 Next, referring to the fourth figure, an oxide layer 250 is deposited on a portion of the epitaxial silicon layer 210 and the gate 230. The oxide layer 250 is deposited by a chemical vapor deposition method and has a thickness of about 2000 angstroms. Referring to the fifth figure, another photoresist pattern layer 246 is formed on the oxide layer 250, and a part of the area above each of the independent complex gates 230 is exposed. Next, using the photoresist pattern layer 246 as an etching mask, an etching process is performed on the oxide layer 250 and the gate 230, respectively, to form a trench structure 248 in the gate 230, and a part of the polycrystalline silicon layer is exposed. This etching method. For example, an anisotropic reactive ion etch (RIE) process can be used to etch the gate 230 to form a trench structure 248 as shown in FIG. 6, and then remove the photoresist pattern layer 246. Next, a tungsten silicide layer is deposited on the oxide layer 250 and the trench structure 248. Since tungsten silicide has the characteristics that it is not easy to adhere to the oxide layer, but is easy to form on the polycrystalline silicon layer, there will be only the complex exposed by the trench structure 248. A deposit of Shi Xihua 260 is formed on the spar layer, as shown in Figure 7. Next, in the eighth figure, the contact window is manufactured. First, an insulating protective layer 270 is formed to cover the tungsten silicide 260 and the oxide layer 250. The insulating cover layer 270 may be, for example, phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). Atmospheric Pressure Chemical Vapor Deposition (APCVD) is used to deposit PSG. ), And Plasma-enhanced Chemical Vapor Deposition (PECVD) method is used to deposit lithosparite glass (BPSG). 1231571 Next, a patterned photoresist layer (not shown in the figure) is formed on the insulating protective layer 270. The sister uses this patterned photoresist layer as a mask to perform a dielectric layer etching process to expose the source regions 242 and In the base region 240, since the formed insulating protective layer 270 is also an oxide layer, while removing a part of the insulating protective layer 270, the oxide layer 25 is also removed. Next, a metal layer 280 is formed on the insulating protective layer 270 and the exposed source region 242 and the base region 24, as shown in the ninth figure. In summary, the high-power transistor disclosed in the present invention has a metal structure with a low resistance value in the gate junction φ structure, which can reduce the gate resistance and enhance the switching speed of the gate electrode. ^ Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the scope of the present invention. Therefore, the scope of guarantee of the present invention shall be determined by the scope of the attached patent application.
11 1231571 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 第一圖描述先前技術中高功率半導體元件的結構剖 面圖； 第圖至第八圖為本發明一較佳實施例之一高功率 半導體元件之製造流程剖面示意圖；以及 第九圖為本發明一較佳實施例之一完成後高功率半 導體元件之剖面示意圖。 【元件代表符號簡單說明】 100 半導體基材 110 梦蠢晶層 120 輕摻雜P井區 130 重摻雜N井區 140 閘層氧化層 150 複晶矽閘極 160 领鱗；5夕玻璃 170 金屬層 180 基底區域 200 半導體基材 210 蟲晶碎層 220 閘層氧化層 230 閘極 240 基底區域 242 源極 248 溝渠結構 12 1231571 250 氧化層 260 矽化鎢 270 絕緣護層 280金屬層11 1231571 [Brief description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: A figure depicts a structural cross-sectional view of a high-power semiconductor element in the prior art; FIGS. 8 to 8 are schematic cross-sectional views illustrating a manufacturing process of a high-power semiconductor element according to a preferred embodiment of the present invention; A schematic cross-sectional view of a high-power semiconductor device after the completion of one of the embodiments. [A brief description of the element representative symbols] 100 semiconductor substrate 110 dream crystal layer 120 lightly doped P well region 130 heavily doped N well region 140 gate oxide layer 150 polycrystalline silicon gate 160 collar scale; 5th glass 170 metal Layer 180 Base area 200 Semiconductor substrate 210 Worm crystal debris layer 220 Gate oxide layer 230 Gate 240 Base area 242 Source 248 Drain structure 12 1231571 250 Oxide layer 260 Tungsten silicide 270 Insulating protective layer 280 Metal layer
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