TWI231466B - Semiconductor element array structure and pixel array structure - Google Patents
Semiconductor element array structure and pixel array structure Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 19
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 30
- 239000004020 conductor Substances 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000002950 deficient Effects 0.000 description 4
- 241000282326 Felis catus Species 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000030833 cell death Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
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Abstract
Description
1231466 五、發明說明（1) 發明所屬之技術領域 本發明是有關於一種半導體元件陣列結構 (Semiconductor element array structure)，且特別是 有關於一種能夠提高液晶面板（Liquid Crystal Display panel, LCD panel)之生產良率（Yield)的畫素陣列結構 (Pixel array structure) ° 先前技術 近年來，液晶顯示技術已經漸漸地廣泛應用於日常生 活上，如液晶電視（LCD TV)、手提電腦（Notebook)或桌上 型電腦的液晶螢幕（LCD)，以及液晶投影機（LCD projector)等。其中，又以液晶投影機為大尺寸顯示不可 或缺的技術之一，由於液晶投影機所使用之液晶顯示面板 必須顧及所投影出之影像解析度（R e s 〇 1 u t i 〇 η )，因此大多 會採用具有相當高解析度之液晶面板。 傳統應用於液晶投影機之液晶面板係一種架構於玻璃 基板或石夕基底（Silicon substrate)上的液晶顯示元件。 由於液晶面板係以薄膜電晶體（T h i n F i 1 m T r a n s i s t 〇 r， TFT)或金屬氧化半導體電晶體1231466 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a semiconductor element array structure, and in particular to a method capable of improving a liquid crystal panel (Liquid Crystal Display panel, LCD panel) Pixel Array Structure for Yield ° Previous Technology In recent years, liquid crystal display technology has gradually been widely used in daily life, such as LCD TVs, notebooks or desks. The liquid crystal display (LCD) of the supercomputer, and the LCD projector. Among them, the liquid crystal projector is one of the indispensable technologies for large-scale display. Since the liquid crystal display panel used by the liquid crystal projector must take into account the projected image resolution (R es 〇1 uti 〇η), most of them LCD panels with fairly high resolution will be used. A liquid crystal panel traditionally used in a liquid crystal projector is a liquid crystal display element structured on a glass substrate or a silicon substrate. Since the liquid crystal panel is a thin film transistor (T h i n F i 1 m T r a n s i s t 〇 r, TFT) or a metal oxide semiconductor transistor
(Metal -Oxide-Semiconductor transistor, MOS transistor)作為主動元件，而這些主動元件可藉由與其 電性連接之反射電極（Reflective eiectrode)驅動液晶， 以達到顯示之目的。由於液晶面板架構於玻璃基板或石夕基 底上’體積小且具有高解析度，所以液晶面板十分符合& 晶投影機在體積上日益縮減的需求。(Metal-Oxide-Semiconductor transistor, MOS transistor) is used as an active element, and these active elements can drive the liquid crystal through a reflective electrode (Reflective eiectrode) electrically connected to the active element to achieve the purpose of display. Since the liquid crystal panel is structured on a glass substrate or a stone substrate, it is small in size and has a high resolution, so the liquid crystal panel is well in line with the demand of the & crystal projector for its shrinking size.
1231466 五、發明說明（2) 第1圖繪示為習知液晶面板之畫素陣列結構的局部電 路圖。請參照第1圖，習知液晶面板之畫素陣列結構1 〇 〇主 要係由多個電晶體1 1 0、多條資料配線1 2 0、多條第一子掃 瞄配線1 3 0以及多條第二子掃瞄配線1 4 0所構成。其中，資 料配線1 2 0係電性連接至電晶體1 1 0之兩個汲極/源極其中 —— 〇 由於資料配線1 2 0與第二子掃瞄配線1 4 0係由同一層金 屬層或導電材料層圖案化而成，因此資料配線1 2 0不能直 接與第二子掃瞄配線1 4 0交錯，需要以第一子掃瞄配線1 3 0 跳線連接第二子掃瞄配線1 4 0。第一子掃瞄配線1 3 0係通過 電晶體1 1 0之通道上方，以作為電晶體1 1 0之閘極，且第一 子掃瞄配線1 3 0係與資料配線1 2 0交錯。第二子掃瞄配線 1 4 0之兩端係分別以單一接觸部電性連接至相鄰之第一子 掃瞄配線1 3 0，且接觸部位於電晶體1 1 0之通道一側。 習知液晶面板中，由於第一子掃瞄配線1 3 0與第二子 掃瞄配線1 4 0之間僅以一接觸部電性連接，因此只要任一 接觸部電性連接不良，就會造成掃瞄配線的不良率（Y i e 1 d 1 o s s)上升，進而影響液晶面板的整體顯示效果。 發明内容 因此，本發明的目的就是在提供一種晝素陣列結構， 適於解決液晶面板的不良率過高之缺點。 本發明的再一目的就是在提供一種半導體元件陣列結 構，適於解決其不良率過高之缺點。 基於上述目的，本發明提出一種畫素陣列結構，適用1231466 V. Description of the invention (2) Figure 1 shows a partial circuit diagram of a pixel array structure of a conventional liquid crystal panel. Please refer to FIG. 1. The pixel array structure 1 of the conventional liquid crystal panel is mainly composed of multiple transistors 1 10, multiple data wirings 1 2 0, multiple first sub-scanning wirings 1 3 0, and many more. The second sub-scanning wiring is composed of 140. Among them, the data wiring 1 2 0 is electrically connected to the two drains / sources of the transistor 1 10. Among them— 〇 because the data wiring 1 2 0 and the second sub-scanning wiring 1 4 0 are made of the same layer of metal Layer or conductive material layer is patterned, so the data wiring 1 2 0 cannot be directly interleaved with the second sub-scanning wiring 1 40, and the first sub-scanning wiring 1 3 0 jumper needs to be connected to the second sub-scanning wiring 1 4 0. The first sub-scanning wiring 130 is passed through the channel of the transistor 110 to serve as the gate of the transistor 110, and the first sub-scanning wiring 130 is interleaved with the data wiring 120. Both ends of the second sub-scanning wiring 140 are electrically connected to the adjacent first sub-scanning wiring 130 by a single contact portion, and the contact portions are located on the channel side of the transistor 110. In the conventional liquid crystal panel, since the first sub-scanning wiring 130 and the second sub-scanning wiring 140 are electrically connected with only one contact portion, as long as the electrical connection of any contact portion is poor, As a result, the defective rate (Yie 1 d 1 oss) of the scanning wiring is increased, which further affects the overall display effect of the liquid crystal panel. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a daylight array structure, which is suitable for solving the disadvantage that the defective rate of a liquid crystal panel is too high. Another object of the present invention is to provide a semiconductor element array structure which is suitable for solving the disadvantage of excessively high defect rate. Based on the above purpose, the present invention proposes a pixel array structure, which is applicable
12051twf.ptd 第8頁 1231466 五、發明說明（3) 於一液晶顯示面板。此晝素陣列結構主要係由多條資料配 線、與資料配線交錯配置之多條掃瞄配線、藉由資料配線 與掃瞄配線驅動之多個電晶體，以及由電晶體控制之多個 晝素電極所構成。 此實施例之晝素陣列結構的特徵在於，每條掃瞄配線 至少包括一條第一子掃瞄配線、多個接觸部以及一條第二 子掃瞄配線。其中，第一子掃瞄配線與對應之資料配線交 錯但不互相電性連接。接觸部分佈於第一子掃瞄配線上至 少二互相分離之區域，並與第一子掃瞄配線電性連接。第 二子掃瞄配線係經由接觸部而電性連接至第一子掃瞄配 線。 基於上述目的，本發明再提出一種半導體元件陣列結 構，主要係由多條資料配線、多條掃瞄配線及多個電晶體 所構成。其中，掃瞄配線係與資料配線交錯配置。電晶體 係藉由資料配線與掃瞄配線驅動。 每一條掃目苗配線至少包括一條第一子掃猫配線、多個 接觸部以及一條第二子掃瞄配線。其中，第一子掃瞄配線 與對應之資料配線交錯但不互相電性連接。接觸部分佈於 第一子掃瞄配線上至少二互相分離之區域，並與第一子掃 瞄配線電性連接。第二子掃瞄配線係經由接觸部而電性連 接至第一子掃目苗配線。 在上述兩種實施例中，接觸部可以是分別位於電晶體 的通道周圍一處上方或兩側。 綜上所述，在本發明之晝素陣列結構與半導體元件陣12051twf.ptd Page 8 1231466 V. Description of the invention (3) On a liquid crystal display panel. This daylight array structure is mainly composed of multiple data wirings, multiple scanning wirings interleaved with the data wirings, multiple transistors driven by the data wirings and scanning wirings, and multiple daylight elements controlled by the transistors. Made of electrodes. The diurnal array structure of this embodiment is characterized in that each scanning wiring includes at least a first sub-scanning wiring, a plurality of contact portions, and a second sub-scanning wiring. Among them, the first sub-scanning wiring is wrong with the corresponding data wiring but is not electrically connected to each other. The contact portion is arranged on at least two separated areas on the first sub-scanning wiring and is electrically connected to the first sub-scanning wiring. The second sub-scanning wiring is electrically connected to the first sub-scanning wiring through the contact portion. Based on the above object, the present invention further proposes a semiconductor element array structure, which is mainly composed of multiple data wirings, multiple scanning wirings, and multiple transistors. Among them, the scanning wiring and the data wiring are arranged alternately. The transistor is driven by data wiring and scanning wiring. Each sweeping seedling wiring includes at least a first sub-scanning cat wiring, a plurality of contact parts, and a second sub-scanning wiring. Among them, the first sub-scanning wiring and the corresponding data wiring are staggered but not electrically connected to each other. The contact portions are arranged on at least two separate areas on the first sub-scanning wiring and are electrically connected to the first sub-scanning wiring. The second sub-scanning wiring is electrically connected to the first sub-scanning wiring through the contact portion. In the above two embodiments, the contact portions may be located above or on both sides of the transistor channel, respectively. In summary, the day element array structure and the semiconductor element array of the present invention
12051twf.ptd 第9頁 1231466 __------------ 五、發明說明（4) 列結構中’第一子掃瞄配線與第二子掃瞄配線之間係以配 置於不同區域之多個接觸部而電性連接。因此，本發明之 畫素陣列結構與半導體元件陣列結構在掃瞄配線的部份， 玎將其電性連接之不良率有效降低，進而提升使用此晝素 降列結構之液晶面板的整體顯示效果且降低生產成本。同 時，亦提升使用此半導體元件陣列結構之電子產品的整體 良率真降低生產成本。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易僅’下文特舉較佳實施例，並配合所附圖式，作詳細 説明如下。12051twf.ptd Page 9 1231466 __------------ 5. Description of the invention (4) In the column structure, the first sub-scanning wiring and the second sub-scanning wiring are arranged between The plurality of contact portions in different regions are electrically connected. Therefore, the pixel array structure and the semiconductor element array structure of the present invention scan the wiring portion, and effectively reduce the defective rate of the electrical connection, thereby improving the overall display effect of the liquid crystal panel using the daylight pixel array structure. And reduce production costs. At the same time, the overall yield of electronic products using this semiconductor element array structure is also improved, which really reduces production costs. In order to make the above and other objects, features, and advantages of the present invention more apparent, only preferred embodiments are described below in detail with reference to the accompanying drawings, as follows.
第2 A、2 β、2 C圖繪示為本發明三種較佳實施例之晝素 陣列結構的局部電路圖。這些較佳實施例之畫素陣列結構 係適用於一液晶顯示面板，在此僅以其中一對晝素結構的 電路圖做介紹。請參照第2 Α圖，畫素陣列結構2 0 0主要係 由多個電晶體2 1 0、多個晝素電極（圖未示）、多條資料配 線2 2 0以及多條掃瞄配線2 3 0所構成。其中，電晶體21 〇例 如係薄膜電晶體或金屬氧化半導體電晶體，每個電晶體 2 1 0例如具有一通道2 1 2、汲極/源極2 1 4、2 1 6。Figures 2A, 2β, and 2C show partial circuit diagrams of the diurnal array structure of the three preferred embodiments of the present invention. The pixel array structure of these preferred embodiments is suitable for a liquid crystal display panel, and only a circuit diagram of a pair of day pixel structures will be described here. Please refer to FIG. 2A. The pixel array structure 2 0 0 is mainly composed of multiple transistors 2 1 0, multiple day electrodes (not shown), multiple data wirings 2 2 0, and multiple scanning wirings 2 3 0. Among them, the transistor 21 is, for example, a thin film transistor or a metal oxide semiconductor transistor, and each transistor 2 1 0 has, for example, a channel 2 1 2 and a drain / source 2 1 4 and 2 1 6.
晝素陣列結構2 0 0的特徵在於，每條掃瞄配線23〇係由 多條第一子掃瞄配線2 3 2，多個接觸部2 3 6以及多條第二掃 瞄子配線2 3 4所構成。其中，第一子掃瞄配線2 3 2係通過電 晶體2 1 0之通道2 1 2上方，例如作為電晶體2 1 〇之閘極。而 且’第一子掃瞄配線2 3 2係與資料配線2 2 0交錯，但彼此不The daylight array structure 2000 is characterized in that each scanning wiring 230 is composed of a plurality of first sub-scanning wirings 2 3 2, a plurality of contact portions 2 3 6 and a plurality of second scanning sub-wirings 2 3 4 composition. Among them, the first sub-scanning wiring 2 3 2 passes above the channel 2 12 of the transistor 2 10, for example, as a gate of the transistor 2 1 0. Moreover, the first sub-scanning wiring 2 3 2 is interlaced with the data wiring 2 2 0, but they are not
1231466 五、發明說明（5) 連接。多個接觸部23 6至少分佈於 上兩個互相分離之區域，並盥第一 子柃瞄配線23 2 接。桩鎚刘9 ^办丨丄/ 兀興弟 子知瞄配線2 3 2電性連 ，接觸部236例如係位於電晶體210之通道212的周圊一 二上方或兩側。每條第二子掃瞄配多& 部2 3 6而分別電性連接 4係經由夕個接觸 中，桩縮卹MR夕a f 對應第一子知瞒配線2 3 2。其 接觸4 2 3 6之位置係以避開通道2丨2正 請參照第2A、2B圖，轮兩阁φ笛 f万為住 鉍暂办丨上於夕曰 〇 此兩圖中第一子掃瞄配線232之 如同Α笛二二ΐ 2，第二子掃瞒配線2 3 4與資料配線2 2。例 之*層。請參照第2。圖，第-子掃瞄配線232 制士八二二3 :晶石夕’第二子掃猫配線2 34與資料配線220 刀”、、第一金屬層或第一金屬層。承上述，若第二子 ^瞄配線234與資料配線22〇係由同一導體層圖案化而形 f ’則可減少在液晶面板的製程中所需形成之金屬層數 量’進而降低約10%的生產成本。 第3圖繪^示為根據本發明一較佳實施例之晝素陣列結 構的7局不意圖。本較佳實施例之晝素陣列結構係適用於 一液晶面板。請參照第3圖，畫素陣列結構3 0 0主要係由多 個電晶體310、多個畫素電極3 0 6、多條資料配線3 20、多 條第一子掃瞒配線3 3 2以及多條第二子掃瞄配線3 34所構 成0 電晶體3 1 0係形成於矽基底3 〇 4上，而電晶體3 1 0具有 通道3 1 2與汲極/源極3丨4、3丨6。相鄰之兩個電晶體3 1 〇例 如係共用一個源極3 1 6。 畫素電極3 0 6係配置於矽基底3 0 4上，且例如經由一接1231466 V. Description of the invention (5) Connection. The plurality of contact portions 23 6 are distributed at least in the two separated areas, and are connected to the first sub-target wiring 23 2. The pile hammer Liu 9 办 Office 丨 / Wu Xing disciples Zhizhi wiring 2 3 2 is electrically connected, the contact portion 236 is, for example, located above or on both sides of the channel 212 of the channel 212 of the transistor 210. Each of the second sub-scans is equipped with multiple & parts 2 3 6 and is electrically connected respectively. 4 series of contacts are connected to each other, and the pile-down shirt MR af corresponds to the first sub-wiring line 2 3 2. The position where it touches 4 2 3 6 is to avoid the passage 2 丨 2 Please refer to Figures 2A and 2B. The two φ flutes f Wan for bismuth live temporarily 丨 on Yu Xiyu 〇 The first child in these two pictures The scanning wiring 232 is the same as the A flute 222, the second scanning wiring 232 and the data wiring 222. Example * layer. Please refer to section 2. Figure, sub-scanning wiring 232 Master 8222: Spar Xi ''s second sub-scanning cat wiring 2 34 and data wiring 220 knife ", the first metal layer or the first metal layer. Following the above, if The second sub-line 234 and the data line 22 are patterned by the same conductor layer, and the shape f 'can reduce the number of metal layers required to be formed in the process of manufacturing the liquid crystal panel, thereby reducing the production cost by about 10%. FIG. 3 is a schematic diagram showing 7 rounds of the daylight array structure according to a preferred embodiment of the present invention. The daylight array structure of the preferred embodiment is suitable for a liquid crystal panel. Please refer to FIG. 3, pixels The array structure 3 0 0 is mainly composed of multiple transistors 310, multiple pixel electrodes 3 0 6, multiple data wirings 3 20, multiple first sub-scanning wirings 3 3 2 and multiple second sub-scanning wirings. The transistor 3 1 0 composed of 3 34 is formed on a silicon substrate 3 04, and the transistor 3 1 0 has a channel 3 1 2 and a drain / source 3 丨 4, 3 丨 6. Two adjacent ones The transistor 3 1 0 is, for example, sharing a source 3 1 6. The pixel electrode 3 0 6 is disposed on a silicon substrate 3 0 4 and is
!231466 五、發明說明（6) ^ = 0而電性連接至汲極3丨4。資料配線3 2 〇係配置於矽 。4上’且例如經由一接觸部3 42而電性連接至源極 綠一子掃瞄配線3 3 2係通過通道312上方，且與資料配 對施父&錯但不互相電性連接。每條第一子掃瞄配線3 32在 I I ί f料’線32〇的兩側皆具有多個接觸部3 36， 338。 雷=* 7*子柃瞄配線3 34係分別藉由多個接觸部3 3 6， 338 對/之第一子掃瞄配線3 3 2。多個接觸部33 6， 3M刀佈於電晶體31〇之通道312周圍上方且與第一子掃 ::通3、di 3接。參照第3圖，兩個第-接觸部3 3 6係 #> ^ ii ^ Q 1 9 一處上方，而另兩個第二接觸部3 3 8例如 位置^以僻μ周圍另一處上方。接觸部33 6， 338之配置 位置係u避開通道312正上方為佳。 在本發明此較佳實施例中，坌一 料配線3 2 0與晝辛雷極& &门第了子知r田配線3 34、貝 成。由於資料配H』V 一導體層所圖案化而形 體層圖案化：点第二子掃瞄配線334係由同一層導 連接坌-工校成，因此才需要以第一子掃猫配線3 3 2跳線 瞒配線334。在此較佳實施例中，每條第-少利:坌、_ ^例如係與兩條資料配線3 2 0交錯，如此可減 性連接“ ：：Ϊ配線334進行跳線之次數，$而降低電 各格Ϊ亡2 f ’在本發明較佳實施例之畫素陣列結構中’ 接至對:掃瞒配線3 34藉由這些接觸部3 3 6， 338電性連 w之第一掃瞒配線3 3 2。因此，即使第二掃瞄配線! 231466 V. Description of the invention (6) ^ = 0 and electrically connected to the drain electrode 3 丨 4. The data wiring 3 2 0 is arranged in silicon. 4 on 'and is electrically connected to the source, for example, via a contact portion 3 42. The green sub-scanning wiring 3 3 2 passes through the channel 312 and is paired with the data, but is not electrically connected to each other. Each of the first sub-scanning wirings 3 32 has a plurality of contact portions 3 36, 338 on both sides of the I I ′ material 32 line. Thunder = * 7 * sub-scanning wiring 3 34 is the first sub-scanning wiring 3 3 2 with multiple contact portions 3 3 6, 338 pairs /. A plurality of contact portions 33 6 and 3M are disposed above and around the channel 312 of the transistor 31 and are connected to the first sub-scan :: 3, di 3. Referring to FIG. 3, the two first-contact portions 3 3 6 are # ^ ii ^ Q 1 9 above one place, and the other two second contact portions 3 3 8 are, for example, located above the other place around the remote μ. . It is preferable that the positions of the contact portions 33 6 and 338 be u directly above the passage 312. In this preferred embodiment of the present invention, the first material wiring 3 2 0 is connected to the day-sinning pole & gate wiring 3 34 and the battery. Because the material is patterned with a conductor layer H′V and the body layer is patterned: the second sub-scanning wiring 334 is connected by the same layer of conductor 工 -work school, so it is necessary to use the first sub-scanning wiring 3 3 2 jumper conceal wiring 334. In this preferred embodiment, each of the first-less profit: 坌, _ ^ is, for example, interleaved with two data wirings 3 2 0, so that the connection can be reduced. ": Ϊ The number of jumpers for wiring 334, $ and Decrease the electric cell death 2 f 'In the pixel array structure of the preferred embodiment of the present invention' Connect to the pair: Sweep the wiring 3 34 Electrically connect the first scan with these contacts 3 3 6, 338 Conceal wiring 3 3 2. So even the second scanning wiring
1231466 五、發明說明（7) 334 —端與任一接觸部336或338電性連接不良，仍可經由 其他接觸部3 3 8或3 3 6與第一子掃目结配線3 3 2電性連接，而 不會增加整條掃瞄配線之電阻值，甚至造成斷路而影響整 條掃瞄配線上的畫素之顯示。其中，本發明較佳實施例所 適用之液晶面板種類例如單晶矽反射液晶面板（L i qu i d Crystal on S i 1 i con display panel，LCOS display panel ) ° 習知液晶面板之畫素陣列結構的不良率係高於5 %， 且以高於7 %為常態。但是在採用本發明較佳實施例之設 計後，畫素陣列結構的不良率可降低到3 %左右。 值得注意的是，任何熟悉此技藝者在參考本發明較佳 實施例後應知，資料配線並不一定侷限須成對設計，其亦 可間隔一電晶體之方式設計。位於第二子掃瞒配線兩端之 接觸部的數量並不侷限於兩個，接觸部的數量亦可做適當 調整以增加良率。第二子掃瞄配線兩端之接觸部的配置位 置不侷限於分佈在電晶體通道的兩側，亦可配置於通道之 一側或更多側。而且，在本發明中雖以掃猫配線做跳線設 計而避開資料配線，但在適當調整後亦可以資料配線做跳 線設計而避開掃瞄配線，若搭配使用本發明之主要特徵’ 亦即增加跳線部份的接觸部，一樣可達到降低電極配線之 電性連接不良率的目的。 綜上所述，本發明之畫素陣列結構在跳線部伤不但增 加接觸部的數量，更將接觸部分佈於至少兩個互相分離之 區域，從機率的觀點來看，因接觸部發生損壞而造成的不1231466 V. Description of the invention (7) 334 —The terminal is poorly connected to any of the contacts 336 or 338, and can still be connected to the first sub-scanning junction 3 3 2 through other contacts 3 3 8 or 3 3 6 It can be connected without increasing the resistance value of the entire scanning wiring, or even causing a disconnection to affect the display of pixels on the entire scanning wiring. Among them, the type of liquid crystal panel applicable to the preferred embodiment of the present invention is, for example, a single crystal silicon reflective liquid crystal panel (L iqu id Crystal on S i 1 i con display panel, LCOS display panel) ° The pixel array structure of the conventional liquid crystal panel is known The defect rate is higher than 5%, and the normal rate is higher than 7%. However, after adopting the design of the preferred embodiment of the present invention, the defective rate of the pixel array structure can be reduced to about 3%. It is worth noting that anyone familiar with this art should know after referring to the preferred embodiment of the present invention that the data wiring is not necessarily limited to the design in pairs, and it can also be designed in the form of a transistor. The number of contact portions at the two ends of the second sub sweep line is not limited to two, and the number of contact portions can be appropriately adjusted to increase the yield. The arrangement positions of the contact portions at both ends of the second sub-scanning wiring are not limited to being distributed on both sides of the transistor channel, but may also be arranged on one or more sides of the channel. Moreover, in the present invention, the cat wiring is used as a jumper design to avoid data wiring, but after proper adjustment, the data wiring can also be used as a jumper design to avoid scanning wiring. If used in conjunction with the main features of the invention ' In other words, increasing the contact portion of the jumper part can also reduce the electrical connection failure rate of the electrode wiring. In summary, the pixel array structure of the present invention not only increases the number of contact portions in the jumper portion, but also arranges the contact portions in at least two separate areas. From the perspective of probability, the contact portion is damaged. And cause
Ϊ 2051twf.ptd 第13頁 1231466 五、發明說明（8) 良率應可大幅降低。而且，在畫素陣列結構的製程中，只 需針對第一層金屬（亦即資料配線與第二掃瞄配線）、介電 層（接觸窗位置）以及多晶矽層（亦即第一掃瞄配線）等三層 材料層之光罩進行修改。更重要的是’並不會影響畫素的 特性。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。51 2051twf.ptd Page 13 1231466 V. Description of the invention (8) The yield should be greatly reduced. Moreover, in the manufacturing process of the pixel array structure, only the first layer of metal (that is, the data wiring and the second scanning wiring), the dielectric layer (the position of the contact window), and the polycrystalline silicon layer (that is, the first scanning wiring) ) And other three masks to modify the mask. What's more important is that it does not affect the characteristics of the pixels. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
12051twf.ptd 第14頁 1231466 圖式簡單說明 第1圖繪示為習知液晶面板之畫素陣列結構的局部電 路圖。 第2 A、2 B、2 C圖繪示為本發明三種較佳實施例之畫素 陣列結構的局部電路圖。 第3圖繪示為根據本發明一較佳實施例之畫素陣列結 構的佈局不意圖。 【圖式標示說明】 1 0 0 :晝素陣列結構 1 1 0 :電晶體 1 2 0 ··資料配線 1 3 0 :第一子掃瞄配線 1 4 0 :第二子掃瞄配線 2 0 0、3 0 0 :晝素陣列結構 2 1 0、3 1 0 :電晶體 212 、 312 :通道 2 1 4、2 1 6、3 1 4、3 1 6 :沒極 / 源極 2 2 0、3 2 0 :資料配線 2 3 0 ··掃瞄配線 2 3 2、3 3 2 ··第一子掃瞒配線 2 3 4、3 3 4 :第二子掃瞄配線 2 3 6 ： 接 觸部 3 04 ·· 矽 基底 3 0 6 ： 畫 素電極 3 3 6 ： 第 一接觸部12051twf.ptd Page 14 1231466 Brief Description of Drawings Figure 1 shows a partial circuit diagram of the pixel array structure of a conventional liquid crystal panel. Figures 2A, 2B, and 2C show partial circuit diagrams of the pixel array structure of the three preferred embodiments of the present invention. FIG. 3 illustrates the layout of the pixel array structure according to a preferred embodiment of the present invention. [Illustration of diagrammatic representation] 1 0 0: day element array structure 1 1 0: transistor 1 2 0 ·· data wiring 1 3 0: first sub-scanning wiring 1 4 0: second sub-scanning wiring 2 0 0 , 3 0 0: day element array structure 2 1 0, 3 1 0: transistor 212, 312: channel 2 1 4, 2 1 6, 3 1 4, 3 1 6: pole / source 2 2 0, 3 2 0: Data wiring 2 3 0 ·· Scanning wiring 2 3 2, 3 3 2 ·· First sub-scanning wiring 2 3 4, 3 3 4: Second sub-scanning wiring 2 3 6: Contact 3 04 ·· Silicon substrate 3 0 6: Pixel electrode 3 3 6: First contact portion
12051twf.ptd 第15頁 1231466 圖式簡單說明 3 38 :第二接觸部 3 4 0、3 4 2 :接觸部 第16頁 12051twf.ptd 111··12051twf.ptd page 15 1231466 Brief description of the drawing 3 38: second contact section 3 4 0, 3 4 2: contact section page 16 12051twf.ptd 111 ··
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