TWI231024B - Wafer level chip scale package with redistribution wires by wire bonding and method for manufacturing the same - Google Patents

Wafer level chip scale package with redistribution wires by wire bonding and method for manufacturing the same Download PDF

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Publication number
TWI231024B
TWI231024B TW092112599A TW92112599A TWI231024B TW I231024 B TWI231024 B TW I231024B TW 092112599 A TW092112599 A TW 092112599A TW 92112599 A TW92112599 A TW 92112599A TW I231024 B TWI231024 B TW I231024B
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Taiwan
Prior art keywords
wafer
redistribution
wire
active surface
bonding
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TW092112599A
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Chinese (zh)
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TW200425448A (en
Inventor
Shr-Jie Jeng
John Liu
Yeong-Ching Chao
Yeong-Her Wang
Yau-Rung Li
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Chipmos Technologies Inc
Chipmos Technologies Bermuda
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Priority to TW092112599A priority Critical patent/TWI231024B/en
Publication of TW200425448A publication Critical patent/TW200425448A/en
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Publication of TWI231024B publication Critical patent/TWI231024B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A wafer level chip scale package with redistribution wires by wire bonding comprises a chip, a plurality of redistribution wires formed by wire-bonding and at least a dielectric upholder. The chip has a bottom surface and an active surface with a plurality of bonding pads. Each redistribution wire has a connecting end, at least a bonding node and a rising tip. The connecting ends are bonded on the bonding pads. The bonding nodes are disposed on the active surface. The rising tips are raising away the active surface of the chip and supported by the dielectric upholder. Thus it is to replace a redistribution layer, a stress buffer layer, a plurality of bumps and an IC carrier.

Description

1231024 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種晶圓級晶片尺寸封裝，特別係有 關於一種免用重分配電路層、應力緩衝層、凸塊及〗(：載板 之晶圓級晶片尺寸封裝結構。 【先前技術】 晶圓級晶片尺寸封裝結構（wafer level chip scale package，WLCSP)係為一種尺寸微小化之封裝結構，其封 裝尺寸係與晶片尺寸接近或相等，晶圓級晶片尺寸封裝結 構在製造過程中係在晶圓型態進行封裝，常見的晶圓級晶1231024 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a wafer-level wafer-size package, and more particularly, to a useless redistribution circuit layer, a stress buffer layer, a bump, and [(: [Previous technology] Wafer level chip scale package (WLCSP) is a miniaturized package structure whose package size is close to the wafer size or Equal, the wafer-level wafer-size package structure is packaged in the wafer type during the manufacturing process. Common wafer-level crystals

片尺寸封裝結構係以銲球或凸塊作為外部電性導接點，由 於晶圓級晶片尺寸封裴結構内晶片與外部接合之印刷電路 板具有不相匹配之熱膨脹係數差異，在接合後會對晶片與The chip size package structure uses solder balls or bumps as external electrical contacts. Because the wafer-level wafer size seal structure has a mismatched thermal expansion coefficient between the wafer and the externally bonded printed circuit board, it will be different after bonding. Pair of chips with

知=*球或凸塊產生熱應力作用，甚至可能導致銲球或凸塊之 金屬疲勞（metal fatigue)，並且在銲球與晶片之間形成 有一應力緩衝層及一重分配電路層，如我國專利公告第 5 1 1 267號「緩衝式雙墊片晶圓級封裝結構」揭示之一種晶 圓級封裝結構，其包含有一矽晶圓，該矽晶圓上形成有複 數個導體柱、絕緣保護層及複數個導電凸塊，利用該些導 體柱與絕緣保護層作為該矽晶圓之應力緩衝層，該此導電 凸塊係供該矽晶圓外部電性連接用，該晶 ^二 包含有-重分配電路層以達到電路重分配之功= = 之重分配電路層需經過繁瑣的濺鍍、上光阻、 影、蝕刻等製程，增加成本。 曝先、顯 此外’另-種晶圓級晶片尺寸封裝結構係如日本公開Knowing that the ball or bump generates thermal stress, and may even cause metal fatigue of the solder ball or bump, and a stress buffer layer and a redistribution circuit layer are formed between the solder ball and the wafer, such as Chinese patents Announcement No. 5 1 1 267 "Buffered Double-Shim Wafer-Level Packaging Structure" discloses a wafer-level packaging structure that includes a silicon wafer on which a plurality of conductive pillars and an insulating protection layer are formed. And a plurality of conductive bumps, using the conductive pillars and the insulating protection layer as a stress buffer layer of the silicon wafer, the conductive bumps are used for external electrical connection of the silicon wafer, and the crystals include- Redistribution of the circuit layer to achieve the function of circuit redistribution = = The redistribution circuit layer needs to undergo tedious sputtering, photoresist, shadowing, etching and other processes, increasing costs. Exposed first, obviously In addition, another kind of wafer-level wafer size package structure is disclosed in Japan

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特許公報之特開2002-05071 7號「半導體裝置及其製造方 法」所揭示者，該專利所揭示之晶圓級尺寸封裝封裝結構 係 >包含有一晶片，該晶片具有一形成有銲墊之主動區域， 在°亥鲜塾上形成有一金屬凸塊（metal projection)，以連 接:金屬配線之一端，使該金屬配線係連接於該金屬凸塊 而受，撐成懸臂樑狀，該金屬配線之另一端連接一銲球以 供外部接合，利用受該金屬凸塊支撐而成懸臂樑狀之該金 屬配線以吸收銲球或金屬凸塊之作用應力，該些金屬凸塊 之結合點係須能承受該些懸臂樑狀金屬配線與該些銲球，· 故應以密封樹脂密封該些金屬凸塊，並以帶狀配線支撐樹j 脂膜連接該些金屬配線，以避免該些懸臂樑狀金屬配線與 該些銲球之脫出。 【發明内容】 本發明之主要目的係在於提供一種利用打線重分配銲 線之晶圓級晶片尺寸封裝結構，利用複數個打線形成之重 分配銲線形成於一晶片之主動面上，每一銲線係具有一結 線端、至少一銲節及一懸空末梢端，利用該些懸空末梢端 作為該晶圓級晶片尺寸封裝結構之外部接點，以該些打線 形成之重分配銲線取代習知之重分配電路層、應力緩衝 層、凸塊及IC載板。 本發明之次一目的係在於提供一種利用打線重分配銲 線之晶圓級晶片尺寸封裝結構’利用複數個打線形成之重 分配銲線形成於一晶片之主動面上，每一銲線係形成有具 彈性之一懸空末梢端作為該晶圓級晶片尺寸封裝結構之外As disclosed in Japanese Patent Laid-Open No. 2002-05071 7, "Semiconductor Device and Manufacturing Method thereof", the wafer-level package and package structure disclosed in the patent contains a wafer having a bonding pad formed thereon. In the active area, a metal projection (metal projection) is formed on the helium coil to connect: one end of the metal wiring, so that the metal wiring is connected to the metal projection, and is supported in a cantilever shape. The metal wiring The other end is connected with a solder ball for external bonding. The metal wiring formed by a cantilever beam supported by the metal bump is used to absorb the stress of the solder ball or the metal bump. The bonding point of the metal bumps must be Can withstand the cantilever-shaped metal wiring and the solder balls, so the metal bumps should be sealed with a sealing resin, and the metal wiring should be connected by a strip-shaped wiring support grease film to avoid the cantilever The metal wire is separated from the solder balls. [Summary of the Invention] The main object of the present invention is to provide a wafer-level wafer size package structure using wire redistribution bonding wires, and a redistribution bonding wire formed by a plurality of bonding wires is formed on the active surface of a wafer. The wire system has a knot wire end, at least one solder joint and a floating tip end. The floating tip ends are used as external contacts of the wafer-level wafer-size package structure, and the conventional redistribution bonding wires formed by the wires are used to replace the conventional ones. Redistribute circuit layers, stress buffer layers, bumps, and IC substrates. A second object of the present invention is to provide a wafer-level wafer size package structure using wire redistribution bonding wires. A redistribution bonding wire formed by a plurality of bonding wires is formed on an active surface of a wafer, and each bonding wire is formed. Flexible one with floating tip as outside of the wafer level wafer size package structure

12310241231024

部接點，該些懸空末梢端係被—鄰接之介電性托護件所支 撐托護，利用該些懸空末梢端與該介電性托護件取代習知 之應力緩衝層、凸塊及1(：載板，彡到晶圓級晶片尺寸 結構之彈性緩衝增益性。Contact, the suspended tip ends are supported by the adjoining dielectric support member, and the suspended tip ends and the dielectric support member are used to replace the conventional stress buffer layer, bump and 1 (: Carrier board, flexible buffer gain of wafer-level wafer size structure.

本發月之再目的係在於提供一種利用打線重分配銲 線之晶圓級晶片尺寸封裝結構之製造方法，其特徵係在 於，打線形成複數個重分配銲線於該晶片之主動面上，每 一銲線具有一結線端、至少一銲節及一懸空末梢端，以該 些懸二末梢、作為該晶圓級晶片尺寸封裝結構之外部接 點’利用該些打線形成之重分配銲線取代習知之重分配電 路層、應力緩衝層、凸塊及1C載板。The purpose of this issue is to provide a manufacturing method of a wafer-level wafer size package structure using wire redistribution bonding wires, which is characterized in that a plurality of redistribution bonding wires are formed on the active surface of the wafer by wire bonding. A bonding wire has a knot end, at least one solder joint, and a floating tip end. The two suspended tips are used as external contacts of the wafer-level wafer-size package structure to replace the redistribution bonding wire formed by the bonding wires. The conventional redistribution circuit layer, stress buffer layer, bump and 1C carrier board.

依本發明之利用打線重分配銲線之晶圓級晶片尺寸封 裝結構，該晶圓級晶片尺寸封裝結構係包含有一晶片、複 數個打線形成之重分配銲線及至少一介電性托護件，該晶 片係具有一主動面及一背面，該主動面係形成有複數個銲 墊及複數個中繼墊，每一銲線係具有一結線端、至少一銲 節及一懸空末梢端，該些結線端係設於該些銲墊上，該些 銲節係結合於之中繼墊，以鄰近該介電性托護件為較佳， 該些懸空末梢端係懸空翹離該晶片之主動面，該介電性托 護件設於該晶片之主動面上並支撐托護該些銲線之懸空末 梢端，刊用該介電性托護件與該些懸空末梢端，取代習知 之應力緩衝層、凸塊及IC載板，此外，利用銲線一端之結 線端與該晶片之銲墊連接並以另一端之懸空末梢端與外部 接合，以取代習知之重分配電路層與凸塊。According to the present invention, a wafer-level wafer size packaging structure using wire redistribution bonding wires is provided. The wafer-level wafer size packaging structure includes a chip, a plurality of redistribution bonding wires formed by a plurality of wires, and at least one dielectric support member. The chip system has an active surface and a back surface. The active surface is formed with a plurality of welding pads and a plurality of relay pads. Each welding line system has a knot end, at least one solder joint and a suspended tip end. The knot ends are disposed on the solder pads, the solder joints are combined with the relay pads, and it is better to be adjacent to the dielectric support member, and the suspended tip ends are suspended and lifted off the active surface of the chip. The dielectric support member is provided on the active surface of the chip and supports the suspended tip ends of the bonding wires. The dielectric support member and the suspended tip ends are used instead of the conventional stress buffering. Layers, bumps, and IC substrates. In addition, the junction end of one end of the bonding wire is connected to the pad of the chip and the floating tip end of the other end is connected to the outside to replace the conventional redistribution circuit layer and bump.

第9頁 1231024 五、發明說明（4) 【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。Page 9 1231024 V. Description of the invention (4) [Embodiment] Referring to the attached drawings, the present invention will enumerate the following embodiment descriptions.

依本發明之第一具體實施例，請參閱第1及2E圖，一 種利用打線重分配銲線之晶圓級晶片尺寸封裝結構丨〇 〇， 包含有一晶片110、複數個打線形成之重分配銲線140及至 少一介電性托護件1 20，該晶片係具有一主動面丨丨1及一背 面112，該主動面ill係形成有複數個銲墊113，於該主動 面111上利用一金屬層130形成之複數個連接墊131及複數 個中繼墊132，該些連接墊131結合於該些銲墊ι13，該些 中繼墊132係鄰近該介電性托護件1 20，每一重分配銲線 1 4 0係具有一結線端1 4 1、一銲節1 4 2及一懸空末梢端1 4 3， 該些結線端141係固設於該些銲墊1 13上之連接墊131，該 些銲節142係結合於鄰近該介電性托護件12〇之中繼墊 132，使該些懸空末梢端143設於該晶片11〇上，該些重分 配銲線140之懸空末梢端143係懸空翹離該晶片11〇之主動 面111並斜向延伸於該介電性托護件1 2 0 ’該介電性托護件 120設於該晶片110之主動面hi上並支撐托護該些重分配 銲線140之懸空末梢端143，利用該些懸空末梢端143與該 介電性托護件120作為晶圓級晶片尺寸封裝結構1〇〇與外部 接合之應力緩衝，利用該些重分配銲線140與該晶片11〇之 銲墊11 3連接並以該些重分配銲線1 4 0之懸空末梢端1 4 3作 為外部接合，達到利用重分配銲線1 4 0作為線路重分配之 晶圓級晶片尺寸封裝1〇〇。較佳地，該些重分配銲線140包 覆有一電鍍層150，如銲料，用以保護該些結線端141、該 1231024 五、發明說明（5) 些銲節142、該些連接塾131及該些中繼墊132，並增加該 些重分配銲線1 4 0之外從’以增進晶圓級晶片尺寸封裝结 構100之可靠度。 、 因此’該些重分配鮮線140係能置換習知晶圓級晶片 尺寸封裝結構之重分配電路層、應力緩衝層、凸塊及1(：載 板’使得該晶圓級晶片尺寸封裝結構丨〇〇具有低成本地以 既有打線封裝设備製作之功效’該些重分配銲線丨4 〇之結 線端1 41作為外部端點，其承受應力係先分散至該些銲節 142與中繼墊132之結合處，不會直接作用於銲墊113，即 使該些銲節142脫離該些中繼墊132或是該些中繼墊132由 a亥b曰片1 1 0主動面111脫洛’仍能保持電性導接，與習知具 有1¾塊之晶圓級晶片尺寸封裝結構比較下，因習^凸塊^ 受應力脫落將導致電性斷路之缺陷，本發明之晶圓級晶片 尺寸封裝結構更具有應力緩衝與低成本製作之功效。 曰曰 本發明之上述利用打線重分配銲線之晶圓級晶片尺寸 封裝結構1 0 0之製造方法係詳述如后，請參閱第2 a圖，提 供有一晶片110，多個晶片110係一體形成一晶圓，且該 片110之該主動面111上形成有該介電性托護件12〇，該介 電性托護件1 2 0係以網板印刷或照相顯影技術設於該晶片 110之主動面111，其厚度係介於30〜500 較佳為介於 6 0〜1 8 0 // m，在本實施例中，該介電性托護件丨2 〇係為印刷 形成之矽膠、橡膠或聚亞醯胺等介電膠條，可呈直線形、 门形或圓形，再請參閱第2B圖，於該晶片11〇之該主動面 111上形成該金屬層130，該金屬層13〇係以濺鍍方式形成According to the first specific embodiment of the present invention, please refer to FIGS. 1 and 2E. A wafer-level wafer size package structure using wire redistribution bonding wires includes a chip 110 and a redistribution solder formed by a plurality of wires. Line 140 and at least one dielectric supporter 120, the chip has an active surface 1 and a back surface 112, the active surface ill is formed with a plurality of bonding pads 113, and an active surface 111 is used. The plurality of connection pads 131 and the plurality of relay pads 132 formed by the metal layer 130 are combined with the solder pads 13, and the relay pads 132 are adjacent to the dielectric supporting member 1 20. A redistribution welding wire 1 4 0 has a knot wire end 1 4 1, a welding joint 1 4 2, and a floating tip end 1 4 3. The knot wire ends 141 are connection pads fixedly mounted on the welding pads 1 13. 131, the solder joints 142 are combined with the relay pad 132 adjacent to the dielectric support member 120, so that the suspended tip ends 143 are set on the wafer 110, and the redistribution bonding wires 140 are suspended. The distal end 143 is suspended and lifted off the active surface 111 of the wafer 11 and extends obliquely to the dielectric support member 1 2 0 'this The electric supporting piece 120 is provided on the active surface hi of the chip 110 and supports the suspended tip ends 143 of the redistribution bonding wires 140. The suspended tip ends 143 and the dielectric supporting piece 120 are used as Wafer-level wafer size package structure 100 and external bonding stress buffer, the redistribution bonding wires 140 are used to connect to the pads 11 of the wafer 110 and the floating tips of the redistribution bonding wires 140 are used. Terminal 1 4 3 is used as an external bond to reach wafer level wafer size package 100 using redistribution bonding wire 1 40 as line redistribution. Preferably, the redistribution bonding wires 140 are covered with a plating layer 150, such as solder, to protect the junction ends 141, the 1231024, and the invention description (5) the solder joints 142, the connection pads 131, and The relay pads 132 increase the reliability of the wafer-level wafer-size package structure 100 by increasing the number of the redistribution bonding wires beyond 140. Therefore, 'these redistribution fresh lines 140 can replace the conventional redistribution circuit layer, stress buffer layer, bump and 1 (: carrier board) of the conventional wafer-level wafer size packaging structure, which makes the wafer-level wafer size packaging structure 丨 〇 〇It has the effect of low-cost production with existing wire packaging equipment. 'The redistribution bonding wires 丨 4 〇The junction end 1 41 is used as the external end point, and its bearing stress is first distributed to the solder joints 142 and relays. The joints of the pads 132 will not directly act on the pads 113, even if the solder joints 142 are detached from the relay pads 132 or the relay pads 132 are released by the active surface 111 'Can still maintain electrical conduction, compared with the conventional wafer-level wafer size package structure with 1 ¾, due to the conventional ^ bump ^ stress shedding will cause the defect of electrical disconnection, the wafer-level wafer size of the present invention The packaging structure has the effect of stress buffering and low-cost production. The manufacturing method of the wafer-level wafer size packaging structure 100 using the above-mentioned redistribution bonding wire of the present invention is described in detail below, please refer to section 2a. Figure, provided with one wafer 110, multiple wafers 110 is integrally formed into a wafer, and the dielectric supporter 120 is formed on the active surface 111 of the sheet 110. The dielectric supporter 120 is designed by screen printing or photographic development technology. The thickness of the active surface 111 of the wafer 110 is between 30 and 500, preferably between 60 and 1 8 0 // m. In this embodiment, the dielectric supporter 2 is Dielectric strips such as silicone, rubber, or polyimide formed by printing can be linear, gate-shaped, or circular. Referring to FIG. 2B, the metal layer is formed on the active surface 111 of the wafer 11 130. The metal layer 13 is formed by sputtering.

1IH 第11頁 1231024 五、發明說明（6) 於該晶片1 1 0之該主動面111上，該金屬層1 30係覆蓋該晶 片110之該些銲墊113與該介電性托護件120，再如、第2C _ · 所示’利用打線機台（圖未繚出）將如金線、銅線或紹線等 之該些重分配銲線1 4 0形成有該些結線端1 41，並使該些結 線端141結合於該些辉墊113上之金屬層130，再將該些重 分配銲線140拉至該介電性托護件1 20旁之金屬層13〇上 方’並使該些重分配銲線1 4 0形成有該些鮮節1 4 2，使該些 銲節142與鄰近該介電性托護件120之金屬層130緊密結 合，再將該些重分配銲線1 40之尾端拉離該晶片1丨〇之該主· 動面111上，使該些重分配銲線丨4〇形成有該些懸空末梢端 143 ’再請參閱第2D圖，將該金屬層13〇未與該些重分配銲 線1 4 0之結線端1 41或銲節14 2結合之部分餘刻移除，使得 該金屬層130形成該些結線端hi下方之連接墊131與該些 鈐節142下方之中繼墊132，使得該些重分配銲線140穩固 結合於該晶片11 0之主動面丨丨1上，而達到線路重分配之功 效’並利用該些懸空末梢端丨4 3與該介電性托護件丨2 〇作為 晶圓級晶片尺寸封裝結構1〇〇與外部接合之應力緩衝，較 佳地如第2E圖所示，以電鍍方式形成該如銲料或其它金屬 材質之電鍍層150，以包覆該些重分配銲線14〇 ,利用該電 鍍層150保濩該些結線端、該些銲節ι42、該些連接墊 _ 131及该些中繼塾132，並增加該些重分配銲線14〇之外 徑，以增進晶圓級晶片尺寸封裝結構1〇〇之可靠度。 本發明之第二具體實施例，請參閱第3及4圖，一種利 用打線重分配銲線之晶圓級晶片尺寸封裝結構2〇〇，包含 1231024 五、發明說明（7) 有一晶片2 1 0、複數個打線形成之重分配銲線24〇及至少一 介電性托護件220，該晶片210係具有一主動面211及一背 面212，該主動面211係形成有複數個銲墊213，並於該主 動面211上形成有由一金屬層構成之複數個連接墊23ι、複 數個第一中繼墊232及複數個第二中繼墊233，該些連接墊 231係結合於該些銲墊213，該些第一中繼墊232係鄰近該 介電性托護件2 2 0，該些第二中繼墊2 3 3係位於該晶片21 0 之主動面211上之任意位置，每一重分配銲線2 4 〇係具有一 結線端241、一第一鲜郎242、一第二鲜節244及一懸空末 梢端243，該些結線端241係固設於該些連接墊231 ,該第 一銲節2 4 2係結合於鄰近該介電性托護件2 2 〇之該些第一中 繼墊232，使該些懸空末梢端243設於該晶片210上並懸空 翹離該晶片210之主動面211，於該些重分配銲線240形'成 該些第一銲節242前，另形成有與該些第二中繼墊233緊密 結合之該些第二銲節244，該些第二銲節244設於對應之該 些結線端241與該些第一銲節242之間，以提昇該些重分配 銲線2 4 0弧南之穩定性’較佳地，每一重分配鋅線2 4 〇之結 線端241、第一銲節242、第二銲節244可不位在同一直線 上，以增進該些重分配銲線2 4 0之配線靈活度，達到線路 重分配之功效，該介電性托護件22 0設於該晶片210之主動 面211上並支撐托護該些銲線重分配240之懸空末梢端 243，利用該些懸空末梢端243與該介電性托護件220作為 晶圓級晶片尺寸封裝結構2 0 0與外部接合之應力緩衝。 本發明之保護範圍當視後附之申請專利範圍所界定者1IH Page 11 1231024 V. Description of the invention (6) On the active surface 111 of the wafer 1 10, the metal layer 1 30 covers the pads 113 and the dielectric support 120 of the wafer 110 Then, as shown in 2C _ · 'Using a wire drawing machine (not shown in the figure), the redistribution bonding wires 1 4 0 such as gold wires, copper wires, or copper wires are formed with the junction ends 1 41 And the junction ends 141 are combined with the metal layers 130 on the glow pads 113, and then the redistribution bonding wires 140 are pulled over the metal layer 13 next to the dielectric supporter 120, and The redistribution bonding wires 1 4 0 are formed with the fresh knots 1 4 2, the soldering knots 142 are tightly combined with the metal layer 130 adjacent to the dielectric support 120, and then the redistribution bonding wires are formed. The trailing end of the line 1 40 is pulled away from the main and moving surface 111 of the wafer 1 so that the redistribution bonding wires 4o are formed with the suspended tip ends 143 '. Please refer to FIG. 2D again. The portion of the metal layer 130 that is not combined with the junction ends 1 41 or the solder joints 14 2 of the redistribution bonding wires 140 is removed in a moment, so that the metal layer 130 forms the connection pads 131 below the junction ends hi. The relay pads 132 below the joints 142 enable the redistribution bonding wires 140 to be firmly bonded to the active surface of the chip 110, and to achieve the effect of redistribution of the line, and to use the suspended tip ends. 4 3 and the dielectric support 丨 2 〇 as a wafer-level wafer-size package structure 100 and external bonding stress buffer, preferably as shown in Figure 2E, the plating such as solder or other The electroplated layer 150 made of metal is used to cover the redistribution bonding wires 140. The electroplated layer 150 is used to protect the junction ends, the solder joints 42, the connection pads 131, and the relays 132. And increase the outer diameter of these redistribution bonding wires 14 to improve the reliability of the wafer-level wafer size package structure 100. A second specific embodiment of the present invention, please refer to FIGS. 3 and 4, a wafer-level wafer size package structure 200 using wire redistribution bonding wires, including 1231024 V. Description of the invention (7) There is a wafer 2 1 0 2. A plurality of redistribution bonding wires 24 formed by a plurality of wires and at least one dielectric supporter 220. The chip 210 has an active surface 211 and a back surface 212. The active surface 211 is formed with a plurality of bonding pads 213. A plurality of connection pads 23m, a plurality of first relay pads 232, and a plurality of second relay pads 233 made of a metal layer are formed on the active surface 211. The connection pads 231 are combined with the welding pads. Pads 213, the first relay pads 232 are adjacent to the dielectric support member 2 2 0, and the second relay pads 2 3 3 are located at any position on the active surface 211 of the chip 21 0, each A redistribution bonding wire 240 has a knot end 241, a first fresh end 242, a second fresh knot 244, and a suspended tip end 243. The knot end 241 is fixed to the connection pads 231. The first solder joints 2 4 2 are coupled to the first relay pads 232 adjacent to the dielectric support member 2 2 0, so that the The suspended tip ends 243 are disposed on the wafer 210 and are suspended away from the active surface 211 of the wafer 210. Before the redistribution bonding wires 240 are formed into the first solder joints 242, the first solder joints 242 are formed with the first solder joints 242. The two relay pads 233 are closely combined with the second solder joints 244, and the second solder joints 244 are disposed between the corresponding junction ends 241 and the first solder joints 242 to enhance the redistribution welds. The stability of the line 2 40 arc south 'Preferably, the junction end 241, the first welding joint 242, and the second welding joint 244 of each redistribution zinc wire 2 4 0 may not be located on the same straight line to enhance the weight The distribution flexibility of the bonding wires 2 40 is achieved to achieve the effect of circuit redistribution. The dielectric support member 22 0 is provided on the active surface 211 of the chip 210 and supports the suspension of the bonding wire redistribution 240. The tip end 243 uses the suspended tip end 243 and the dielectric supporter 220 as a stress buffer for the wafer-level wafer size package structure 200 and external bonding. The scope of protection of the present invention shall be defined by the scope of the attached patent application

Μ 第13頁 1231024 五、發明說明（8) 為準，任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。 第14頁 1231024 圖式簡單說明 【圖式簡單說明] 第1 圖·依據本發明之第一具體實施例，一種利用打 、線重分配銲線之晶圓級晶片尺寸封裝結構之 立體示意圖； 第2A至2E圖：依據本發明之第一具體實施例，該利用打線 重分配銲線之晶圓級晶片尺寸封裝結構之製 造方法之晶片截面圖； 第3 圖·依據本發明之第二具體實施例，一種利用打 線重分配銲線之晶圓級晶片尺寸封裝結構之、 部分上視示意圖；及 馨 第4 圖：依據本發明之第二具體實施例，該利用打線 重分配銲線之晶圓級晶片尺寸封裝結構之截 面圖。 元件符號簡單說明： I 〇 〇晶圓級晶片尺寸封裝結構 II 0晶片 111主動面 112背面 113銲墊 1 2 0介電性托護件Μ Page 13 1231024 V. Description of the invention (8) shall prevail. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. Page 14 1231024 Brief Description of Drawings [Simplified Description of Drawings] Figure 1 · According to the first specific embodiment of the present invention, a three-dimensional schematic diagram of a wafer-level wafer size package structure using bonding and wire redistribution of bonding wires; Figures 2A to 2E: cross-sectional views of a wafer-level wafer-size package structure manufacturing method using wire redistribution bonding wires according to a first embodiment of the present invention; FIG. 3 is a second specific implementation according to the present invention For example, a schematic top view of a wafer-level wafer size package structure using wire redistribution bonding wires; and Figure 4: According to a second embodiment of the present invention, the wafer using wire redistribution bonding wires A cross-sectional view of a wafer-level package structure. Brief description of component symbols: I 〇 〇 Wafer-level wafer size package structure II 0 Wafer 111 Active surface 112 Back side 113 Solder pad 1 2 0 Dielectric support

130金屬層 131連接墊 132中繼墊 14 0重分配銲線 141結線端 14 2銲節 1 4 3懸空末梢端 150電鍍層 2〇〇晶圓級晶片尺寸封裝結構130 metal layer 131 connection pad 132 relay pad 14 0 redistribution wire 141 junction end 14 2 solder joint 1 4 3 floating tip 150 plating layer 200 wafer level wafer size package structure

第15頁 1231024 圖式簡單說明 21 0 晶片 211 主動面 21 2 背面 213 銲墊 220 介電性托護件 231 連接墊 232 第一中繼墊 233 第二中繼墊 240 重分配銲線 241 結線端 242 第一銲節 243 懸空末梢端 244第二銲節Page 15 1231024 Brief description of the diagram 21 0 Chip 211 Active surface 21 2 Back surface 213 Solder pad 220 Dielectric support 231 Connection pad 232 First relay pad 233 Second relay pad 240 Redistribution wire 241 Junction end 242 first weld joint 243 suspended tip 244 second weld joint

第16頁Page 16

Claims (1)

12310241231024 六、申請專利範圍 【申請專利範圍】 1、一種利用打線重分配銲線之晶圓級晶片尺寸封裝結 構，包含·· 一晶片，其係具有一主動面及一背面，該主動面係形 成有複數個銲墊； 複數個中繼墊，形成於該主動面上； 複數個打線形成之重分配銲線，設於該晶片之主動面 上，每一重分配銲線係具有一結線端、一第一銲節及一 懸空末梢端，該些結線端係固設於該些銲墊，該些第一 銲節係結合於該些中繼墊，該些懸空末梢端係懸空翹離+ 該主動面；及 至少一介電性托護件，凸設於該晶片之該主動面，用 以托護支撐該些重分配銲線之懸空末梢端。 2、 如申請專利範圍第1項所述之利用打線重分配銲線之 晶圓級晶片尺寸封裝結構，其中該些銲墊與該些重分配 銲線之結線端之間係形成有複數個連接墊。 3、 如申請專利範圍第1項所述之利用打線重分配銲線之 晶圓級晶片尺寸封裝結構，其另形成有一電鍍層，該電 鑛層包覆該些重分配鋅線。 4、 如申請專利範圍第1項所述之利用打線重分配銲線之 晶圓級晶片尺寸封裝結構，其中每一重分配銲線另包含 有一第二銲節，該些第二銲節設於對應之該些結線端與 該些第一銲節之間。 5、如申請專利範圍第4項所述之利用打線重分配銲線之6. Scope of patent application [Scope of patent application] 1. A wafer-level wafer size package structure using wire redistribution bonding wires, including a wafer, which has an active surface and a back surface, and the active surface is formed with A plurality of bonding pads; a plurality of relay pads formed on the active surface; a redistribution bonding wire formed by a plurality of wires is set on the active surface of the chip, each redistribution bonding wire has a knot end, a first A solder joint and a suspended tip end, the knot ends are fixed to the solder pads, the first solder joints are coupled to the relay pads, and the suspended tip ends are suspended and lifted off + the active surface ; And at least one dielectric supporting member protruding from the active surface of the chip to support the suspended distal ends of the redistribution bonding wires. 2. The wafer-level wafer size package structure using redistribution bonding wires as described in item 1 of the scope of the patent application, wherein a plurality of connections are formed between the pads and the junction ends of the redistribution bonding wires. pad. 3. The wafer-level wafer size package structure using redistribution bonding wires as described in item 1 of the scope of the patent application, which additionally has an electroplated layer, which covers the redistribution zinc wires. 4. The wafer-level wafer-size package structure using wire redistribution bonding wires as described in item 1 of the scope of the patent application, wherein each redistribution bonding wire further includes a second bonding joint, and the second bonding joints are provided at corresponding locations. Between the junction ends and the first solder joints. 5.As described in item 4 of the scope of patent application, the use of wire redistribution of welding wire 1231024 '申請專利範圍 曰:圓級晶片尺寸封裝結構，其 R線端、” 一銲節及該第4::銲線之該結 6、 如申請專利範圍第i項所述用呈/匕線排列。 晶圓級晶片尺寸封裝結構 】用打線重为配銲線之 介電性托護件。 、中5亥二第一銲節係鄰近該 7、 如申請專利範圍第1項所 晶圓級晶片尺寸封裝結構，^線之 係斜向延伸於該介電性托護件。/ 一 、’之"；二末梢端 8 如申凊專利範圍第1項所述之利用打線重分配銲線之 晶圓級晶片尺寸封裝結構，其中該介電性托護件係為印 刷形成之介電膠條。 9、如申請專利範圍第丨項所述之重分配銲線之 晶圓級晶片尺寸封裝結構，其中該托瘦件之厚度係介於 3〇〜50 0 //m之間。 n虹城 u、如申請專利範圍第1；^所述之 1鳟重分配銲線之 晶圓級晶片尺寸封裝結構，其〃 s牛之厚度係介 於60~180 之間。 利用打始+、 11、如申請專利範圍第〗項所述之 銲为配銲線之 晶圓級晶片尺寸封裝、结構，其卜^線為金線 '銅 線或鋁線。 Π] Μ Θ 1 2、一種利用打線重分配銲線之日日、日日片尺寸封裝結 構，包含： 众 咎品 -晶片，其係具有〆炙動面 ’該主動面係 形成有複數個銲塾；及1231024 'Scope of patent application: Round-level chip-size package structure, its R wire end, "a solder joint and the 4 :: knot of the wire 6, as described in item i of the patent scope Arrangement. Wafer-level wafer size package structure] Dielectric supporter with wire bonding as the bonding wire. The first solder joint is adjacent to the 7, such as the wafer level of the first patent application scope. Chip size package structure, the wire system extends obliquely to the dielectric support. / 1. "of" two ends 8 as described in item 1 of the scope of patent application to redistribute bonding wires Wafer-level wafer-size package structure, wherein the dielectric support is a printed dielectric tape. 9. Wafer-level wafer-size package with redistributed bonding wires as described in item 丨 of the patent application scope. Structure, wherein the thickness of the supporting piece is between 30 ～ 50 0 // m. N Hongcheng u, as described in the patent application scope No. 1; ^ 1 trout redistribution bonding wire wafer-level wafer The size of the package structure, the thickness of 〃 s cattle is between 60 ~ 180. Use start +, 11, such as application The welding described in item〗 of the scope of benefit is a wafer-level wafer-size package and structure with bonding wires. The wires are gold wires, copper wires, or aluminum wires. Π] Μ Θ 1 Day-to-day, day-to-day chip size package structure, including: blame products-wafers, which have an active surface; the active surface is formed with a plurality of solder joints; and 1231024 六、申請專利範圍 複數個重分配銲線，設於該晶片之主動面上，每一 重分配銲線係具有一結線端、至少一銲節及一懸空末 梢端，該些結線端係固設於該些銲墊上，該些銲節係 形成於該主動面上，該些懸空末梢端係懸空勉離該主 動面。 1 3、如申請專利範圍第1 2項所述之利用打線重分配銲線 之晶圓級晶片尺寸封裝結構’其另形成有一電鑛層， 該電鍍層包覆該些重分配銲線。 1 4、一種利用打線重分配銲線之晶圓級晶片尺寸封裝結 構之製造方法，包含： 提供一晶片，該晶片係具有一主動面及一背面，該 主動面包含有複數個銲墊； 形成一金屬層，覆蓋於該晶片之主動面上； 形成複數個重分配銲線於該晶片之主動面上，每一 重分配鮮線係具有一結線端、至少一銲節及一懸空末 梢端，該些結線端係結合於該些銲墊上之金屬層，而 該些銲節係固設於該主動面上之該金屬層，該些懸空 末梢端係懸空翹離該主動面；及 触刻該金屬層，使得該金屬層形成複數個在結線端 下之連接墊以及複數個在該些銲節下方之中繼墊。 1 5、如申請專利範圍第1 4項所述之利用打線重分配銲線 之晶圓級晶片尺寸封裝結構之製造方法’其另包含之 步驟有：於形成該金屬層之前’形成有至少一介電性 托護件於該晶片之主動面。1231024 6. The scope of the patent application is a plurality of redistribution bonding wires, which are set on the active surface of the chip. Each redistribution bonding wire has a knot end, at least one solder joint, and a suspended tip end, and these knot ends are fixed. On the welding pads, the welding joints are formed on the active surface, and the suspended tip ends are suspended away from the active surface. 1 3. The wafer-level wafer size package structure using wire redistribution bonding wires as described in item 12 of the scope of the patent application, further comprising an electric ore layer, and the plating layer covers the redistribution bonding wires. 14. A method for manufacturing a wafer-level wafer size package structure using wire redistribution bonding wires, comprising: providing a wafer having an active surface and a back surface, the active bread containing a plurality of bonding pads; forming a A metal layer covers the active surface of the wafer; a plurality of redistribution bonding wires are formed on the active surface of the wafer. Each redistribution fresh wire has a knot end, at least one solder joint, and a floating tip end. The knot ends are bonded to the metal layers on the pads, the solder joints are fixed to the metal layer on the active surface, and the suspended tip ends are suspended and lifted away from the active surface; and the metal layer is etched; , So that the metal layer forms a plurality of connection pads under the junction end and a plurality of relay pads under the solder joints. 15. The manufacturing method of a wafer-level wafer size package structure using wire redistribution bonding wires as described in item 14 of the scope of patent application, which further includes the steps of: forming at least one before forming the metal layer. A dielectric support is on the active side of the chip. 第19頁 1231024 六、申請專利範圍 1 6、如申請專利範圍第1 4項所述之利用打線重分配銲線 之晶圓級晶片尺寸封裝結構之製造方法，其另包含之 步驟有：於蝕刻該金屬層後，形成一電鍍層，該電鍍 層係包覆該些重分配鮮線。Page 19 1231024 VI. Application for patent scope 16 6. The manufacturing method of the wafer-level wafer size package structure using wire redistribution bonding wires as described in item 14 of the scope of patent application, which further includes the steps of: etching After the metal layer, a plating layer is formed, and the plating layer covers the redistribution fresh wires. 第20頁Page 20
TW092112599A 2003-05-08 2003-05-08 Wafer level chip scale package with redistribution wires by wire bonding and method for manufacturing the same TWI231024B (en)

Priority Applications (1)

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TW092112599A TWI231024B (en) 2003-05-08 2003-05-08 Wafer level chip scale package with redistribution wires by wire bonding and method for manufacturing the same

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