TWI229382B

TWI229382B - Method for preventing tungsten-plug corrosion

Info

Publication number: TWI229382B
Application number: TW91137267A
Authority: TW
Inventors: Chung-Lung Yiu; Szu-Tsun Ma; Kent-Kuohua Chang
Original assignee: Macronix Int Co Ltd
Priority date: 2002-12-25
Filing date: 2002-12-25
Publication date: 2005-03-11
Also published as: TW200411756A

Abstract

A method for preventing tungsten-plug corrosion in semiconductor device manufacturing process, wherein a tungsten-plug is formed on substrate and the tungsten-plug is connected to a conduction line formed on substrate electrically. The substrate is treated by a charge neutralizer for removing the charge, which is generated during conductive line etching process, from the conduction line surface. Then a wet clean process is performed.

Description

12293821229382

五、發明說明（1) 術領域本發明是有關於一種半導體製程，且特別是有關於種防止鎢插塞腐蝕的方法。先前技術，著半導體元件線寬之持續微型化，使得高速、多功能、南元件積集度、低功率消耗及低成本之極大型積體電路晶片得以大量生產製造。由於半導體元件之微型化及集積度的增加，内連線數目不斷地增多，使得晶片表面無法提供足夠的表面積來容納曰益增多的内連線。為了解決此V. Description of the Invention (1) Technical Field The present invention relates to a semiconductor process, and more particularly, to a method for preventing corrosion of a tungsten plug. In the prior art, the continuous miniaturization of the line width of semiconductor components has enabled mass production of very large integrated circuit chips with high speed, multi-function, south component accumulation, low power consumption, and low cost. Due to the miniaturization of semiconductor devices and the increase in the degree of integration, the number of interconnects has been increasing, making the wafer surface unable to provide sufficient surface area to accommodate the increased interconnects. To solve this

項問題，多重金屬内連線結構便被提出，而成為積體電路製造技術所必須採取的方式。 ^在多重金屬内連線製程中，當金屬鎢插塞完成後，接著疋下一層金屬導線的製作。當元件的尺寸（因為内連線造成）較大時，通常導線會將與之接觸的下層鎢插塞完全覆蓋。因此，鎢插塞腐蝕所產生的問題，僅在微影步進機發生錯誤對準，導致圖案化的導線層並未對準鎢插塞的上方時方才會浮現。然而，當元件的尺寸縮小時，通常導線層並不會完全對準其下方的鎢插塞。因此，鎢插塞與上層導線的腐蝕問題仍是製程所關切的問題。In this case, the multi-metal interconnect structure has been raised, and it has become a way that integrated circuit manufacturing technology must adopt. ^ In the multi-metal interconnection process, after the metal tungsten plug is completed, the next layer of metal wire is produced. When the size of the component (caused by the interconnect) is large, usually the wire will completely cover the underlying tungsten plug that it contacts. Therefore, the problems caused by the corrosion of tungsten plugs only emerge when the lithography stepper is misaligned and the patterned wire layer is not aligned above the tungsten plugs. However, when the size of the component is reduced, the wire layer usually does not align perfectly with the tungsten plug below it. Therefore, the corrosion of tungsten plugs and upper wires is still a concern of the manufacturing process.

第1 A圖至弟1 B圖為不習知》—種金屬内連線之製程剖面圖。圖式中包括基底100、内層介電材料1Q2、黏著層 1〇4、鎢插塞1〇6、金屬導線108與圖案化光阻層110，其中黏著層1 0 4之材料包括氮化鈦、鈦化鎢或其他的阻障材料。在第1 A圖中，内連線的導線1 〇 8並未完全覆蓋下層的Figures 1A to 1B are cross-sectional views of the manufacturing process of a kind of metal interconnects. The figure includes a substrate 100, an inner dielectric material 1Q2, an adhesive layer 104, a tungsten plug 106, a metal wire 108, and a patterned photoresist layer 110. The material of the adhesive layer 104 includes titanium nitride, Tungsten Titanium or other barrier materials. In Figure 1A, the inner wires 108 do not completely cover the lower layers.

1229382 五、發明說明（2) 鶴插塞1 〇 6。圖案化的導複1 Q β ^ A t 午、艮108可能因為錯誤對準而並去蚪準鎢插塞1 0 6或是為了節省曰y^ 未對的鎢插塞1 0 6 ◦ 1 ^ 清爹照弟1 B圖，利用童带蔣成η η 虱电漿蝕刻步驟灰化圖案化光阻層，接著再以清除溶液(stripping s〇luti〇n):阻 EKC科技公司之EKC_265TM)，在酸鹼值pH為ι 〇 ι 2下進行渴 =洗乎製程，以去除殘留的光阻與高分子殘留物。由於内連線之導線108並未對準鎢插塞1〇6，或是内連線之導線 1 〇 8故思不兀全覆盍鎢插塞1 〇 6，而使得鎢插塞1 〇 6的—部份1 6裸露出來。因此。以清除溶液進行濕式洗淨程序，°以去除基底1 00上的光阻與高分子殘餘物時，清除溶液會腐餘鐵插塞1 0 6所裸露出來的部分，而在鎢插塞丨〇 6之中形成一個孔洞Π 2。鎢腐蝕，是因為在圖案化以形成導線丨〇 8的餘刻過程中或是以氧電漿灰化光阻層丨丨0的過程中，電荷 (+ )累積在導線1 〇 8表面所造成。帶著電荷的導線1 〇 §與嫣插基106之間具有很大的電化學勢能（Eiectr〇chemiCai1229382 V. Description of the invention (2) Crane plug 106. The patterned guide compound 1 Q β ^ A t may be misaligned and removed the tungsten plug 1 0 6 or to save y ^ Wrong tungsten plug 1 0 6 ◦ 1 ^ According to the picture of Qingdi 1B, the patterned photoresist layer was ashed using the plasma strip etching process of Tong Cheng Jiang Cheng η η, and then the stripping solution (stripping solution: EKC_265TM of EKC Technology) The thirst = washing process is performed at a pH value of ι 2 to remove residual photoresist and polymer residues. Because the inner conductor 108 is not aligned with the tungsten plug 106, or the inner conductor 108 is not covered, the tungsten plug 1 106 is completely covered, so that the tungsten plug 1 06 Yes-Part 16 is exposed. therefore. The cleaning solution is used to perform a wet cleaning procedure. When the photoresist and polymer residues on the substrate 100 are removed, the cleaning solution will rot the exposed part of the iron plug 1 06, and the tungsten plug 丨A hole Π 2 is formed in 〇6. Tungsten corrosion is caused by the accumulation of electric charge (+) on the surface of the wire 108 during the remaining time of patterning to form the wire 丨〇8 or during the process of ashing the photoresist layer with oxygen plasma 丨 0. . The charged wire 1 〇 § has a large electrochemical potential energy with the Yan insert 106 (Eiectr〇chemiCai

Potential)(具有不同電化學勢能的兩金屬層會產生電轉合（Galvanic Couple))，因此，以pH值為1〇-12的清除溶液處理之後，所裸露的鎢金屬將氧化成離子態（例如是W04 )’而此離子態的鎢金屬在後續的濕式洗濯步驟中將被移除’而導致鎢插塞1 0 6中形成孔洞1 1 2。由於鎢插塞丨〇 6遭到腐姓’鎢插塞1 〇 6與圖案化的金屬導線1 〇 8的接觸面積減小’導線的阻值將會增加，而導致積體電路失效而無法使用〇Potential) (Two galvanic couples with different electrochemical potentials will generate Galvanic Couple), so after treatment with a cleaning solution with a pH value of 10-12, the exposed tungsten metal will be oxidized to an ionic state (for example It is W04) ', and this ionic tungsten metal will be removed in the subsequent wet washing step', resulting in the formation of holes 1 12 in the tungsten plug 106. Because the tungsten plug 丨〇6 is subject to the rot name 'Tungsten plug 106 and the patterned metal wire 1 08's contact area is reduced', the resistance of the wire will increase, and the integrated circuit will fail and cannot be used. 〇

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1229382 五、發明說明（3) 習知解決上述問題的方法，係將基底浸泡於一中性溶液（例如電解液）或去離子水中數小時，再以清除溶液進行濕式洗淨程序。將基底浸於中性的離子溶液中可以有效去除導線表面所累積的電荷，但是，此方法雖可保護鎢插塞防止其發生電化學腐姓，卻會使得鶴插塞表面上的内連線之導線腐蝕（亦即導線金屬會與中性離子溶液中的鹽或電解液反應）。而且，習知的方法中，以中性溶液（例如電解液）或去離子水處理基底的時間不但冗長，將基底進行浸泡步驟之後，還必須額外進行清洗-乾燥步驟以去除殘留在基底上的溶液（即鹽/電解液）。因此，提出一種可以快速且有效的防止鎢插塞腐蝕的方法是很重要的。發明内容有鑑於此，本發明提供一種在半導體製程中防止鎢插塞腐蝕的方法。此方法的步驟包括：提供已形成有一鎢插塞的基底，鎢插塞係與形成在基底上的導線耦接。首先，利用除電裝置處理基底，以移除附著在導線表面之電荷，接著再進行習知的濕式清除步骤。而除電裝置處理基底的時間為3分鐘至6分鐘。本發明係使用除電裝置（電離器）去除累積在導線上的電荷，以防止鎢插塞發生電化學腐蝕。一旦累積在導線上的電荷去除之後，在後續的濕式清除步驟中鎢插塞與導線之間的電化學勢能將大幅降低，鎢金屬不會發生氧化，因此可以保護鎢插塞，防止腐蝕的現象。而且，使用除電裝置處理基底也不會侵蝕鎢插塞上的内連線導線圖案，因1229382 V. Description of the invention (3) The conventional method to solve the above problems is to soak the substrate in a neutral solution (such as electrolytic solution) or deionized water for several hours, and then perform a wet cleaning procedure with the cleaning solution. Submerging the substrate in a neutral ionic solution can effectively remove the charge accumulated on the surface of the wire. However, although this method can protect the tungsten plug from electrochemical rot, it will make the interconnect on the surface of the crane plug. Corrosion of the wires (that is, the wire metal will react with the salt or electrolyte in the neutral ion solution). Moreover, in the conventional method, the time required to treat the substrate with a neutral solution (such as an electrolytic solution) or deionized water is not only tedious. After the substrate is subjected to the soaking step, an additional cleaning-drying step must be performed to remove the remaining residue on the substrate. Solution (ie salt / electrolyte). Therefore, it is important to propose a method that can quickly and effectively prevent corrosion of tungsten plugs. SUMMARY OF THE INVENTION In view of this, the present invention provides a method for preventing corrosion of a tungsten plug in a semiconductor process. The method includes the steps of: providing a substrate having a tungsten plug formed thereon, the tungsten plug being coupled to a wire formed on the substrate. First, the substrate is treated with a static elimination device to remove the charge attached to the surface of the wire, and then a conventional wet-cleaning step is performed. On the other hand, the time required for the static elimination device to process the substrate is 3 to 6 minutes. The invention uses a static elimination device (ionizer) to remove the electric charge accumulated on the wire to prevent electrochemical corrosion of the tungsten plug. Once the charge accumulated on the wire is removed, the electrochemical potential energy between the tungsten plug and the wire will be greatly reduced in the subsequent wet removal step, and the tungsten metal will not be oxidized, so the tungsten plug can be protected from corrosion. phenomenon. Moreover, the use of a static elimination device to treat the substrate will not erode the interconnecting wire patterns on the tungsten plugs, because

10066twf.pui 第8頁 1229382 五、發明說明（4) 此，亦可以防止導線發生腐姓的現象。本發明另外提供一種半導體元件之製造方法，此方法係提供已形成鎢插塞之基底，並依序於基底上形成一層金屬層與一層圖案化光阻層。然後，以圖案化光阻層為罩幕，蝕刻金屬層以形成導線，此導線並未完全覆蓋鎢插塞。接著，利用除電裝置處理基底，並移除圖案化光阻層。而除電裝置處理基底的時間為3分鐘至6分鐘。本發明在蝕刻金屬層之後，利用除電裝置處理基底，而可以除去在導線蝕刻製程中累積在導線與圖案化光阻層表面上的電荷，因此在後續的去除圖案化光阻層的步驟中，可以避免鎢插塞所裸露出來的部分不會氧化而被移除。而且，使用除電裝置處理基底也不會侵蝕鎢插塞上的内連線導線圖案，因此，亦可以防止導線發生腐蝕的現象。本發明又提供一種金屬内連線之製造方法，此方法係提供以形成有鎢插塞之基底。然後，依序於基底上形成一層金屬層與一層圖案化光阻層，並以圖案化光阻層為罩幕，蝕刻金屬層以形成導線，且導線並未完全覆蓋鎢插塞。接著，以氧電漿灰化圖案化光阻層後，利用除電裝置處理基底，以移除附著在導線上之電荷。之後，進行一濕式清潔步驟，移除殘留於該基底表面之光阻與高分子殘留物。而除電裝置處理基底的時間為3分鐘至6分鐘。本發明在形成導線、並利用氧電漿灰化圖案化光阻層之後，利用除電裝置處理基底，而可以除去在導線蝕刻製10066twf.pui Page 8 1229382 V. Description of the invention (4) This can also prevent the phenomenon of rotten names on the wires. The invention further provides a method for manufacturing a semiconductor device. This method provides a substrate on which a tungsten plug has been formed, and sequentially forms a metal layer and a patterned photoresist layer on the substrate. Then, using the patterned photoresist layer as a mask, the metal layer is etched to form a conductive line, which does not completely cover the tungsten plug. Next, the substrate is processed with a static elimination device, and the patterned photoresist layer is removed. The time taken by the static elimination device to process the substrate is 3 to 6 minutes. In the present invention, after the metal layer is etched, the static elimination device is used to process the substrate, so that the charges accumulated on the surfaces of the conductive lines and the patterned photoresist layer during the wire etching process can be removed. It can prevent the exposed part of the tungsten plug from being removed without oxidation. Moreover, the use of a static elimination device to treat the substrate does not erode the interconnecting wire pattern on the tungsten plug, and therefore, it is possible to prevent the corrosion of the wire. The present invention also provides a method for manufacturing a metal interconnect. This method is to provide a substrate having a tungsten plug. Then, a metal layer and a patterned photoresist layer are sequentially formed on the substrate, and the patterned photoresist layer is used as a mask. The metal layer is etched to form a wire, and the wire does not completely cover the tungsten plug. Next, the patterned photoresist layer is ashed with an oxygen plasma, and then the substrate is treated with a static elimination device to remove the charges attached to the wires. Then, a wet cleaning step is performed to remove photoresist and polymer residues remaining on the substrate surface. The time taken by the static elimination device to process the substrate is 3 to 6 minutes. In the present invention, after a conductive wire is formed and the patterned photoresist layer is ashed with an oxygen plasma, the substrate is treated with a static elimination device, so that the conductive etching process can be removed

10066twf.pta 第9頁 1229382 五、發明說明（5) 程與光阻層灰化製程中累積在導線表面上的電荷，因此在後續的濕式清除步驟中，可以避免鎢插塞所裸露出來的部分不會氧化而被移除。而且，使用除電裝置處理基底也不會侵蝕鎢插塞上的内連線導線圖案，因此，亦可以防止導線發生腐蝕的現象。而且，本發明係直接在蝕刻裝置的晶圓裝載/卸載區或獨立氮氣儲櫃中加裝除電裝置（電離器）。當金屬層蝕刻後，直接將晶圓傳送至設置有除電裝置之晶圓裝載/卸載區或獨立氮氣儲櫃中，並以除電裝置處理數分鐘，就可以達到除去在導線蝕刻製程中累積於導線與圖案化光阻層表面上的電荷，並防止鎢插塞在後續製程受到腐蝕。因此，本發明之製程可以簡化半導體金屬層之製造程序並且可以節省製造之成本。而且，因為無須更換製程設備或加裝昂貴的製程設備，所以可以減少製程的時間與製程設備的成本，並且也可以減少生產線被污染的可能。為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：實施方式第2A圖至第2D圖繪示本發明實施例之一種半導體元件的製造流程剖面圖。請參照第2A圖，提供一個基底2 0 0，在此基底2 0 0上已形成有一層内層介電層202，在此内層介電層202中形成有一層黏著層2 0 4與鎢插塞2 0 6。當然，在此基底2 0 0中還形10066twf.pta Page 9 1229382 V. Description of the invention (5) The charge accumulated on the surface of the wire during the ashing process of the photoresist layer, so that the tungsten plug can be prevented from being exposed during the subsequent wet removal step. Parts are not oxidized and are removed. In addition, the use of a static elimination device to treat the substrate does not erode the interconnect wiring pattern on the tungsten plug, and therefore, the corrosion of the wiring can be prevented. Moreover, the present invention is to add a static elimination device (ionizer) directly in the wafer loading / unloading area of the etching device or in a separate nitrogen storage cabinet. After the metal layer is etched, the wafer is directly transferred to the wafer loading / unloading area provided with a static elimination device or an independent nitrogen storage cabinet, and the static elimination device is processed for several minutes to remove the accumulation in the conductor during the wire etching process. And pattern the charges on the surface of the photoresist layer and prevent the tungsten plug from being corroded in subsequent processes. Therefore, the manufacturing process of the present invention can simplify the manufacturing process of the semiconductor metal layer and can save the manufacturing cost. Moreover, because there is no need to replace process equipment or add expensive process equipment, it can reduce the process time and cost of process equipment, and also reduce the possibility of contamination of the production line. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: Embodiments 2A to 2D A cross-sectional view of a manufacturing process of a semiconductor device according to an embodiment of the present invention is shown. Referring to FIG. 2A, a substrate 200 is provided. An inner dielectric layer 202 has been formed on the substrate 200, and an adhesive layer 204 and a tungsten plug have been formed in the inner dielectric layer 202. 2 0 6. Of course, in this base 2 0 0

100661 w t'. p t d 第10頁 1229382 五、發明說明（6) 成有其他元件或金屬導線，但是為了簡化起見，並未繪示於圖式中。接著，依序於基底200上形成一層金屬層208與層圖案化光阻層2 1 〇。金屬層2 〇 8之材質例如是鋁合金、銅金屬或銅合金。 , 接著’請參照第2B圖，將基底2 〇〇置於蝕刻裝置中， =以圖案化光阻層2 1 〇為罩幕，移除部分金屬層2 〇 8直到暴，出内層介電層2 〇 2表面，以形成導線2丨2。蝕刻裝置例如，乾餘刻装置。在此步驟中所形成的導線2丨2並未完全覆盖其下層的鹤插塞2 0 6，其例如是依照目前的0 · 1 8微米設计準則（或更小的設計準則）之製程技術所形成者。而且， f蚀刻$屬層2 0 8之後，圖案化光阻層21〇表面會帶有負電何、’而導線2 1 2則帶有正電荷，此種導線2丨2帶電的情況即為造成，後續製程中，鎢插塞腐蝕之原因。抓罟，f壯清參照第2C圖’將基底2 0 0從钮刻裝置傳送至二曰二=2置之氮氣儲櫃中。此氮氣儲櫃例如是钱刻裝置分：二t而載區。當然，氮氣儲櫃也可以從蝕刻裝置 :声理且古早獨設置。然後，在氮氣儲櫃中，利用除電裝烏插塞20 6、導線212、圖案化光阻層210的基屛2 1 〇表μ除在蝕刻製程中累積在導線2 1 2與圖案化光阻 ^，除I壯的電荷。除電裝置例如是電離器（Ionizer) 使用除電^署處理基底2〇0的時間例如是3〜6分鐘左右。減少累積^鎢^方法與習知的方法相比較，除了可有效的插塞206與導線=20 6或導f 212上的電荷，還可以避免鎢、泉2 1 2的表面發生腐蝕的問題。100661 w t '. P t d Page 10 1229382 V. Description of the invention (6) Other components or metal wires are formed, but for the sake of simplicity, they are not shown in the drawings. Next, a metal layer 208 and a patterned photoresist layer 21 are sequentially formed on the substrate 200. The material of the metal layer 208 is, for example, an aluminum alloy, a copper metal, or a copper alloy. Next, please refer to FIG. 2B, and place the substrate 200 in the etching device, and use the patterned photoresist layer 2 10 as a mask, and remove a part of the metal layer 2 08 until the inner dielectric layer is exposed. 2 02 surface to form a wire 2 2. Etching device is, for example, a dry-etching device. The conductive wire 2 丨 2 formed in this step does not completely cover the lower-layer crane plug 2 06, which is, for example, a process technology according to the current 0. 18 micron design guidelines (or smaller design guidelines). Formed by. In addition, after the etching of the metal layer 208, the surface of the patterned photoresist layer 21 will be negatively charged, and the lead 2 1 2 will have a positive charge. Such a situation that the lead 2 2 is charged is caused. , Causes of tungsten plug corrosion in subsequent processes. Grabbing, f Zhuangqing refer to Figure 2C 'to transfer the substrate 2 0 from the button-engraving device to a nitrogen storage cabinet of 2 = 2. This nitrogen storage cabinet is, for example, a money engraving device. Of course, the nitrogen storage cabinet can also be set from the etching device: acoustically and anciently. Then, in a nitrogen storage cabinet, the electric plug 206, the lead wire 212, and the base 2 of the patterned photoresist layer 210 are used to remove the accumulated lead 2 1 2 and the patterned photoresist during the etching process. ^, Except I strong charge. The static elimination device is, for example, an ionizer (Ionizer). The time for processing the substrate 2000 using the static elimination agent is, for example, about 3 to 6 minutes. Compared with the conventional method, the method of reducing the accumulation of tungsten can effectively avoid the problem of corrosion of the surface of tungsten and spring 2 1 2 in addition to the effective charge on the plug 206 and the wire = 20 6 or the conductor f 212.

]〇〇66rwf.ptd 第11頁 1229382] 〇〇66rwf.ptd Page 11 1229382

五、發明說明（7) 接著，請參照第2D圖，將基底2 0 0從氮氣室傳送至應室中，然後利用氧電漿灰化圖案化光阻層2 1 〇。然彳灸反再將基底2 0 0從反應室傳送至洗淨裝置中，對具有鶴^丄 2 〇 6與導線2 1 2的基底2 0 0進行濕式清除製程，以移除殘，於基底2 0 0表面之光阻或高分子殘留物，而可以得到^遠内連線。後續完成半導體之製程為熟知此技藝者所周|知1 在此不再贅述。 α 〇，依照上述實施例之内容，本發明在蝕刻金屬層之後利用除電裝置處理基底，而可以除去在蝕刻製 1 道厶 Τ 糸積在 >、、泉與圖案化光阻層表面上的電荷，因此在後續的光阻、、甚式清洗製程中，可以避免鎢插塞所裸露出來的部分不奋=、化而被移除，並且可以避免金屬導線被腐蝕。㈢氣而且，本發明係直接在蝕刻裝置的晶圓裝載/卸載區或獨立氮氣儲櫃中加裝除電裝置（電離器）。當金屬層钱°°刻 ^ ’直接將晶圓傳送至設置有除電裝置之晶圓裝栽/卸載區2獨立氮氣儲櫃中，並以除電裝置處理數分鐘，因此並不而要另外加裝其他昂貴的設備，就可以達到除去在導綠餘刻製程中累積在導線與圖案化光阻層表面上 ^ , v甩何，而」U即省成本。陝恭此外，在上述實施例中，其係以在蝕刻金屬層後進行二兒處理為實例做說明，當然本發明也可以在進行氧電 j化光阻層之步驟之後，進行光阻濕式清洗製程之月， 4kJ- «· ^ 野暴抵進行除電處理，同樣可以防止鎢插塞腐蝕。由於本發明只需在蝕刻装置的晶圓裝載/卸載區或獨V. Description of the invention (7) Next, referring to FIG. 2D, the substrate 200 is transferred from the nitrogen chamber to the reaction chamber, and then the patterned photoresist layer 21 is ashed with an oxygen plasma. However, the moxibustion will then transfer the substrate 200 from the reaction chamber to the washing device, and perform a wet cleaning process on the substrate 2 0 with crane ^ 2 06 and the lead 2 12 to remove the residue. The photoresist or polymer residue on the surface of the substrate 200 can be used to obtain the inner interconnection. Subsequent completion of the semiconductor manufacturing process is well known to those skilled in the art | Knowledge 1 I will not repeat them here. α 〇 According to the content of the above embodiments, the present invention uses a static elimination device to process the substrate after etching the metal layer, and can remove the one deposited on the surface of the >, spring, and patterned photoresist layer by etching. Therefore, in the subsequent photoresist, and even cleaning processes, the exposed part of the tungsten plug can be prevented from being removed without being exposed, and the metal wire can be prevented from being corroded. Krypton In addition, the present invention is to add a static elimination device (ionizer) directly in the wafer loading / unloading area of the etching device or in a separate nitrogen storage cabinet. When the metal layer is °° engraved ^ 'The wafer is directly transferred to the wafer loading / unloading area 2 equipped with a static elimination device in an independent nitrogen storage cabinet, and is processed by the static elimination device for several minutes. Other expensive equipment can be used to remove the accumulation on the surface of the wire and the patterned photoresist layer in the green-leaving process, and "U" means cost savings. Shan Gong In addition, in the above embodiment, it is described by taking an example of performing a second treatment after the metal layer is etched. Of course, the present invention may also perform a photo-resistance wet-type after performing the step of forming an oxygen-resistance photoresist layer. In the cleaning process month, 4kJ- «· ^ wild storm arrives for static elimination treatment, which can also prevent tungsten plug corrosion. Since the present invention only needs to be in the wafer loading / unloading area or

1229382 五、發明說明（8) 立氮氣儲櫃中加裝除電裝置（電離器），因此本發明不需昂貴的設備也不需花很長的時間，只需使用除電裝置處理基底數分鐘，即可移除金屬導線於蝕刻時所累積的電荷。因此金屬插塞在後續以清洗溶液處理時，不會有被腐蝕的狀況發生，造成電路斷路的問題。雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。1229382 V. Description of the invention (8) The static elimination device (ionizer) is installed in the vertical nitrogen storage cabinet. Therefore, the invention does not require expensive equipment and does not take a long time. It only needs to use the static elimination device to process the substrate for several minutes, that is, The charge accumulated on the metal wire during etching can be removed. Therefore, when the metal plug is subsequently treated with a cleaning solution, it will not be corroded, which will cause the circuit to open. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

10066twf.ptd 第13頁 1229382 圖式簡單說明第1 A圖至第1 B圖為習知一種金屬内連線之製程剖面圖，以及第2 A圖至第2 D圖為本發明較佳實施例之一種金屬内連線之製程剖面圖。圖式標示說明： 1 00、2 0 0 :基底 102、202 :内層介電層 1 0 4、2 0 4 :黏著層 1 0 6、2 0 6 :鎢插塞 1 0 8、2 1 2 :導線 1 1 0、2 1 0 :光阻層 1 1 2 :孔洞 2 0 8 :金屬層10066twf.ptd Page 13 1229382 Brief description of the drawings Figures 1A to 1B are cross-sectional views of a conventional process for manufacturing a metal interconnect, and Figures 2A to 2D are preferred embodiments of the present invention. Process cross-sectional view of a metal interconnect. Description of the graphical symbols: 1 00, 2 0 0: substrates 102, 202: inner dielectric layers 1 0 4, 2 0 4: adhesive layers 1 0 6, 2 0 6: tungsten plugs 1 0 8, 2 1 2: Lead 1 1 0, 2 1 0: Photoresist layer 1 1 2: Hole 2 0 8: Metal layer

10066twf.ptd 第14頁10066twf.ptd Page 14

Claims

1229382 六、申請專利範圍 1 . 一種防止鎢插塞腐蝕的方法，該方法包括：提供形成於一基底中的一鎢插塞，該鎢插塞係與該基底上的一導線耦接；利用一除電裝置處理該基底；以及進行一濕式清潔步驟。 2. 如申請專利範圍第1項所述之防止鎢插塞腐蝕的方法，其中該除電裝置係實質上去除累積於該導線表面上的電荷。 3. 如申請專利範圍第1項所述之防止鎢插塞腐蝕的方法，其中該除電裝置包括電離器。 4 ·如申請專利範圍第1項所述之防止鎢插塞腐蝕的方法，其中利用該除電裝置處理該基底之時間包括3〜6分鐘左右。 5.如申請專利範圍第1項所述之防止鎢插塞腐蝕的方法，其中該導線為鋁合金導線。 6 ·如申請專利範圍第1項所述之防止鎢插塞腐蝕的方法，其中該導線為銅導線或銅合金導線。 7. 如申請專利範圍第1項所述之防止鎢插塞腐蝕的方法，其中該除電裝置係設置於蝕刻裝置的晶圓裝載/卸載 ° 8. 如申請專利範圍第1項所述之防止鎢插塞腐蝕的方法，其中該除電裝置係設置於氮氣室中。 9. 一種半導體元件之製造方法，該方法包括：提供一基底，該基底中已形成有一鎢插塞；1229382 VI. Application Patent Scope 1. A method for preventing corrosion of tungsten plugs, the method comprising: providing a tungsten plug formed in a substrate, the tungsten plug being coupled to a wire on the substrate; using a The static elimination device processes the substrate; and performs a wet cleaning step. 2. The method for preventing corrosion of tungsten plugs as described in item 1 of the scope of the patent application, wherein the static elimination device substantially removes electric charges accumulated on the surface of the wire. 3. The method for preventing corrosion of tungsten plugs as described in item 1 of the scope of patent application, wherein the static elimination device includes an ionizer. 4 · The method for preventing corrosion of tungsten plugs as described in item 1 of the scope of patent application, wherein the time for processing the substrate by the static elimination device includes about 3 to 6 minutes. 5. The method for preventing corrosion of a tungsten plug according to item 1 of the scope of the patent application, wherein the wire is an aluminum alloy wire. 6. The method for preventing corrosion of tungsten plugs as described in item 1 of the scope of patent application, wherein the wire is a copper wire or a copper alloy wire. 7. The method for preventing corrosion of tungsten plugs as described in item 1 of the scope of patent application, wherein the static elimination device is a wafer loading / unloading device provided in an etching device. 8. The tungsten prevention as described in item 1 of the scope of patent application A method for plug corrosion, wherein the static elimination device is disposed in a nitrogen chamber. 9. A method for manufacturing a semiconductor device, the method comprising: providing a substrate, a tungsten plug has been formed in the substrate;

100661 w f.p t d 第15頁 1229382 六、申請專利範圍於該基底上形成一金屬層；於該金屬層上形成一圖案化光阻層；以該圖案化光阻層為罩幕，蝕刻該金屬層以形成一導線，該導線並未完全覆蓋該鎢插塞；利用一除電裝置處理該基底；以及移除該圖案化光阻層。 1 0.如申請專利範圍第9項所述之半導體元件之製造方法，其中該除電裝置係實質上去除累積於該導線與該圖案化光阻層表面上的電荷。 1 1.如申請專利範圍第9項所述之半導體元件之製造方法，其中該除電裝置包括電離器。 1 2.如申請專利範圍第9項所述之半導體元件之製造方法，其中利用該除電裝置處理該基底之時間包括3〜6分鐘左右。 1 3.如申請專利範圍第9項所述之半導體元件之製造方法，其中該導線為鋁合金導線。 1 4.如申請專利範圍第9項所述之半導體元件之製造方法，其中該導線為銅導線或銅合金導線。 1 5.如申請專利範圍第9項所述之半導體元件之製造方法，其中該除電裝置係設置於蝕刻裝置的晶圓裝載/卸載 · 區。 1 6.如申請專利範圍第9項所述之半導體元件之製造方法，其中該除電裝置係設置於氮氣儲櫃中。 1 7.如申請專利範圍第9項所述之半導體元件之製造方100661 w fp td Page 15 1229382 6. The scope of the application for a patent forms a metal layer on the substrate; forms a patterned photoresist layer on the metal layer; uses the patterned photoresist layer as a mask to etch the metal layer To form a wire, the wire does not completely cover the tungsten plug; use a static elimination device to process the substrate; and remove the patterned photoresist layer. 10. The method for manufacturing a semiconductor device according to item 9 of the scope of the patent application, wherein the static elimination device substantially removes charges accumulated on the surfaces of the wires and the patterned photoresist layer. 1 1. The method for manufacturing a semiconductor device according to item 9 of the scope of patent application, wherein the static elimination device includes an ionizer. 1 2. The method for manufacturing a semiconductor device according to item 9 of the scope of the patent application, wherein the time for processing the substrate by the static elimination device includes about 3 to 6 minutes. 1 3. The method for manufacturing a semiconductor device according to item 9 of the scope of the patent application, wherein the wire is an aluminum alloy wire. 1 4. The method for manufacturing a semiconductor device according to item 9 of the scope of the patent application, wherein the wire is a copper wire or a copper alloy wire. 1 5. The method for manufacturing a semiconductor device according to item 9 of the scope of the patent application, wherein the static elimination device is provided in a wafer loading / unloading area of the etching device. 1 6. The method for manufacturing a semiconductor device according to item 9 of the scope of the patent application, wherein the static elimination device is installed in a nitrogen storage cabinet. 1 7. The manufacturer of the semiconductor device as described in item 9 of the scope of patent application

10066twf.ptd 第16頁 1229382 六、申請專利範圍法，其中移除該圖案化光阻層之步驟包括：以氧電漿灰化該圖案化光阻層；以及進行一濕式清潔步驟移除殘留於該基底表面之光阻與高分子殘留物。 1 8. —種金屬内連線之製造方法，該方法包括：提供一基底，該基底中以形成有一鎢插塞；於該基底上形成一金屬層；於該金屬層上形成一圖案化光阻層；以該圖案化光阻層為罩幕，餘刻該金屬層以形成一導線，該導線並未完全覆蓋該鎢插塞；以氧電漿灰化該圖案化光阻層；利用一除電裝置處理該基底；以及進行一濕式清潔步驟。 1 9.如申請專利範圍第1 8項所述之金屬内連線之製造方法，其中該除電裝置係實質上去除累積於該導線與該圖案化光阻層表面上的電荷。 2 0.如申請專利範圍第1 8項所述之金屬内連線之製造方法，其中該除電裝置包括電離器。 2 1.如申請專利範圍第1 8項所述之金屬内連線之製造方法，其中利用該除電裝置處理該基底之時間包括3〜6分鐘左右。 2 2.如申請專利範圍第1 8項所述之金屬内連線之製造方法，其中該導線為鋁合金導線。 2 3.如申請專利範圍第1 8項所述之金屬内連線之製造10066twf.ptd Page 16 1229382 6. The patent application method, wherein the step of removing the patterned photoresist layer includes: ashing the patterned photoresist layer with an oxygen plasma; and performing a wet cleaning step to remove the residue Photoresist and polymer residue on the substrate surface. 18. A method of manufacturing a metal interconnect, the method comprising: providing a substrate in which a tungsten plug is formed; forming a metal layer on the substrate; forming a patterned light on the metal layer A resist layer; using the patterned photoresist layer as a mask, and engraving the metal layer to form a wire, the wire does not completely cover the tungsten plug; ashing the patterned photoresist layer with an oxygen plasma; using a The static elimination device processes the substrate; and performs a wet cleaning step. 19. The method for manufacturing a metal interconnect as described in item 18 of the scope of the patent application, wherein the static elimination device substantially removes charges accumulated on the surface of the wire and the patterned photoresist layer. 20. The method for manufacturing a metal interconnect as described in item 18 of the scope of patent application, wherein the static elimination device includes an ionizer. 2 1. The method for manufacturing a metal interconnect as described in item 18 of the scope of patent application, wherein the time for processing the substrate by the static elimination device includes about 3 to 6 minutes. 2 2. The method for manufacturing a metal interconnect as described in item 18 of the scope of patent application, wherein the wire is an aluminum alloy wire. 2 3. Manufacture of metal interconnects as described in item 18 of the scope of patent application

l(K)66twf. ptd 第17頁 1229382 ^、申請專利範圍方法，其中該導線為銅導線或銅合金導線。 2 4.如申請專利範圍第1 8項所述之金屬内連線之製造方法，其中該除電裝置係設置於蝕刻裝置的晶圓裝載/卸載區。 2 5.如申請專利範圍第1 8項所述之金屬内連線之製造方法，其中該除電裝置係設置於氮氣儲櫃中。l (K) 66twf. ptd Page 17 1229382 ^ Method of patent application, wherein the wire is a copper wire or a copper alloy wire. 2 4. The method for manufacturing a metal interconnect as described in item 18 of the scope of patent application, wherein the static elimination device is disposed in a wafer loading / unloading area of the etching device. 25. The method for manufacturing metal interconnects as described in item 18 of the scope of the patent application, wherein the static elimination device is installed in a nitrogen storage cabinet.

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