TWI226601B

TWI226601B - System and method of synthesizing a plurality of voices

Info

Publication number: TWI226601B
Application number: TW092101050A
Authority: TW
Inventors: Chao-Wen Chi
Original assignee: Winbond Electronics Corp
Priority date: 2003-01-17
Filing date: 2003-01-17
Publication date: 2005-01-11
Also published as: GB2397737B; GB2397737A; JP2004226968A; GB0328325D0; DE10356054A1; TW200414125A

Abstract

A system and method of synthesizing a plurality of voices are described. The system has a processing unit, a register, a latch unit, a timer and a digital/analog converter. The processing unit decodes voice data into decoded voices and the decoded data are then transmitted to the register. A plurality of different sampling signals of the timer are sent to the latch unit to trigger periodically the latch unit so that latch unit sequentially acquires the decoded voices stored in the register to avoid effectively jitters when the voice data are synthesized.

Description

1226601 修正 _案號 92101050 : ^ 日五、發明說明C〇 OIZICM^^ 發明所屬之技術領域法，特別是有關於 11 e r )現象的語音合本發明是有關於一種語音合成系統及方一種使用栓鎖裝置來避免音訊跳動（j丄成系統及方法。先前技術隨著資訊技術的快速發展及通訊網路音”應用更加普遍化，例如在電子心是；㈣經吊使用語音編碼來處理語音的發送，特別是使用語音合成技術來進行語音的壓縮處理，使操作者可以清楚地收聽 =聲音合成之後的效果，以達到娛樂及互相溝通的目的。第1圖為傳統a吾音合成系統的方塊圖。此語音合成系統主，=含處理器100、暫存器102、數位/類比轉換器1〇4及揚聱即1 0 6進行操作時，先將一時脈訊號1 〇 8輸入至處理器、1 〇 0及暫存1 〇 2中，使處理器丨〇〇依據時脈訊號j 〇 8的週期進=音訊資料的計算解碼步驟，以產生解碼音訊。接著暫存器102亦利用此時脈訊號ι〇8來觸發暫存器1〇2，以接收來自處理器1 〇〇的解碼音訊，並且將計算完成的解碼音訊依序傳送至數位/類比轉換器1 〇 4以及揚聲器1 〇 6中。第2圖繪示第丨圖的語音合成系統之輸出時序 :;:敗：轴為訊號的振幅’其"ι，”，.'Τη表二訊號的取樣週期（Sampllng Cycle，sp)，D1，D2，.·. =處理器分別在取樣週期（T1，T2，···，Tn)的範圍内’，使^ 早刃體程式（F i rmware )來執行副程式運算所獲得的解碼音1226601 Amendment_Case No. 92101050: ^ 5th, invention description COOIZICM ^^ Law of the technical field to which the invention belongs, especially about the speech synthesis of the phenomenon of 11 er) The present invention relates to a speech synthesis system and a method using a plug Locking the device to prevent audio beating (j 丄成 *** 和方法. The previous technology with the rapid development of information technology and communication network tones "applications are more common, such as in the electronic heart; ㈣ The use of voice coding to handle the transmission of voice In particular, the use of speech synthesis technology for speech compression processing, so that operators can clearly listen to the effect after sound synthesis, to achieve the purpose of entertainment and communication with each other. Figure 1 is a block diagram of the traditional a voice synthesis system The main system of this speech synthesis system is: including processor 100, register 102, digital / analog converter 104 and yang, ie 106, input clock signal 1 08 to the processor, In 〇0 and temporary storage 〇02, the processor 丨〇〇 is calculated according to the cycle of the clock signal j 〇 = audio data calculation and decoding steps to generate decoded audio. Then, the register 102 also uses the current pulse signal ι 08 to trigger the register 10 to receive the decoded audio from the processor 100, and sequentially transmit the decoded audio that has been calculated to the digital / analog conversion. Device 1 〇4 and speaker 1 〇6. Figure 2 shows the output timing of the speech synthesis system of Figure 丨 ::: Failure: the axis is the amplitude of the signal 'its " ι, ",.' Tη table two signals Sampling cycle (Sampllng Cycle, sp), D1, D2, ... = the processor is within the range of the sampling cycle (T1, T2, ..., Tn), respectively, so that ^ is earlier than the body program (F i rmware ) To perform decoding

案號 92101050 1226601Case No. 92101050 1226601

修正五、發明說明（2) ^ 訊。理論上，處理器必須依庠蔣成立^ 、週期（T1，T2)結束之前傳送到暫存器'曰，戒(f，02)在取樣轉換器1 04擷取到解碼音訊，而1 : 能使數位/類比推。而其餘的解碼音訊依此類實際上，處理器1 00在執行週期12内，除仃計算解碼之外，還必須接受來 +曰Λ貝枓進 "，使得處理器i。〇需要花費又額末外自的其中斷訊號η，以致於處理器二： = :;間來處理這些解碼立π Π9认4 #处為iU〇無法在取樣週期T2内完成 :二曰§fl D2的计舁，而必須延遲至下一個取樣週期τ3。亦抑=理益1 00無法將解碼音訊！)2在Τ2的範圍内傳送至暫存 :1 02，只能延遲至丁3以後才能送出。 r疋在夕工的°σ曰合成系統中，處理器1 〇 0在執行週期邳=内將會接受多個中斷訊號1 η，由於中斷訊號會佔用 !、周Γ100佔用的指令時間，以致於無法及時在特定的取斬Ϊ產生解碼音訊，使得數位/類比轉換器104無法從曰子為中碩取解音訊，導致整個音訊的合成波形產生扭曲立utortion)，造成音訊跳動（Jitter)的效應。換言之， ^訊跳動係指處理器100對音訊資料進行音訊合成時"，在合成音訊中會有訊號失真或是夾雜噪音的現象，大語音合成的品質。田- =^ ’如何利用語音合成系統來消除音訊跳動的現象，使浯t合成系統產生清晰的語音合成訊號，以提昇音訊合成的品質’已經成為目前業界亟需解決的課題。曰 -tS_121〇l〇5Q 1^^：Amendment 5. Description of invention (2) ^ News. Theoretically, the processor must be transferred to the register before the end of the cycle (T1, T2) ', said, or (f, 02) capture the decoded audio at the sampling converter 1 04, and 1: Make digital / analog inferences. And the rest of the decoded audio and so on. In fact, in the execution cycle 12 of the processor 100, in addition to calculating and decoding, it must also accept + Λ 贝枓进 " so that the processor i. 〇 It needs to spend its extra interrupt signal η, so that processor two: = :; to process these decodes π Π9 recognize 4 #iU # can not be completed within the sampling period T2: §fl The calculation of D2 must be delayed until the next sampling period τ3. Yi Yi = Li Yi 1 00 cannot decode audio! ) 2 is transmitted to the temporary storage within the range of T2: 1 02, which can only be sent after Ding 3. r 疋 In Xi Gong's ° σ synthesis system, the processor 1 00 will receive multiple interrupt signals 1 η within the execution cycle 邳 =, because the interrupt signal will take up the instruction time occupied by!, week Γ100, so that The inability to generate decoded audio in a specific fetch in a timely manner makes the digital / analog converter 104 unable to extract audio from the master and the master, resulting in a distortion of the entire audio waveform (tortertion), resulting in a jitter effect . In other words, ^ bounce means that when the processor 100 performs audio synthesis on the audio data ", there will be signal distortion or noise in the synthesized audio, and the quality of large speech synthesis. Tian-= ^ 'How to use the speech synthesis system to eliminate the phenomenon of audio bounce, so that the 浯 t synthesis system generates clear speech synthesis signals to improve the quality of audio synthesis' has become an urgent issue in the industry. -TS_121〇l〇5Q 1 ^^:

修正 1226601 五、發明說明（3) 發明内容本^潑^日月夕 __ 時器產生=2的為提供一種語音合成系統及方法，利用計取ΐί = :訊號控制一栓鎖裝置，使栓鎖裝置主動榻敷使用@ 胃解碼音讯，解決處理器中指令時間（MIPS)不本題，以提高處理器執行多工處理的效能。數個計時考1的為提供一種語音合成系統及方法，使用複非同步的敗::別產生複數個非同步的取樣訊號，藉由每個據取樣旬i t訊號來觸發複數個栓鎖裝置，使栓鎖裝置依的合成立^6、週期來傳送解碼音訊，以避免每個通道之間口乂曰訊產生音訊跳動的現象。本發明· η ^ 數個計時残I為提供一種語音合成系統及方法，利用複個不同取楛t 3產生複數個非同步取樣訊號，以形成複數使體办門頻率的音訊通道，減少儲存解碼音訊所需的記根據：i之：：省Ϊ音合t系統的整體製造成本。此語音合试，發明提出一種語音合成系統及方法。時器及數:、、、主要包含處理器、暫存器、栓鎖裝置、計用時脈訊_觸^^轉換器。其中處理11連接於記憶體，利料，並且ί二處理器，使處理器讀取記憶體内的音訊資訊。暫存器遠：用於對音訊資料進行解碼來形成解碼音使暫存器接收爽t ί理1 ’亦利用時脈訊號觸發暫存器，栓鎖裝置連ί =理器的解碼音訊。鎖裝置掏藉！計時；控制检鎖裝置，使栓號至栓鎖穿置二：的解碼曰訊’其中計時器傳送取樣訊凌置，裎鎖裝置依據取樣訊號的週期定期地觸發Amendment 122661 V. Description of the invention (3) Summary of content The present invention provides a speech synthesis system and method using a clock generator = 2 to obtain a signal to control a latching device to make the latch The lock device actively uses the @ gastric decoding audio to solve the problem of instruction time (MIPS) in the processor, so as to improve the performance of the processor in performing multiplexing. In order to provide a speech synthesis system and method using several timed tests 1, do not use multiple non-synchronous failures :: Do not generate multiple non-synchronous sampling signals, and trigger multiple latching devices with each it sampling signal. The latching device is combined to form a ^ 6 cycle to transmit the decoded audio to avoid the phenomenon of audio bounce between the mouth-to-mouth communication between each channel. The present invention provides a speech synthesizing system and method, which uses a plurality of different fetches t3 to generate a plurality of asynchronous sampling signals to form a plurality of audio channels with a gate frequency and reduces storage decoding. The required memorandum for audio information is: i :: Save the overall manufacturing cost of the audio and t system. In this joint speech test, the invention proposes a speech synthesis system and method. Timing and number: ,,,, mainly include processor, register, latching device, clock signal_touch ^^ converter. Among them, the processing 11 is connected to the memory, and the second processor enables the processor to read the audio information in the memory. The register is far: used to decode the audio data to form a decoded sound, so that the register receives it. The clock 1 is also used to trigger the register. The latching device is connected to the decoded audio of the processor. The lock device is borrowed! Timing; control the lock detection device, so that the latch to the lock pass through the second: the decoded message ‘of which the timer sends the sampling signal and the lock device is triggered periodically according to the cycle of the sampling signal

_SR_92101〇50_SR_92101〇50

1226601 五、發明說明（4) 音訊。換器將並且輪個計時取動音訊資傳送的據取樣可以完以*硬體響處理間，使算完成送解碼指令時之解碼器，使解碼音栓鎖裝置’使栓鎖裝置主動接你水2 數位/類比轉換器連結於拴鎖梦Λ地理器的解碼數位髮丨的解碼音訊轉㈣類、此數位/類比轉出至揚聲器。巧頬比型式的合成音訊，具體而言，本發明利用栓鎖裝置搭器，藉由計時器形成取樣气辨個或疋稷數作，使栓鎖裝置在預定的裝置的存料，並且傳送至揚聲器，用載暫存窃内的模式。由於本發明的每—筆二：傳統處理器控制訊號的週期進行傳送，因=:H…定期地依全解決音訊跳動的現象此本發明之語音合成系統分開獨立運作，且栓鎖裝置係器的操作。亦即栓鎖鎖裝置f:影得於梢壯苗m分^ 會佔用處理器的指令時 ,^、依據取樣週期定時地擷取及傳送計立；碼音訊’然後栓鎖裴置定時地分別預定時間傳。若是在處理器的執行週期範圍之内有足夠的 :來計算音m資料來形&修上不同的取樣週期日λ ’則本發明的栓鎖裝置可配置兩個以上的計時拴鎖裂置依據每個計時器的取樣週期來擷取及傳送訊。要的疋本無明特別適用於複數個不同取樣週期（非 :步的取樣訊唬）之多通道語音合成系統。因為傳統上以處理器控制解碼音訊的傳送，其中處理器必須準時在、1226601 V. Description of the invention (4) Audio. The converter will take time to take a sample of the data transmitted by the audio data. The hardware can be used to process the decoder, so that the decoder when the decoding instruction is sent is completed, so that the decoded sound lock device 'makes the lock device actively pick you up. The water 2 digital / analog converter is connected to the decoded audio data of the decoded digital transmitter of the lock geometries, and the digital / analog output is sent to the speaker. The synthesizing audio of the type is specifically, specifically, the present invention utilizes a latch device to form a sample gas or a clock by a timer, so that the latch device is stored in a predetermined device and transmitted. To the speaker, use the temporarily stored theft mode. Since each of the two of the present invention: the traditional processor controls the period of the signal to be transmitted, because =: H ... periodically resolves the phenomenon of audio bounce. The speech synthesis system of the present invention operates independently and locks the device. Operation. That is, the latching device f: the shadow is captured in the shoots and m points ^ When it will occupy the processor's instructions, ^, periodically capture and transmit the calculation according to the sampling cycle; code the audio and then lock the Pei periodically Scheduled transmission. If it is sufficient within the scope of the processor's execution cycle: to calculate the sound m data to shape & repair different sampling cycle days λ ', the latching device of the present invention can be configured with more than two timing latching splits Capture and send messages based on the sampling period of each timer. The essential transcript is particularly suitable for multi-channel speech synthesis systems with multiple different sampling periods (non-: sampling sampling steps). Because traditionally the processor controls the transmission of decoded audio, the processor must be on time,

1226601 MM 92101050 五、發明說明（5) 個執行週期之内完成音机。為了簡化語音作穩定度，語音合成斷訊號互相使用。亦傳送解碼音訊的過程用第二取樣週期傳送完成傳送解碼音訊的通道的中斷要求。本發明的栓鎖裝置配置，使栓鎖裝置主動擷取暫存器内的解碼每個語音通道内的解每個語音通道之間解時器的取樣週期來決成系統中音訊跳動的總之’本發明利用語栓鎖裝置，使栓鎖裝解決處理器中指令時行多工處理的效能。數個非同步的取樣訊週期來依序傳送解碼一年月曰修正一個通道合成系統糸统並不即當第一中，若是解螞音訊動作之後合複數個依據第_ 音訊，並碼音訊不碼音訊的疋傳送的現象。音合成系置主動掏間不敷使特別是使號，使栓音訊，以貫施方式針對傳統語音合成系統及方法或是複數個語音通道的解碼的運作’並且提高系統的操開放每個語音通道之間的中語音通道利用第一取樣週期第二語音通道要求處理器利，則必須等到第一語音通道 ’處理器才會處理第二語音計時器個別來觸發栓鎖裝取樣週期及第二取樣週期來且定期地傳送解碼音訊，使會有遲滯的現象。換言之，不會相互影響，而是依據計順序’大幅解決多通道語音統及方法，利用計時器控制取暫存器内的解碼音訊，以用的問題，以提高處理器執用複數個計時器分別產生複鎖裝置依據每個取樣訊號的避免音訊跳動的現象。的缺點’本發明提供一種語1226601 MM 92101050 Fifth, the description of the invention is completed within 5 execution cycles. In order to simplify the stability of the speech, the speech synthesis interrupt signals are used for each other. The process of transmitting decoded audio also uses the second sampling period to transmit the interrupt request for the channel that transmits the decoded audio. The configuration of the latching device of the present invention enables the latching device to actively capture the decoding in the register to decode the sampling period of the timer between each voice channel to determine the audio bounce in the system. The present invention utilizes a latching device to enable the latching to solve the performance of multiplexing when instructions are executed in the processor. Several non-synchronous sampling signal cycles are sequentially transmitted and decoded for one year and one month. Correcting a channel synthesizing system is not immediately the first. If it is to deactivate the audio action, a plurality of _ audios are combined and the audio is not. Phenomena of coded audio transmission. The synthesizing system is active enough, especially to make use of the signal, so that the audio can be applied in a consistent manner to the traditional speech synthesis system and method or the decoding operation of multiple speech channels' and improve the operation of the system. The middle voice channel between the channels uses the first sampling period and the second voice channel requires the processor to benefit. You must wait until the first voice channel 'processor will process the second voice timer individually to trigger the latching sampling period and the second The sampling period comes and the decoded audio is transmitted periodically, so that there will be a lag. In other words, they will not affect each other, but rather solve the multi-channel voice system and method according to the counting sequence. The timer control is used to fetch the decoded audio in the register to use the problem to improve the processor's execution of multiple timers. The phenomenon that the locking device avoids audio bounce according to each sampling signal is generated separately. Disadvantages ’the present invention provides a language

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1226601 五、發明說明（6) 音合成系統及方法，利用一。裝置主動擷取暫存器内的解碼A f空制栓鎖裝置，使栓鎖時間（MIPS)不敷使用的問題:二=、，以解決處理器中指令器分別形成複數個非同步的取樣—進一步使用複數個計時取樣訊號來觸發栓鎖裝置，使於:藉由每個非同步的週期來依序傳送不同通道的解^立^置依據每個取樣訊號間的合成音訊產生音訊跳動的現1訊，以避免每個通道之首先參閱第3圖，繪示依據本發明之％立圖。此語音合成系統藉由計管立:日a成系統的方塊以避免在合成音訊中產生音十；料形成合成音訊’用資料儲存於記憶體中。I本上，：：現象j其中先將音訊理器20 0、暫存器2〇2、检鎖裝置^、气成系統主要包含處 …，Tn)及數位/類比轉換 2 0 0連接於記憶體2 1 〇，利用時脈、，、中處理益使處理考？ηη读*々降μ 脈5虎212觸發處理器2 0 0，於2 0 0對音$ ^料^2 1 0内的音訊資料，並且處理器用接於處理器2 0 0，亦利用時脈訊號曰孔暫存益2 0 2連暫存器2 0 2接收來自處理器2〇〇的解碼音‘。子器2〇2’使 2Γ連μ暫存11 m’藉由計時器_制栓鎖，\使栓鎖裝置2°4擷取暫存器2。2内的解Ϊ Γ訊 ”中计日年為2 0 6傳达取樣訊號至栓鎖裝置2 〇 4 銷 ΓΓ2:4==: t…賴__置2二使栓鎖 f置：04主動接收來自處理器2〇〇的解碼音中，计時器206例如可為一個或是複數個1^貫1226601 V. Description of the invention (6) Sound synthesis system and method, using one. The device actively captures the decoded A f empty latching device in the register to make the locking time (MIPS) insufficient. Two =, to solve the problem that the commander in the processor forms a plurality of asynchronous samples. —Further use a plurality of timing sampling signals to trigger the latching device, so that: by each asynchronous cycle, the solutions of different channels are transmitted in sequence ^ standing ^ The audio beat is generated according to the synthesized audio between each sampling signal Now, to avoid each channel, please refer to FIG. 3 first, and show the% vertical map according to the present invention. This speech synthesizing system is based on the following: the system of the system is used to avoid the generation of tones in the synthesized audio; it is expected that the synthesized audio is used to store the data in the memory. I :: Phenomenon j: firstly connect the audio processor 20 0, the temporary storage device 202, the lock detection device ^, the main components of the pneumatic system ..., Tn) and the digital / analog conversion 2 0 0 to the memory Body 2 1 〇, using the clock, ,, and medium to deal with the benefits? ηη read * 々 lower μ Pulse 5 Tiger 212 triggers processor 2 0, and the pairing of audio data in 2 $ 0 ^ ^ 2 1 0, and the processor is connected to the processor 2 0 0, and also uses the clock The signal said that the hole temporary storage benefit 202 and the temporary storage device 202 received the decoded tone from the processor 200. The slave device 2〇2 'makes 2Γ and μ temporarily store 11 m'. By the timer _ latch lock, the lock device 2 ° 4 captures the buffer 2. The solution in 2 Γ is counted in the day. The year is 2 0 6 to transmit the sampling signal to the latching device 2 〇4 pin ΓΓ2: 4 ==: t ... Lay __ 2 Set the lock f 2: 04 Actively receive the decoded sound from the processor 200 The timer 206 may be one or more

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1226601 _案號 921Q1050 五、發明說明（7) (Timer)。數位/類比轉換器2〇8連結於栓鎖裝置2〇4，此數位/類比轉換器2 0 8將數位型式的解碼音訊轉換為類比型式的合成音訊’並且輸出至揚聲器214，以收聽合成音訊，$ 例如擴音器。本發明之較佳實施例中，拴鎖裝置2〇4設有複數層資料結構，用以儲存多層的解碼音訊。其中此複數層資料結構用先進先出（FIFO)的法則，使栓鎖裝置2〇4依據先進先出 (FIFO)將解碼音訊傳送至數位/類比轉換器2〇8。而處理器 2 0 0例如可為6 5 0 2系列的微控制器（肘1^〇 — (：〇][11：1^116]〇/° 單晶片或是一般用途的中央處理器2〇〇(central Processing Unit, CPU)。此外，處理器2 0 0中解碼音訊係於時域（Time D〇main^ 用的波形編碼法進行音訊資料的編碼，其中波形編碼法例如可為自適性差動脈衝碼調變（Adaptive Dif fei^ntiai1226601 _ Case No. 921Q1050 V. Description of the invention (7) (Timer). The digital / analog converter 208 is connected to the latching device 204. This digital / analog converter 208 converts digital type decoded audio into analog type synthetic audio 'and outputs it to the speaker 214 to listen to the synthesized audio , $ For example a loudspeaker. In a preferred embodiment of the present invention, the latching device 204 is provided with a plurality of layers of data structure for storing multiple layers of decoded audio. The data structure of the multiple layers uses the first-in-first-out (FIFO) principle, so that the latching device 204 transmits the decoded audio to the digital / analog converter 208 according to the first-in-first-out (FIFO). The processor 2000 can be, for example, a microcontroller of the 6502 series (Elbow 1 ^ 〇— (: 〇) [11: 1 ^ 116] 〇 / ° single chip or a general-purpose central processor 2〇〇 (central Processing Unit, CPU). In addition, the decoded audio in the processor 2000 is in the time domain (Time Domain). The waveform encoding method is used to encode the audio data. The waveform encoding method can be, for example, poorly adaptive. 1. dynamic pulse code modulation (Adaptive Dif fei ^ ntiai

Pulse Code Modulation，ADPCM)及差動脈衝碼調變 (Differential Pulse Code Modulation， DPCM)。其中自適性差動脈衝碼調變（ADPCM)使用數位化取樣編碼技術，將類比型式的語音訊號轉換成數位型式的訊號。而且自高性差動脈衝碼調變（ADPCM)係採取相鄰兩樣本之間的差別、作記錄，所以自適性差動脈衝碼調變（ADpcM)儲存相同聲音所需的空間比一般脈衝碼調變（pul Se Code 耳Pulse Code Modulation (ADPCM) and Differential Pulse Code Modulation (DPCM). Among them, adaptive differential pulse code modulation (ADPCM) uses digital sampling coding technology to convert an analog voice signal into a digital signal. In addition, ADPCM uses the difference between two adjacent samples for recording, so the adaptive differential pulse code modulation (ADpcM) requires more space to store the same sound than ordinary pulse code modulation. Change (pul Se Code ear

Modulation, PCM)編碼技術更小。具體而言，本發明利用栓鎖裝置2〇4搭配一個或是複數個計時器2 0 6，藉由計時器2 0 6形成取樣訊號來控制栓鎖裝®置Modulation (PCM) coding technology is even smaller. Specifically, the present invention utilizes the latching device 204 and one or more timers 206, and the timer 206 forms a sampling signal to control the latching device.

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1226601 ’、其繪示依據本發明第3圖中使用單-計時器，的垢^曰%成糸統的時序圖。橫軸為時間軸，縱軸為訊唬的振幅，SC表示處理器的工作訊號，的執行週期，Μ為處理器20 0在一個執行週中期=乍，被 :=::rL表示計時器m的取樣訊二 =號SL的取樣週期。進行操作時，計時器2〇6利用取 :裝：2 0 4，使栓鎖裝置議取暫存器2。2内的揚類比轉換成合成音訊，然後將合成音訊輸出1 “ U 此類推，检鎖裝置204利用計時器2〇6的觸 =依序= 本發明之拴鎖装置204使用計時器206的取樣訊號來接收暫1226601 ', which shows a time sequence diagram using a single-timer according to the third figure of the present invention. The horizontal axis is the time axis, the vertical axis is the amplitude of the bluff, SC is the working signal of the processor, the execution cycle of M, and M is the processor 20 0 in the middle of an execution cycle = 乍, is: = :: rL means timer m Sampling signal II = No. SL sampling period. During operation, the timer 206 uses the fetch: install: 2 0 4 to make the latch device fetch the temporary register 2. The analog analog in 2 is converted into synthesized audio, and then the synthesized audio is output 1 "U and so on, The lock detection device 204 uses the touch of the timer 206 = sequentially = The latching device 204 of the present invention uses the sampling signal of the timer 206 to receive temporary signals.

第13頁 1226601 案號 92101050 五、發明說明（9) Μ; 厂i Ε] ί ^ f器2 0 2的資料，由於計時器2 0 6與處理器2〇〇分開獨立運 :，所以栓鎖裝置2 0 4並不會影響處理器2 〇〇的操作，亦栓鎖裝置204不會佔用處理器.2 0 0的指令時間。具俨而二，若處理器2 0 0在栓鎖裝置204的取樣週期之前先^對^於忒取樣週期的解碼音訊，並將解碼音訊儲存於暫存器2 〇 2 内，則栓鎖裝置2 0 4便可依據取樣週期依序地擷取解碼音訊i以定時地操取及傳送該解碼音訊傳送至數位/類比^ 換器2 0 8中，解決在單一通道的語音合成系統中因為延遲傳送解碼音訊所造成的音訊跳動現象。參閱第5圖，其繪示依據本發明第3圖中使用複數個計時器 2 Of的語音合成系統之時序圖。基本上，本發明第5圖類似於第3圖，主要的差異在於第5圖使用複數個計時器2 〇 6來控制栓鎖裝置2 0 4，為了方便說明起見，將以兩個計時器 2 0 6說明之，分別定義為第一計時器τ丨及第二計時器丁2。橫軸為時間軸，縱軸為訊號的振幅，sc表示處理器的工作訊號，其中T C表示處理器2 0 0的執行週期，D11，D 2 1表示處理器2 0 0在一個執行週期内計算完成的兩個解碼音訊。sL i 表示第一計時器T1的取樣訊號，TL1表示取樣訊號SL1的取樣週期。而SL2表示第二計時器T2的取樣訊號，TL2表示取樣訊號SL2的取樣週期。進行操作時，第一計時器τ丨及第二計時器Τ2分別依據第一取樣週期TL1及第二取樣週期几2，使暫存器2 0 2内的解碼音訊〇11，〇21在預定的時間 ?11，？2卜利用第一計時器2 0 6及第二計時器2〇6觸發栓鎖裝置2 0 4，使栓鎖裝置2 0 4擷取解碼音訊Dll, D21。依此類Page 13 1226601 Case No. 92101050 V. Description of the invention (9) Μ; Factory i Ε] ^ f 器 2 0 2's data, because the timer 206 and the processor 2000 are operated separately and independently: so the latch is locked The device 204 does not affect the operation of the processor 2000, and the latching device 204 does not take up the instruction time of the processor 2.0. Specifically, if the processor 200 first decodes the decoded audio in the sampling period before the sampling period of the latching device 204, and stores the decoded audio in the register 200, the latching device 2 0 4 can sequentially capture the decoded audio i according to the sampling cycle to periodically manipulate and transmit the decoded audio to the digital / analog ^ converter 208, which solves the problem of delay in a single-channel speech synthesis system. Audio bounce caused by sending decoded audio. Refer to FIG. 5, which shows a timing diagram of a speech synthesis system using a plurality of timers 2 Of according to FIG. 3 of the present invention. Basically, FIG. 5 of the present invention is similar to FIG. 3, and the main difference is that FIG. 5 uses a plurality of timers 206 to control the latching device 204. For convenience of explanation, two timers will be used 2 0 6 indicates that they are respectively defined as the first timer τ 丨 and the second timer D2. The horizontal axis is the time axis, the vertical axis is the signal amplitude, sc is the working signal of the processor, where TC is the execution cycle of the processor 2 0, D11, D 2 1 is the calculation of the processor 2 0 0 in one execution cycle Two decoded audio completed. sL i represents the sampling signal of the first timer T1, and TL1 represents the sampling period of the sampling signal SL1. SL2 indicates the sampling signal of the second timer T2, and TL2 indicates the sampling period of the sampling signal SL2. During the operation, the first timer τ 丨 and the second timer T2 are based on the first sampling period TL1 and the second sampling period 2 respectively, so that the decoded audio in the register 2 02 is at the predetermined Time? 11 ,? 2. The first timer 206 and the second timer 206 are used to trigger the latching device 204, so that the latching device 204 captures the decoded audio Dll, D21. By this

第14頁 1226601 案號 92101050 五、發明說明（10) - 推 ’栓鎖裝置20 4利用第一計時器T1及第二計時器T2的觸發機制依序地接收 (1)11，1)21)，（012,013,022)，〜，（〇1111，0211)等解碼音訊，]^ 分別於預定時間（Pll，P21)，（P12, P13, P22)，···， (Plm，P2n)傳送之。由於第一計時器2 0 6及第二計時器2 0 6與處理器2 0 0分開獨立運作，且栓鎖裝置2 0 4係以硬體方式設置於語音合成系統中’因此栓鎖裝置2 0 4不會影響處理器2 〇〇的操作。亦、gPage 14 1226601 Case No. 92101050 V. Description of the invention (10)-Pushing the latch device 20 4 Using the trigger mechanism of the first timer T1 and the second timer T2 to sequentially receive (1) 11, 1) 21) , (012,013,022), ~, (〇1111, 0211) and other decoded audio,] ^ are transmitted at predetermined times (Pll, P21), (P12, P13, P22), ..., (Plm, P2n). Since the first timer 206 and the second timer 206 operate separately from the processor 200, and the latching device 2 0 4 is provided in the speech synthesis system in a hardware manner, therefore the latching device 2 0 4 will not affect the operation of the processor 2000. Also, g

检鎖裝置2 04不會佔用處理器2 0 0的指令時間，使得栓鎖壯P 置2〇、f可以依據第一取樣週期及第二取樣週期定時地擷衣及傳送計算完成的解碼音訊，然後栓鎖裝置2〇4定 =預定時間P11，P21傳送解碼音訊D11，D21。因此解刀 =:d21在處理器2 0 0的執行週期内TC，藉由第—樣，弟二取樣週期願取及傳送解碼音訊， | f，月產生訊號失真。个s使合成音訊換言之，若是在處理器2〇〇的執行週 :的指令時間來計算音訊資料來形成兩個以：不之内有足丄=之解碼音訊，則本發明的栓鎖裝置 5 、取樣士的計時器m，使栓鎖裂置2〇4依二置兩個以樣週期來擷取及傳送解碼音訊。母個计時為2 0 6的取本發明特別適用於複數個^同取樣週唬）之多通道語音合成系統。因為傳統】冋=的取樣訊 :f碼音訊的傳送，其中處理器200必須準二:理器2 0 0控期之内完成—個通道或是複數個語音通道行 1226601 一^-型】。千』日修正五、發明說明（11) 一" ^S- 為了簡化語音合成系統的運作，並且提高系統的操作穩定度，語音合成系統並不開放每個語音通道之間的中斷訊號互相使用。亦即當第一語音通道利用第一取樣週期傳送解碼音訊的過程中，若是第二語音通道要求處理器2 0 0利用第二取樣週期傳送解碼音訊，則必須等到第一語音通道完成傳达解碼音訊的動作之後，處理器2 〇〇才會處理第二注音通道的中衡要求。 °° 因此j在傳統的語音合成系統中，第二語音道中解碼音訊必然受制於第一語音通道’以致於輪出的合成音訊發生音訊跳動。相對地，本發明的栓鎖裝置204與處理器2 0 0完全分離並配合複數個計時器2 0 6個別來觸發栓鎖裝置204，使权鎖衣置2 0 4主動依據第一取樣週期及第二取樣週擷取暫存器20 2内的解碼音訊，並且定期地傳送解碼音 j ’使：個語音通道内的解碼音訊不會有遲滯的現象。換 a之，母個語音通道之間解碼音訊的不會相互影塑，依據計時器2 0 6的取樣週q f彳# # 疋 ίΓ6:二Γί本發明之語音合成系統的操作流程圖。首取利用時脈頻率觸發處理器，使處理器讀口己隐體内的音訊資料。拉菩力6 Π 9本抓、資料進行解瑪牛_ 、接者在^ 2步驟中處理器對音訊 ;，以形成解碼音訊。然後在步驟_ 利用時脈頻率觸發暫存器，使處理哭直接載入至暫存器中。时直接將解碼音訊接著在6 0 6步驟中利用複數個計時器〜成的稷數個取樣訊 MM 92101050The lock detection device 204 will not take up the instruction time of the processor 2000, so that the latches P20 and f can periodically retrieve clothes and transmit the calculated decoded audio according to the first sampling period and the second sampling period. Then the locking device 204 is set to the predetermined time P11, P21 to transmit the decoded audio D11, D21. Therefore, during the execution cycle of the processor 2 0, TC == d21, by the first sample, the second sample cycle is willing to fetch and transmit the decoded audio, | f, the month produces signal distortion. In other words, the synthesized audio means that if the audio data is calculated at the instruction time of the processor 2000: to form two audio signals: if there is not enough decoded audio within =, the latch device 5 of the present invention 2. The timer m of the sampler enables the latch to be set to 204 to capture and transmit decoded audio in two sample periods. The present invention is particularly applicable to a multi-channel speech synthesis system with multiple sampling times. Because of the traditional] 冋 = sampling signal: f-code audio transmission, the processor 200 must be completed within two control period: processor 2 0 0-a channel or a plurality of voice channel lines 1226601 a ^ -type]. Thousands of Days Amendment V. Description of the Invention (11) ^ S- In order to simplify the operation of the speech synthesis system and improve the stability of the system's operation, the speech synthesis system does not open the interrupt signals between each speech channel to use each other . That is, when the first voice channel uses the first sampling period to transmit decoded audio, if the second voice channel requires the processor 200 to use the second sampling period to transmit the decoded audio, it must wait until the first voice channel has completed transmitting and decoding. After the audio action, the processor 2000 will process the balance request of the second Zhuyin channel. °° Therefore, in the traditional speech synthesis system, the decoded audio in the second speech channel is bound to be restricted by the first speech channel ', so that the synthesized audio in turn has audio bounce. In contrast, the latching device 204 of the present invention is completely separated from the processor 200, and cooperates with a plurality of timers 20 to trigger the latching device 204 individually, so that the weight locker 204 is actively set according to the first sampling period and The second sampling cycle captures the decoded audio in the register 202, and periodically transmits the decoded audio j 'so that the decoded audio in each voice channel will not lag. In other words, the decoded audio between the parent speech channels will not affect each other. According to the sampling cycle of the timer 2 06 q f 彳 # # 疋 Γ6: 二 Γί The operation flowchart of the speech synthesis system of the present invention. The first fetch uses the clock frequency to trigger the processor, so that the processor reads the audio data in its own body. Lapu Li 6 Π 9 this capture, the data is analyzed, and then the processor processes the audio in ^ 2 steps to form decoded audio. Then in step _ use the clock frequency to trigger the register, so that the processing cry is directly loaded into the register. Will directly decode the audio and then use a plurality of timers to generate a number of sampled signals in step 6 6 MM 92101050

修正置依據每裝置主動對應於每準時地傳音訊跳動解碼音訊數位/類糸統，使器中多工生複來觸依序明利由不，以之栓检鎖指令處理數個發栓傳送用複同頻節省 1226601 五、發明說明（12) 號來觸發栓鎖裝置，期定時地觸發栓鎖裝的解碼音訊，其中每訊，栓鎖裝置藉由每成音訊，以避免合成 6 0 8步驟中，數位/類的解碼訊號。最後在型式的解碼音訊輸出綜上所述，本發明利存器，利用計時器控存器内的解碼音訊，使用的問題，以提高進一步使用複數個計说’藉由每個非同步裝置依據每個取樣訊免音訊跳動的現象。產生複數個非同步取減少儲存解碼音訊的製造成本。本發明已揭示較佳實實施，非用以限定本領悟本發明之精神後可作些許更動潤飾及視後附之申請專利範其中栓鎖裝置，使栓鎖一取樣訊號一取樣訊號音訊中產生比轉換器將 6 1 0步驟中至揚聲器。用$吾音合成制栓鎖裝置以解決處理處理器執行時器分別產的取樣訊號號的週期來此外’本發樣机號，藉記憶體空間施例如上，僅用於幫發明之精神，而熟悉 ’在不脫離本發明之等同之變化替換，其園及其等同領域而定一取樣訊號的週擷取來自處理器 ~通道的合成音送每一通道的合的現象。隨後在轉換為類比型式比轉換器將類比鎖裝置來控制暫裝置主動擷取暫時間（MIPS)不敷的效能。本發明非同步的取樣訊鎖裝置，使栓鎖解碼音訊，以避數個計時器分別率的語音通道， s吾音合成系統的助暸解本發明之此領域技藝者於精神範圍内，當專利保護範圍當The correction setting is based on each device actively corresponding to each punctual and timely audio beating and decoding of the audio digital / type system, so that the multiplexer in the device can come back in order to determine whether it is beneficial or not, and use the lock check command to process several hairpin transmissions. Multiple co-frequency savings 1226601 V. Inventory No. (12) to trigger the latching device, and periodically trigger the decoded audio of the latching device, in which each latching device uses every audio to avoid synthesizing 6 0 8 steps Medium, digital / class decoding signal. Finally, in terms of the type of decoded audio output, in summary, the memory of the present invention uses the decoded audio in the timer control register to improve the use of a plurality of countermeasures. Each sampled signal is free of audio bounce. Generating multiple asynchronous fetches reduces the manufacturing cost of storing decoded audio. The present invention has been disclosed for better implementation, and is not intended to limit the understanding of the spirit of the present invention. Some modifications can be made, and the attached patent application includes the locking device, which locks a sampling signal and a sampling signal audio. Than the converter will step 6 10 to the speaker. The use of $ Goyin synthesizing the latching device to solve the cycle of the sampling signal produced by the processing processor execution timer, in addition to the "prototype number of this hair, borrowed from the memory space for example, is only used to help the spirit of the invention, And it is familiar with the phenomenon of changing the equivalent of the present invention, its circle and its equivalent field, and the sampling of a sampling signal from the processor to the channel to synthesize the sound of each channel. Then in the conversion to the analog type, the analog converter locks the device to control the performance of the device ’s active acquisition time (MIPS). The non-synchronous sampling signal lock device of the present invention enables the latch to decode audio to avoid speech channels with a number of timers. The syllabary synthesizing system helps those skilled in this field of the present invention to understand the spirit of When the scope of protection

第17頁 1226601 案號 92101050 /y f正替換頁1 Θ ; M C月丨 ! 曰修正圖式簡單說明圖式簡單說明為使本發明之上述和其他目的、特徵及優點更明顯易懂，配合後附圖式，作詳細說明如下：第1圖繪示傳統語音合成系統的方塊圖；第2圖繪示第1圖的語音合成系統之輸出時序圖；第3圖繪示依據本發明的語音合成系統之方塊圖；第4圖繪示依據本發明第3圖中使用單一計時器之語音合成系統之輸出時序圖；Page 17 1226601 Case No. 92101050 / yf is replacing page 1 Θ; MC Month !! Modified schema is briefly explained. The schema is simply to make the above and other objects, features, and advantages of the present invention more obvious and easy to understand. The diagram is described in detail as follows: FIG. 1 shows a block diagram of a conventional speech synthesis system; FIG. 2 shows an output timing diagram of the speech synthesis system of FIG. 1; and FIG. 3 shows a speech synthesis system according to the present invention. Block diagram; Figure 4 shows the output timing diagram of the speech synthesis system using a single timer according to Figure 3 of the present invention;

第5圖繪示依據本發明第3圖中使用複數個計時器之語音合成系統之輸出時序圖；以及第6圖繪示依據本發明之語音合成系統的操作流程圖。圖式標記說明 1 0 0、2 0 0 : 處理器 1 0 2、2 0 2 : 暫存器 1 0 4、2 0 8 : 數位/類比轉換器 1 0 6、2 1 4 : 揚聲器 1 0 8、2 1 2 : 時脈訊號 2 0 4 ：栓鎖裝置 2 0 6 ：計時器 210 ：記憶體Fig. 5 shows an output timing chart of the speech synthesis system using a plurality of timers according to Fig. 3 of the present invention; and Fig. 6 shows an operation flowchart of the speech synthesis system according to the present invention. Description of the graphical symbols 1 0 0, 2 0 0: Processor 1 0 2, 2 0 2: Register 1 0 4, 2 0 8: Digital / analog converter 1 0 6, 2 1 4: Speaker 1 0 8 , 2 1 2: Clock signal 2 0 4: Latching device 2 0 6: Timer 210: Memory

Claims

1226601 ' -~~~- — 六、申請專利範圍 1 · 一種語音合並且避免在該成系統至少包一記憶一處理使該處對該音一暫存器以一栓鎖置，使計時器樣訊號接收來生音訊體，用器連接理器讀訊資料器連接使該暫裝置連該拴鎖傳送取的週期自該處跳動的成系統，合成音訊含·· 以儲存該於該記憶取該記憶作解碼，於該處理存器接收結於該暫裝置擷取樣訊號至定時地觸理器的該現象；以 1210105(11226601 '-~~~-— VI. Application for patent scope 1 · A voice synthesizer and avoiding at least one memory and one processing in the finished system so that the sound register is locked with a latch there, making the timer-like The signal receives the incoming audio body, and the device is connected to the reader to read the data. The device is connected to the latch to transmit the cycle from the system. The synthesized audio contains ... to store the data in the memory and retrieve the data. The memory is decoded, and the processing register receives the phenomenon that the sampling signal captured by the temporary device is sent to the timing controller; with 1210105 (1

藉由計算音中產生音訊訊資料形成合成音訊’ 跳動的現象，該語音合音訊資料；體，利用時體内的該音以形成解碼為’利用該來自该處理存器，藉由該暫存器内該栓鎖裝置發該检鎖裝解碼音訊，及脈訊號觸發該處理器，訊資料，並且該處理器音訊； 0寸脈訊號觸發該暫存器的該解碼音訊； —計時器控制該栓鎖裝的該解碼音訊，其中該 ’該栓鎖裝置依據該取置，使該栓鎖裝置主動以避免該合成音訊中彥數位/類比轉換器連結於$权鎖裝置，該數位/類比轉換器將數位型式的該解碼音訊轉換為類比型式的該合成音訊，並且將該合成音訊輸出至揚聲器，以收聽該合成音訊。 2·如申請專利範圍第1項所述之語音合成系統，其中該检鎖裝置設有複數層資料結構’用以接收該解碼音訊。 3 ·如申請專利範園第2項所述之語音合成系統，其中該暫By calculating the generated audio data in the sound, the phenomenon of "combined audio" is formed, and the speech is combined with the audio data; when the sound in the body is used to form the decoding, it is "utilized from the processing memory, through the temporary storage" The latching device in the device sends the lock detection decoding audio, and the pulse signal triggers the processor, the data, and the processor audio; the 0-inch pulse signal triggers the decoding audio of the register; the timer controls the The decoded audio of the latch is installed, wherein the latch device makes the latch device take the initiative to avoid the synthetic audio Nakahiko digital / analog converter connected to the $ right lock device, the digital / analog conversion The converter converts the decoded audio of the digital type into the synthesized audio of the analog type, and outputs the synthesized audio to a speaker to listen to the synthesized audio. 2. The speech synthesis system according to item 1 of the scope of patent application, wherein the lock detection device is provided with a plurality of layers of data structure 'for receiving the decoded audio. 3. The speech synthesis system described in item 2 of the patent application park, wherein the temporary

1226601 if _金號H〇l(j政六、申請專利範圍月曰修正存器至少包含隨機存取記憶體（Rand〇in Access Memory RAM)。， 4 ·如申請專利範圍第2項所述之語音合成系統，其中該些層資料結構至少包含使用先進先出（FIF〇)的法則，以將該解碼音訊傳送至該栓鎖裝置中。 5 ·如申請專利範圍第1項所述之語音合成系統，其中該處理器至少包含微控制器（M i c r 0 — c 0 n t r 〇 1 1 e r )或是中央處理器（Central Processing Unit， CPU)。 6·^申請專利範圍第1項所述之語音合成系統，其中該處理器包含使用波形編碼（W a v e f 〇 r m c 〇 d i n g )法則對該音訊餐料編碼。 I.如申請專利範圍第6項所述之語音合成系統，其中該波形編碼（WaVef0rm Coding)法則至少包含碼薄激發線^預、、扁碼（C 〇 d e E X c i t e d L i n e a r P r e d i c t i ο η，C E L P )法則。 l如申請專利範圍第6項所述之語音合成系統，其中該波、、烏碼法則至少包含自適性差動脈衝碼調變（A 0 p [ μ y各則。 ) 9.如申請專利範圍第6項所述之語音合成系統，其中該波1226601 if _ 金号 H〇l (J Zhengli, the scope of the patent application, the correction memory contains at least random access memory (RandOin Access Memory RAM)., 4 as described in the second scope of the patent application Speech synthesis system, where the layers of data structure include at least the first-in-first-out (FIF) rule to transmit the decoded audio to the latching device. 5 · Speech synthesis as described in item 1 of the scope of patent application System, where the processor includes at least a microcontroller (Micr 0 — c 0 ntr 〇1 1 er) or a central processing unit (CPU). 6 · ^ The voice described in item 1 of the scope of patent application A synthesis system, wherein the processor includes encoding the audio frequency meal using a waveform encoding (Wavef omc ding) rule. I. The speech synthesis system as described in item 6 of the patent application scope, wherein the waveform encoding (WaVef0rm Coding) ) The rule includes at least the codebook excitation line ^ pre, and flat code (C ode EX cited Linear Redicti ο η, CELP) rule. L As described in the sixth item of the scope of patent application The speech synthesis system, wherein the wave and black code rules at least include adaptive differential pulse code modulation (A 0 p [μ y each.) 9. The speech synthesis system described in item 6 of the scope of patent application, Where the wave

第20頁 ,二-----------------, „ _ 級…92眷 1226601 修正月曰六、申請專利範圍形編石馬法則至少媽調變（dpcm)法則 1°二種語音合成系統’藉由計算記憶體内的音吒資枓以形成複數個通道之合成音内的曰？枓’ ”音訊跳動的現象，㈣音合成系成音訊中 dt ί接於該記憶體，利用-時脈訊號觸發該處理 =使该處理器讀取該記憶體内的該音又：處理 :器對該音訊資料作解石馬，以形成解碼音訊心並且該處 ;ί:ί;Γ=;,利用該時脈訊號觸發該暫存一使孩暫存裔接收來自該處理器的該解碼立却· 全鎖裝置連結於該暫存器，利用複數個昉二二丄、— 固取樣訊號來控制該栓鎖裝置，該栓鎖裝置:攄^」複數 :樣訊號的週期定時地觸發該栓鎖裝i，使‘於：：些 =擷取來自該處理器的該解碼音訊，•中每二二2主應於每二該些通道的該合成音訊，該栓鎖裝置夢：二、μ些取樣訊號定期地傳送每一該些通道的該人二1母以避免該合成音訊中產生音訊跳動的現象· ^ ^ Λ 比轉換 ^取祖^八的邊解碼音訊轉換為類比型式的誃人立吼，用以輸出至揚聲器，以收聽該合成音訊。口曰 11 ·如申請專利範圍第1 0項所述之語音合成系統，農φ 拴鎖裝置設有複數層資料結構，用以接收該解碼音气。ΜPage 20, two -----------------, _ _ grade ... 92 dependent 1226601 Amendment of the sixth month, the patent application scope of the rule of the shape of the stone horse at least the mother modulation (dpcm) Rule 1 ° Two kinds of speech synthesis systems 'by calculating the audio data in the memory to form a composite sound of a plurality of channels, "?"' The phenomenon of audio bounce, the sound synthesis is a dt in the audio. In the memory, use the -clock signal to trigger the processing = to cause the processor to read the audio in the memory again: processing: the processor makes a calculus of the audio data to form a decoded audio heart and there; ί: ί; Γ = ;, using the clock signal to trigger the temporary storage so that the child temporary storage can receive the decoding from the processor. The full-lock device is connected to the temporary storage device, using a plurality of 昉 22丄, — The sampling device is fixed to control the latching device. The latching device: 摅 ^ ”plural: the periodicity of the sample signal triggers the latching device i at regular intervals, so that ':: some = captures from the processor The decoded audio, • Every two, two and two of the masters should synthesize the audio of every two of these channels, and the latching device dreams: two μ Some sampled signals are transmitted regularly to each person's two mothers of each of these channels to avoid the phenomenon of audio bounce in the synthesized audio. A human roars to output to a speaker to listen to the synthesized audio. Mouth 11 · According to the speech synthesis system described in item 10 of the scope of the patent application, the agricultural φ locking device is provided with a plurality of layers of data structure to receive the decoded sound. Μ

第21頁 1226601 含 --- 六、申請專利範圍Page 21 1226601 Contains --- VI. Scope of patent application

月曰修正丨―lirilTlir - - … 1 2 ·如申請專利範圍第11項所述之語音合成系統，其中該些層資料結構至少包含使用先進先出（F I F 0)的法則將該解石馬音訊傳送至該栓鎖裝置中。 1 3 .如申請專利範圍第1 〇項戶斤述之語音合成系統，其中該處理器至少包含微控制器（Micro-control ler)或是中央處理為、（Central Processing Unit, CPU)。 1 4 ·如申請專利範圍第丨0項所述之語音合成系統，其中該處理器包含使用波形編碼（Waveform Coding)法則對該音訊資料編碼。 1 5 ·如申請專利範圍第1 4項所述之語音合成系統，其中該波形編碼（W a v e f 〇 r m C 〇 d i n g )法則至少包含碼薄激發線性預測編碼（Code Excited Linear Prediction， CELP)法則。 1 6 ·如申請專利範圍第1 4項所述之語音合成系統，其中該波形編碼法則至少包含自適性差動脈衝碼調變（ADPCM)法則。 1 7 ·如申請專利範圍第1 4項所述之語音合成系統，其中該波形編碼法則至少包含差動脈衝碼調變（DPCM )法則。Modification of the month 丨 ―lirilTlir--… 1 2 · The speech synthesis system described in item 11 of the scope of patent application, wherein the data structure of these layers at least includes the first-in-first-out (FIF 0) rule Transfer to the latching device. 1 3. According to the speech synthesis system described in Item 10 of the scope of patent application, the processor includes at least a microcontroller (Micro-controller) or a central processing unit (CPU). 1 4 · The speech synthesis system as described in item 0 of the patent application scope, wherein the processor includes encoding the audio data using a Waveform Coding rule. 15 · The speech synthesis system as described in item 14 of the scope of patent application, wherein the waveform coding (W af f r r C C d i n g) rule includes at least a codebook excited linear prediction coding (Code Excited Linear Prediction, CELP) rule. 16 · The speech synthesis system according to item 14 of the scope of patent application, wherein the waveform coding rule includes at least the adaptive differential pulse code modulation (ADPCM) rule. 17 · The speech synthesis system according to item 14 of the scope of patent application, wherein the waveform coding rule includes at least the differential pulse code modulation (DPCM) rule.

第22頁 1226601 卩 _SS_92M5^ .1 ·,./., 人， ”:V.fl it 六、申請專利範圍 _ ^ 以形成複數個通成道之去合成\由：算記憶體内的音訊資料， ;生音訊跳動的現象合: = = ^ 利用時脈訊號觸發處理器，該音訊資料； μ地°。唄取該記憶體内的該處理器對該音訊資料進 ^ 、利用該時脈訊號觸發暫存哭碼，j =成解碼音訊；理器的該解碼音訊；…使該暫存器接收來自該處利用複數個計時5| ^ 置，該栓鎖裝置依攄备丄^ t個取樣訊號來觸發栓鎖裝該栓鎖裝置，使今於稍驶^些取樣訊號的週期定時地觸發碼音訊，复由^ ^权鎖凌置主動擷取來自該處理器的該解合六立> 、▲母忒些取樣訊號對應於每一該些通道的該每_ ^孔、及柽鎖裝置藉由每一該些取樣訊號準時地傳运 4些通這的該合成音訊，以避免該合成音訊中產生音訊跳動的現象；以及數位/類比轉換器將該解碼音訊轉換為類比型式的該解瑪訊號’並且輸出至音訊產生裝置。 1 9 ·如申請專利範圍第丨8項所述之語音合成方法，其中該栓鎖裝置設有複數層資料結構，用以接收該解碼音訊。 2 0 ·如申請專利範圍第1 9項所述之語音合成方法，其中S 些層資料結構至少包含使用先進先出（FIFO)的法則，以將Page 221226601 SS_SS_92M5 ^ .1 ·,. /., Person, ”: V.fl it 六、 Application for patent scope _ ^ To form a number of meditations to synthesize \ From: Count the audio data in the memory The phenomenon that the audio bounces together: = = ^ uses the clock signal to trigger the processor, the audio data; μ ground °. The processor in the memory takes the audio data ^, and uses the clock signal Trigger the temporary crying code, j = decoded audio; the decoded audio of the processor; ... make the register receive from there using a plurality of timing 5 | ^ settings, the latching device is prepared 丄 t samples The signal is used to trigger the latch to install the latch device, so that the code audio will be triggered periodically at a period of a few sampling signals, and the ^ ^ lock setting will actively retrieve the disengagement from the processor >;, ▲ The mother sample signals correspond to the holes in each of the channels, and the shackle device transmits the synthesized audio signals on time through each sample signal to avoid the Audio bounce in synthesized audio; and a digital / analog converter The audio signal is converted into an analog type of the solution signal and output to the audio generating device. 1 9 · The speech synthesis method according to item 8 of the patent application scope, wherein the latching device is provided with a plurality of layers of data structure for Receive the decoded audio. 20 · The speech synthesis method described in item 19 of the scope of the patent application, wherein the data structure of the layers includes at least a first-in-first-out (FIFO) rule to convert

第23頁 1226601 案申請專利範圍 93; 9 :一嗟土月曰修正該解碼音訊t運」•裝置中 2 1 ·如申請專利範圍第1 8項所述之語音合成方法，其中該處理器至少包含微控制器（M i c r 〇 - c ο n t r ο 1 1 e r )或是中央声王里器（Central Processing Unit, CPU)。 2 2 ·如申請專利範圍第丨8項所述之語音合成方法，其中該處理器包含使用波形編碼（Waveform Coding)法則對該^ A負料編碼。 2 3 ·如申請專利範圍第2 2項所述之語音合成方法，其中該波形編碼（Waveform Coding)法則至少包含碼薄激發線性預剛編碼（Code Excited Linear Prediction，CELP)法則。 2 4 ·如申請專利範圍第2 2項所述之語音合成方法，其中該波形編碼法則至少包含自適性差動脈衝碼調變（ADPCM)法則。 2 5 ·如申請專利範圍第2 2項所述之語音合成方法，其中該波形編碼法則至少包含差動脈衡碼調變（DPCM)法則。Page 23, 1226601, applied for a patent range of 93; 9: a fixed date to modify the decoded audio signal. "• 2 in the device. · The speech synthesis method described in item 18 of the scope of patent application, wherein the processor is at least Contains a microcontroller (Micr 〇- c ο ntr ο 1 1 er) or a central processing unit (CPU). 2 2 · The speech synthesis method as described in item 8 of the patent application scope, wherein the processor includes encoding the ^ A negative material using a Waveform Coding rule. 2 3 · The speech synthesis method described in item 22 of the scope of patent application, wherein the Waveform Coding rule includes at least the Code Excited Linear Prediction (CELP) rule. 2 4 · The speech synthesis method as described in item 22 of the scope of patent application, wherein the waveform coding rule includes at least the adaptive differential pulse code modulation (ADPCM) rule. 2 5 · The speech synthesis method as described in item 22 of the scope of patent application, wherein the waveform coding rule includes at least the differential arterial code modulation (DPCM) rule.