TWI226121B - Chip-packaging with bonding options connected to a package substrate - Google Patents
Chip-packaging with bonding options connected to a package substrate Download PDFInfo
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- TWI226121B TWI226121B TW93103107A TW93103107A TWI226121B TW I226121 B TWI226121 B TW I226121B TW 93103107 A TW93103107 A TW 93103107A TW 93103107 A TW93103107 A TW 93103107A TW I226121 B TWI226121 B TW I226121B
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- packaging substrate
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- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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Abstract
Description
1226121 五、發明說明（1) 【發明所屬之技術領域】 本發明提供一種晶片封裝與方法，尤指一種具有連 接於包裝基板之壓焊選擇的晶片封裝與其相關之方法。 【先前技術】 在現今的積體電路設計中，需要利用壓焊（bonding) 的方法將積體電路中各種需與外界接線的輸出入端接至 外面的電源或其它電路。因此，關於焊墊的配置與壓焊 方法的選擇就是一個非常基本確是重要的技術。在同一 顆電路晶片上會有許多不同的接腳，而常常一顆積體電 路晶片會有不同的功能，在不同的需要考量下使用，所 以，這些不同的接腳並不會在每種場合都使用到，因 此，常常會提供某些腳位具有「賦能」（Enable)與「失 能」（D i sab 1 e )的功能。所謂腳位具有「賦能」的功能是 說當該腳位給定一個固定的高電壓（通常是電源供應電 壓）時，而這個晶片會使它具有的其中某種功能啟動，相 似地，「失能」的功能就是指使得晶片的某種功能停 止，而具有「失能」功能的腳位通常接至電路的地電 位。藉由這些具有賦能與失能的腳位，可以讓使用者選 擇晶片中不同的功能來使用，所以晶片的使用會變得更 有效率。1226121 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention provides a chip package and method, and more particularly, a chip package having a pressure bonding option connected to a packaging substrate and a related method. [Previous technology] In today's integrated circuit design, it is necessary to use bonding to connect various inputs and outputs of the integrated circuit to the external power supply or other circuits. Therefore, the choice of pad configuration and pressure welding method is a very basic and indeed important technology. There will be many different pins on the same circuit chip, and often an integrated circuit chip will have different functions and be used under different needs. Therefore, these different pins will not be used in each occasion. They are all used, therefore, some feet are often provided with the functions of "Enable" and "Disability" (D i sab 1 e). The so-called pin has the function of "enabling" when the pin is given a fixed high voltage (usually the power supply voltage), and this chip will enable one of the functions it has. Similarly, " The "disabled" function means that a certain function of the chip is stopped, and the pin with the "disabled" function is usually connected to the ground potential of the circuit. With these enabled and disabled pins, users can choose different functions in the chip to use, so the use of the chip will become more efficient.
1226121 五、發明說明（2) 關於如何讓一顆晶片的腳位可以提供使用者選擇 「賦能」，「失能」以及「輸出入」的功能，則在晶片 内部壓焊的過程中運用一種叫做壓焊選擇（bonding 〇 p t i ο η )的技巧，這種壓焊選擇技巧除了讓使用者選擇性 的改變積體電路内的硬體組態，同時提供積體電路的測 試與除錯。 在習知技術中，一種壓焊選擇通常包含複數個焊 墊。這些複數個焊墊可以提供不同的壓焊選擇，比如說 可以焊接至高電愿點（例如系統的供應電壓）或是低電壓 點（例如接地點）。習知的壓焊選擇架構包括了兩種型 式，第一種型式翁做「内定值」型式，第二種稱做「電 源端/地端鄰近」型式。請參閱圖一和圖二，圖一和圖二 所示是一個「内定值」型式的壓焊選擇架構。在這種架 構中，每個選擇壓墊已在内部連結至某個屬於邏輯「1」 的高電壓或是邏輯「0」的低電壓。如果選擇壓墊的腳位 在外界並無任何的輸入訊號寫入，則這個腳位就會維持 一個内定的邏輯位準，即是選擇壓墊在内部所連結的邏 輯電位。比如說在圖一所示的「内定值」型式壓焊選擇 架構中’它的内定邏輯是局電位的「1」’如果外界不將 此接腳的邏輯做定義時，則這個接腳會自動設定成邏輯 「1」。而圖二所示的「内定值」型式壓焊選擇架構中， 它的内定邏輯是地電位的「0」，所以如果外界不將此接 腳的邏輯做定義時，則這個接腳會自動設定成邏輯1226121 V. Description of the invention (2) Regarding how to make the pins of a chip provide the user with the functions of "enabling", "disabling" and "input / output", a method is used in the process of internal pressure bonding of the chip This technique is called bonding 〇pti ο η. In addition to allowing users to selectively change the hardware configuration in the integrated circuit, it also provides testing and debugging of the integrated circuit. In the conventional art, a pressure bonding option usually includes a plurality of pads. These pads can provide different pressure welding options, for example, they can be soldered to high voltage points (such as the system's supply voltage) or low voltage points (such as the ground point). The conventional pressure welding selection architecture includes two types, the first type is the “default” type, and the second type is the “power / ground proximity” type. Please refer to Fig. 1 and Fig. 2. Fig. 1 and Fig. 2 show a “default setting” type welding selection structure. In this architecture, each selection pad is internally linked to a high voltage of logic "1" or a low voltage of logic "0". If the pin of the selection pad does not have any input signal written to the outside, this pin will maintain a predetermined logic level, which is the logic potential of the selection pad internally connected. For example, in the "internal value" type pressure welding selection structure shown in Figure 1, 'its internal logic is local potential "1". If the outside world does not define the logic of this pin, this pin will automatically Set to logic "1". In the “Internal Setting” type pressure welding selection architecture shown in Figure 2, its internal logic is “0” of the ground potential, so if the logic of this pin is not defined by the outside world, this pin will be set automatically. Into logic
1226121 五、發明說明（3) 「0」° 更詳細的說明圖一與圖二的運作原理。請參考圖 一，圖一的「内定值」型式壓焊選擇元件12包含一個被 動電路10。被動電路10的一邊連接至圖中的電源端，而 另一邊連接至電壓供應端（power supply)，在圖中是由 一顆P型的金氧半電晶體所組成。被動電路10具有相當小 的電阻，使得它具有相當高的導電性。當被動電路1 0導 通的時候，被動電路1 0兩端幾乎是沒有跨壓的，因此， 使得圖示的電源點直接設定成與電壓供應端相同的電 位，也就是說，當電源端沒有外來訊號時，被動電路1 0 將被導通，並將電源端拉抬至高電位。這會讓内部的電 路收到一個邏輯「1」的訊號。 請參考圖二。圖二中「内定值」型式壓焊選擇元件 1 6包含一個被動電路1 4。被動電路1 4的一邊連接至圖中 的地端，而另一邊連接至系統的地（g r 〇 u n d )，在圖中是 由一顆N型的金氧半電晶體所組成。被動電路14 一樣具有 非常小的電阻，使得它具有非常高的導電性。當被動電 路1 4導通的時候，被動電路1 4兩端幾乎是沒有跨壓的， 因此’使得圖不的地端直接設定成糸統的地電位’也就 是說，當電源端沒有外來訊號時，被動電路1 4將被導 通，並強迫地端變成地電位，使得内部的電路收到一個 邏輯「0」的訊號。1226121 V. Description of the invention (3) "0" ° A more detailed explanation of the operating principles of Figure 1 and Figure 2. Please refer to FIG. 1. The “default” type pressure welding selection element 12 of FIG. 1 includes a driven circuit 10. One side of the passive circuit 10 is connected to the power supply terminal in the figure, and the other side is connected to the power supply terminal. In the figure, it is composed of a P-type metal-oxide semiconductor transistor. The passive circuit 10 has a relatively small resistance, so that it has a relatively high electrical conductivity. When the passive circuit 10 is turned on, there is almost no voltage across the passive circuit 10. Therefore, the power point shown in the figure is directly set to the same potential as the voltage supply terminal. That is, when there is no external power supply terminal At the time of signal, the passive circuit 10 will be turned on and the power terminal will be pulled up to a high potential. This will cause the internal circuit to receive a logic "1" signal. Please refer to Figure 2. The “default” type pressure welding selection component 16 in FIG. 2 includes a passive circuit 14. One side of the passive circuit 14 is connected to the ground terminal in the figure, and the other side is connected to the ground of the system (g r oo n d). In the figure, it is composed of an N-type metal-oxide semiconductor transistor. The passive circuit 14 also has a very small resistance, making it very conductive. When the passive circuit 14 is turned on, there is almost no voltage across the two ends of the passive circuit 14, so 'make the ground terminal of the figure directly set to the common ground potential'. That is, when there is no external signal at the power terminal The passive circuit 14 will be turned on, and the ground terminal will be forced to ground potential, so that the internal circuit will receive a logic "0" signal.
1226121 五、發明說明（4) 不過這樣的習知架構有一個缺點，如果當這個腳位 接至外界的輸入訊號，而且這個輸入訊號的邏輯與内定 的訊號不同時，就會產生額外的功率損耗。這樣的缺點 在現今的小尺寸而需要以電池當作供應電源的這些電子 產品中，將是非常嚴重的問題。 請參考圖三。圖三所示是習知的「電源端/地端鄭 近」型式壓焊選擇架構17。這種架構包含了複數個選擇 壓墊，每個壓墊所設置的位置兩邊都會靠近一個電源點 與一個接地點。但是這些壓墊並沒有内定的邏輯位準。 如果其中的一個壓塾必需接至代表邏輯「1」的高電位， 則把選擇壓墊與圖三上的電源點相連，如果其中的一個 壓墊必需接至代表邏輯「0」的地電位，則把選擇壓墊與 圖三上的接地點相連。這樣的架構不但可以提供該壓墊 的邏輯「1」或邏輯「0」，而且不會有上述「内定值」 型式壓焊選擇架構中功率浪費的問題。然而，為了達到 這種方式的壓焊選擇架構，如前面部分所述，每個壓墊 所設置的位置兩邊都必須靠近一個電源點與一個接地 點，因此，每個壓墊與各個電源點和接地點的擺置必須 特別的安排，如果一個晶片需要有許多腳位，也就是需 要很多的壓墊，則在這種情況下壓墊的的擺置就是個很 令人頭痛的問題。1226121 V. Description of the invention (4) However, this conventional structure has a disadvantage. If this pin is connected to the external input signal, and the logic of this input signal is different from the predetermined signal, additional power loss will occur. . Such a disadvantage will be a very serious problem in today's small-sized electronic products that require a battery as a power supply. Please refer to Figure 3. Figure 3 shows the conventional “Power / Ground Terminal” type pressure welding selection architecture17. This architecture includes multiple selection pads, each of which is located close to a power point and a ground point on both sides. But these pressure pads do not have an established logical level. If one of the pressure pads must be connected to a high potential representing logic "1", then the selection pad is connected to the power point on Figure 3. If one of the pressure pads must be connected to the ground potential representing logic "0", Connect the selection pad to the ground point on Figure 3. Such a structure not only provides a logic "1" or a logic "0" of the pressure pad, but also does not have the problem of waste of power in the "default" type pressure welding selection architecture. However, in order to achieve this type of pressure welding selection architecture, as described in the previous section, each pressure pad must be positioned close to a power point and a ground point on both sides. Therefore, each pressure pad and each power point and The placement of the ground point must be specially arranged. If a chip needs to have many feet, that is, a lot of pressure pads, then the placement of the pressure pads is a headache in this case.
1226121 五、發明說明（5) 【發明内容 本H月，露—種具有連接於包裝基板之焊墊的晶片 ΐ κ ^ :包裝基板，一晶片，以及-引線框架。 !a 了又··於该包裝基板上，而且該晶片包含有複數個 該 ；；^ ^ ΐ ^琢包裝暴板上，而且該晶片包含有複數 ϊ ί綠個焊整中之一焊墊係連接於該包裝基板 忒引線框杀係連接於該複數個焊墊中之一焊墊。 【實施方式】 杜ϋ ί考圖四。圖四是利用本發明之焊墊選擇架構1 9 3 ί 裝/結構示意圖。這個包裝結構包含了複數個引 線框木20 (lead frame)，複數條焊線24，一晶片“，一 ,以及複數個焊墊26。其中，整個晶片28處 在匕裝土板22之上；而複數個焊塾26置於晶片28上，圍 ^在晶片28邊緣的四周，讓晶片28内部的輸出入端能夠 接至晶片28外部。複數個引線框架2〇分佈於晶片28的外 圍’絰j焊線2 4與晶片2 8上的焊墊2 6相連接。焊墊2 6可 以看成疋晶片2 8欲從内部連接至外部的接點，而引線框 架20則是從外部連接至晶片28内部的接點。詳細說明請 參，圖五1圖五是圖四的整體包裝結構中說明各標示物 功能的示意圖。與圖四類似，圖五的整體包裝結構包含 了一引線框架20A，一焊線24A，一晶片28A，一包裝基板 22A，以及一知塾26A。而晶片28Δ中另包含一電路30A。1226121 V. Description of the invention (5) [Summary of the invention] In this month, a kind of wafer with a solder pad connected to a packaging substrate ΐ κ ^: a packaging substrate, a wafer, and a lead frame. ! a on the packaging substrate, and the wafer contains a plurality of the ;; ^ ^ ΐ ^ cut the packaging board, and the wafer contains a plurality of ϊ green pads The lead frame connected to the packaging substrate is connected to one of the plurality of bonding pads. [Embodiment] Du Yan FIG. 4 is a schematic diagram of an assembly / structure using the pad selection structure of the present invention. This packaging structure includes a plurality of lead frames 20 (lead frame), a plurality of bonding wires 24, a wafer ", a, and a plurality of bonding pads 26. Among them, the entire wafer 28 is located on the dagger 22; A plurality of soldering pads 26 are placed on the wafer 28 and surrounded by the edges of the wafer 28, so that the input and output ends of the wafer 28 can be connected to the outside of the wafer 28. A plurality of lead frames 20 are distributed on the periphery of the wafer 28. j The bonding wire 2 4 is connected to the bonding pad 2 6 on the chip 2 8. The bonding pad 2 6 can be regarded as the contact of the chip 2 8 from the inside to the outside, and the lead frame 20 is connected to the chip from the outside. 28 internal contacts. Please refer to Figure 5 for details. Figure 5 is a schematic diagram illustrating the functions of the markers in the overall packaging structure of Figure 4. Similar to Figure 4, the overall packaging structure of Figure 5 includes a lead frame 20A. A bonding wire 24A, a wafer 28A, a packaging substrate 22A, and a chip 26A. The wafer 28Δ further includes a circuit 30A.
1226121 五、發明說明（6) 電路3 Ο A在動作的過程中需要外界提供一輸入訊號，而此 輸入訊號即由焊墊26A中進入。不過，如前所述，焊墊 2 6 A只是晶片内部連結至外部的接點，所以焊墊2 6 A經由 焊線2 4 A與引線框架2 Ο A相連，由外部提供的輸入訊號將 連結至引線框架20A，最後進入電路30A達成外部訊號輸 入晶片内部的功能。而整個焊墊選擇架構的主要功能即 是讓晶片内部的訊號輸出入點能連結至晶片外部，同時 又能提供晶片測試的功能。 請參考圖六。圖六是本發明壓焊選擇結構6 0的實施 例示意圖。這個壓焊選擇的細部結構包含一第一引線框 架40A，一第二引線框架40B，一包裝基板42，一焊線 44，一晶片46，和一壓焊選擇單元50。圖六的結構是基 於圖五的概念延伸而成的，所以與圖五相同名稱的各個 標示物，其功能是相同的。壓焊選擇單元50連接到晶片 46的内部電路，包含焊墊48 ，讓晶片46内的輸出入端能 夠透過焊墊48與外界相連。如先前技術所述，常常晶片 中的一壓焊選擇單元必須連結至三種可能的連結點，分 別是系統的地端，系統的電源端以及壓焊選擇端。因為 同一顆晶片内部常常具有不同的功能，組態或使用方 式，因此，某些腳位必須在出廠時定義它們的腳位電位 為「賦能」或是「失能」。「賦能」通常用代表邏輯 「1」的高電位（也就是系統的電源端電位）來表示，也就 是說當這個腳位接上電源端電位時，晶片内部的某種功1226121 V. Description of the invention (6) Circuit 3 0 A requires an external input signal during the operation, and this input signal is entered from the pad 26A. However, as mentioned earlier, the pad 2 6 A is only a contact connected to the outside of the chip, so the pad 2 6 A is connected to the lead frame 2 0 A through the bonding wire 2 4 A, and the input signal provided by the outside will connect Go to the lead frame 20A, and finally enter the circuit 30A to achieve the function of the external signal input chip. The main function of the entire pad selection architecture is to allow signal I / O points inside the chip to be connected to the outside of the chip, and at the same time provide the function of chip testing. Please refer to Figure 6. Fig. 6 is a schematic diagram of an embodiment of a pressure welding selection structure 60 according to the present invention. The detail structure of the pressure bonding selection includes a first lead frame 40A, a second lead frame 40B, a packaging substrate 42, a bonding wire 44, a wafer 46, and a pressure bonding selection unit 50. The structure of Fig. 6 is based on the concept of Fig. 5, so each marker with the same name as Fig. 5 has the same function. The pressure-bonding selection unit 50 is connected to the internal circuit of the chip 46 and includes the bonding pads 48, so that the I / O terminals in the chip 46 can be connected to the outside through the bonding pads 48. As described in the prior art, often a pressure bonding selection unit in the chip must be connected to three possible connection points, namely the system ground, the system power terminal, and the pressure bonding selection terminal. Because the same chip often has different functions, configurations or usage methods, certain pin positions must be defined as “enable” or “disable” at the factory. "Empowering" is usually represented by a high potential representing the logic "1" (that is, the power supply terminal potential of the system), that is, when this pin is connected to the power supply terminal potential, a certain function inside the chip
1226121 五、發明說明（7) 能就可以啟動。相對地，「失能」通常用代表邏輯「0」 的低電位（也就是系統的地電位）來表示，而當具有賦能 或失能的腳位接上地電位時，晶片内部的某種功能會被 停止。如此的好處不但讓同種晶片出廠時，可以依照各 腳位賦能與失能的定義來改變晶片内不同的功能。同 時，「賦能」與「失能」又意謂著加給某腳位邏輯「1」 與邏輯「0」的訊號，能同時做為測試晶片功能的信號。 當然，壓焊選擇單元5 0除了可能接上「賦能」與 「失能」所需要的兩種電位（系統的電源端電位與地電 位）之外，更重要的是它也可能接至外界的控制訊號，這 樣才有辦法讓外界輸入訊號進入晶片4 6中’或者’讓晶 片4 6内部的輸出訊號輸出。因此，請參照圖六，在一個 焊墊4 8的周圍提供了三種連結點，它們分別是當作第一 壓焊選擇的引線框架40A，當作第二壓焊選擇的引線框架 4 0B，以及當作第三壓焊選擇的包裝基板42。第一壓焊選 擇提供給晶片對外的輸出入訊號做使用。第二壓焊選擇 和第三壓焊選擇分別提供系統的電源端電位與地電位。 在本發明的實施例中，當作第二壓焊選擇的引線框架40 B 提供系統的電源端電位，則當作第三壓焊選擇的包裝基 板4 2提供系統的地電位。當然也可以反過來讓引線框架 4 0 B提供地電位而包裝基板4 2提供系統的電源端電位。所 以，以本實施例來講，當壓焊選擇單元5 0需要接至電源 端電位時，就利用焊線44將焊墊48與引線框架40B相連，1226121 V. Description of the invention (7) It can be started. In contrast, "disability" is usually represented by a low potential (that is, the system ground potential) representing a logic "0". When a pin with an enable or disable is connected to ground potential, The function will be stopped. This benefit not only allows the same kind of chip to be shipped from the factory, it can change the different functions in the chip according to the definition of each pin's enabling and disabling. At the same time, "enable" and "disable" mean that the signals of logic "1" and logic "0" added to a pin can be used as signals for testing chip functions at the same time. Of course, in addition to the two potentials (power supply terminal potential and ground potential) required for "enabling" and "disabling", the pressure welding selection unit 50 may also be connected to the outside world. Control signal, so that there is a way to allow external input signals to enter chip 46, or to let the internal output signals of chip 46 be output. Therefore, referring to FIG. 6, three connection points are provided around a pad 48, which are the lead frame 40A used as the first pressure welding option, the lead frame 40B used as the second pressure welding option, and The packaging substrate 42 is selected as the third pressure bonding. The first pressure welding is used to select external I / O signals provided to the chip. The second pressure welding option and the third pressure welding option provide the system's power terminal potential and ground potential, respectively. In the embodiment of the present invention, the lead frame 40 B as the second pressure welding option provides the power supply terminal potential of the system, and the packaging substrate 42 as the third pressure welding option provides the system ground potential. Of course, the lead frame 40B can also be provided with a ground potential in turn, and the package substrate 42 can be provided with the power supply terminal potential of the system. Therefore, in this embodiment, when the pressure-bonding selection unit 50 needs to be connected to the power terminal potential, the bonding pad 48 is connected to the lead frame 40B by using the bonding wire 44.
第12頁 1226121 五、發明說明（8) ~ ' ---- 這樣電源端電位即輸入給壓焊選擇單元5 〇並進入晶片4 6 的内部電路。當壓焊選擇單元50需要接至地電位^，焊 線44將焊墊48與包裝基板42相連，壓焊選擇單元5〇則具 有地電位。最後一種情況，壓焊選擇單元5 〇經由焊線 連到引線框架4 0 A ’提供晶片與外界之間輸出入訊號傳輸 的路徑。Page 12 1226121 V. Description of the invention (8) ~ '---- In this way, the potential of the power supply terminal is input to the pressure welding selection unit 5 0 and enters the internal circuit of the wafer 4 6. When the pressure welding selection unit 50 needs to be connected to the ground potential ^, the bonding wire 44 connects the bonding pad 48 to the packaging substrate 42, and the pressure welding selection unit 50 has a ground potential. In the last case, the pressure-bonding selection unit 50 is connected to the lead frame 40 A 'through a bonding wire to provide a path for transmitting input and output signals between the chip and the outside world.
必須特別δ兄明的’圖六的貫施例中對一單一的壓焊 選擇單元5 0設置了二個引旅框架4 0 Α和4 0 Β，的確，兩個 引線框架即可實現本發明的功能。然而，對於單一的壓 焊選擇單元5 0所設的引線框架不一定為兩個，如有特別 的用途，可使用三個以上的引線框架，甚至只有一個引 線框架，這將由晶片本身的設計功能與使用者的使用目 的做決定。關於這些引線框架數目上的變化，只要使用 到包裝基板42提供某一電位給焊墊48，即包含在本發明 的範圍裡面。It must be particularly clear that in the embodiment of FIG. 6, two lead frames 40 0 A and 40B are provided for a single pressure welding selection unit 50. Indeed, two lead frames can implement the present invention. Functions. However, there are not necessarily two lead frames for a single pressure bonding selection unit 50. If there are special applications, more than three lead frames can be used, or even only one lead frame, which will be determined by the design function of the chip itself. Decide with the purpose of use. Regarding the change in the number of these lead frames, as long as the packaging substrate 42 is used to provide a certain potential to the pads 48, it is included in the scope of the present invention.
習知技術所提的「内定值」型式壓墊選擇結構中， 當這個腳位接至外界的輸入訊號，而且這個輸入訊號的 邏輯與内定的訊號不同時，由於被動電路在訊號的^换 過程中會有額外的電流流通，因此產生額外的功率損 耗。這在現今講求低功率、低耗電的電子電路技術中， 是非常大的缺點。雖然，在「電源端/地端鄰近」型式的 壓墊選擇結構中，避免了這種額外功率損耗的問題，但In the "internal value" type pressure pad selection structure mentioned in the conventional technology, when this pin is connected to an external input signal, and the logic of the input signal is different from the internal signal, the passive circuit is in the process of changing the signal. There will be extra current flowing in it, thus causing extra power loss. This is a very big disadvantage in today's electronic circuit technology that requires low power and low power consumption. Although this type of pressure pad selection structure of the "power / ground proximity" type avoids this problem of extra power loss,
第13頁 1226121 五、發明說明（9) 是由於壓墊所設置的位置兩邊都必須靠近一個電源點與 一個接地點，因此，每個壓墊與各個電源點和接地點的 擺置必須特別的安排，造成一個晶片具有多個腳位的情 況下，壓墊無法有彈性的擺置，而且常常需要增加許多 額外的壓墊。值得一提的，内部的電路和壓墊都會耗去 晶片的面積，而且壓墊是很占面積的，如果壓墊的數目 非常多的話，整個晶片的面積會因這些壓墊的增加而變 大，使得製作成本提高了許多。所以，習知技術中「電 源端/地端鄰近」型式的壓墊選擇結構，還可能有增加佈 局面積，提高製作成本的缺點。 相較於習知技術，本發明利用包裝上的包裝基板當 作是其中的一個電位，比如說是系統地電位或系統的電 源供應電位，不但減少了額外引線框架的數目，也達成 壓墊選擇的功能。因此，本發明具有下列的優點：1、擴 展晶片的使用功能以及提供晶片方便的測試，同時，讓 單一晶片可以操作在不用的功能下。2 、只需要一個引 線框架當作是電源供應電位或是地電位，使得引線框架 的排列更容易。3 、對於壓焊選擇的使用與維持上更容 易。4 、較少引線框架具有較小佈局面積與較低製作成 本。這些種種的優點不但包含了習知技術原本就具備的 優點，同時，本發明特徵所具有的其它優點是習知技術 無法達成的。Page 13 1226121 V. Description of the invention (9) Because the two sides of the position where the pressure pad is set must be close to a power point and a ground point, therefore, the placement of each pressure pad and each power point and ground point must be special Arrangement, in the case that a chip has multiple foot positions, the pressure pad cannot be placed elastically, and often many additional pressure pads need to be added. It is worth mentioning that the internal circuit and pressure pads will consume the area of the chip, and the pressure pads occupy a large area. If the number of pressure pads is very large, the area of the entire wafer will become larger due to the increase of these pressure pads. , Making the production cost much higher. Therefore, the pressure pad selection structure of the "power source / ground end proximity" type in the conventional technology may also have the disadvantages of increasing the layout area and increasing the production cost. Compared with the conventional technology, the present invention utilizes the packaging substrate on the package as one of the potentials, such as the system ground potential or the system's power supply potential, which not only reduces the number of additional lead frames, but also achieves pad selection. Functions. Therefore, the present invention has the following advantages: 1. Expand the use function of the wafer and provide convenient testing of the wafer, while allowing a single wafer to operate under unused functions. 2. Only one lead frame is needed as the power supply potential or ground potential, making the arrangement of the lead frame easier. 3. It is easier to use and maintain the pressure welding option. 4. Fewer lead frames have a smaller layout area and lower manufacturing costs. These advantages not only include the advantages inherent in the conventional technology, but also other advantages of the features of the present invention that cannot be achieved by the conventional technology.
第14頁 1226121Page 14 1226121
第15頁 1226121 圖式簡單說明 圖式之簡單說明 圖一係為一個「内定值」型式壓焊選擇架構的示意圖。 圖二係為一個「内定值」型式壓焊選擇架構的示意圖。 圖三係為習知「電源端/地端鄰近」型式壓焊選擇架構的 示意圖。 圖四是利用本發明之焊墊選擇架構的整體包裝結構示意 圖。 圖五是圖四的整體包裝結構中說明各標示物功能的示意 圖。Page 15 1226121 Simple illustration of the drawing Simple illustration of the drawing Figure 1 is a schematic diagram of a "default" type pressure welding selection framework. Figure 2 is a schematic diagram of a "default" type pressure welding selection framework. Figure 3 is a schematic diagram of the conventional “Power / Ground Proximity” type pressure welding selection architecture. Figure 4 is a schematic diagram of the overall packaging structure using the pad selection architecture of the present invention. Figure 5 is a schematic diagram illustrating the function of each marker in the overall packaging structure of Figure 4.
圖六是本發明壓焊選擇結構的實施例示意圖。 圖式之符號說明 被動電路 壓焊選擇元件 塵焊選擇架構 引線框架 包裝基板 焊線 焊墊 晶片 電路 壓焊選擇單元FIG. 6 is a schematic diagram of an embodiment of a pressure welding selection structure of the present invention. Symbol description of the drawing Passive circuit Pressure welding selection component Dust welding selection architecture Lead frame Packaging substrate Welding wire Pad Wafer Circuit Circuit Pressure welding selection unit
1 0、14 12 、 16 、 18 17 > 191 0, 14 12, 16, 18 17 > 19
20、20A、40A、40B 22、2 2 A、4 2 24、24A、44 26、26A、48 28、28A、4620, 20A, 40A, 40B 22, 2 2 A, 4 2 24, 24A, 44 26, 26A, 48 28, 28A, 46
30A 5030A 50
第16頁 1226121 圖式簡單說明 6 0 晶片封裝Page 16 1226121 Schematic description of 6 0 chip package
第17頁Page 17
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