TWI226069B - Reading circuit, reference circuit, and semiconductor memory device - Google Patents

Abstract

A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.

Description

1226069 玖、發明說明： 【發明所屬之技術領域】 電 本發明涉及一讀取電路、 路和這類參考電路的半導 先前技術】 一參考電路， 體記憶體裝置 和包括這類讀取 一般而言，用於從包括複數個記憶體單元的記憶體單元 陣列中讀取資料的讀取電路，會提供電流至其中儲存有資 枓的二憶體單元，並比較以參考電流流過記憶體單元的電 流（單元u)’以便判斷該單元電流的位準是高於或低於諸 參考電流的位準。因此，來讀取窝入記憶體單元中的資： 。這類讀取資料的系統被稱為「電流感應系統」。 例如，參考圖9B描述如下，從可在一記憶體單元中儲妁 個位元的所渭兩層式記憶體單元内讀取資料。會預先設定 在第一狀態中單元電流位準高於參考電流位準（對應到資 料「1」），且在第二狀態中單元電流位準低於參考電流位 準（對應到資料「〇」）的狀況。該參考電流位準設定成在第 一狀態和第二狀態之間的中間位準。然後，記憶體單元的 單元電流位準與參考電流位準相比較，因此可以讀取儲存 在記憶體單元的1位元的資料。實際上，單元電流和參考電 流必須接受電流電壓轉換，並且單元電流流過的感應線的 電位會與參考電流流過的參考線的電位相比較。 除了這類兩層式記憶體單元，最近也在研究可在一個記 憶體單元中儲存2位元或以上的資料之多層式記憶體單元 ’以便增加儲存容量及/或減少半導體晶片的生產成本。 87062 1226069 在本專利說明書中，名詞「多層式記憶體單元」表示三 層或以上的圮憶體單元，也就是指，可以在一記憶體單元 中儲存1·5位元或以上資料的記憶體單元。 例如，參考圖9Α描述如下，從可在一記憶體單元中儲存2 位元資料的四層式記憶體單元内讀取資料。會預先設定單 疋電流所處的四種狀態。更明確地說，會以單元電流位準 的順序來設定第-狀態、第：狀態、第三狀態和第四狀態 。單兀電流位準在第一狀態中最高，在第四狀態中最低。 在k個範例中，第一狀態對應到資料「丨丨」，第二狀態對應 到資料「10」，第三狀態對應到資料「〇1」，第四狀態對應 到資料「00」。 二後一個參考電洗位準設定成介於單元電流的四個狀 態之間。更明確地說，一第一參考電流位準乙設定在第一狀 態（對應到資料「U」）和第二狀態（對應到資料「1〇」）之間 勺中間位準，一第二參考電流位準“設定在第二狀態（對應 J ^料10」）和第二狀態（對應到資料「〇 1」）之間的中間 位準，以及一第三參考電流位準定在第三狀態（對應到 資料「01」）和第四狀態(對應到資料「00」）之間的中間位 準。 依此方式设定的參考電流位準，會與記憶體單元中的單 元電流位準相比較，因此可根據單元電流位準讀取2 資料。 為了要從可以在-記憶體單元中儲存此元資料的一般 多層式記憶體單元中讀取’必須預先設定該單元電流可處 87062 1226069 之2Π個狀態，還要設定A個參考電流位準。 可從圖9A和卯瞭解到，一 ^ ^ 叙而3 ’要從多層式記憶體單 疋的早7C電流位準和參者 準声m ,, 考 準之間取得足夠的電流位 。在f+ V L、肖豆早兀中取得，要更為困難 在每類情況中，由认留— 、 的兩Mm % %隸準和參考電流位準之間 的私成位準差相當小， 不谷易取得夠大的操作極限， 尤其在躓取電路中更是不易。 在一多層式記憶體單元中，為 罝分m 凡甲為了要碩取儲存在-記憶體 早疋的資料，必須將單元雪 、册早兀电泥位準與許多類型的參考電流 位準作比較。例如，Α τ i 4 _ 為了要續取2位疋的資料，該記憶體單 7C的單元電流位準需要與三個參考電流位準相比較。如 此來，便意外地延長讀取時間。 為了要解決這些問題，已經提出複數個用於從—多 記憶體單元讀取資料的系統。—這類系統是—分時感^ 統，猎由孩系、统’記憶體單元中的單元電流位準一次會與 另一參考電流位準相比較，而且根據比較結果，單元電流 位準會與另-參考電流位準㈣較n電流位準以^ 時方^循序比較。另一系統是一平行感應系統，藉由該系 統，單元電流位準一次會與複數個參考電流位準相比較。 作為分時感應系統的範例，從可以在—記憶體單元中儲 存2位元的多層式記憶體單元（圖9A)讀取資料的操作，將參 考圖10加以描述。 圖10是從分時感應系統的記憶體單元讀取資料的傳統讀 取電路J100的一電路圖。 87062 -9- 1226069 在圖Η)中，該讀取電路mG只從_記憶體單元讀取資料 2這只是示H ’而且讀取電路⑽可從選自複數個記憶體 單元中之一選定記憶體單元來讀取資料。 孩讀取電路；1GG包括施加—電壓到要從中讀取資料之選 定單元J7的一汲極的電流負載電路J1，以取得一讀取電流 (單元電流，和一用於取得參考電流的電流負載電路Μ。 提供一感應線J9,用於將選定的單元；7的汲極連接至電 流負載電路η，並提供一參考線m，用於將電流負載電路 J2連揍至選擇電路J6。豸選擇電路；6透㊣參考電流的般將 資源J80之一連接至電流負載電路J2。 該感應線〗9和參考線則分別連接至_感應放大器J3的輸 入區焱。該感應放大器J3感應在感應線J9電位和參考線 電位之間的電位差並擴大該電位差。 感應放大器J3的一輸出區段係連接至用於在第一感應週 期期間鎖住從感應放大器J3之輸出的一第一資料閂鎖電路 J4 ,並連接至用於在第二感應週期期間鎖住從感應放大器 J3之輸出的一第二資料閂鎖電路乃，該第二感應週期係位 於該第一感應週期之後。 第一資料閂鎖電路J4經由線J111連接至選擇電路：6。選擇 電路J6根據從第一資料閂鎖電路J4之輸出透過參考電流的 J82選取資源j80之一，並將所選取的資源連接至參考線 J10 〇 具有上述結構的分時感應系統之讀取電路j丨〇〇，以下列 方式從選定的單元J7讀取資料。在下列說明中，選擇電路 87062 •10- 1226069 J6將參考線ji〇連接至初始狀態的資源J8〇。 第一’一適當電壓施加至所選定單元J7的閘極和沒極， 藉以產生流過該選定單元J7的一單元電流。接下來，根據 產生的單元電流，降低感應線J9的電位。 同樣地，產生從由選擇電路J6選取的資源J8〇流出的參考 電流。根據參考電流，降低參考線j10的電位。 然後，該感應放大器J3感應在感應線J9電位和參考線J1〇 電位之間的電位差並擴大該電位差。當單元電流的位準低 於參考電流的位準時，感應放大器J3輸出「〇」。當單元 電流的位準高於參考電流的位準時，感應放大器J3輸出 「1」。 第一感應週期時從感應放大器J3的輸出由第一資料閂鎖 電路J4鎖住。 第一感應週期期間，選擇電路％選取的參考電流的資源 J80係用於取得三個參考電流位準之中介於第二狀態（圖 9A)(對應到資料「1〇」）和第三狀態（對應到資料「〇1」）之 間的電流位準「M」。 一般而言，如資源则錢2,使縣定電壓受到嚴密調 整之記憶體單元具有相同結構和相同特性 便取得適當的參考電流。 參考早70 接下來’基於在第一感應週期期間從感應放大器的輸 出，該輸出受到第-資料閃鎖電賴鎖住，選擇電路⑽ 參考電流的資源從J8〇切換到了81或J82。 當第一資料閃鎖電路_住資料「0」（也就是說當單元 87062 •11· 1226069 電流位準料參考以 切換到二。當第一資相鎖電路J4鎖住「現的資源被 說，當單元電流位準高於參 ^ Λ丨」（也就是 流的資源被切換到J82。 ㈣位準時）的時候，參考電 資源川係用於取得在三 狀態（圖9A)(對應到資科「〇1 / 準（中的第三 「00 Mm a 」）和第四狀態（對應到資料 「〇〇」）《間的-參考電流位準 j貝科 ^ ^ ^ / si 」貝源J82係用於取得 在弟一狀態（圖9A)(對應到資科 件 月科10」）又間的一參考電流位準「L」。 然後’在第二個感應週期中， ^ ^ . L 上與罘一感應週期 相同的万式執行感應操作， ^ F亚且該弟一資料問鎖電路J 5在 第二感應週期中鎖住來自感應放大IU3的輸出。 依此方式，可以讀取儲存在所敎單元中的2 料。 貝 上述說明係關於可在-記憶體單元中儲存2位元資料的 四層式C憶體單元。分時感應系統也可用於可在一記憶體 單兀中儲存卜位元的記憶體單元。在這情況中，可以只執 行n次的感應操作來讀取η-位元資料。 藉由分時感應系統，只使用一個感應放大器，即可讀取 衩數個位元的資料。因此，可以縮減由感應放大器所佔用 的晶片區域、瞬間消耗的電流位準等。由於電流負載電路 J1和J2的電路常數和其他參數互相切換，因此可以容易地 在每一週期的感應操作期間取得較大的操作極限。 但是’分時感應系統不但在每一週期的感應操作期間需 87062 -12- 1226069 要設定/保持時間，用以由資料⑽電路；4和了5鎖住來自感 應放大器J3的輸出，在感應週期之間還需要切換時間 此’很難以高速執行資料讀取。 接下來’將描述該平行錢系統單元，藉由該單元電流 位準一次可與複數個參考電流位準相比較。 作為平行感應系統的範例，從可以在—記憶體單元中儲 存2位元的多層式記憶體單元（圖9A)讀取資料的操作，將參 考圖11加以描述。 圖11是從平行感應系統的記憶體單元讀取資料的傳統讀 取電路H100的一電路圖。 在圖11中，該讀取電路H100只從一記憶體單元讀取資料 。這只是示範，而且讀取電路H100可從選自複數個記憶體 草元中之一選定記憶體單元來讀取資料。 該讀取電路H100包括施加一電壓到要從中讀取資料之選 定單元H8之一汲極的電流負載電路hi，以及施加電壓到參 考電流資源H80至H82之電流負載電路H2至H4,以分別取得 參考電流位準。該電流負載電路H1至H4具有相同的特性。 提供一感應線H9,用於將選定的單元H8w汲極連接至電 泥負載電路H1，並提供一參考線H10，用於將資源H8〇連接 土電流負載電路H2。提供一參考線Η11，用於將資源H8 1連 接至电流負載電路Η3 ’並提供一參考線Η12，用於將資源 Η82連接至電流負載電路Η4。 該感應線Η9和參考線Η10分別連接至一感應放大器Η5的 輸入區段。該感應放大器Η5感應在感應線Η9電位和參考線 8706： -13 - 1226069 HI0電位之間的電位差並擴大該電位差。 該感應線Η9和參考線HI 1分別連接至一感應放大器Η6的 輸入區段。該感應放大器Η6感應在感應線Η9電位和參考線 Η11電位之間的電位差並擴大該電位差。 該感應線Η9和參考線Η12分別連接至一感應放大器Η7的 輸入區段。該感應放大器Η7感應在感應線Η9電位和參考線 Η12電位之間的電位差並擴大該電位差。 邏輯電路Η13係連接至感應放大器Η5至Η7每一個的一輸 出區段’而且2位元的資料係經由線hi4和Η15從邏輯電路 Η13的一輸出區段讀取。 具有上述結構的平行感應系統之讀取電路Η1 〇〇，以下列 方式從選定的單元Η8讀取資料。 第一，一適當電壓施加至所選定單元閘極和汲極， 藉以產生流過該選定單元H8的一單元電流。接下來，根據 產生的單元電流’降低感應線H9的電位。 同樣地，產生從資源H80流出的參考電流。根據參考電流 ’降低參考線mo的電位。當產生從資源服流出的參考電 流時，會根據產生的參考電流降低參考線Hu的電位。當產 生從資源H82流出的參考電流時，會根據產生的參考電流降 低參考線H12的電位。 參考電流的資請G係料取得在三財考電流位準之 中的第三狀態（圖9A)(對應到資料「〇1」）和第四狀態（對應 到貝料「G。」）之間的_參考電流位準「H」。參考電流的資 細1係用於取得第二狀態（圖9AX對應到資料「10」）和第 87062 •14· 1226069 二狀態（對應到資料「〇 1」）之間的一參考電流位準「Μ」。 參考電流的資源Η82係用於取得在第一狀態（圖9Α)(對應到 資料「11」）和第二狀態（對應到資料「1〇」）之間的一參考 電流位準「L」。 一般而言，如資源Η80至Η82，使用限定電壓受到嚴密調 盏之圮憶m單元具有相同結構和相同特性的參考單元，以 便取得適當的參考電流。 每一該個感應放大器H5至H7平行感應在感應線H9電位 和參考線H10至H12電位之間的電位差並擴大該電位差。因 此，3位元的資料從感應放大器115至]9[7輸出到邏輯電路 H13。 從感應放大器H5至H7輸出的3位元資料由邏輯電路Ή13 轉換為貫際讀取的2位元資料。 藉由參考圖12和13，將描述邏輯電路扪3(圖u)的特定具 體實施例。 圖12顯示記憶體單元可以具有的單元電流位準和參考電 泥位準，與感應放大器H5至H7(圖n)的輸出之間的關係。 如上所述，資源H80的參考電流位準設定為第三狀態（對 2資料「(H」）和第四狀態（對應到資料「⑼」）之間的位 卞Η」。資源H8丨的參考電流位準設定為第二狀態（對應到 資料「10」）和第三狀態（對應到資料「〇1」）之間的位準「 M」。資源H82的參考電流位準設定為第一狀態（對應到資料 J )和第一狀態（對應到資料r 1 〇」）之間的位準「乙」。 在這一範例中，當單元電流位準高於參考電流位準時， 87062 -15 - 1226069 每個感應放大器H5至H7都會輸出資料「1」至邏輯電路H13 。當單元電流位準低於參考電流位準時，每個感應放大器 H5至H7都會輸出資料「〇」至邏輯電路m3。 如圖12所示，當單元電流位準是在第一至第三狀態中任 一狀態時，感應放大器H5的輸出是「1」，當單元電流位準 是在第四狀態時，輸出是「〇」。當單元電流位準是在第一 和第二狀態中任一狀態時，感應放大器則的輸出是Γ 1」， 當單元電流位準是在第三和第四狀態中任一狀態時，輸出 是「0」。當單元電流位準是在第一狀態時，感應放大器H7 的輸出疋「1」，當單元電流位準是在第二至第四狀態中任 一狀態時，輸出是「0」。 圖13顯示一事實表，用於說明邏輯電路Hu(圖u)執行的 3位元輸入轉換為2位元輸出。該邏輯電路Hu是一 3位元輸 入/2位元輸出邏輯電路，可實現如圖n所示的事實表。 如圖13所示，當感應放大器H5、H6和H7的輸出是「〇」、 「0」和「0」的時候，這意謂單元電流位準是在對應到資 料「00」的第四狀態卜在這情況中，邏輯電路H13經由線 H14輸出「0」並經由線H15輸出「〇」。 當感應放大器H5、H6和H7的輸出是「1」、「〇」和「〇 的時候’這意謂單元電流位準是在對應到資料「〇1」的第 三狀態卜在這情況中，邏輯電路H13經由線Hi」4輸出 「0」並經由線H15輸出「1」。 當感應放大器H5、H6和H7的輸出是「i 、「 」、1」和「0」 的時候，這意謂單元電流位準是在對應到資料「1〇」的第 87062 -16- 1226069 二狀態中。在這情況中，邏輯電路H丨3經由線H丨4輸出 「1」並經由線H15輸出「〇」。 當感應放大器H5、H6和H7的輸出是「ι」、「ι」和「1」 的時候，這意謂單元電流位準是在對應到資料「u」的第 一狀態中。在這情況中，邏輯電路H13經由線H14輸出 「1」並經由線H15輸出「1」。 用於從可在一記憶體單元中儲存2位元資料的四層式記 憶體單元中讀取資料的讀取電路H1〇〇,包括三個感應放大 器。用於從可在一記憶體單元中儲存n位元資料的多層式記 憶體單元中讀取資料的讀取電路，理論上需要包括個感 應放大器。 透過平行感應系統，可藉由允許平行操作複數個感應放 大器（圖11範例中的H5至H7)，在一週期的感應操作中讀取n 位元資料。因此，平行感應系統對於增加資料讀取速度非 常有利。 但是，需要複數個感應放大器的平行感應系統，其缺點 為，例如會增加感應放大器佔用的晶片區域並增加瞬間消 耗的電流位準。 由於感應放大器H5至H7會接收不同位準的參考電流，所 以電流負載電路H1至H4具有相同的特性但是感應放大器 H5至H7具有不同的操作點。因此，在讀取電路Η1〇〇的情況 下，包括感應放大器Η5至Η7的大範圍單元電流位準，必須 取得一致的操作極限。這使得要放大感應放大器Η5至117的 每一操作點之絕對操作極限變得很困難。 87062 -17- 1226069 以下，將描述在分時感應系統和平行感應系統中的讀取 電路的操作極限。在下列說明中，「感應電壓轉換效率」一 巧被疋義為感應電壓差/單元電流差的絕對值，即是感應電 壓差與單元電流差的比。感應電壓差表示感應電壓和參考 電壓 < 間的差距。單元電流差表示單元電流位準和參考電 泥位準之間的差距。感應電壓表示感應線的電位，而參考 私壓表不參考線的電位。當感應電壓轉換效率較大的時候 ，碩取電路的操作極限也較大。即使當單元電流差相同時 ,一較大的感應電壓差（也就是說，比較高的感應電壓轉換 效率）將導致一較大的操作極限。一較大的操作極限有利於 縮短讀取時間。 以下將根據電流負載電路的負載特性顯示單元電流和感 應電壓之間的關係，來描述操作極限和感應電壓轉換效率。 圖14A顯示使用一電阻當作一般電流負載的讀取電路 200 〇 在圖14A中顯示的讀取電路2〇〇中，電流負載電路L1〇使用 电阻L1當作一電流負載’而電流負載電路L20使用電阻L2 當作一電流負載。 當產生流過記憶體單元L5的單元電流時，會根據所產生 的單元電流位準，降低感應線L3的電位。 同樣地’當產生流過參考單元L6的參考電流時，會根據 所產生的參考電流位準，降低參考線L4的電位。 圖14B是一統計圖表，說明讀取電路200中的單元電流和 感應電壓之間的關係。在圖14B中，曲線梯度絕對值表示感 87062 •18- 1226069 應電壓轉換效率。 由於電阻L1和L2被當作讀取電路200的電流負載電路L10 和L20的電流負載，因此表示感應電壓和單元電流之間關係 的曲線是線性的。 在具有線性負載特性的讀取電路200中，感應電壓轉換效 率在整個單元電流位準的區域上是一致的（常數）。 在平行感應系統中，感應操作需要在複數個操作點處執 行。因此，較好使用如圖14B所示具有線性負載特性的讀取 電路，以便每一操作點都取得一致的操作極限。但是，這 類讀取電路具有的感應電壓轉換效率比具有非線性負載特 性（如下所述）的讀取電路要低，因此不適合用於單元電流位 準具有較小差異的多層式記憶體單元。 假使用於一週期感應操作的操作點數與分時感應系統一 樣為有限的，則可以使用具有非線性負載特性、且由於該 特性在操作點附近的感應電壓轉換效率比其餘地方要高的 讀取電路。 圖15A顯示一讀取電路300，當作具有非線性負載特性的 電流負載電路的範例。在讀取電路300中，PMOS電晶體係 彼此電流鏡射連接。 在圖15A中顯示的讀取電路300中，電流負載電路K10使 用PMOS電阻K1當作一電流負載，而電流負載電路K20使用 PMOS電阻K2當作一電流負載。PMOS電晶體K2的一汲極和 一閘極彼此相連，而且PMOS電晶體K1的一閘極係經由參考 線K4連接至PMOS電晶體K2的一閘極。 87062 -19- 1226069 田產生流過參考單元R6的單元電流時，會根據所產生的 參考電流位準，降低參考線K4的電位。同樣地，當產生流 過記憶體單元Κ5的單元電流時，會根據所產生的單元電流 位準，降低感應線Κ3的電位。 圖15Β是-統計圖，說明讀取電路3〇〇中的單元電流和感 應電壓之間的關係。 由於PMOS電晶體Κ^Κ2係用來當作電流負載電路κι〇 和Κ20的電流負載，所以表示感應電壓和單元電流之間的關 係曲線係非線性的。 在具有非線性負載特性的讀取電路3〇〇中，在單元電流位 準與參考電流位準相等處的點附近的感應電壓轉換效率 (由圖15Β的曲線梯度的絕對值表示），會比在讀取電路2〇〇 (圖^和_中的感應電壓轉換效率要高。#感應電壓轉 換效率比較高的時候，即使單元電流差很小，讀取操作極 限仍會較大。因此，這類讀取電路適用於多層式記憶體單 元。但是，這類讀取電路除了參考電流位準以外，在單元 電流位準區域中具有較低的感應電壓轉換效率，因此不容 易在複數個操作點執行感應操作。 如上所述，當分時感應系統用於採用電流感應系統的多 層式記憶體單元時，較好使用具有非線性讀取負載特性的 β取電路’以放大操作點附近區域的操作極限。但是，每 —感應週期都需要有設定/保持時間用於鎖住感應放大器 的輪出，因此不容易增加讀取時間。 當使用平行感應系統的時候，必須在每一複數個操作點 87062 -20- 1226069 貫負上放大一致的操作極限。因此，很難放大一絕對操作 極限。因此，平行感應系統不適用於多層式記憶體單元。 【發明内容】 根據本發明的觀點，提供從複數個記憶體單元的一記憶 體單元讀取資料的讀取電路。該讀取電路包括複數個分區 感應電路，每一分區感應電路均透過複數個感應線中對應 的一感應線，連接至該一記憶體單元；以及一電流電壓轉 換電路，用於將流過每一該複數個感應線的電流，轉換為 代表每一該複數個感應線電位的感應電壓。每一該複數個 分區感應電路包括一電流負載電路，用於透過複數個感應 線中的對應感應線，提供電流至該一記憶體單元，以及一 感應放大器，用於感應對應的感應線的電位與複數個參考 線的對應參考線電位之間的電位差。包含在複數個分區感 應電路中至少一分區感應電路中的電流負載電路，具有一 電流供應能力，該能力不同於包含在複數個分區感應電路 中的另-分區感應電路中的電流負載電路的電流供應能力。 在本發明的一具體實施例中，電流電壓轉換電路包括一 單元電流分區區段，用於連接複數個感應線至該一記憶體 單元，或將前述兩者分隔開。 在本發明的一具體實施例中，該讀取電路另包括一第一 參考電路，用於將代表複數個參考線中一參考線電位的一 第一類型參考電壓施加到對應到複數個感應放大器 中的該 一參考線的一感應放大器。 在本發明的一具體實施例中，每一該複數個電流負載電 87062 -21· 1226069 路的電流供應能力，均由代表複數個參考線 ^ τ對應的一參 亏、，泉電位的一第一類型參考電壓所控制。 在本發明的-具體實施例中，每一該複數個電流負載電 路包括一 PMOS電晶體，其具有透過該複數個參考線中對應 的一參考線施加參考電壓的一閘極。 〜 在本發明的一具體實施例中，讀取電路另包括一第二參 考電路，用於施加-第二類型參考電壓，以控制每=複 數個電流負載電路的電流供應能力。 ~ 在本發明的-具體實施例中，每—複數個電流負載電路 包括-PMOS電晶體，具有連接至該第二參考電路的一閘 極。 在本發明的一具體實施例中，該讀取電路另包括一第一 ^考電路，用於將代表複數個參考線中—參考線電位的一 第一類型參考電壓施加到對應到複數個感應放大器中的該 參考線的一感應放大器；以及一第二參考電路，用於施 加-第二類型參考轉，以控制每—複數個電流負載電路 的電流供應能力。該第一參考電路係電連接至該第二參考 電路。 在本發明的一具體實施例中，該單元電流分區區段包括 複數個NMOS電晶體。每一複數個NM〇s電晶體包括一閘極 以及一源極連接至該閘極。 在本發明的一具體實施例中，每一複數個^^^〇§電晶體係 連接至複數個電流負載電路中對應的一電流負載電路。每 一複數個NMOS電晶體的電流供應能力，係根據連接至對應 87062 •22- 1226069 載電路的電流供應能力而有所不 的NMOS電晶體的電流負 同0 在本發明的一具體眘 貫施例中，當每一複數個NMOS電晶體 的電流供應能力較高睡，、击 、 争連接至該電流負載電路的電流供 4力日較低’而當每_複數個讀〇§電晶體的電流供應能 力較低時’連接至該電流負載電路的電流供應能力會較高。 在本發明的-具體實施財，複數個分區感應電路平行 操作。 在本發明的—具體實施例中，每-複數個記憶體單元係 一多層式記憶體單元。 在本發明的-具體實施例中，該第—參考電路包括複數 個參考电壓叹疋電路’其每一個都包括複數個電流負載電 路，該每個電路透過複數個子參考線中對應的一子參考線 連接至-參考TG件，以及一電流電壓轉換電路，用於將流 經複數個子參考線中-子參考線的電流，轉換為代表一子 參考線電位的-參考電壓。從複數個參考電壓設定電路中 的一參考電壓設定電路輸出的參考電壓，可控制包含在複 數個參考電壓設定電路中的另一參考電壓設定電路中的至 少—複數個電流負載電路的電流供應能力。 在本發明的-具體實施例中’該第二參考電路包括複數 個參考電壓設定電路，其每一個都包括複數個電流負載電 路，該每個電路透過複數個子參考線中對應的一子參考線 連接至-參考元#，以及-電流電壓轉換電&，用於將流 經複數個子參考線中一子參考線的電流，轉換為代表一子 87062 ^ 1226069 Γ=的一參考電壓。從第-參考電路輪出的參考電 =:控制包含在複數個參考電壓設^電 泰 壓設定電路中的至少一複數 々參考电 力。 ，、戰电路的電流供應能 根據本發明的觀點，提供一參考電路， 個記憶體單元的-記憶體單元讀取資料的—參考電壓7 2電路包括複數個參考電壓設定電路，其每一個都包括 複數個電流負載電路，該每個電路透過複數個子參考線中 對應的—子參考線連接至—參考元件，以及一電流電壓轉 換電路’用於將流經複數個子參考線中一子參考線的電流 ’轉換為代表一子參考線電位的-參考電壓。從複數個參 考電壓設定電路中的一參考電壓設定電路輸出的參考電壓 ’可控制包含在複數個參考電壓設定電路中的另一參考電 壓汉疋電路中的至少一複數個電流負載電路的電流供應能 力0 在本發明的-具體實施例中，每一複數個電流電壓轉換 电路包括一參考電流分區區段，用於連接複數個子參考線 到該參考元件，或將前述兩者分隔開。 在本發明的一具體實施例中，每一複數個參考電流分區 區#又包括複數個NMOS電晶體。每一複數個nm〇S電晶體包 括一閘極以及一源極連接至該閘極。 在本發明的一具體實施例中，每一複數個NMOS電晶體係 連接至複數個電流負載電路中對應的一電流負載電路。每 一複數個NMOS電晶體的電流供應能力，係根據連接至對應 87062 -24- 1226069 的nmos電晶體的電流負載電路的電流供應能力而有所不 同。 在本發明的具體實施例中，當每一複數個NMOS電晶體 的電流供應能力較高時，連接至該電流負載電路的電流供 應能力會較低；而當每一複數個1^]^[〇8電晶體的電流供應能 力較低時，連接至該電流負載電路的電流供應能力會較高。 在本發明的一具體實施例中，該參考元件具有實質上與 每一複數個記憶體單元相同的結構。 在本發明的一具體實施例中，每一複數個電流負載電路 包括一 PMOS電晶體。 在本發明的一具體實施例中，包含在複數個參考電壓設 定電路中的一參考電壓設定電路中的複數個電流負載電路 中的一電流負載電路的PMOS電晶體，係與包含在複數個參 考電壓設定電路中的另一參考電壓設定電路中的複數個電 泥負載電路中的一電流負載電路的一 PM〇s電晶體電流鏡 射連接。 根據本發明的觀點，提供一參考電路，用於產生從複數 個記憶體單元的一記憶體單元讀取資料的一參考電壓。該 參考電路包括一第一參考電路；以及一第二參考電路。該 弟一參考電路包括複數個參考電壓設定電路，其每一個都 包括複數個電流負載電路，該每個電路透過複數個子參考 線中對應的一子參考線連接至一參考元件，以及一電流電 壓轉換電路，用於將流經複數個子參考線中一子參考線的 電流’轉換為代表一子參考線電位的一參考電壓。從複數 87062 -25 - 1226069 個參考電壓設定電路中的一 口°纟考-壓设足電路輪出的參考 电，可控制包含在複數個參考電壓設定電路中的另一 考電壓設定電路中的至少一複數個電流負載電路的 應能力。該第二參考電路包括複數個參考電壓設定電路 其每-個都包括複數個電流負載電路，該每個電路透過複 數個子參考線中對應的_子參考線連接至_參考元件，以 及一電流電壓轉換電路，用於將流經複數個子參考線中一 子參考線的電流，轉換為代表一子參考線電位的一參考電 壓。從第-參考電路輸出的參考電壓，可控制包含在該； 二參考電路的複數個參考電壓設定電路中的一參考電壓設 定电路中的至-複數個電流負載電路的電流供應能力。 根據本發明的一觀點，一半導體記憶體裝置包括包含複 數個記憶體單元的一記憶體單元陣列；以及一讀取電路， 用於從複數個記憶體單元中的一記憶體單元讀取資料。該 讀取電路包括複數個分區感應電路，每一分區感應電路均 透過該複數個感應線中對應的一感應線，連接至該一記憶 體單元；以及一電流電壓轉換電路，用於將流過每一複數 個感應線的電流，轉換為代表每一複數個感應線電位的感 應電壓。每一複數個分區感應電路包括一電流負載電路， 用於透過複數個感應線中的對應感應線，提供電流至該一 記憶體單元’以及一感應放大器，用於感應對應的感應線 的電位與複數個參考線中對應的一參考線電位之間的電位 差。包含在複數個分區感應電路中至少一分區感應電路中 的電流負載電路，具有一電流供應能力，該能力不同於包 87062 -26- 1226069 含在複數個分區馬庥雷政击 中的另—分區感應電路中的電流 負载電路的電流供應能力。 电/此 一：本發明的一具體實施例中，每一複數個記憶體單元係 一夕層式記憶體單元。 一 根據本發明的—觀點，—半導體記憶體裝置包括包 數個記憶體單元的一記憶體單元陣列·，以及用於產生1參 考电壓的參考電路’用於從複數個記憶體單元中的一記 2體單元讀取資料。該參考電路包括複數個參考電塾設定 電路，其每-個都包括複數個電流負載電路，該每個電路 透過複數個子參考線中對應的-子參考線連接至-參考元 件，以及-電流電壓轉換電路，用於將流經複數個子參考 線中一子參考線的電流，轉換為代表一子參考線電位的一 2考電壓。從複數個參考電壓設定電路中的_參考電壓設 —电路輸出的參考電壓，可控制包含在複數個參考電壓設 定電路中的另一參考電壓設定電路中的至少一複數個電流 負載電路的電流供應能力。 根據本發明的讀取電路，動作如下所示。 _複數個分區感應電路經由複數個感應線供給複數個分區 單^流。複數個分區單元電流連結在一起形成流過一記 憶體单元的單元電流。流過該感應線的每一分區單元電流 係經由電流電壓轉換處理，以提供一代表該感應線電位的 感應電壓。感應，㈣電位和參考㈣電位之間的電位差， 係由每一複數個感應電路中的感應放大器感應。因此，一 感應操作可以在複數個不同的操作點平行執行。 87062 -27- 1226069 分別供給分區單元電流給複數個感應線的複數個電流負 載電路’具有不同的電流供應能力。因此’電流供應能力 可以設定成使感應電壓轉換效率在感應放大器的操作點是 高的。因此，操作極限可以是大於其中負載特性在複數個 操作點實質上是一樣的傳統讀取電路中的操作極限。 例如，在其中電流負載電路包括一 PMOS電晶體的情況下 ，一參考電壓施加到PMOS電晶體的閘極，則該電流負載電 路的電流供應能力可以受到參考電壓控制。 在其中電流負載電路包括一如上的PMOS電晶體的情況 下，則可取得其中感應電壓只有在操作點處及其附近地方 才具有高轉換效率的非線性負載特性。 除了施加與該感應電壓相比較的參考電壓的一參考電路 之外，還可提供另一參考電路。在這情況下，該另一參考 電路施加一參考電壓到電流負載電路的PMOS電晶體的閘 極。因此，可以控制該電流供應能力。 在這情況下，兩個參考電路可以彼此電連接，使得參考 電路之一的參考電壓可以控制另一參考電路的電流供應能 力。 在本發明的一具體實施例中，該單元電流分區區段包括 複數個NMOS電晶體，在該每個電晶體中閘極與源極彼此相 連，以及該複數個NM0S電晶體根據連接至個別NMOS電晶 體的電流負載電路的電流供應能力具有不同的電流供應能 力。在這情況下，操作極限可以進一步地放大。1226069 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconducting prior art of a reading circuit, a circuit, and such reference circuits] A reference circuit, a body memory device, and a device including such a reading. In other words, a read circuit for reading data from a memory cell array including a plurality of memory cells provides a current to a memory cell having a memory therein, and compares a reference current to the memory cell. Current (unit u) 'in order to determine whether the level of the unit current is higher or lower than the reference current levels. Therefore, to read the data in the memory unit:. This type of system for reading data is called a "current sensing system". For example, referring to FIG. 9B, it is described as follows, reading data from a two-level memory cell that can store one bit in a memory cell. The unit current level is preset to be higher than the reference current level in the first state (corresponding to the data "1"), and the unit current level is lower than the reference current level (corresponding to the data "0") in the second state ). The reference current level is set to an intermediate level between the first state and the second state. Then, the cell current level of the memory cell is compared with the reference current level, so that the 1-bit data stored in the memory cell can be read. In fact, the cell current and the reference current must accept current-voltage conversion, and the potential of the induction line through which the cell current flows is compared with the potential of the reference line through which the reference current flows. In addition to this two-layer memory cell, a multi-layer memory cell that can store 2 bits or more of data in one memory cell has recently been studied in order to increase the storage capacity and / or reduce the production cost of semiconductor wafers. 87062 1226069 In this patent specification, the term "multi-layer memory unit" means three or more layers of memory unit, that is, a memory that can store data of 1.5 bits or more in a memory unit unit. For example, referring to FIG. 9A, it is described as follows, reading data from a four-level memory unit that can store 2-bit data in one memory unit. The four states of the single current are preset. More specifically, the first state, the third state, and the fourth state are set in the order of the cell current levels. The unit current level is highest in the first state and lowest in the fourth state. In the k examples, the first state corresponds to the data "丨 丨", the second state corresponds to the data "10", the third state corresponds to the data "01", and the fourth state corresponds to the data "00". The second and subsequent reference levels are set between the four states of the unit current. More specifically, a first reference current level B is set between the first state (corresponding to the data "U") and the second state (corresponding to the data "1〇"), a second reference The current level is "set between the second state (corresponding to J ^ material 10") and the second state (corresponding to the data "01"), and a third reference current level is set to the third state (Corresponds to the data "01") and the fourth state (corresponds to the data "00"). The reference current level set in this way is compared with the unit current level in the memory unit, so 2 data can be read based on the unit current level. In order to read from a general multi-level memory unit that can store this metadata in a -memory unit, it is necessary to set the current of the unit to 2 87062 1226069 states, and set a reference current level. It can be understood from Figs. 9A and ， that one ^ ^ and 3 'must obtain a sufficient current level between the early 7C current level of the multi-layer memory unit and the reference m, m, and c criteria. Obtained in f + VL, Xiaodou early, it is more difficult. In each type of case, the difference between the private level between the two Mm%% slave standards and the reference current level is quite small. Gu Yi achieved a sufficiently large operating limit, especially in the snatch circuit. In a multi-level memory cell, in order to obtain the data stored in the memory, it is necessary to set the unit's snow level, early voltage level, and many types of reference current levels. compared to. For example, Δ τ i 4 _ In order to continue to acquire the data of 2 bits, the cell current level of the memory cell 7C needs to be compared with the three reference current levels. As a result, the reading time is unexpectedly extended. To solve these problems, a plurality of systems for reading data from a multi-memory unit have been proposed. —This type of system is — time-sharing system. The unit current level in the memory unit will be compared with another reference current level once, and according to the comparison result, the unit current level will be compared. Compared with the other-reference current level, the n current level is compared ^ time ^ sequentially. The other system is a parallel induction system, by which the unit current level is compared with a plurality of reference current levels at a time. As an example of a time-sharing sensing system, the operation of reading data from a multi-level memory unit (FIG. 9A) that can store 2-bits in a memory unit will be described with reference to FIG. 10. Fig. 10 is a circuit diagram of a conventional reading circuit J100 for reading data from a memory unit of a time-sharing sensing system. 87062 -9- 1226069 In figure Η), the read circuit mG only reads data from the _memory unit 2 This is only shown H 'and the read circuit ⑽ can select the memory from one selected from a plurality of memory units Body unit to read data. Read circuit; 1GG includes a current load circuit J1 that applies a voltage to a drain of the selected unit J7 from which data is to be read to obtain a read current (cell current, and a current load for obtaining a reference current). Circuit M. An induction line J9 is provided for connecting the selected unit; the drain of 7 is connected to the current load circuit η, and a reference line m is provided for connecting the current load circuit J2 to the selection circuit J6. 豸 Select 6; the reference current is generally connected to one of the resource J80 to the current load circuit J2. The induction line 9 and the reference line are connected to the input area of the sense amplifier J3. The sense amplifier J3 is sensed in the sense line. The potential difference between the potential of J9 and the reference line and expands the potential difference. An output section of the sense amplifier J3 is connected to a first data latch circuit for locking the output from the sense amplifier J3 during the first sensing period. J4, and is connected to a second data latch circuit for locking the output from the sense amplifier J3 during the second sensing period, the second sensing period is located in the first sensing period The first data latch circuit J4 is connected to the selection circuit via line J111: 6. The selection circuit J6 selects one of the resources j80 based on the reference current J82 from the output of the first data latch circuit J4, and selects the selected resource. Connected to the reference line J10. The reading circuit j 丨 〇〇 of the time-sharing induction system with the above structure reads data from the selected unit J7 in the following manner. In the following description, the selection circuit 87062 • 10-1226069 J6 will refer to The line ji〇 is connected to the resource J8 in the initial state. First, an appropriate voltage is applied to the gate and non-pole of the selected unit J7, thereby generating a unit current flowing through the selected unit J7. Next, according to the generated The unit current reduces the potential of the sense line J9. Similarly, a reference current flowing from the resource J80 selected by the selection circuit J6 is generated. The potential of the reference line j10 is reduced according to the reference current. Then, the sense amplifier J3 senses the sense line The potential difference between the potential of J9 and the potential of the reference line J10 and expands the potential difference. When the level of the unit current is lower than the level of the reference current, the sense amplifier J3 outputs "0" is output. When the level of the unit current is higher than the reference current level, the sense amplifier J3 outputs "1". The output from the sense amplifier J3 during the first sensing period is locked by the first data latch circuit J4. During an induction period, the reference current resource J80 selected by the selection circuit% is used to obtain the three reference current levels between the second state (Fig. 9A) (corresponding to the data "1〇") and the third state (corresponding to To the data level "〇1"). Generally speaking, if the resource is the money, then the memory cell whose county constant voltage is tightly adjusted has the same structure and the same characteristics to obtain an appropriate reference current. Reference early 70 Next 'based on the output from the inductive amplifier during the first induction cycle, the output is locked by the -data flash lock, the selection circuit ⑽ the reference current resource is switched from J80 to 81 or J82. When the first data flash lock circuit_holds the data "0" (that is, when the unit 87062 • 11 · 1226069 current level reference to switch to two. When the first data phase lock circuit J4 locks "the current resource is said When the unit current level is higher than the reference ^ Λ 丨 "(that is, the stream resource is switched to J82. ㈣ level is on time), the reference power resource is used to obtain the three states (Figure 9A) (corresponding to the resource Section "〇1 / quasi (the third" 00 Mm a ") and the fourth state (corresponding to the data" 〇〇 ")" Between-the reference current level j Beco ^ ^ ^ / si "Beiyuan J82 It is used to obtain a reference current level "L" in the first state (Figure 9A) (corresponding to the asset department month department 10 "). Then, in the second induction cycle, ^ ^. L In the same way as the first induction period, the induction operation is performed in the same way. ^ F and the data lock circuit J 5 locks the output from the induction amplifier IU3 in the second induction period. In this way, it can be read and stored in The 2 elements in the unit. The above description is about four layers that can store 2-bit data in the -memory unit. C memory unit. The time-sharing sensing system can also be used for a memory unit that can store bits in a memory unit. In this case, it can only perform n sensing operations to read n-bit data By using a time-sharing induction system, only one sense amplifier can be used to read multiple bits of data. Therefore, the chip area occupied by the sense amplifier, the current level consumed instantly, etc. can be reduced. Due to the current load The circuit constants and other parameters of circuits J1 and J2 are switched with each other, so it is easy to achieve a larger operating limit during each period of induction operation. But the 'time-sharing induction system not only requires 87062 during each period of induction operation- 12- 1226069 To set / hold the time for the data to hold the circuit; 4 and 5 lock the output from the sense amplifier J3, and it is necessary to switch the time between sensing cycles. This is difficult to perform data reading at high speed. Next 'The parallel money system unit will be described, by which the current level of the unit can be compared with a plurality of reference current levels at a time. As an example of a parallel induction system The operation of reading data from a multi-level memory unit (Figure 9A) that can store 2-bits in a memory unit will be described with reference to Figure 11. Figure 11 is reading data from the memory unit of a parallel sensing system A circuit diagram of the conventional read circuit H100. In FIG. 11, the read circuit H100 reads data from only one memory cell. This is only an example, and the read circuit H100 can be selected from a plurality of memory cells. One of the memory cells is selected to read data. The reading circuit H100 includes a current load circuit hi that applies a voltage to a drain of the selected cell H8 from which data is to be read, and applies a voltage to the reference current resources H80 to H82. Current load circuits H2 to H4 to obtain reference current levels respectively. The current load circuits H1 to H4 have the same characteristics. An induction line H9 is provided for connecting the selected unit H8w drain electrode to the cement load circuit H1, and a reference line H10 is used for connecting the resource H80 to the earth current load circuit H2. A reference line Η11 is provided for connecting the resource H8 1 to the current load circuit Η3 'and a reference line Η12 is used for connecting the resource Η82 to the current load circuit Η4. The sense line Η9 and the reference line Η10 are connected to the input section of a sense amplifier Η5, respectively. The sense amplifier Η5 senses the potential difference between the potential of the sense line Η9 and the reference line 8706: -13-1226069 HI0 potential and enlarges the potential difference. The sense line Η9 and the reference line HI1 are connected to the input section of a sense amplifier Η6, respectively. The sense amplifier Η6 senses a potential difference between the potential of the sense line Η9 and the potential of the reference line Η11 and enlarges the potential difference. The sense line Η9 and the reference line Η12 are connected to the input section of a sense amplifier Η7, respectively. The sense amplifier Η7 senses a potential difference between the potential of the sense line Η9 and the potential of the reference line Η12 and enlarges the potential difference. Logic circuit Η13 is connected to an output section of each of sense amplifiers Η5 to Η7 'and the 2-bit data is read from an output section of logic circuit Η13 via lines hi4 and Η15. The reading circuit Η100 of the parallel induction system having the above structure reads data from the selected unit Η8 in the following manner. First, an appropriate voltage is applied to the gate and drain of the selected cell to generate a cell current flowing through the selected cell H8. Next, the potential of the induction line H9 is lowered in accordance with the generated cell current '. Similarly, a reference current flowing from the resource H80 is generated. The potential of the reference line mo is lowered according to the reference current '. When the reference current flowing from the resource server is generated, the potential of the reference line Hu is reduced according to the generated reference current. When a reference current flows from the resource H82, the potential of the reference line H12 is lowered according to the generated reference current. For the reference current, the G system is required to obtain the third state (Figure 9A) (corresponding to the data "01") and the fourth state (corresponding to the "G.") among the three financial test current levels. _ Reference current level "H". Reference 1 of the reference current is used to obtain a reference current level between the second state (Figure 9AX corresponds to the data "10") and the two states 87062 • 14 · 1226069 (corresponds to the data "〇1") Μ ". The reference current resource Η82 is used to obtain a reference current level "L" between the first state (Fig. 9A) (corresponding to the data "11") and the second state (corresponding to the data "1"). Generally speaking, if the resources Η80 to Η82 are used, the reference unit with a limited voltage is closely adjusted. The reference unit with the same structure and the same characteristics is used to obtain an appropriate reference current. Each of the sense amplifiers H5 to H7 senses a potential difference between the potential of the induction line H9 and the potential of the reference lines H10 to H12 in parallel and enlarges the potential difference. Therefore, the 3-bit data is output from the sense amplifier 115 to] 9 [7 to the logic circuit H13. The 3-bit data output from the sense amplifiers H5 to H7 is converted by logic circuit Ή13 into the 2-bit data that is read from time to time. By referring to Figs. 12 and 13, a specific embodiment of the logic circuit 扪 3 (Fig. U) will be described. Figure 12 shows the relationship between the cell current level and the reference level that the memory cell can have and the outputs of the sense amplifiers H5 to H7 (Figure n). As described above, the reference current level of the resource H80 is set to the third state (the position 对 between the data "(H") 2 and the fourth state (corresponding to the data "⑼"). The reference for the resource H8 丨The current level is set to the level "M" between the second state (corresponding to the data "10") and the third state (corresponding to the data "01"). The reference current level of resource H82 is set to the first state (Corresponds to the data J) and the first state (corresponds to the data r 1 〇) level "B". In this example, when the cell current level is higher than the reference current level, 87062 -15- 1226069 Each sense amplifier H5 to H7 will output data "1" to logic circuit H13. When the unit current level is lower than the reference current level, each sense amplifier H5 to H7 will output data "0" to logic circuit m3. As shown in Fig. 12, when the unit current level is in any of the first to third states, the output of the sense amplifier H5 is "1", and when the unit current level is in the fourth state, the output is "〇" ”. When the unit current level is in the first and second states In either state, the output of the inductive amplifier is Γ 1 ". When the unit current level is in any of the third and fourth states, the output is" 0 ". When the unit current level is in the first In the state, the output of the sense amplifier H7 is "1", and when the unit current level is in any of the second to fourth states, the output is "0". Figure 13 shows a fact table for explaining the logic circuit The 3-bit input performed by Hu (picture u) is converted into a 2-bit output. The logic circuit Hu is a 3-bit input / 2-bit output logic circuit, which can implement the fact table shown in Figure n. Figure 13 As shown, when the outputs of the sense amplifiers H5, H6, and H7 are "0", "0", and "0", this means that the unit current level is in the fourth state corresponding to the data "00". In this case, the logic circuit H13 outputs "0" via line H14 and "0" via line H15. When the outputs of the sense amplifiers H5, H6, and H7 are "1", "0", and "0" this means a unit The current level is in the third state corresponding to the data "〇1". In this case, the logic circuit H13 Output "0" from line Hi "4 and" 1 "via line H15. When the outputs of the sense amplifiers H5, H6, and H7 are" i, "" 1, "" 1, "and" 0 ", this means the unit current bit It must be in the two states of 87062 -16-1226069 corresponding to the data "10". In this case, the logic circuit H 丨 3 outputs "1" via line H 丨 4 and outputs "〇" via line H15. When When the outputs of the sense amplifiers H5, H6, and H7 are "ι", "ι", and "1", this means that the unit current level is in the first state corresponding to the data "u". In this case, The logic circuit H13 outputs "1" via a line H14 and outputs "1" via a line H15. A reading circuit H100 for reading data from a four-layer memory unit capable of storing 2-bit data in a memory unit includes three inductive amplifiers. A reading circuit for reading data from a multi-layered memory cell capable of storing n-bit data in a memory cell theoretically needs to include a sense amplifier. Through the parallel induction system, n-bit data can be read in a period of induction operation by allowing a plurality of induction amplifiers to be operated in parallel (H5 to H7 in the example in Fig. 11). Therefore, the parallel sensing system is very beneficial for increasing the data reading speed. However, a parallel sensing system that requires a plurality of sense amplifiers has disadvantages such as increasing the chip area occupied by the sense amplifiers and increasing the level of instantaneous current consumption. Since the sense amplifiers H5 to H7 receive reference currents at different levels, the current load circuits H1 to H4 have the same characteristics but the sense amplifiers H5 to H7 have different operating points. Therefore, in the case of the read circuit Η100, a wide range of unit current levels including the sense amplifiers Η5 to Η7 must achieve consistent operating limits. This makes it difficult to amplify the absolute operating limit of each operating point of the sense amplifiers Η5 to 117. 87062 -17- 1226069 Hereinafter, the operating limits of the read circuit in the time-sharing sensing system and the parallel sensing system will be described. In the following description, "induction voltage conversion efficiency" is accidentally defined as the absolute value of the induced voltage difference / unit current difference, which is the ratio of the induced voltage difference to the unit current difference. Induced voltage difference indicates induced voltage and reference voltage < gap. The unit current difference represents the difference between the unit current level and the reference level. The induced voltage indicates the potential of the sensing line, and the reference voltage meter does not refer to the potential of the line. When the induced voltage conversion efficiency is large, the operating limit of the master circuit is also large. Even when the cell current difference is the same, a larger induced voltage difference (that is, a higher induced voltage conversion efficiency) will result in a larger operating limit. A larger operating limit is beneficial for shortening the reading time. The operation limit and induced voltage conversion efficiency will be described below based on the relationship between the unit current and the induced voltage according to the load characteristics of the current load circuit. FIG. 14A shows a reading circuit 200 using a resistor as a general current load. In the reading circuit 200 shown in FIG. 14A, the current load circuit L10 uses the resistor L1 as a current load and the current load circuit L20. Use resistor L2 as a current load. When a cell current flowing through the memory cell L5 is generated, the potential of the sensing line L3 is lowered according to the level of the generated cell current. Similarly, when a reference current flowing through the reference cell L6 is generated, the potential of the reference line L4 is lowered according to the generated reference current level. FIG. 14B is a statistical chart illustrating the relationship between the cell current and the induced voltage in the reading circuit 200. FIG. In Figure 14B, the absolute value of the curve gradient indicates the 87062 • 18-1226069 voltage conversion efficiency. Since the resistors L1 and L2 are used as the current loads of the current load circuits L10 and L20 of the read circuit 200, the curve representing the relationship between the induced voltage and the cell current is linear. In the read circuit 200 having a linear load characteristic, the induced voltage conversion efficiency is uniform (constant) over the entire area of the cell current level. In parallel sensing systems, sensing operations need to be performed at multiple operating points. Therefore, it is preferable to use a read circuit having a linear load characteristic as shown in FIG. 14B, so that a uniform operating limit is obtained at each operating point. However, this type of read circuit has a lower induced voltage conversion efficiency than a read circuit with a non-linear load characteristic (described below), so it is not suitable for use in multi-level memory cells with small differences in cell current levels. If the number of operating points used in a period of induction operation is the same as that of the time-sharing induction system, you can use a non-linear load characteristic, and because of this characteristic, the conversion efficiency of the induced voltage near the operating point is higher than that of other places. Take the circuit. Fig. 15A shows a reading circuit 300 as an example of a current load circuit having a non-linear load characteristic. In the reading circuit 300, the PMOS transistor systems are galvanically connected to each other. In the reading circuit 300 shown in Fig. 15A, the current load circuit K10 uses the PMOS resistor K1 as a current load, and the current load circuit K20 uses the PMOS resistor K2 as a current load. A drain and a gate of the PMOS transistor K2 are connected to each other, and a gate of the PMOS transistor K1 is connected to a gate of the PMOS transistor K2 via a reference line K4. 87062 -19- 1226069 When the field current flowing through the reference cell R6 is generated, the potential of the reference line K4 will be lowered according to the level of the reference current generated. Similarly, when a cell current flowing through the memory cell K5 is generated, the potential of the sensing line K3 is lowered according to the level of the generated cell current. Fig. 15B is a statistical diagram illustrating the relationship between the cell current and the induced voltage in the read circuit 300. Since the PMOS transistor K ^ K2 is used as the current load of the current load circuits κι〇 and Κ20, the relationship curve between the induced voltage and the cell current is nonlinear. In a reading circuit 300 having a non-linear load characteristic, the induced voltage conversion efficiency (represented by the absolute value of the curve gradient of FIG. 15B) near the point where the cell current level is equal to the reference current level is smaller than In the reading circuit 2000 (Figures ^ and _, the induced voltage conversion efficiency is higher. # When the induced voltage conversion efficiency is relatively high, even if the cell current difference is small, the read operation limit will still be large. Therefore, this Class-like read circuits are suitable for multi-layer memory cells. However, in addition to the reference current level, this type of read circuit has low induced voltage conversion efficiency in the cell current level region, so it is not easy to operate at multiple operating points. Perform a sensing operation. As described above, when a time-sharing sensing system is used in a multi-layer memory unit employing a current sensing system, it is better to use a β fetch circuit having a non-linear read load characteristic to amplify the operation near the operating point. Limit. However, every sensing period needs a set / hold time to lock the rotation of the sense amplifier, so it is not easy to increase the reading time. When used When using a parallel induction system, the operating limit must be enlarged at each of the multiple operating points 87062 -20-1226069. Therefore, it is difficult to enlarge an absolute operating limit. Therefore, the parallel induction system is not suitable for multi-layer memory [Summary of the Invention] According to the aspect of the present invention, a reading circuit for reading data from a memory unit of a plurality of memory units is provided. The reading circuit includes a plurality of partition induction circuits, and each partition induction circuit passes through A corresponding one of the plurality of inductive lines is connected to the memory unit; and a current-voltage conversion circuit for converting a current flowing through each of the plurality of inductive lines to represent each of the plurality of inductive lines. Induction voltage of line potential. Each of the plurality of partitioned induction circuits includes a current load circuit for supplying current to the memory unit through corresponding induction lines of the plurality of induction lines, and an induction amplifier for induction. Potential difference between the potential of the corresponding sensing line and the potential of the corresponding reference line of the plurality of reference lines. Included in the plurality The current load circuit in at least one of the partition induction circuits in the partition induction circuit has a current supply capability, which is different from the current supply capability of the current load circuit in another partition induction circuit included in the plurality of partition induction circuits. In a specific embodiment of the present invention, the current-voltage conversion circuit includes a unit current partition section for connecting a plurality of sensing lines to the memory unit or separating the foregoing two. In a specific aspect of the present invention, In an embodiment, the read circuit further includes a first reference circuit for applying a first type reference voltage representing a reference line potential among the plurality of reference lines to the one reference line corresponding to the plurality of sense amplifiers. In a specific embodiment of the present invention, the current supply capability of each of the plurality of current load circuits 87062-21 · 1226069 is represented by a reference loss corresponding to a plurality of reference lines ^ τ, A first type of reference voltage is controlled by the spring potential. In a specific embodiment of the present invention, each of the plurality of current load circuits includes a PMOS transistor having a gate that applies a reference voltage through a corresponding one of the plurality of reference lines. ~ In a specific embodiment of the present invention, the reading circuit further includes a second reference circuit for applying a second reference voltage to control the current supply capability of each of the plurality of current load circuits. ~ In a specific embodiment of the present invention, each of the plurality of current load circuits includes a -PMOS transistor having a gate connected to the second reference circuit. In a specific embodiment of the present invention, the reading circuit further includes a first reference circuit for applying a first type of reference voltage representing the reference line potential to the plurality of reference lines. An inductive amplifier of the reference line in the amplifier; and a second reference circuit for applying a second type of reference turn to control the current supply capability of each of the plurality of current load circuits. The first reference circuit is electrically connected to the second reference circuit. In a specific embodiment of the present invention, the unit current partition section includes a plurality of NMOS transistors. Each of the plurality of NMOS transistors includes a gate and a source connected to the gate. In a specific embodiment of the present invention, each of the plurality of ^^^ 〇§ transistor systems is connected to a corresponding one of the plurality of current load circuits. The current supply capability of each multiple NMOS transistor is based on the current supply capability of the corresponding 87062 • 22-1226069 load circuit. The current of the NMOS transistor is negatively the same as zero. For example, when the current supply capability of each of the plurality of NMOS transistors is high, the current supplied to the current load circuit for 4 power days is lower. When the current supply capability is low, the current supply capability of the circuit connected to the current load is higher. In the embodiment of the present invention, a plurality of partition induction circuits operate in parallel. In a specific embodiment of the present invention, each of the plurality of memory cells is a multi-layer memory cell. In a specific embodiment of the present invention, the first reference circuit includes a plurality of reference voltage sighing circuits, each of which includes a plurality of current load circuits, and each circuit passes a corresponding one of a plurality of sub-reference lines. The line is connected to the -reference TG device, and a current-voltage conversion circuit is used to convert the current flowing through the -reference line of the plurality of sub-reference lines into a -reference voltage representing the potential of the one-reference line. The reference voltage output from one reference voltage setting circuit in the plurality of reference voltage setting circuits can control the current supply capability of at least one of the plurality of current load circuits included in another reference voltage setting circuit included in the plurality of reference voltage setting circuits. . In a specific embodiment of the present invention, the second reference circuit includes a plurality of reference voltage setting circuits, each of which includes a plurality of current load circuits, and each circuit passes a corresponding one of the plurality of sub-reference lines. Connected to-reference element #, and-current-voltage conversion circuit & is used to convert a current flowing through a sub-reference line among a plurality of sub-reference lines into a reference voltage representing a sub-87062 ^ 1226069 Γ =. The reference power output from the -th reference circuit =: controls at least one of the reference voltage setting circuits included in the reference voltage setting circuit 设 reference power. According to the viewpoint of the present invention, the current supply of the war circuit can provide a reference circuit. The memory unit-the memory unit reads the data-the reference voltage 72. The circuit includes a plurality of reference voltage setting circuits, each of which is It includes a plurality of current load circuits, each of which is connected to a reference component through a corresponding one of the plurality of sub-reference lines, and a current-voltage conversion circuit for flowing through a sub-reference line in the plurality of sub-reference lines. The current 'is converted into a -reference voltage representing the potential of a sub-reference line. A reference voltage 'output from a reference voltage setting circuit in the plurality of reference voltage setting circuits may control current supply of at least one current load circuit in another reference voltage setting circuit included in the plurality of reference voltage setting circuits. Ability 0 In the specific embodiment of the present invention, each of the plurality of current-voltage conversion circuits includes a reference current partition section for connecting a plurality of sub-reference lines to the reference element, or separating the foregoing two. In a specific embodiment of the present invention, each of the plurality of reference current partition regions # further includes a plurality of NMOS transistors. Each of the plurality of nmOS transistors includes a gate and a source connected to the gate. In a specific embodiment of the present invention, each of the plurality of NMOS transistor systems is connected to a corresponding one of the plurality of current load circuits. The current supply capability of each NMOS transistor varies according to the current supply capability of the current load circuit connected to the corresponding MOS transistor of 87062 -24-1226069. In a specific embodiment of the present invention, when the current supply capability of each of the plurality of NMOS transistors is high, the current supply capability of the current load circuit connected to the NMOS transistor is low; and when each of the plurality of NMOS transistors is 1 ^] ^ [ 〇 When the current supply capability of the transistor is low, the current supply capability of the current load circuit will be higher. In a specific embodiment of the invention, the reference element has substantially the same structure as each of the plurality of memory cells. In a specific embodiment of the present invention, each of the plurality of current load circuits includes a PMOS transistor. In a specific embodiment of the present invention, a PMOS transistor of a current load circuit among a plurality of current load circuits included in a reference voltage setting circuit of a plurality of reference voltage setting circuits is related to a PMOS transistor included in the plurality of references. A PMOS transistor current mirror connection of a current load circuit in a plurality of cement load circuits in another reference voltage setting circuit in the voltage setting circuit. According to an aspect of the present invention, a reference circuit is provided for generating a reference voltage for reading data from a memory cell of a plurality of memory cells. The reference circuit includes a first reference circuit; and a second reference circuit. The reference circuit includes a plurality of reference voltage setting circuits, each of which includes a plurality of current load circuits, and each circuit is connected to a reference element through a corresponding one of the plurality of sub-reference lines and a current-voltage The conversion circuit is configured to convert a current 'flowing through a sub-reference line among the plurality of sub-reference lines into a reference voltage representing a potential of the sub-reference line. From one bit of the plurality of 87062 -25 to 1226069 reference voltage setting circuits, the test-voltage reference circuit can control at least one of the other test voltage setting circuits included in the plurality of reference voltage setting circuits. The capacity of a plurality of current load circuits. The second reference circuit includes a plurality of reference voltage setting circuits, each of which includes a plurality of current load circuits, and each circuit is connected to a _ reference element through a corresponding _sub-reference line of the plurality of sub-reference lines, and a current voltage The conversion circuit is configured to convert a current flowing through one of the plurality of sub-reference lines into a reference voltage representing a potential of the one-reference line. The reference voltage output from the -th reference circuit can control the current supply capability of the-to the plurality of current load circuits included in a reference voltage setting circuit among the plurality of reference voltage setting circuits of the two reference circuits. According to an aspect of the present invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells; and a read circuit for reading data from a memory cell of the plurality of memory cells. The reading circuit includes a plurality of partition induction circuits, and each partition induction circuit is connected to the memory unit through a corresponding induction line of the plurality of induction lines; and a current-voltage conversion circuit is used to pass the current through The current of each of the plurality of sensing lines is converted into an induced voltage representing the potential of each of the plurality of sensing lines. Each of the plurality of partitioned sensing circuits includes a current load circuit for supplying current to the memory unit through corresponding sensing lines of the plurality of sensing lines and a sensing amplifier for sensing the potentials of the corresponding sensing lines and The potential difference between the corresponding reference line potentials in the plurality of reference lines. The current load circuit included in at least one of the partition induction circuits of the plurality of partition induction circuits has a current supply capability, which is different from the package 87062 -26-1226069 contained in the plurality of partition induction circuits. Current supply capability of a current load circuit in an induction circuit. Electricity / This: In a specific embodiment of the present invention, each of the plurality of memory cells is a layered memory cell. According to an aspect of the present invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells, and a reference circuit for generating a reference voltage 'for one from a plurality of memory cells. Record the data of 2 body units. The reference circuit includes a plurality of reference voltage setting circuits, each of which includes a plurality of current load circuits, each of which is connected to a -reference element through a corresponding -sub-reference line of the plurality of sub-reference lines, and -current The conversion circuit is configured to convert a current flowing through one of the plurality of sub-reference lines into a 2 test voltage representing the potential of the one-reference line. The reference voltage output from the reference voltage setting circuit in the plurality of reference voltage setting circuits can control the current supply of at least one current load circuit in another reference voltage setting circuit included in the plurality of reference voltage setting circuits. ability. The reading circuit according to the present invention operates as follows. _ A plurality of partition induction circuits supply a plurality of partition single streams via a plurality of induction lines. A plurality of partitioned unit currents are connected together to form a unit current flowing through a memory unit. The current flowing through each partition unit of the induction line is processed by current-voltage conversion to provide an induced voltage representing the potential of the induction line. Induction, the potential difference between the ㈣ potential and the reference ㈣ potential is sensed by a sense amplifier in each of the plurality of sense circuits. Therefore, a sensing operation can be performed in parallel at a plurality of different operation points. 87062 -27- 1226069 Each of the plurality of current load circuits ′ which supply the current of the division unit to the plurality of induction lines has different current supply capabilities. Therefore, the 'current supply capability can be set so that the conversion efficiency of the induced voltage is high at the operating point of the sense amplifier. Therefore, the operation limit may be greater than the operation limit in a conventional reading circuit in which the load characteristics are substantially the same at a plurality of operation points. For example, in the case where the current load circuit includes a PMOS transistor and a reference voltage is applied to the gate of the PMOS transistor, the current supply capability of the current load circuit can be controlled by the reference voltage. In the case where the current load circuit includes the PMOS transistor as above, a non-linear load characteristic in which the induced voltage has high conversion efficiency only at the operating point and in the vicinity thereof can be obtained. In addition to a reference circuit that applies a reference voltage compared to the induced voltage, another reference circuit may be provided. In this case, the other reference circuit applies a reference voltage to the gate of the PMOS transistor of the current load circuit. Therefore, the current supply capability can be controlled. In this case, the two reference circuits can be electrically connected to each other so that the reference voltage of one of the reference circuits can control the current supply capability of the other reference circuit. In a specific embodiment of the present invention, the unit current partition section includes a plurality of NMOS transistors, in each of which the gate and source are connected to each other, and the plurality of NMOS transistors are connected to individual NMOS according to The current supply capability of the current load circuit of the transistor has different current supply capabilities. In this case, the operating limit can be further enlarged.

例如，包含在單元電流分區區段中的每一複數個NMOS 87062 -28 - 1226069 電晶體，係連接至該對應的電流負載電路。電流負載電路 的電流供應能力和NMOS電晶體的電流供應能力係設定成 如下所示《當電流負載電路的電流供應能力較高時，NM〇s 電晶體的電流供應能力較低；以及當電流負載電路的電流 供應能力較低時，NMOS電晶體的電流供應能力較高。因 =，即使在-單元電流位準是低的區域中，較大量的分區 單元電流仍可以提供給該分區感應電路，用以決定單元電 流位準係高於或低於被規定的參考電流位準。For example, each of the plurality of NMOS 87062 -28-1226069 transistors included in the cell current partition section is connected to the corresponding current load circuit. The current supply capability of the current load circuit and the current supply capability of the NMOS transistor are set as follows: "When the current supply capability of the current load circuit is high, the current supply capability of the NMOS transistor is low; and when the current load is When the current supply capability of the circuit is low, the current supply capability of the NMOS transistor is high. Because =, even in the area where the -unit current level is low, a large amount of zoned unit current can still be provided to the zone induction circuit to determine whether the unit current level is higher or lower than the specified reference current level quasi.

一根據本發明的參考電路，動作如下所示。 複數個電流負載電路經由複數個子參考線供應複數個； 區參考電流》複數個分區單元電流係連結在—起，以形力 流過-參考元件的-參考電流。連接至每—複數個子心 線的電流負載電路的電流供應能力，係受到從另一參考$ 壓-又疋电路的电流負載電路輸出的參考電壓所控制。因4 可以實現與包含在讀取電路中的電流負載電路具有實賀 上相同的非線性負載特性的參考電路。A reference circuit according to the present invention operates as follows. The plurality of current load circuits supply a plurality of through a plurality of sub-reference lines; the zone reference current >> the plurality of division unit currents are connected together and flow with a reference force through the -reference element. The current supply capability of the current load circuit connected to each of the plurality of sub-cores is controlled by a reference voltage output from the current load circuit of another reference voltage circuit. Because 4 can realize a reference circuit with the same non-linear load characteristics as the current load circuit included in the read circuit.

包含在讀取電路和參考電路中的電晶體，可具有相同^ 配：模式，因此可以容易地具有相同的電晶體特性。該讀 取电路和參考电路較不可能受到電晶體特性變化的影響。 :本發明的一具體實施例中，每一複數個電流負載電路 包括一 PMOS電晶體，品η —人上 t^^^ , 且匕口在一參考電壓設定電路中的 Μ負載電路巾的PMQSm可 壓設定電路中的電令备“ 、已。在另參考電 /,U、載*路中的PMOS電晶體電流鏡射 連接。由料類結構，電流負載電路㈣流供應能力可以 87062 •29- 1226069 電壓控制參考$壓设定電路中的電流負載電路輸出的參考 在本發明的另—呈髀音 路中的電嗉自恭泰 列中，包含在參考電壓設定電 感應電二=中裁？_電晶體，係與包含在分區 接。由於這類結構十體電流鏡射連 供應能力可以二電流負載電路的電流 出的參考電壓控制。I又疋电路中的電流負載電路輸 j參考電路供應的參考電壓，可連接至包含在參考電壓 路的電流負載電路中的p聰電晶體的閉極。電流負 載電路的電流供應能力也可以由這類結構㈣。 一適當的參考元件可以很容易地如下所示取得。使用且 :與該ί憶體單元相同結構的元件，並調整其相關的臨界 ，使得該元件具有與記憶體單元相同的特@。 因此’此處描述的本發明具有以τ好處··提供—讀取電 路和參考電路’用以放大多層式記憶體單元的讀取操作極 並；加多層式兄憶體單元的讀取速度，以及提供包括這 類讀取電路和這類參考電路的半導體記憶體裝置。 要…、身本技術之專業人士詳讀並瞭解下文中參考附圖 的詳細說明，將可明白本發明的這些及其它優點。 【實施方式】 接下來，本發明將藉由說明性範例並參考所附圖式來作 說明。 在下列範例中，將描述從當作半導體記憶體裝置範例的 87062 -30- 1226069 半：體記憶體裝置讀取資科的操作。本發明可以 1電喊應㈣讀取料的任何半導社悻體裝 置在且不限於非揮發性或揮發性半導體記憶體裝置： 電路下列^种’只描述讀取資料的操作。省略掉-窝入 切電路控制電路和_發性半導體記憶體 装置的其他元件。 (範例1) 圖1係根據本發明的第—範例之半導體記憶裝置15〇〇的 示意圖； 半導體記憶體裝置测包括包含—複數個記憶體單元的 ，一=體單元陣列15G，—讀取電路咖，用於從複數個記 隐to單兀乏一讀取資料，以及一參考電路11〇,用於產生讀 取資料的一參考電壓。 在圖1中，讀取電路1000顯示為只從一記憶體單元讀取資 料這疋示範，而且該Ί買取電路1 〇〇〇可從複數個記憶體 單元中的一選定記憶體單元9讀取資料。 如圖1所示，讀取電路1〇〇〇經由一位元線8，供應一單元 電流給複數個記憶體單元中選定的記憶體單元9，並藉由電 流电壓轉換’將流經記憶體單元9的單元電流位準轉換為一 感應電壓。然後，該讀取電路1〇〇〇比較一感應電壓和一參 考電壓，因此讀取儲存在記憶體單元9的資料。 讀取電路1000包括複數個分區感應電路20至2n和一電流 電壓轉換電路100。包含在讀取電路1000中的複數個分區感 應電路的數量為2或以上的任何整數。 87062 -31 - 1226069 分區感應電路2 0經由感應線5 0連接至電流電壓轉換電路 100。該分區感應電路20包括一電流負載電路3〇，用於供靡 一分區單元電流至該感應線50，以及一感應放大器4〇，用 於感應及擴大該感應線5 0的電位和參考線6 〇的電位之間的 電位差。 分區感應電路21經由感應線51連接至電流電壓轉換電路 100。該分區感應電路21包括一電流負載電路31，用於供應 一分區單元電流至該感應線51，以及一感應放大器41，用 於感應及擴大該感應線5 1的電位和參考線61的電位之間的 電位差。 圖1顯tf分區感應電路2n。這個參考數字中的字母「η」 表示一 1或以上的整數。圖1也顯示一電流負載電路311、一 感應放大器4η、一感應線5η、一參考線6η、和PMOS電晶體 7η。這些參考數字中的「η」也表示一 1或以上的整數。這 意謂讀取電路1000包括至少兩個分區感應電路、至少兩個 電流負載電路、至少兩個感應放大器、至少兩個感應線、 至少兩個參考線，和至少兩個PMOS電晶體。 在下列說明中，「η」是2或以上；也就是讀取電路1000包 括至少三個分區感應電路、至少三個電流負載電路、至少 三個感應放大器、至少三個感應線、至少三個參考線，和 至少三個PMOS電晶體。 在下列說明中，參考線60至611統稱為「參考線群組6」。 電流電壓轉換電路1〇〇將流過感應線50的分區感應電流 轉換為代表感應線50電位的一感應電壓，將流過感應線51 87062 -32- 1226069 的为區感應電流轉換為代表感應線5i電位的一感應電壓， 同樣地將流過感應線5η的分區感應電流轉換為代表感應線 5η電位的·一感應電壓。 根據本發明，一流過一記憶體單元的單元電流，由連結 在一起的複數個分區單元電流形成。根據本發明，單元電 流不是「分開的」，但是單元電流位準可以被認為是分為個 別流過複數個感應線的分區單元電流位準。 電流電壓轉換電路100包括一單元電流分區區段1，用於 透過位元線8將感應線50至5η連接至記憶體單元9或將兩者 分隔開’以及一反相器1 〇 1，用於控制單元電流分區區段1。 在這一範例中，單元電流分區區段i包括一 NM0S電晶體 10 ’具有一閘極以及一源極，經由反相器1〇1彼此相連，一 NMOS電晶體11具有一閘極和一源極，經由反相器丨〇丨彼此 相連’以及同樣地，一 NMOS電晶體1 η具有一閘極和一源極 ，經由反相器101彼此相連。 在這一範例中，電流負載電路30包括一 PMOS電晶體70 。PMOS電晶體70的一閘透過參考線60接收一參考電壓。該 參考線60的參考電壓控制該電流負載電路3〇的電流供應能 力。 電流負載電路31包括一 PMOS電晶體71。PMOS電晶體71 的一閘極透過參考線61接收一參考電壓。該參考線61的參 考電壓控制該電流負載電路3 1的電流供應能力。 同樣地，電流負載電路3n包括一 PMOS電晶體7n。PMOS 電晶體7n的一閘極透過參考線6n接收一參考電壓。該參考 87062 -33· 1226069 線6η的參考電壓控制該電流負載電路3η的電流供應能力。 在該讀取電路1000中，包含在分區感應電路20至2η中的 至少一個複數個電流負載電路30至3η，具有不同於另一分 區感應電路電流供應能力的電流供應能力。 該參考電路110透過分別對應到複數個分區感應電路20 至2η的參考線60至6η，施加一參考電壓到電流負載電路30 至3η的PMOS電晶體70至7η的閘極。 在上述說明中，參考電路110不包含在讀取電路1000中。 另一方面，讀取電路1000可包含參考電路110。 圖2是一電路圖，說明該讀取電路1000從一記憶體單元陣 列150的一部份讀取資料。 如圖2所示的記憶體單元陣列150，在一矩陣中包括複數 個記憶體單元CELL 11至CELL44。 記憶體單元陣列150個別列中的記憶體單元的閘極，係共 同連接至字線WL1至WL4。明確地說，字線WL1係連接至記 憶體單元CELL11至CELL14的閘極，而且字線WL2係連接至 記憶體單元CELL21至CELL24的閘極。字線WL3係連接至記 憶體單元CELL31至CELL34的閘極，而且字線WL4係連接至 記憶體單元CELL41至CELL44的閘極。 記憶體單元陣列150個別行中的記憶體單元的汲極，係共 同連接至位元線BL1至BL4。明確地說，位元線BL1係連接 至記憶體單元CELL11至CELL41的汲極，而且位元線BL2係 連接至記憶體單元€£1^12至€£1^42的汲極。位元線81^3係 連接至記憶體單元CELL13至CELL43的汲極，而且位元線 87062 -34- 1226069 BL4係連接至記憶體單元CELL14至CELL4W々汲極。 每行中兩個毗連記憶體單元的汲極係彼此相連，然後連 接至該位元線。例如，記憶體單元CELL11和CELL21的汲極 係相連，而且這些汲極係連接至位元線BL1。記憶體單元 CELL31和CELL41的汲極係相連，而且這些汲極係連接至位 元線BL1。 所提供的字線WL1至WL4以及位元線BL1至BL4係彼此成 垂直。 記憶體單元CELL 11至CELL44的源極係以每一區塊為基 礎共同連接至共同的源極線SRC。每個區塊包括複數個記 憶體單元。 每一行中的兩個毗連記憶體單元的源極係彼此相連。例 如，記憶體單元CELL21和CELL31的源極係相連，而且這些 源極係連接至源極線SRC。 複數個位元線BL1至BL4係經由一解碼器電路（未顯示）或 電流電壓轉換電路100(圖1)連接至例如分區感應電路20至 2n 〇 參考電路110(圖1)包括記憶體單元，當作參考單元，類似 記憶體單元陣列1 50中的記憶體單元。 回到圖1，將描述這一範例中讀取電路1000的操作。 在這一範例中，將描述從一如圖9 A所示可以儲存2位元資 料的多層式記憶體單元中讀取資料的電路結構。圖1參考數 字中的「η」被假設是2。因此，下列元件將描述為由下列 參考數字表示。NMOS電晶體In是12。分區感應電路2η是22 87062 -35 - 1226069 。電流負載電路3η是32。感應放大器4ϋ是42。感應線5η是 52。參考線6ιι是62。包含在該電流負載電路32中的pM〇s電 晶體7n是72 〇 從一可以儲存m位元資料加是2或以上的整數）的記憶體 單元中讀取資料時，η被設定成2m-l。 在下列說明中，感應線的電位將稱為「感應電壓」，而參 考線的電位則稱為「參考電壓」。 將先描述讀取電路1000從如圖9]3所示兩層式記憶體單元 執行讀取資料的操作之後，再描述從多層式記憶體單元讀 取資料的操作，以便於瞭解。 在下列說明中，參考線60至62具有相同位準的參考電壓 NMOS电日日體1〇至12具有相同的尺寸。pM〇s電晶體70至 72具有相同的尺寸。每個]^]^〇3電晶體1〇至12以及]?]^〇§電 晶體70至72的電流供應能力，主要由電晶體尺寸和閘極電 位決定。NMOS電晶體1〇至12具有相同的閘極電位，因此具 有相同的電流供應能力。PM〇s電晶體7〇至72具有相同的閘 極電位，因此具有相同的電流供應能力。換句話說，由於 參考、泉60至62具有相同的電位，因此pM〇s電晶體至具 有相同的電流供應能力。 當一適當的電壓施加到所選定的記憶體單元9的一閘極 的時候，t降低位元線8的電位，因此降低連接至位元線8 反相器ιοί輸入的電位。因此，從反相器1〇1的輸出電位會 增加。因此，包含在單元電流分區區段丨中的nm〇s電晶體 10至12變成有導電性。 87062 -36 - 1226069 當NMOS電晶體1〇至12有導電性時，感應線5〇至52的電位 會根據位元線8的電位降低。因此，分別包含在電流負載電 路30至32中的每一PM〇s電晶體7〇至72的源極和汲極之間 ，會產生足夠的電位差。 在這狀態中，一參考電壓施加到參考線6〇至62，且pM〇s 電晶體70至72變成有導電性。然後，位元線8經由感應線％ 至52和NMOS電晶體1〇至12充電。當增加位元線8的電位時 ’電位差在記憶體單元9的汲極和源極之間產生，因此一單 元電流流動。 為了要正確地執行感應操作，當單元電流位準等於參考 電流位準時，如以上參考圖9B所述，透過參考線6〇至62施 加至分區感應電路20至22的參考電壓係設定成感應線5〇至 52的感應電壓。 當位元線8被充電到所規定的電位時，可降低從包含在電 流電壓轉換電路1 〇〇中反相器1 〇 1的輸出電位，因此每個 NMOS電晶體10至12的電流供應能力會降低。當位元線8的 電位、流過記憶體單元9的單元電流位準、以及流過nm〇s 電晶體10至12的電流位準達到平衡狀態時，可使讀取電路 1000中的電位和電流位準變穩定。 由於參考線60至62具有相同的電位，NMOS電晶體1〇至12 具有相同的閘極電位和相同的汲極一源極電位。因此，相 同位準的汲極一源極電流可以流過NMOS電晶體1〇至12。因 此，流入每個NMOS電晶體1〇至12的電流位準係該單元電流 位準的1/3。此時，由於PMOS電晶體70至72，感應線50至52 87062 -37- 1226069 取得一相等的感應電壓。 感應線5〇至52的電位和參考線60至62的電位之間的電位 差’分別由感應放大器40至42感應及擴大。因此，讀取到 資料。如上所述，感應線50至52具有相同的電位。因此， 感應放大器40至42執行相同的操作並輸出相同的結果。因 此，當參考線60至62具有相同的電位時，從記憶體單元9讀 取「1」或「0」的1位元資料。 接下來，將描述讀取電路1000根據第一範例從多層式記 憶體單元讀取資料的操作。在下列說明中，一多層式記憶 體單元可以儲存2位元的資料，也就是說，四個值。 在這範例中，NM〇S電晶體10至12具有相同的電晶體尺 寸’如同兩層式記憶體單元的情況。pM〇s電晶體7〇至以 -有相同的電晶體尺寸。因此，NM〇s電晶體⑺至Η具有相 同的閘極電位’因此具有相同的電流供應能力。 為I要正確地執行讀取操作當單元電流位準等於每一 參考電流位準時’如電晶體尺寸等的電路常數和參考電壓 ’=定成使感應線5G至52的電位分別等於參考線6〇至62 A —(施加至參考線6()至62的參考電壓）。參考線⑼至62 =電=與從兩層式記憶體單元讀取資料的情況不同，係為 不相♦’且設定成如下所示。 考等9於資料「。。」和資料「°1」之間的參 ^ ^ ^ 」 A)時，施加到參考線60的參考電壓係 β又疋成♦於感輕50的感應電壓。 當單元電流位準等於資料「…和資料「Π)」之間的參 87062 -38· 1226069 考電流位準「M」（圖9A)時’施加到參考線61的參考電壓係 設定成等於感應線51的感應電壓。 同樣地，當單元電流位準等於資料「1〇」和資料「“」 之間的參考電流位準「L」（圖9A)時，施加到參考線62的^ 考电壓係$又疋成等於感應線5 2的感應電壓。 因此，參考線60至62的電位係分別設定成相當高、中等 和低。 當一適當的電壓施加到所選取的記憶體單元9的閘極時 ，會降低位元線8的電位。因此，會增加從包含在電流電壓 轉換電路100中的反相器101輸出的電位。因此，包含在單 兀電流分區區段1中的NMOS電晶體1〇至12變成有導電性。 然後，感應線50至52的電位會根據位元線8的電位而降低。 因此’为別包含在電流負載電路3〇至32中的每一 PMO S電晶 體70至72的源極和汲極之間，會產生足夠的電位差。 在這狀態中，一參考電壓施加到參考線6〇至62，且pM〇s 電晶體70至72變成有導電性。然後，位元線8經由感應線5〇 至52和NMOS電晶體10至12充電。當增加位元線8的電位時 ’电位差在$己憶體單元9的沒極和源極之間產生，因此一單 元電流流動。特別是，PMOS電晶體具有一特性，當施加到 相關閘極的參考電壓較高時，流過PM〇s電晶體的電流位準 會較低。 當位元線8被充電到所規定的電位時，可降低從包含在電 流電壓轉換電路100中反相器1 〇 1的輸出電位，因此每個 NMOS電晶體10至12的電流供應能力會降低。當位元線8的 87062 -39- 1226069 電位、流過記憶體單元9的單元電流位準、以及流過NM〇s 電晶體10至12的電流位準達到平衡狀態時，可使讀取電路 1000中的電位和電流位準變穩定。 當NMOS電晶體1〇至12在一飽和區域（_五極真空管區 域）操作時，NMOS電晶體10至12具有相同的閘極電位。因 此，NMOS電晶體10至12可以允許實質上相同位準的汲極— 源極電流流過，不會很明顯地依賴其相關的汲極—源極電 位。 由於參考線60至62具有不同的電位，因此pM〇s電晶體7〇 具有的電流供應能力與PMOS電晶體71和72的電流供應能 力不同。明確地說，參考線60的電位大於參考線61和62的 電位，因此PMOS電晶體70的電流供應能力低於pM〇s電晶 體71和72的電流供應能力。 因此，當NMOS電晶體1〇至12具有實質上一樣的電流供應 月b力時，感應線50的電位會低於感應線5丨和52的電位。 參考線61的電位高於參考線62的電位，因此pM〇s電晶體 71的電流供應能力低於PM0S電晶體72的電流供應能力。 因此，感應線51的電位低於感應線52的電位。 現在，將討論參考電壓和感應電壓之間的關係。如上所 述，當單元電流位準等於參考電流位準時，參考電壓會設 定成等於感應電壓。因此，當單元電流位準比參考電流位 準高的時候，會增加包含在單元電流分區區段i中的每一 NMOS电θ曰體1 〇至12的電流供應能力。同樣可觀察到，當單 元电流位準高於參考電流位準的時候，感應線的電位會因 87062 •40- 1226069 較大位準而降低，因此感應電壓變得低於參考電壓。 相反地，當單元電流位準低於參考電流的時候，感應電 壓會變得高於參考電壓。 分別由感應放大器40至42擴大感應線5〇至52的電位和參 考= 6^62的電位之間的電位差，來讀取資料。當感應線 的电位巧於對應的參考線的電位時，每一感應放大器仆至 42都會輸出「〇」，當感應線的電位低於對應的參 位時，則輸出「！」。 「列如，當記憶體單元9的單元電流位準係處於對應到資料 「〇〇」的第四狀態（圖9A)中的時候，單元電流位準係低於 三個參考電流中的任一個。因此，感應線5〇至”的電位分 別同於參考線6〇至62的電位。所以每—個感應放大器糾至 都輸出〇」。從感應放大器4〇至42輸出的3位元資料「〇〇〇 」係由實現圖13所示的事實表的邏輯電路（圖W《顯示）來 解碼。因此，讀取到2位元資料「00」。 同樣地，當記憶體單元9的單元電流位準係處於對應到資 料「10」的第：狀細9A)中的時候，單元電流㈣係言 於參考電流位準「H」和「M」，但是低於參考電流位: 「〜因此，感麟5〇和51的電位分別低於參考線6〇和^ 的電位。感應線52的電位高於參考線62的電位。因此咸 應放大器40至42輸出3位元的資料「UG」。3位元的資料二 11〇」由上述邏輯電路解碼。因此，讀取到2位 「10 ,。 种 01 當記憶體單元9的單元電流位準係處於對應到資料 87062 -41 - 1226069 的第三狀態（圖9A)中以及對應到資料「u」的第一狀態中 的時候，實質上以相同方式讀取資料。 如上所述，謂取電路1000可以藉由平行操作分區感應電 路20至2n由平行感應系統來讀取多層式資料。 由於電流負載電路30至3n分別包括？]^〇3電晶體7〇至711 ，因此分區感應電路20至2n的每一個都可以當做如圖15B所 示具有非線性特性的電路來操作。 圖3是一統計圖，說明如圖i所示讀取電路1〇〇〇中的感應 電壓和單元電流位準之間的關係。 特別是，當參考線的電位較高的時候，對應的感應電壓 係較低。理由是當參考線的電位係較高時，流過pM〇s電晶 體的電流位準會較低，因此感應線的電位會因較小的位準 而降低。 如圖3所示，讀取電路1〇〇〇具有非線性特性。因此，藉由 增加在單元電流位準等於每一參考電流位準點附近及該區 域中的感應電壓轉換效率，即可放大讀取操作極限。 為何讀取電路1000具有非線性特性，還在平行感應系統 中執行感應操作的原因係：藉由透過複數個感應線提供分 區單元電流給記憶體單元9 , 一個讀取電路1〇〇〇可具有複數 個操作點。 在上述說明中，流過感應線50的分區單元電流、流過感 應線51的分區單元電流、和流過感應線52的分區單元電流 ，在一位元線上連結在一起，因此形成一單元電流。本發 明並不爻限於此，本發明可適用於任意結構，藉由該結構 87062 -42· 1226069 流過複數個感應線的分區單元電流係連結在一起，且形成 流過一記憶體單元的單元電流。 如上所述，讀取電路1〇〇〇由平行感應系統執行感應操作 ’這有利於增加讀取速度，同時具有可實現適用多層式記 憶體單元較大操作極限的非線性特性。因此，根據第一範 例，提供能夠高速操作、且具有適用大的多層式記憶體單 元的大操作極限之讀取電路。 (範例2) 在第一範例中，並非描述參考電路的特定結構。在本發 明的第二範例中，將描述參考電路110的示範結構。 圖4顯示圖1的參考電路11〇的電路組態。 如圖4所示，參考電路11〇包括複數個參考電壓設定電路 uo-o至m-ο在第二範例中，包含在參考電路ιι〇中的參 考電壓設定電路的數量為2或以上的整數。 參考電壓設定電路110-0經由參考位元線8r〇提供參考電 流給狀的參考元件9善並將流過參考元件W的參考電 流轉換為參考電壓。 參考電壓設定電路110·由參考位元線8ri提供參考電 流給選定的參考元件9_r卜並將流過參考元件^的 流轉換為參考電壓。 「在圖4顯示的參考電路UG中，參考電壓設定電路110_n的 「n」表…或以上的整數。在下列說明中參考電路㈣ 括至少三個參考電壓狀電路：也就是說，「n」是2或以 87062 -43 - 1226069 參考電壓設定電路110-0至110-n的每一個包括一電流電 壓轉換電路和複數個電流負載電路。 參考電壓設定電路lio-o包括一電流電壓轉換電路1〇〇_r〇 和複數個電流負載電路30-r0至3n-r0。電流電壓轉換電路 l〇〇-rO將流過子參考線50_r0的一分區參考電流轉換為表示 子參考線50-r0電位的電壓，將流過子參考線51^〇的一分區 參考電流轉換為表示子參考線5 1 -r0電位的電壓，且同樣地 將流過子參考線5n-r0的一分區參考電流轉換為表示子參考 線5n-r0電位的電壓。 電流電壓轉換電路100·Γ0包括一參考電流分區區段Kr〇 ,用於經由參考位元線8-ΐΟ連接子參考線5〇^〇至5η-Γ〇到參 考單元9-rO或將兩者分隔開，以及一反相器1〇1^〇,用於控 制參考電流分區區段l-r〇。 流過子參考線50-r0至5n-r〇的分區參考電流係連結在一 起’以形成一流過參考元件9-rO的參考電流。 參考電壓設定電路110-丨包括一電流電壓轉換電路1〇〇_Γΐ 和複數個電流負載電路30-rl至3n-rl。電流電壓轉換電路 l〇〇-rl將流過子參考線50_rH々一分區參考電流轉換為表示 子參考線50-irl電位的電壓，將流過子參考線51^丨的一分區 參考電流轉換為表示子參考線51-rl電位的電壓，且同樣地 將流過子參考線5n-r 1的一分區參考電流轉換為表示子參考 線5n-rl電位的電壓。 流過子參考線50-rl至5n-rl的分區參考電流係連結在— 起，以形成一流過參考元件9-r 1的參考電流。 87062 -44- 1226069 同樣地，參考電壓設定電路110_n&括一電流電壓轉換電 路1 ΟΟ-rn和複數個電流負載電路3〇_1»11至3η_Γη。電流電壓轉 換電路100-m將流過子參考線50_rn的一分區參考電流轉換 為表示子參考線50-rn電位的電壓，將流過子參考線51_rr^々 刀區參考電流轉換為表示子參考線5i _Γη電位的電壓，且 同樣地將流過子參考線5n-rn的一分區參考電流轉變為表示 子參考線5 π - r π電位的電壓·。 流過子參考線50-rn至5n-rn的分區參考電流係連結在一 起’以形成一流過參考元件9-rn的參考電流。 根據本發明，一流過一記憶體單元的參考電流，由連結 在一起的複數個分區參考電流形成。根據本發明，參考電 流不疋分開的」’但是參考單元電流位準可以被認為是分 為個別流過複數個子參考線的分區參考電流位準。 為簡單起見，圖4省略電流電壓轉換電路⑺^“和1〇〇_rn 的内部結構。電流電壓轉換電路100_rl和1〇〇-rn具有與電流 電壓轉換電路l〇〇-r〇相同的結構。 如參考元件9·γ0至9-rn，使用限定電壓受到嚴密調整之記 憶體單元具有相同結構和相同特性的參考單元，以便取得 適當的參考電流。 在這一範例中，參考電流分區區段l-r〇包括複數個NMOS 電晶體10-r0至ln-rO，其每一個都具有一閘極以及一源極， 透過反相器101-Γ〇彼此相連。 NMOS電晶體i〇-r〇至ΐη-rO受到控制，使得複數個子參考 線50_r〇至5卜Γ〇分別與參考位元線電連接或分隔開。當複數 87062 -45- 1226069 個子參考線50_r〇至5n-r〇藉著NM0S電晶體1〇^〇至1η_Γ〇電 連接至參考位元線8-r〇時，分區參考電流係連結在一起，以 形成流過參考位元線8_Γ〇的參考電流。 複數個子參考線（卩^印至5η_Γ〇)至^^⑺至5n_m)係分別連 接至電流負載電路（3〇-r〇至3n-r0)至（30-rn至3n-rn)，用於 提供分區參考電流給子參考線（5〇^〇至化^㈨至（5〇_m至 5n-rn) 〇 參考電壓設定電路11 〇-〇至ll〇_n分別施加一參考電壓到 參考線60r至6nr 明確地說，參考電壓設定電路110_0施加一參考電壓至參 考線60r ’參考電壓設定電路11〇_1施加一參考電壓至參考線 61r，以及參考電壓設定電路丨⑺巧施加一參考電壓至參考線 6nr ° 參考線60r至6nr統稱為「參考線群組6r」。 明確地說，在參考電壓設定電路110-0中，電流負載電路 30-r〇施加一參考電壓至參考線6〇r。參考線6〇r係連接至參 考電壓設定電路110-1的電流負載電路30-rl，還連接至參考 電壓設定電路110-n的電流負載電路30-rn。每個電流負載電 路30-rl和30-rn的電流供應能力，係受到電流負載電路3〇4〇 的參考電壓的控制。 在參考電壓設定電路110-1中，電流負載電路31-rl施加一 參考電壓至參考線61r。參考線6lr係連接至參考電壓設定電 路110-0的電流負載電路31_r*0,還連接至參考電壓設定電路 110-n的電流負載電路3 1 -rn。每個電流負載電路3 1 -Γ〇和 87062 -46- 1226069 31-m的電流供應能力，係受到電流負載電路31_r^々參考電 壓的控制。 ^ 在參考電壓設定電路110-n中，電流負載電路3心m施加— 參考電壓至參考線6nr。參考線6nr係連接至參考電壓設定電 路110-0的電流負載電路3n-r0，還連接至參考電壓設定電路 Π0-1的電流負載電路3iwl。每個電流負載電路311^〇和 3rwl的電流供應能力，係受到電流負載電路“-⑺的參考電 壓的控制。 如上所述，從複數個參考電壓設定電路其中之一輸出的 參考電壓，可控制包含在另一參考電壓設定電路中至少一 個電流負載電路的電流供應能力。 在這一範例中，電流負載電路（3〇4〇至3114〇)分別包括 PMOS電晶體（70-r0至7n-r0)。電流負載電路 分別包括PMOS電晶體（70-rl至7n-rl)。電流負載電路（3〇rn 至3rwn)分別包括PMOS電晶體（70-rn至7n-rn)。包含在一參 考電壓設定電路的至少一個電流負載電路中的pM〇s電晶 體，係與包含在另一參考電壓設定電路的電流負載電路中 的PMOS電晶體電流鏡射連接。 例如，在參考電壓設定電路110_0中，連接至包含在電流 負載電路30-r0中的PMOS電晶體70-H)輸出的參考線6〇Γ，係 連接至包含在另一參考電壓設定電路11〇_1至1〇〇_η中的電 流負載電路30-rl至30-rn中的每個PMOS電晶體7〇-rl至70-rn 的閘極，以實現電流鏡射連接。因此，由參考電壓設定電 路110-0中的電流負載電路30-r0施加的參考電壓，可控制每 87062 -47- 1226069 一電流負載電路30-rl至30-rn的電流供應能力。 施加到每一參考線61 r至6nr的參考電壓，可以控制包含在 產生參考電壓的參考電壓設定電路以外的參考電壓設定電 流中的電流負載電路的電流供應能力。 例如，由參考電壓設定電路110-1提供有參考電壓的參考 線61r，係連接至包含在電流負載電路31_Γ〇中的pM〇s電晶 體71 -r0的一閘極，也連接至包含在電流負載電路3 1-m中的 PMOS電晶體71_rn的一閘極，以實現電流鏡射連接。 由參考電壓設定電路1 l〇-n提供有參考電壓的參考線 ’係連接至包含在電流負載3n-r0中的PMOS電晶體7n-r0的 一閘極，也連接至包含在電流負載電路3rwi中的PM〇s電晶 體7n-rl的一閘極，以實現電流鏡射連接。 除此之外，包含在每一參考電壓設定電路中的電流負載 電路中的至少一個PMOS電晶體，也與包含在分區感應電路 (圖1)中的電流負載電路中的PMOS電晶體電流鏡射連接。 例如，在參考電壓設定電路11〇-〇中，連接至包含在電流 負載電路30-r0中的PMOS電晶體70-H)的參考線6〇r ,係與包 含在分區感應電路20(圖1)的電流負載電路3〇中的pM〇s電 晶體70的一閘極電流鏡射連接。因此，參考線6〇1<的參考電 壓可以控制分區感應電路20的電流負載電路3〇的電流供應 能力。 參考線61r至6nr的參考電壓，也可控制以實質上相同方式 包含在分區感應電路（圖1)中的電流負載電路的電流供應能 力0 87062 -48- 1226069 例如，由參考電壓設定電路11(M提供有參考電壓的參考 線…，係連接至包含在電流負載電路31_ri(圖4)中的觸s 電晶體71·Γ1的—閘極，也連接至包含在分區感應電路21 (圖1)的電流負載電路31中的PMOS電晶體71的—問極，以形 成電流鏡射連接。 ^ 由參考電壓設定電路U0_n提供有參考電壓的參考線― ，係連接至包含在電流負載電路3n_rn(圖4)中的pM〇s電晶 體7n-rn的-閘極，也連接至包含在分區感應電路μ(圖⑽ 電流負載電路3η中的PMOS電晶體711的一閘極，以形成電流 鏡射連接。 以下，將描述第二範例中參考電路U〇的操作。在這一範 例中，從一如圖9Α所示儲存2位元資料的記憶體單元讀取資 料。此處，圖4所示參考數字中的rn」被假設是2。因此， 例如下列元件將描述為具有下列參考數字。包含在參考電 流分區區段l-r〇中的NM0S電晶體1-Γ〇是12_r〇。電流負載電 路3rw0是32-Γ〇。子參考線5η_Γ〇*52_Γ〇。參考線6虹是62^ 包含在該電流負載電路32-r〇中的PM〇s電晶體711^〇是72r〇 。參考位元線8-rn是8-r2。參考元件9-rn是9-r2。 從一可以儲存爪位元資料化是2或以上的整數）的記憶體 單元中漬取資料時，η被設定成2m-l。 在下列說明中，假設圖1顯示的讀取電路1000中的參考線 群組6與圖4顯示的參考電路11〇的參考線群組&相同，而且 參考線60至62與參考線60r至62r相同。參考線群組將以參考 數字「6」表示，而且參考線將以參考數字6〇至62表示。 87062 -49- 1226069 還假設第四狀態（圖9A)(對應到資料「〇〇」）和第三狀態 (對應到資料「(H」）之間的參考電流位準「h」由參考元件 9-r〇取得，第三狀態（對應到資料「〇1」）和第二狀態（對應到 資料「1〇」）之間的參考電流位準「M」衫考元件9-仙 得，以及第二狀態（對應到料「1〇」）和第一狀態（對應到 資料「11」）之間的參考電流位準「L」由參考元件9_r2取 得。 假設PMOS電晶體70_r0至72_r〇、70·Γ1至72七以及7〇-r2 至72-r2具有相同的電晶體尺寸，且NM〇s電晶體ι〇‘至 U-rO、ΙΟ-rl至12-Γ1以及⑺-以至12_r2也具有相同的電晶體 尺寸（為簡單起見，NMOS電晶體ι〇_Γι至ΐ2-Γι以及i〇-r2 至12-r2從圖4省略）。 當一適當的電壓施加到參考電流設定電路11〇_〇至丨1〇_2 中選定的參考元件9-rO至9-r2的閘極時，會降低參考位元線 8-rO至8-r2的電位。因此，會增加從包含在電流電壓轉換電 路100-1*0至l〇〇_r2中的反相器101_r〇至101_r2的輸出電位。因 此’包含在參考電流分區區段l-r〇至1_Γ2中的每一個nm〇s 電晶體（ΙΟ-rO至12-rO)至（10-r2至12-r2)變成有導電性。 然後’根據參考位元線8-rO至8-r2的電位降低子參考線 (50-r0至52-rO)至（50-r2至52-r2)的電位。然後，在包含於電 流負載電路（30-Γ0至32-rO)至（30_r2至32-r2)中的每個PM0S 電晶體（70-r0至72·γ0)至（70-1*2至72-r2)的源極和汲極之間， 產生足夠的電位差。 因此，其中閘極和汲極彼此相連的PMOS電晶體7〇-r〇、 87062 •50· 1226069 71-rl和72-r2，變成具有導電性。因此，連接至參考線6〇rThe transistors included in the read circuit and the reference circuit can have the same matching: mode, and thus can easily have the same transistor characteristics. The read circuit and reference circuit are less likely to be affected by changes in transistor characteristics. : In a specific embodiment of the present invention, each of the plurality of current load circuits includes a PMOS transistor, the product η is a human t ^^^, and the PMQSm of the M load circuit towel in a reference voltage setting circuit The voltage setting circuit in the voltage setting circuit ", has been. The PMOS transistor current mirror connection in the other reference circuit, U, load circuit. By the material structure, the current supply capacity of the current load circuit can be 87062 • 29 -1226069 Voltage control reference The reference of the output of the current load circuit in the voltage setting circuit is included in the other of the present invention—the electric circuit in the sound path is included in the Gongtai column, which is included in the reference voltage setting electric induction electric second = medium cut. The transistor is connected to the included zone. Due to the structure of this structure, the supply capacity of the ten-body current mirror can be controlled by the reference voltage of the current of the two current load circuits. The current load circuit in the circuit also inputs the reference circuit. The supplied reference voltage can be connected to the closed pole of a p-conductor included in the current load circuit of the reference voltage circuit. The current supply capability of the current load circuit can also be determined by such a structure. An appropriate reference element It can be easily obtained as follows. Use and: use the element with the same structure as the memory unit, and adjust its relevant criticality, so that the element has the same characteristics as the memory unit. Therefore, the The invention has the advantage of providing τ-reading circuits and reference circuits' to amplify the reading operation of the multi-layer memory unit; adding the reading speed of the multi-layer memory unit, and providing including such reading These and other advantages of the present invention will be understood by those skilled in the art who have read and understood the following detailed description with reference to the accompanying drawings. In the following, the present invention will be described by way of illustrative examples and with reference to the attached drawings. In the following examples, description will be made of 87062 -30-1226069 half: body memory device reading data as an example of semiconductor memory device The operation of the invention. The present invention can be used to read any material of the semiconductor device in the semiconductor device without limitation to the non-volatile or volatile semiconductor memory device: under the circuit ^ Kind 'describes only the operation of reading data. Omitting the control circuit and other components of the semiconductor memory device are omitted. (Example 1) FIG. 1 is a semiconductor memory device according to a first example of the present invention. The diagram of a semiconductor memory device includes:-a plurality of memory cells, one = a body cell array 15G,-a read circuit for reading data from a plurality of secrets to a single unit, And a reference circuit 11 is used to generate a reference voltage for reading data. In FIG. 1, the reading circuit 1000 is shown as an example of reading data from only a memory cell, and the buying circuit 1 is 〇〇 〇 Data can be read from a selected memory unit 9 of the plurality of memory units. As shown in FIG. 1, the reading circuit 1000 supplies a unit current to the plurality of memory units via a bit line 8. The selected memory cell 9 is selected, and the current level of the cell flowing through the memory cell 9 is converted into an induced voltage by current-voltage conversion. Then, the read circuit 1000 compares an induced voltage with a reference voltage, and thus reads the data stored in the memory cell 9. The reading circuit 1000 includes a plurality of partition induction circuits 20 to 2n and a current-voltage conversion circuit 100. The number of the plurality of partitioned sensing circuits included in the reading circuit 1000 is any integer of 2 or more. 87062 -31-1226069 The zone induction circuit 20 is connected to the current-voltage conversion circuit 100 via an induction line 50. The zone sensing circuit 20 includes a current load circuit 30 for supplying a zone unit current to the sense line 50, and a sense amplifier 40 for sensing and expanding the potential of the sense line 50 and the reference line 6 The potential difference between the potentials of 〇. The zone induction circuit 21 is connected to the current-voltage conversion circuit 100 via an induction line 51. The zone sensing circuit 21 includes a current load circuit 31 for supplying a zone unit current to the sensing line 51, and a sense amplifier 41 for sensing and expanding the potential of the sensing line 51 and the potential of the reference line 61. Potential difference between the two. Figure 1 shows the tf zone induction circuit 2n. The letter "η" in this reference number represents an integer of 1 or more. Fig. 1 also shows a current load circuit 311, a sense amplifier 4n, a sense line 5n, a reference line 6n, and a PMOS transistor 7n. "Η" in these reference numbers also represents an integer of 1 or more. This means that the read circuit 1000 includes at least two zone sensing circuits, at least two current load circuits, at least two sense amplifiers, at least two sense lines, at least two reference lines, and at least two PMOS transistors. In the following description, "η" is 2 or more; that is, the read circuit 1000 includes at least three zone sensing circuits, at least three current load circuits, at least three sense amplifiers, at least three sense lines, and at least three references. Line, and at least three PMOS transistors. In the following description, the reference lines 60 to 611 are collectively referred to as "reference line group 6". The current-voltage conversion circuit 100 converts the zone induced current flowing through the induction line 50 into an induced voltage representing the potential of the induction line 50, and converts the zone induced current flowing through the induction line 51 87062 -32-1226069 into the representative induction line. An induced voltage of 5i potential similarly converts the zone induced current flowing through the induction line 5n into an induced voltage representing the potential of the induction line 5n. According to the present invention, a cell current passing through a memory cell is formed by a plurality of partitioned cell currents connected together. According to the present invention, the unit current is not "separated", but the unit current level can be considered as a divided unit current level flowing through a plurality of sensing lines. The current-voltage conversion circuit 100 includes a unit current partitioning section 1 for connecting the sensing lines 50 to 5η to the memory unit 9 or separating the two through the bit line 8 ', and an inverter 101. For control unit current division section 1. In this example, the cell current section i includes an NMOS transistor 10 'having a gate and a source, which are connected to each other via an inverter 101, and an NMOS transistor 11 having a gate and a source. The electrodes are connected to each other via an inverter 丨 〇 丨. Similarly, an NMOS transistor 1 n has a gate and a source, and is connected to each other via an inverter 101. In this example, the current load circuit 30 includes a PMOS transistor 70. A gate of the PMOS transistor 70 receives a reference voltage through the reference line 60. The reference voltage of the reference line 60 controls the current supply capability of the current load circuit 30. The current load circuit 31 includes a PMOS transistor 71. A gate of the PMOS transistor 71 receives a reference voltage through the reference line 61. The reference voltage of the reference line 61 controls the current supply capability of the current load circuit 31. Similarly, the current load circuit 3n includes a PMOS transistor 7n. A gate of the PMOS transistor 7n receives a reference voltage through the reference line 6n. The reference 87062 -33 · 1226069 line 6η reference voltage controls the current supply capability of the current load circuit 3η. In the reading circuit 1000, at least one of the plurality of current load circuits 30 to 3n included in the zone induction circuits 20 to 2η has a current supply capability different from that of another zone induction circuit. The reference circuit 110 applies a reference voltage to the gates of the PMOS transistors 70 to 7η of the current load circuits 30 to 3η through reference lines 60 to 6η corresponding to the plurality of partitioned induction circuits 20 to 2η, respectively. In the above description, the reference circuit 110 is not included in the read circuit 1000. On the other hand, the read circuit 1000 may include a reference circuit 110. FIG. 2 is a circuit diagram illustrating that the read circuit 1000 reads data from a part of a memory cell array 150. The memory cell array 150 shown in FIG. 2 includes a plurality of memory cells CELL 11 to CELL 44 in a matrix. The gates of the memory cells in the individual rows of the memory cell array 150 are commonly connected to the word lines WL1 to WL4. Specifically, the word line WL1 is connected to the gates of the memory cells CELL11 to CELL14, and the word line WL2 is connected to the gates of the memory cells CELL21 to CELL24. The word line WL3 is connected to the gates of the memory cells CELL31 to CELL34, and the word line WL4 is connected to the gates of the memory cells CELL41 to CELL44. The drains of the memory cells in individual rows of the memory cell array 150 are connected in common to the bit lines BL1 to BL4. Specifically, the bit line BL1 is connected to the drains of the memory cells CELL11 to CELL41, and the bit line BL2 is connected to the drains of the memory cells € 1 ^ 12 to € 1 ^ 42. Bit line 81 ^ 3 is connected to the drains of memory cells CELL13 to CELL43, and bit line 87062 -34- 1226069 BL4 is connected to the memory cells CELL14 to CELL4W4 drain. The drains of two adjacent memory cells in each row are connected to each other and then to the bit line. For example, the drains of the memory cells CELL11 and CELL21 are connected, and these drains are connected to the bit line BL1. The drains of the memory cells CELL31 and CELL41 are connected, and these drains are connected to the bit line BL1. The provided word lines WL1 to WL4 and bit lines BL1 to BL4 are perpendicular to each other. The sources of the memory cells CELL 11 to CELL 44 are commonly connected to a common source line SRC on a per-block basis. Each block includes a number of memory cells. The sources of two adjacent memory cells in each row are connected to each other. For example, the sources of the memory cells CELL21 and CELL31 are connected, and these sources are connected to the source line SRC. The plurality of bit lines BL1 to BL4 are connected to, for example, a zone sensing circuit 20 to 2n via a decoder circuit (not shown) or a current-voltage conversion circuit 100 (FIG. 1). The reference circuit 110 (FIG. 1) includes a memory unit. As a reference unit, it is similar to the memory cells in the memory cell array 150. Returning to FIG. 1, the operation of the read circuit 1000 in this example will be described. In this example, a circuit structure for reading data from a multi-layered memory cell capable of storing 2-bit data as shown in FIG. 9A will be described. The "η" in the reference numeral in Fig. 1 is assumed to be 2. Therefore, the following elements will be described as indicated by the following reference numerals. The NMOS transistor In is 12. The zone sensing circuit 2η is 22 87062 -35-1226069. The current load circuit 3η is 32. The sense amplifier 4ϋ is 42. The sensing line 5η is 52. The reference line 6ιι is 62. The pM0s transistor 7n included in the current load circuit 32 is 72. When reading data from a memory unit that can store m-bit data plus an integer of 2 or more), η is set to 2m- l. In the following description, the potential of the sensing line will be referred to as the "induced voltage" and the potential of the reference line will be referred to as the "reference voltage". The operation of reading data from the two-layer memory unit shown in FIG. 9] 3 by the reading circuit 1000 will be described first, and then the operation of reading data from the multi-layer memory unit will be described for easy understanding. In the following description, reference lines 60 to 62 have reference voltages of the same level. NMOS electric sun bodies 10 to 12 have the same size. The pMos transistors 70 to 72 have the same size. Each] ^] ^ 〇3 transistors 10 to 12 and]?] ^ 〇§ The current supply capability of transistors 70 to 72 is mainly determined by the size of the transistor and the gate potential. NMOS transistors 10 to 12 have the same gate potential and therefore have the same current supply capability. PM0s transistors 70 to 72 have the same gate potential and therefore have the same current supply capability. In other words, since the reference, springs 60 to 62 have the same potential, the pMOS transistor has the same current supply capability. When an appropriate voltage is applied to a gate of the selected memory cell 9, t lowers the potential of the bit line 8 and thus lowers the potential of the inverter connected to the bit line 8 input. Therefore, the output potential of the slave inverter 101 will increase. Therefore, the nmos transistors 10 to 12 contained in the cell current division section 丨 become conductive. 87062 -36-1226069 When the NMOS transistors 10 to 12 are conductive, the potential of the sensing lines 50 to 52 will decrease according to the potential of the bit line 8. Therefore, a sufficient potential difference is generated between the source and the drain of each of the PMOS transistors 70 to 72 contained in the current load circuits 30 to 32, respectively. In this state, a reference voltage is applied to the reference lines 60 to 62, and the pMOS transistors 70 to 72 become conductive. Then, the bit line 8 is charged via the induction lines% to 52 and the NMOS transistors 10 to 12. When the potential of the bit line 8 is increased ', a potential difference is generated between the drain and source of the memory cell 9, so that a cell current flows. In order to perform the sensing operation correctly, when the unit current level is equal to the reference current level, as described above with reference to FIG. 9B, the reference voltage applied to the zone sensing circuits 20 to 22 through the reference lines 60 to 62 is set as the sensing line 50 to 52 induced voltage. When the bit line 8 is charged to a predetermined potential, the output potential of the inverter 1 0 1 included in the current-voltage conversion circuit 100 can be reduced, and therefore, the current supply capability of each NMOS transistor 10 to 12 is reduced. Will decrease. When the potential of the bit line 8, the level of the cell current flowing through the memory cell 9, and the level of the current flowing through the nmos transistor 10 to 12 reach equilibrium, the potential in the reading circuit 1000 and the The current level becomes stable. Since the reference lines 60 to 62 have the same potential, the NMOS transistors 10 to 12 have the same gate potential and the same drain-source potential. Therefore, the drain-source current of the same level can flow through the NMOS transistor 10-12. Therefore, the current level of 10 to 12 flowing into each NMOS transistor is 1/3 of the cell current level. At this time, due to the PMOS transistors 70 to 72, the induction lines 50 to 52 87062 -37-1226069 obtain an equal induced voltage. The potential difference 'between the potential of the sense lines 50 to 52 and the potential of the reference lines 60 to 62 is sensed and enlarged by the sense amplifiers 40 to 42 respectively. Therefore, the information is read. As described above, the induction lines 50 to 52 have the same potential. Therefore, the sense amplifiers 40 to 42 perform the same operation and output the same result. Therefore, when the reference lines 60 to 62 have the same potential, 1-bit data of "1" or "0" is read from the memory cell 9. Next, the operation of the reading circuit 1000 to read data from the multi-layered memory cell according to the first example will be described. In the following description, a multi-level memory cell can store 2-bit data, that is, four values. In this example, the NMOS transistors 10 to 12 have the same transistor size 'as in the case of a two-layer memory cell. pM0s transistors 70 to-have the same transistor size. Therefore, the NMOS transistors ⑺ to Η have the same gate potential 'and therefore have the same current supply capability. To perform the read operation correctly when the cell current level is equal to each reference current level, 'circuit constants such as transistor size and reference voltage' = set so that the potentials of the induction lines 5G to 52 are equal to the reference line 6 respectively 〇 to 62 A — (reference voltage applied to reference lines 6 () to 62). The reference line ⑼ to 62 = electricity = is different from the case of reading data from the two-level memory cell, it is inconsistent and is set as shown below. For reference 9 in the reference between the data "..." and the data "° 1" ^ ^ ^ "A), the reference voltage system β applied to the reference line 60 is again formed to the induced voltage of the sense light 50. When the unit current level is equal to the data “…” and the data “Π), please refer to 87062 -38 · 1226069 to test the current level“ M ”(Figure 9A). The reference voltage applied to the reference line 61 is set equal to the induction. Induced voltage on line 51. Similarly, when the unit current level is equal to the reference current level "L" (Figure 9A) between the data "1" and the data "", the test voltage applied to the reference line 62 is again equal to The induced voltage of the induction line 5 2. Therefore, the potentials of the reference lines 60 to 62 are set to be quite high, medium, and low, respectively. When an appropriate voltage is applied to the gate of the selected memory cell 9, the potential of the bit line 8 is lowered. Therefore, the potential output from the inverter 101 included in the current-voltage conversion circuit 100 is increased. Therefore, the NMOS transistors 10 to 12 included in the single current division section 1 become conductive. Then, the potentials of the sensing lines 50 to 52 decrease according to the potential of the bit line 8. Therefore, 'is a sufficient potential difference between the source and the drain of each of the PMOS transistors 70 to 72 included in the current load circuits 30 to 32. In this state, a reference voltage is applied to the reference lines 60 to 62, and the pMOS transistors 70 to 72 become conductive. Then, the bit line 8 is charged via the induction lines 50 to 52 and the NMOS transistors 10 to 12. When the potential of the bit line 8 is increased ', a potential difference is generated between the source and the source of the memory cell 9, so that a cell current flows. In particular, PMOS transistors have a characteristic that when the reference voltage applied to the relevant gate is high, the level of current flowing through the PMOS transistor will be lower. When the bit line 8 is charged to a predetermined potential, the output potential from the inverter 1 〇1 included in the current-voltage conversion circuit 100 can be reduced, so the current supply capability of each NMOS transistor 10 to 12 is reduced. . When the potential of 87062 -39-1226069 of bit line 8, the level of cell current flowing through memory cell 9, and the level of current flowing through NMOS transistor 10 to 12 reach equilibrium, the reading circuit can be made The potential and current levels in 1000 become stable. When the NMOS transistors 10 to 12 are operated in a saturation region (the pentagonal vacuum tube region), the NMOS transistors 10 to 12 have the same gate potential. Therefore, the NMOS transistors 10 to 12 can allow the drain-source currents to flow at substantially the same level without depending on their associated drain-source potentials significantly. Since the reference lines 60 to 62 have different potentials, the current supply capability of the pMOS transistor 70 is different from that of the PMOS transistors 71 and 72. Specifically, the potential of the reference line 60 is greater than the potential of the reference lines 61 and 62, so the current supply capability of the PMOS transistor 70 is lower than the current supply capability of the pMOS transistors 71 and 72. Therefore, when the NMOS transistors 10 to 12 have substantially the same current supply force, the potential of the induction line 50 will be lower than that of the induction lines 5 and 52. The potential of the reference line 61 is higher than the potential of the reference line 62, so the current supply capability of the pMOS transistor 71 is lower than the current supply capability of the PMOS transistor 72. Therefore, the potential of the induction line 51 is lower than the potential of the induction line 52. Now, the relationship between the reference voltage and the induced voltage will be discussed. As mentioned above, when the cell current level is equal to the reference current level, the reference voltage is set equal to the induced voltage. Therefore, when the cell current level is higher than the reference current level, the current supply capacity of each of the NMOS voltages θ to 10 included in the cell current section i is increased. It can also be observed that when the unit current level is higher than the reference current level, the potential of the induction line will decrease due to the larger level of 87062 • 40-1226069, so the induced voltage becomes lower than the reference voltage. Conversely, when the cell current level is lower than the reference current, the induced voltage becomes higher than the reference voltage. The sense amplifiers 40 to 42 respectively expand the potential difference between the potentials of the sensing lines 50 to 52 and the potential of the reference = 6 ^ 62 to read the data. When the potential of the sensing line is coincident with the potential of the corresponding reference line, each of the sense amplifiers will output "0", and when the potential of the sensing line is lower than the corresponding parameter, it will output "!". "For example, when the cell current level of the memory cell 9 is in the fourth state (FIG. 9A) corresponding to the data" 〇〇 ", the cell current level is lower than any of the three reference currents . Therefore, the potentials of the sense lines 50 to "are the same as the potentials of the reference lines 60 to 62, so each sense amplifier outputs 0". The 3-bit data "OOOO" output from the sense amplifiers 40 to 42 is decoded by a logic circuit (shown in Fig. W) that implements the fact table shown in Fig. 13. Therefore, the two-digit data "00" is read. Similarly, when the unit current level of the memory cell 9 is in the position corresponding to the data "10": the shape 9A), the unit current is referred to the reference current levels "H" and "M", But below the reference current level: "~ Therefore, the potentials of inductors 50 and 51 are lower than the potentials of reference lines 60 and ^. The potential of induction line 52 is higher than the potential of reference line 62. Therefore, the amplifier 40 to 42 outputs 3-bit data "UG". The 3-bit data 2 11 ″ is decoded by the above-mentioned logic circuit. Therefore, two digits "10" are read. When the cell current level of memory cell 9 is in the third state (Figure 9A) corresponding to data 87062 -41-1226069 and the data corresponding to data "u" In the first state, the data is read in substantially the same way. As described above, the prefetch circuit 1000 can read multi-layered data by a parallel induction system by operating the partition induction circuits 20 to 2n in parallel. Since the current load circuits 30 to 3n each include? ^ 〇3 transistors 70 to 711, so each of the partition induction circuits 20 to 2n can be operated as a circuit having non-linear characteristics as shown in Fig. 15B. Fig. 3 is a statistical diagram illustrating the relationship between the induced voltage and the cell current level in the reading circuit 1000 shown in Fig. I. In particular, when the potential of the reference line is high, the corresponding induced voltage is low. The reason is that when the potential of the reference line is high, the level of the current flowing through the pM0s transistor will be lower, so the potential of the sensing line will be lowered due to the lower level. As shown in FIG. 3, the reading circuit 1000 has a non-linear characteristic. Therefore, by increasing the conversion efficiency of the induced voltage near the cell current level equal to each reference current level point and in the region, the read operation limit can be enlarged. The reason why the read circuit 1000 has a non-linear characteristic and the sensing operation is also performed in a parallel sensing system is: by providing a partition unit current to the memory unit 9 through a plurality of sensing lines, one reading circuit 1000 can have A plurality of operating points. In the above description, the divisional unit current flowing through the induction line 50, the divisional unit current flowing through the induction line 51, and the divisional unit current flowing through the induction line 52 are connected together on one bit line, thereby forming a unit current. . The present invention is not limited to this, and the present invention can be applied to any structure. By means of the structure 87062 -42 · 1226069, the partition unit currents flowing through a plurality of induction lines are connected together to form a unit flowing through a memory unit. Current. As described above, the sensing operation of the reading circuit 1000 is performed by the parallel sensing system ′, which is advantageous for increasing the reading speed, and has a non-linear characteristic capable of realizing a large operation limit of a multi-layer memory cell. Therefore, according to the first example, a reading circuit capable of high-speed operation and having a large operation limit for a large multi-layer memory unit is provided. (Example 2) In the first example, the specific structure of the reference circuit is not described. In the second example of the present invention, an exemplary structure of the reference circuit 110 will be described. FIG. 4 shows a circuit configuration of the reference circuit 110 of FIG. 1. As shown in FIG. 4, the reference circuit 11 includes a plurality of reference voltage setting circuits uo-o to m-ο. In the second example, the number of reference voltage setting circuits included in the reference circuit ιι is an integer of 2 or more. . The reference voltage setting circuit 110-0 supplies a reference current to the reference element 9 through the reference bit line 8r0 and converts the reference current flowing through the reference element W into a reference voltage. Reference voltage setting circuit 110. The reference bit line 8ri supplies a reference current to the selected reference element 9_r and converts the current flowing through the reference element ^ into a reference voltage. "In the reference circuit UG shown in Fig. 4, the" n "table of the reference voltage setting circuit 110_n ... or an integer above. In the following description, the reference circuit includes at least three reference voltage-like circuits: that is, "n" is 2 or 87062 -43-1226069 each of the reference voltage setting circuits 110-0 to 110-n includes a current voltage Conversion circuit and multiple current load circuits. The reference voltage setting circuit lio-o includes a current-voltage conversion circuit 100-r0 and a plurality of current load circuits 30-r0 to 3n-r0. The current-voltage conversion circuit 100-r0 converts a partition reference current flowing through the sub-reference line 50_r0 into a voltage representing the potential of the sub-reference line 50-r0, and converts a partition reference current flowing through the sub-reference line 51 ^ 〇 into The voltage representing the potential of the sub-reference line 5 1 -r0, and similarly converting a partitioned reference current flowing through the sub-reference line 5n-r0 to the voltage representing the potential of the sub-reference line 5n-r0. The current-voltage conversion circuit 100 · Γ0 includes a reference current partition section Kr〇 for connecting the sub-reference lines 5〇 ^ 〇 to 5η-Γ〇 or the reference unit 9-rO via the reference bit line 8-ΐΟ. It is divided and divided, and an inverter 101 is used to control the reference current partition section lr0. The divisional reference currents flowing through the sub-reference lines 50-r0 to 5n-r0 are connected together 'to form a reference current passing through the reference element 9-rO. The reference voltage setting circuit 110- 丨 includes a current-voltage conversion circuit 100_Γΐ and a plurality of current load circuits 30-rl to 3n-rl. The current-voltage conversion circuit 100-rl converts a reference current flowing through the sub-reference line 50_rH into a voltage representing the potential of the sub-reference line 50-irl, and converts a reference current flowing through the sub-reference line 51 ^ 丨 into The voltage representing the potential of the sub-reference line 51-rl, and similarly converting a partitioned reference current flowing through the sub-reference line 5n-r 1 to the voltage representing the potential of the sub-reference line 5n-rl. The divided reference currents flowing through the sub-reference lines 50-rl to 5n-rl are connected together to form a reference current passing through the reference element 9-r1. 87062 -44- 1226069 Similarly, the reference voltage setting circuit 110_n & includes a current-to-voltage conversion circuit 100-rn and a plurality of current load circuits 3〇_1 »11 to 3η_Γη. The current-voltage conversion circuit 100-m converts a partitioned reference current flowing through the sub-reference line 50_rn into a voltage representing the potential of the sub-reference line 50-rn, and converts the reference current flowing through the sub-reference line 51_rr ^ into the blade region into a sub-reference The voltage of the potential of the line 5i _Γη, and similarly converts a partitioned reference current flowing through the sub-reference line 5n-rn to a voltage · representing the potential of the sub-reference line 5 π-r π. The divided reference currents flowing through the sub-reference lines 50-rn to 5n-rn are connected together 'to form a reference current passing through the reference element 9-rn. According to the present invention, the reference current passing through a memory cell is formed by a plurality of partitioned reference currents connected together. According to the present invention, the reference currents are not separated "', but the reference cell current level can be considered as a divided reference current level divided into individual flows through a plurality of sub-reference lines. For simplicity, FIG. 4 omits the internal structure of the current-voltage conversion circuits ⑺ ^ ″ and 100-rn. The current-voltage conversion circuits 100_rl and 100-rn have the same configuration as the current-voltage conversion circuits 100-r〇 Structure. For reference elements 9 · γ0 to 9-rn, use memory cells that have the same structure and the same characteristics as the memory cells that have been tightly adjusted for a limited voltage in order to obtain an appropriate reference current. In this example, the reference current partition area Segment lr0 includes a plurality of NMOS transistors 10-r0 to ln-rO, each of which has a gate and a source, and are connected to each other through an inverter 101-Γ〇. NMOS transistors i〇-r〇 至ΐη-rO is controlled so that the plurality of sub-reference lines 50_r0 to 5bΓ〇 are electrically connected or separated from the reference bit line, respectively. When the plural 87062 -45-1226069 sub-reference lines 50_r0 to 5n-r〇 When the NM0S transistors 1〇 ^ 〇 to 1η_Γ〇 are electrically connected to the reference bit line 8-r〇, the partition reference currents are linked together to form a reference current flowing through the reference bit line 8_Γ〇. A plurality of sub-reference lines (卩 ^ 印 至 5η_Γ〇) to ^^ ⑺ to 5n_m) Connected to the current load circuits (30-r0 to 3n-r0) to (30-rn to 3n-rn), respectively, for providing a partitioned reference current to the sub-reference lines (5〇 ^ 〇 至 化 ^ ㈨ to (5 〇_m to 5n-rn) 〇 Reference voltage setting circuit 11 〇-〇 to ll〇_n Apply a reference voltage to the reference line 60r to 6nr Specifically, the reference voltage setting circuit 110_0 applies a reference voltage to the reference line 60r 'The reference voltage setting circuit 11〇_1 applies a reference voltage to the reference line 61r, and the reference voltage setting circuit ⑺ accidentally applies a reference voltage to the reference line 6nr ° The reference lines 60r to 6nr are collectively referred to as "reference line group 6r". Specifically, in the reference voltage setting circuit 110-0, the current load circuit 30-r0 applies a reference voltage to the reference line 60r. The reference line 60r is a current load connected to the reference voltage setting circuit 110-1. The circuit 30-rl is also connected to the current load circuit 30-rn of the reference voltage setting circuit 110-n. The current supply capability of each of the current load circuits 30-rl and 30-rn is subject to the current load circuit 304. Control of the reference voltage In the reference voltage setting circuit 110-1, The load circuit 31-rl applies a reference voltage to the reference line 61r. The reference line 6lr is a current load circuit 31_r * 0 connected to the reference voltage setting circuit 110-0, and is also connected to the current load circuit 3 of the reference voltage setting circuit 110-n. 1 -rn. The current supply capability of each of the current load circuits 3 1 -Γ〇 and 87062 -46-1222269 31-m is controlled by the reference voltage of the current load circuit 31_r ^ 々. ^ In the reference voltage setting circuit 110-n, the current load circuit 3 is applied from the center 3 m — the reference voltage is to the reference line 6nr. The reference line 6nr is connected to the current load circuit 3n-r0 of the reference voltage setting circuit 110-0, and is also connected to the current load circuit 3iwl of the reference voltage setting circuit Π0-1. The current supply capacity of each of the current load circuits 311 ^ 0 and 3rwl is controlled by the reference voltage of the current load circuit "-⑺. As mentioned above, the reference voltage output from one of the plurality of reference voltage setting circuits can be controlled. The current supply capability of at least one current load circuit included in another reference voltage setting circuit. In this example, the current load circuits (3040 to 3114) include PMOS transistors (70-r0 to 7n-r0, respectively). ). Current load circuits include PMOS transistors (70-rl to 7n-rl). Current load circuits (30rn to 3rwn) include PMOS transistors (70-rn to 7n-rn). Included in a reference voltage The pM0s transistor in at least one current load circuit of the setting circuit is mirror-connected to the PMOS transistor current included in the current load circuit of another reference voltage setting circuit. For example, in the reference voltage setting circuit 110_0, The reference line 6〇Γ connected to the output of the PMOS transistor 70-H) included in the current load circuit 30-r0 is connected to the reference line setting circuit 11〇_1 to 100〇_η Electricity The gates of each of the PMOS transistors 70-rl to 70-rn of the load circuits 30-rl to 30-rn for current mirror connection. Therefore, the current load circuit in the reference voltage setting circuit 110-0 The reference voltage applied at 30-r0 can control the current supply capability of a current load circuit 30-rl to 30-rn per 87062 -47-1226069. The reference voltage applied to each reference line 61 r to 6nr can be controlled to be included in Current supply capability of a current load circuit in a reference voltage setting current other than a reference voltage setting circuit that generates a reference voltage. For example, a reference line 61r provided with a reference voltage by the reference voltage setting circuit 110-1 is connected to the current load included in the current load. A gate of the pM0s transistor 71-r0 in the circuit 31_Γ〇 is also connected to a gate of the PMOS transistor 71_rn included in the current load circuit 3 1-m to realize a current mirror connection. By reference The voltage setting circuit 1 l0-n is provided with a reference line of a reference voltage, which is connected to a gate of the PMOS transistor 7n-r0 included in the current load 3n-r0, and also connected to a gate included in the current load circuit 3rwi. PM〇s transistor 7n A gate of -rl to achieve current mirror connection. In addition, at least one PMOS transistor in the current load circuit included in each reference voltage setting circuit is also connected to the partition induction circuit (Figure 1). PMOS transistor current mirror connection in the current load circuit in). For example, in the reference voltage setting circuit 110-〇, connect to the reference of the PMOS transistor 70-H included in the current load circuit 30-r0) The line 60r is connected to a gate current mirror of the pMOS transistor 70 included in the current load circuit 30 of the partition induction circuit 20 (FIG. 1). Therefore, the reference line 6〇1 < The reference voltage can control the current supply capability of the current load circuit 30 of the partition induction circuit 20. The reference voltages of the reference lines 61r to 6nr can also control the current supply capability of the current load circuit included in the zone induction circuit (Figure 1) in substantially the same way. 0 87062 -48-1226069 For example, the reference voltage setting circuit 11 ( M provides a reference line with a reference voltage ... which is connected to the gate of the transistor 71 · Γ1 included in the current load circuit 31_ri (Figure 4), and also to the zone induction circuit 21 (Figure 1) Of the PMOS transistor 71 in the current load circuit 31 to form a current mirror connection. ^ The reference voltage reference line provided by the reference voltage setting circuit U0_n is connected to the current load circuit 3n_rn (Figure The gate of the pM0s transistor 7n-rn in 4) is also connected to a gate of the PMOS transistor 711 included in the zone induction circuit μ (Figure ⑽ current load circuit 3η) to form a current mirror connection In the following, the operation of the reference circuit U0 in the second example will be described. In this example, data is read from a memory cell that stores 2-bit data as shown in Fig. 9A. Here, reference is shown in Fig. 4 `` Rn in numbers '' is assumed to be 2 Therefore, for example, the following components will be described as having the following reference numbers. The NMOS transistor 1-Γ〇 included in the reference current section lr〇 is 12_r〇. The current load circuit 3rw0 is 32-Γ〇. 〇 * 52_Γ〇. The reference line 6 is 62 ^ The PM 0s transistor 711 ^ 〇 included in the current load circuit 32-r〇 is 72r〇. The reference bit line 8-rn is 8-r2. Reference element 9-rn is 9-r2. When fetching data from a memory unit that can store claw bit data (integers of 2 or more), η is set to 2m-1. In the following description, assume that Figure 1 The reference line group 6 in the read circuit 1000 shown is the same as the reference line group & of the reference circuit 11 shown in FIG. 4, and the reference lines 60 to 62 are the same as the reference lines 60r to 62r. The reference line group will be It is indicated by the reference number "6", and the reference line will be indicated by the reference numbers 60 to 62. 87062 -49-1226069 It is also assumed that the fourth state (Fig. 9A) (corresponding to the data "〇〇") and the third state (corresponding to The reference current level "h" to the data "(H") is obtained by the reference element 9-r〇, the third state ( The reference current level "M" between the data "〇1") and the second state (corresponding to the data "1〇") is a test element 9-sende, and the second state (corresponding to the material "1〇" ") And the first state (corresponding to the data" 11 ") the reference current level" L "is obtained from the reference element 9_r2. Assume that the PMOS transistors 70_r0 to 72_r0, 70 · Γ1 to 72, and 7〇-r2 To 72-r2 have the same transistor size, and NMOS transistors to U-rO, 10-rl to 12-Γ1, and ⑺- to 12_r2 also have the same transistor size (for simplicity, NMOS transistors ι〇_Γι to ΐ2-Γι and i〇-r2 to 12-r2 are omitted from FIG. 4). When an appropriate voltage is applied to the gates of the reference elements 9-rO to 9-r2 selected in the reference current setting circuits 11〇_〇 to 丨 1_2, the reference bit lines 8-rO to 8- r2 potential. Therefore, the output potential from the inverters 101_r0 to 101_r2 included in the current-voltage conversion circuit 100-1 * 0 to 100_r2 is increased. Therefore, each of the nmos transistors (10-rO to 12-rO) to (10-r2 to 12-r2) contained in the reference current partitioned sections l-r0 to 1_Γ2 becomes conductive. Then, the potential of the sub-reference lines (50-r0 to 52-rO) to (50-r2 to 52-r2) is lowered according to the potentials of the reference bit lines 8-rO to 8-r2. Then, each of the PM0S transistors (70-r0 to 72 · γ0) to (70-1 * 2 to 72) included in the current load circuits (30-Γ0 to 32-rO) to (30_r2 to 32-r2) -r2) generates a sufficient potential difference between the source and the drain. Therefore, the PMOS transistors 70-r0, 87062 • 50 · 1226069 71-rl, and 72-r2 in which the gate and the drain are connected to each other become conductive. Therefore, connect to reference line 60〇r

、61r和 62r的 PMOS 電晶體 70-r 卜 70-r2、71-r〇、71-r2、72-rO 和72-rl也變成具有導電性。因此，係透過子參考線（5〇_r〇 至 52-rO)至（50-r2至 52_r2)和 NMOS 電晶體（ΐ〇-Γ〇至 12_Γ〇)至 (10-r2至12-r2)對參考位元線8-Γ〇至8-r2充電。當增加位元線 8- r〇至8-r2的電位時，會在每個參考元件9_Γ〇至…r2的汲極和 源極之間產生電位差。因此，參考電流流動。 當參考位元線8-rO至8-r2被充電到一規定的電位時，會增 加從包含在電流電壓轉換電路1〇〇_Γ〇至1〇〇_r2中的反相器 101-r0至l〇l-r2輸出的電位。因此，會減少每一 NM〇s電晶 體（ΙΟ-rO至12-rO)至（l〇-r2至l2-r2)的電流供應能力。 當參考位元線8-rO至8-r2的電位、流過參考元件9-Γ〇至 9- r2的參考電流位準、以及流過NM〇s電晶體（丨〇_r〇至丨2_r〇) 至（10-r2至12_r2)的電流位準達成平衡狀態時，會使參考電 路110中電流的電位和位準變穩定。 參考元件9-Γ〇係設定成取得資料「〇〇」和資料「〇1」（圖 9Α)之間的參考電流位準「Hj,參考元件9_Γΐ係設定成取得 資料「〇1」和資料「10」間的參考電流位準「Μ」，以及參 考7G件9·Γ2係設定成取得資料「1〇」和資料「u」之間的參 考電流位準「L」。因此，參考線6〇1：、61r和62r的電位係分 別設定成相當高、中等和低。 圖1中的分區感應電路20的PMOS電晶體70和參考電壓設 疋电路110_0的PMOS電晶體7〇—r〇彼此係以電流鏡射連接。 將從參考電壓設定電路110_0(圖4中的參考線6〇r的電位）輸 87062 -51- 1226069 出的參考電壓提供給分區感應電路2〇。 參考电壓設定電路110-0包括三個電流負載電路3〇4〇至 32_r0。排除作用中的電流負載電路3〇^〇後的電流負載電路 以決疋參考電壓也就是電流負載電路31-1&gt;〇和32_r〇係如下 所示連接。電流負載電路31 -Γ〇係連接至參考線6丨，其接著 連接至作用中的電流負載電路31-rl，以決定參考線61的電 位。電流負載電路32-rO係連接至參考線62，其接著連接至 作用中的電流負載電路32-r2 ,以決定參考線62的電位。因 此，每個電流負載電路31-rO和電流負載電路32^〇的電流供 應能力都受到控制。 同樣地，也透過參考線61和62將參考電壓提供給分別包 含在分區感應電路21和22(圖1)中的電流負載電路31和32。 因此，如圖1所示的分區感應電路21的電流負載電路31以 及如圖4所示的參考電壓設定電路丨丨的電流負載電路 31-r0的電流供應能力，均受到參考線61的控制。同樣地， 如圖1所示的分區感應電路22的電流負載電路32以及如圖4 所示的參考電壓設定電路110-0的電流負載電路的電 流供應能力，均受到參考線62的控制。 因此，流過記憶體單元9的單元電流和流過參考元件9-Γ〇 的參考電流，實質上都以相同方式受到影響。尤其當單元 電流位準和參考電流位準彼此相等的時候，單元電流和參 考電流係以完全相同的方式受到影響。 這類影響會被從讀取電路1000和參考電路U〇取消。然後 ’包含在電流負載電路30中的PMOS電晶體70係與包含在圖 87062 -52- 1226069 15A所示的電流負載雷玫 電路30-r〇中的pM〇s電晶體7〇 r〇電流 鏡射連接，並顯示如圖】^ ^ 圖1 5B所不的非線性負載特性，這可提 供較大的操作極限。 因此’分區感應電路20中的感應放大器40可以決定單元 電流位準是否位於相對於資料「〇〇」和資料「〇1」之間邊 界的資料「OO」的-侧或是資料「Qi」的—侧。這個決定 將以設定為參考電流位準「H」的參考元件9__生的參考 電壓為基礎來加以執行。 同樣地，分區感應電路21中的感應放大㈣可以決定單 元電流位準是否位於相對於資料「〇1」和資料「1〇」之間 邊界的資料「G1」的-侧或是資料卜這個決 定將以歧為參考電流位準「Μ」的參考元件W產生的參 考電壓為基礎來加以執行。分區感應電路22中的感應放大 器42可以決定單元電流位準是否位於相對於資料「1〇」和 資料「U」之間邊界的資料「1G」的_側或是資料「u」 的-側。這個決定將以設定為參考電流位準％的參考元 件9-Γ2產生的參考電壓為基礎來加以執行。 如上所述，這-範例的參考電路很容易地產生圖】顯示的 讀取電路麵所需之參考電壓，還允許包含在讀取電路 麵和參考電路11G中的電晶體具有相同的配置模式。因此 ，具有相同的電晶體特性的電路可以很容易地產生。 因此，這-範例的參考電路相當容易接受製造流程期間 所導致的電晶體特性變化，並適用於多層式記憶體單元。 (範例3) 87062 -53 - 1226069 在本發明的弟三範例Φ L+A- .L* ^ , A » 观1’將描述包括兩個參考電路的半 導體記憶體裝置。 圖5根據本發明第三範例概略顯示半導體記憶體裝置 2500的結構。 半導體記憶體裝置25GG包括包含—複數個記憶體單元的 一記憶體單元陣列15〇, 一讀取電路2〇〇〇，用於從複數個記 憶體單元之一讀取資料，以及參考電路110和120，用於產 生讀取資料的一參考電壓。 在下列說明中，具有實質上相同功能如第一和第二範例 的元件，具有相同的參考數字，且相同的功能將不再贅述。 碩取電路2000包括複數個分區感應電路2〇至211和一電流 電壓轉換電路100。 兩個參考電路（參考電路11〇和120)將兩類型的參考電壓 提供給每一分區感應電路2〇至2n。 參考電路120經由一第一參考線群組5(包括參考線5〇n至 5nr)將一種類型的參考電壓提供給每一個感應放大器4〇至 4n 〇 參考電路110經由一第二參考線群組6(包括參考線60至 6n)將另一類型的參考電壓提供給每一個電流負載電路3〇 至3n，用以控制每一個電流負載電路30至311的電流供應能 力。 參考電路110和120可當作一參考電路使用。 參考電路110和120不包含在圖5的讀取電路2000中。本發 明並不受限於此種結構。讀取電路2000可包括參考電路110 87062 -54· 1226069 和 120。 圖6是圖5顯示的參考電路120的部分電路圖。 如圖6所示，參考電路120包括複數個參考電壓設定電路 420-0至420-n。參考電壓設定電路420-0至420-n透過參考位 元線408-r0至408-rn提供參考電流給選定的參考元件409-rO 至409-m(在複數個參考元件中），接著將流過參考元件 409-r0至409-rn的參考電流分別轉換為參考電壓。 如參考元件409-r0至409-rn，使用限定電壓受到嚴密調整 之記憶體單元具有相同結構和相同特性的參考單元，以便 取得適當的參考電流。 參考電壓設定電路420-0至420-n分別包括電流電壓轉換 電路400-rO至400-rn和複數個電流負載電路430-r0至43n-r0 、430-r 1 至 43n-rl、以及430-rn至 43n-rn 〇 為簡單起見，圖6不顯示電流電壓轉換電路400-rl至 400-rn的内部結構。電流電壓轉換電路400-rl至400-m具有 與電流電壓轉換電路400-r0相同的内部結構。 電流電壓轉換電路400·ι·0至400-rn包括參考電流分區區 段401-rO至401-m，用於透過參考位元線408-r0至408-rn連接 或分隔開子參考線450-rO至45n-r0、450-rl至45n-rl和450-rn 至45n-rn與參考單元409-r0至409-rn，還包括反相器501-r0 至501-rn，用以控制參考電流分區區段401-rO至401-rn。 在這一範例中，參考電流分區區段401-rO至401-m分別包 括複數個 NMOS 電晶體（410-r0 至 41n-r0)至（410-rn 至 41n-rn) ，其具有一閘極和一源極，透過反相器501-r0至501-m彼此 87062 -55- 1226069 相連。複數個子參考線（450-r0至45n-rn)至（450-rn至45n-rn) ，係分別由 NMOS電晶體（410-r0至 41n-r0)至（410-rn至 41n-rn) 電連接至參考位元線408-r0至408-rn或將前述參考位元線 分隔開。當這些元件係電連接的時候，分區參考電流係連 結在一起以形成參考電流，並分別被提供給參考位元線 408-r0至 408-rn 〇 複數個子參考線（450-r0至45n-r0)至（450_rn至45n-rn)係分 別連接至電流負載電路（430-r0至43n-r0)至（430-rn至43n-rn) ，因此將分區參考電流提供給該複數個子參考線。 參考電壓設定電路420-0至420-n分別施加一參考電壓到 參考線450r至45nr。 參考電路110和120之間的差異如下所示。 在參考電路110中，從參考電壓設定電路輸出的參考電壓 ，係與包含在另一參考電壓設定電路中的至少一電流負載 電路電流鏡射連接。因此，包含在另一參考電壓設定電路 中的至少一個電流負載電路受到控制。在參考電路120中， 參考電壓係透過參考線450r至45nr輸出。參考線450r至45nr 將統稱為「參考線群組45r」。參考線群組45r概略顯示於圖6 的右下部份。 在參考電路120中，參考電壓設定電路420-0至420-n的電 流供應能力係受到參考電路110透過參考線60r至6nr所施加 的參考電壓的控制。 在這一範例中，電流負載電路（430-γΟ至43n-r0)至（430-rn 至 43n-rn)分別包括 PMOS 電晶體（470-r0 至 47η_ι*0)至（470-rn 87062 -56- 1226069 至47π-πι)。包含在參考電路110中的參考電壓設定電路的至 少一個電流負載電路中的PMOS電晶體，係與包含在參考電 路120的參考電壓設定電路的電流負載電路中的PMOS電晶 體，電流鏡射連接。 例如，連接至包含在參考電路110的參考電壓設定電路 110-0的電流負載電路30-r0中的PMOS電晶體70-rO的參考線 60r，係與包含在參考電路120的參考電壓設定電路420-0至 420-n的電流負載電路430-rO至430-rn中的PMOS電晶體 470-rO至470-rn的閘極，電流鏡射連接。因此，每個電流負 載電路430-1*0至430-rn的電流供應能力都受到控制。 同樣地，連接至參考電路110的參考線61r至6nr的電位， 分別控制包含在參考電路120的參考電壓設定電路420-0至 420-n中的電流負載電路的電流供應能力。 以下，將描述具有上述結構的參考電路120的操作。在這 一範例中，從一如圖9A所示儲存2位元資料的記憶體單元讀 取資料。 此處，圖6所示參考數字中的「η」被假設是2。因此，例 如下列元件將描述為具有下列參考數字。包含在參考電流 分區區段401-r·0中的NMOS電晶體41n-Γ0是412-r·0。電流負載 電路43n-r0是432-rO。子參考線45n-r0是452-rO。參考線45nr 是452r。參考線46nr是462r。包含在該電流負載電路432-rO 中的PMOS電晶體47n-r0是472-rO。參考位元線408-rn是 408-Γ2。參考元件 409-rn 是 409-r2。 從一可以儲存m位元資料（m是2或以上的整數）的記憶體 87062 -57- 1226069 單元中讀取資料時，n被設定成。 還假設第四狀態（圖9Α)(對應到資料「〇〇」）和第三狀態 (對應到資料「01」）之間的參考電流位準「Η」由參考元件 409_r0取得，第三狀態（對應到資料「〇i」）和帛二狀態（對應 到資料「10」）之間的參考電流位準「M」由參考元件4〇9ri 取得，以及第二狀態（對應到資料「1〇」）和第一狀態（對應 到資料「11」）之間的參考電流位準「L」由參考元件4〇9_r2 取得。因此，包含在參考線群組4&amp;的參考線45心至45以的 電位，分別變成等於包含在參考線群組6中的參考線6〇至62 的電位。 假設在參考電路12〇中，PMOS電晶體47〇1〇至4724〇、 470-rl至472-rl以及470-r2至472-r2具有相同的電晶體尺寸 ’且 NMOS 電晶體 410-r0至 412-rO、410-rl 至 412-rl 以及 410-r2至412-r2也具有相同的電晶體尺寸。（為簡單起見， NMOS電晶體410-rl至412-rl以及410-1*2至412-Γ2從圖6省 略）〇 當一適當的電壓施加到參考電流設定電路12〇-〇至12〇-2 中選定的參考元件409_r0至409_r2的閘極時，會降低參考位 元線408-r0至408-Γ2的電位。因此，會增加從包含在電流電 壓轉換電路501-r0至501-r2中的反相器400-r0至4〇〇-r2的輸 出電位。因此，包含在參考電流分區區段4〇ΐ-Γ〇至4〇1_γ2中 的每一個 NMOS 電晶體（410-r〇 至 412·Γ〇)至（410-r2 至 412-r2) 變成有導電性。 然後，根據參考位元線408-r0至408-Γ2的電位降低子參考 87062 -58- 1226069 線（450-r0至452-rO)至（450-r2至452-1*2)的電位。然後，在包 含於電流負載電路（430-rO至432-1*0)至（430-1*2至432-1*2)中的 每個 PMOS 電晶體（470-r0 至 472_r0)至（470-r2 至 472-r2)的源 極和汲極之間，產生足夠的電位差。 因此，包含在參考電路110中且以實質上相同方式操作的 PMOS電晶體70-r0、71-rl和72·ι·2，變成具有導電性。因此 ，分別連接至PMOS電晶體70-rO、71-rl和72-r2的PMOS電晶 體（470-r0至472-rO)至（470-Γ2至472-r2)也變成具有導電性。 因此，係透過子參考線（450-rO至452_r0)至（450_r2至452_r2) 和 NMOS 電晶體（410_r0 至 412·γ0)至（410-r2 至 412-r2)對參 考位元線408-r0至408-r2充電。當增加參考位元線408-rO至 408- r2的電位時，會在每個參考元件409-r0至409-Γ2的汲極 和源極之間產生電位差。因此，參考電流流動。 當參考位元線408-rO至408-1*2被充電到一規定的電位時 ，會增加從包含在電流電壓轉換電路400-r0至400-r2中的反 相器501-rO至501-r2輸出的電位。因此，會減少每一NMOS 電晶體（410-Γ0至412-rO)至（410-r2至412-r2)的電流供應能 力。 當參考位元線408-r0至408-r2的電位、流過參考元件 409- r0至409-r2的參考電流位準、以及流過NMOS電晶體 (410-r0至412-rO)至（410-r2至412-r2)的電流位準達成平衡狀 態時，會使參考電路120中電流的電位和位準變穩定。 參考元件409-1*0係設定成取得資料「00」和資料「01」 (圖9A)之間的參考電流位準「H」，參考元件409-rl係設定 87062 -59- 1226069 2::料「〇1」”料「1〇」間的參考電流位準「M」， 及參考元件9-γ2係設定成取得資料「 考電流位準I因此，參考㈣、―電 位係分別設定成相當高、中等和低。 透k連接至參考電路12〇的參考電壓設定電路^㈣至 -2的參考線撕至价，將參考電壓提供給請示的分 ^感應電路20至22。因此’分區感應電路加中的感應放大 =40可以決疋單疋電流位準是否位於相對於資料「〇〇」和 &gt;料01」之間邊界的資料「〇〇」的一側或是資料「〇 1」 的-側。這個決定的執行方式，係藉由將設定為參考電路 120中參考電流位準「η」的參考元件彻續產生的參考 線45〇r的電位與感應線5〇的電位兩相比較。 同樣地，分區感應電路21中的感應放大器41決定單元電 流位準是否位於相料資料「Q1」和資料「1()」之間邊界 的資料「01」的一側或是資料「1〇」的一側。這個決定的 執行方式，係藉由將設定為參考電路12〇中參考電流位準 「M」的參考元件4〇9_rl所產生的參考線451r的電位與感應 線5 1的電位兩相比較。分區感應電路22中的感應放大器42 決疋單元電流位準是否位於相對於資料「1〇」和資料「U」 之間邊界的資料「10」的一側或是資料ru」的一側。這 個決定的執行方式，係藉由將設定為參考電路12〇中參考電 流位準「L」的參考元件4〇9-τ2所產生的參考線452γ的電位 與感應線52的電位兩相比較。 如上所述，在這一範例的讀取電路2〇〇〇中，參考線群 87062 •60- 1226069 45r和參考線群組6彼此分隔開。此結構具有以下的效果。 在圖1讀取電路1000中，參考線60和感應線50係連接至感 應放大器40的輸入。該參考線60具有包含在該參考電路11〇 的PMOS電晶體70-r0的一閘極電容和一汲極電容、子參考線 50-r0的一線電容、PMOS電晶體70的一閘極電容和感應放大 器的一輸入端子電容等。 感應線50有該感應線50的一線電容、該感應放大器的一 輸入端電容等。 因此，參考線60的電容通常大於感應線50的電容。參考 線60和感應線50之間的電容差，會在雜訊傳送至電源供應 時產生例如擺動差，直到參考電壓和感應電壓達到電穩定 後才停止。該過程同樣適用其他感應放大器41至4n。這被 視為會大幅影響使用讀取電路1 〇〇〇從記憶體單元讀取資料 所需之時間。 相反地，在第三個範例的讀取電路2〇〇〇中，用於控制電 流負載電路的電流供應能力的參考線60至6n，可以與輸入 至感應放大器40至4n的參考線45 Or至45 nr分隔開。因此，在 感應放大器40至4n兩末端信號之間的電容差，以及因雜訊 或類似事物所導致的上述影響，可以被減少。這放大讀取 操作極限。讀取電路2〇〇〇較適用於多層式記憶體單元。 (範例4) 在第一至第二範例中，包含在單元電流分區區段i中的 NMOS電晶體10至in係設定成具有相同的電晶體尺寸以及 具有相同的閘極電位。因此，NM〇s電晶體1〇至匕具有相等 87062 -61 - 1226069 的電流供應能力。 同樣地，在第一至第三範例中，包含在參考電流分區區 段Ι-rO至丨—⑺的NM〇s電晶體（丨^…至丨^⑴至（i〇_m至im) 係叹疋成具有相同的電晶體尺寸，且具有相同的閘極電位 因此’ NMOS電晶體（10_r0至ln_r0)至（l〇-rn至in_rn)具有 相等的電流供應能力。 本發明並不受限於此種具體實施例。 在本發明的第四範例中，最佳化每一 NM〇s電晶體的電流 供應能力以進一步放大操作極限。 以下將參考圖4、7和8說明第四範例的讀取電路和參考電 路與第一至第三範例之不同點。 在這一範例中，也將描述從一如圖9A所示可以儲存複數 個位元資料的多層式記憶體單元中讀取資料的電路結構。 此範例參考的圖式中的參考數字裡的「η」被假設是2。 在這一範例中，讀取電路的一單元電流分區區段包括具 有不同電晶體尺寸的NMOS電晶體10至12。 包含在參考電路11〇中的每_NM〇s電晶體丨^⑼至i2 r〇 、l〇-rl至12^1和1〇42至12_γ2的電流供應能力，都以實質上 像對應NMOS電晶體的電流供應能力的相同方式設定。 如上所述，參考線60至62的電位具有參考線6〇&gt;參考線 61&gt;參考線62的關係。電流負載電路3〇至32的電流供應能力 具有電流負載電路30&lt;電流負載電路3 1&lt;電流負載電路32的 關係。 可實現上述關係的理由為：施加至參考線6〇的電壓對應 87062 -62- 1226069 到參考電流位準「Η」，且施加至參考線62的電壓對應到參 考电流位準「L」’後者是較大量的電流。 在描述其中NMOS電晶體10至12具有不同電流供應能力 的具體實施例之前，將先描述其中NM〇s電晶體1〇至12具有 相同電流供應能力的具體實施例。 圖7係一統計圖，說明當NMOS電晶體1〇至12具有相同的 电流供應能力（也就是說，相同的電晶體尺寸）時，每個 NMOS電晶體10至12的單元電流和源極—汲極電流之間的 關係。 該單元電流係藉由結合流過NMOS電晶體1〇至12的分區 單元電流而取得。因此，源極一汲極電流的總位準與單元 電流位準相等。 當單元電流位準位於參考電流位準rL」的附近時，流過 NMOS電晶體12的分區單元電流對單元電流有最高的貢獻 比（點c)。導致這個結果的原因為電流負載電路％至w具有 不同的電流供應能力。如圖7所示，NM〇s電晶體⑺和丨丨無 法提供比相關電流負載電路的電流位準高的電流位準。因 此，在三個NMOS電晶體1〇至12之中提供有最高位準電流的 電流NMOS電晶體12，對單元電流貢獻最大。 在這情況下，限制住包含在電流負載電路3〇至32中的流 過每個PMOS電晶體70至72的電流。因此，NM〇s電晶體1〇 至12實質上對感應線50至52的電位毫無影響。 當單元電流位準位在參考電流位準「H」（點八）的附近時 ，NMOS電晶體1〇至12的源極_汲極電流具有實質上相同的 87062 -63 - 1226069 位準。理由說明如下： 雖然電流負載電路30至32具有不同的電流供應能力，但 是單元電流位準是低的，因此分區單元電流不會受到包含 在電流負載電路30至32中的PMOS電晶體7〇至72太多的 限制。因此，感應線50至52的電位只略為下降，所以還是 高。 因此，在每一NMOS電晶體10至12的源極和汲極之間產生 大的電位差，且NMOS電晶體10至12在一飽和區域（一五極 真艾管區域）操作，並在實質上相同的電流位準達到飽和。 因此，流過NMOS電晶體1〇至12的分區單元電流具有實質上 相同的位準，且單元電流位準約是一分區單元電流位準的3 雀上所述，單元电流位準是鬲於或低於參考電流位準 L」係由連接至NMOS電晶體12汲極的感應放大器42決定 。單元電流位準是高於或低於參考電流位準「H」係由連接 至NMOS電晶體1〇汲極的感應放大器4〇決定。 當單元電流位準是高（圖7的點c)的時候，用於決定單元 電流位準是高於或低於參考電流位準「L」的分區感應電路 22對單元電流貢獻最大。當單元電流位準是低（圖玲點八） 的時候，每個分區單元電路對單元電流的貢獻只有1/3。 /此，當單元電流位於參考電流位準「L」附近時的相斜 操作極限，係與當單疋電流位於參考電流位準「h」附近的 相對操作極限不相同。 因此’為了要實現即使是低單元電流位準時，分區感應 87062 •64- 1226069 電路仍對單元電流貢獻最大，以決定單元電流位準係高於 或低於對應參考電流位準的狀態，包含在單元電流分區區 段1中的每個NMOS電晶體的電流供應能力要設定成如下所 示。當電流負載電路30至32的對應電路的電流供應能力較 高時，每個NMOS電晶體10至12的電流供應能力係設定成較 低，而當電流負載電路30至32的對應電路的電流供應能力 較低時，則設定成較高。 在這個範例中，電流負載電路30至32的電流供應能力具 有電流負載電路30〈電流負載電路3 1〈電流負載電路3 2的關 係。因此，NMOS電晶體10至12的電流供應能力被設定成具 有NMOS電晶體10&gt;NMOS電晶體11&gt;NM0S電晶體12的關 係。 包含在參考電路110中的NMOS電晶體的電流供應能力也 被設定成具有NMOS電晶體10-r0至10-r2&gt;NMOS電晶體 Π-rO至 ll-r2&gt;NMOS 電晶體 12-rO至 12_r2的關係。 圖8是一統計圖，說明當NMOS電晶體10至12的電流供應 能力具有NMOS電晶體10&gt;NMOS電晶體ll&gt;NMOS電晶體12 的關係時，單元電流和源極一沒極電流之間的關係。 當單元電流位準高時，單元電流位準會受限於電流負載 電路30至32的電流供應能力。因此，讀取電路和參考電路 的操作實質上與圖7的情況相同。 當單元電流位準低時，即使當Ν Μ Ο S電晶體10至12在飽和 區域操作時，NMOS電晶體10至12仍會在不同電流位準達到 飽和。因為NMOS電晶體10至12具有不同的電流供應能力， 87062 -65- 1226069 所以發生這種狀況。 例如，NMOS電晶體10至12的電流供應能力位準設定為3 • 2· 1。當單元電流位準位於參考電流「h」（點a，）附近時 ’對單7G電流而1 ’流過連接至分區感應電路2〇&amp;NM〇s 電晶體10的分區單元電流的貢獻是3/6。對單元電流而言， /虎過連接至分區感應電路2丨的NM〇s電晶體丨丨的分區單元 電流的貢獻是2/6。對單元電流而言，流過連接至分區感應 電路22的NMOS電晶體12的分區單元電流的貢獻是1/6。 因此，即使當單元電流位準是低的時候，用於決定單元 電流位準是高於或低於參考電流位準「H」的分區感應電路 20仍可對單7〇電流貢獻最大。因&amp;，可以縮小單元電流位 準所導致的相對操作極限差，實現能夠以較高速操作和具 有較高讀取精密度的讀取電路。 在本發明的第四範例中，描述1^]^〇8電晶體1〇至12的電流 供應能力。更明確地說，NM〇s電晶體的電流供應能力可根 據电日EI體尺寸、閘極電位或兩者來加以調整。 如上所述，根據本發明的讀取電路兼具以下兩點⑴具有 以較高讀取速度操作優點的平行感應系統，以及（ί〇提供較 大操作極限的非線性負載特性。因此，根據本發明的讀取 電路適用於多層式記憶體單元。 根據本發明的參考電路可以很容易地產生本發明讀取電 路所需的一參考電壓，並允許包含在讀取電路和參考電路 中的複數個電晶體具有同等的配置模式。因此，該參考電 路很容昜就接受製造流程期間所導致的電晶體特性變化， 87062 • 66 · 1226069 並適用於多層式記憶體單元。 在每個單元電流分區區段和參考電流分區區段都具有複 數個NMOS電晶體，而且將每個NMOS電晶體的電流供應能 力都最佳化的具體實施例中，可縮小單元電流位準所導致 的相對操作極限差。因此，可提供能夠執行較高速操作且 具有較高讀取精密度的讀取電路。 包含根據本發明的讀取電路及/或參考電路的半導體記 憶體裝置，可以執行較高速的操作並具有較大的操作極限 和較高的讀取精密度。 各種不同的其他修改，對本發明的專家是顯而易見，且 本發明的專家可立即進行，而不脫離本發明的範疇和精神 。因此，隨附的申請專利範圍並不希望受限於本文中提供 的說明，而應對該等申請專利範圍作廣泛的解釋 【圖式簡單說明】 圖1係根據本發明的第一範例之半導體記憶裝置的示意 ΓΕΙ · 圃， 圖2係电路圖，說明圖1顯示的半導體記憶體裝置的一 記憶體單元陣列； 圖3係統叶圖，說明根據本發明第一範例的讀取電路的 示範特性； 圖4疋一電路圖，說明根據本發明的第二範例的參考電 路； 圖5係t路圖，說明根據本發明的第三範例之半導體記 憶裝置； 87062 •67- !226〇69 圖6是一電路圖 路； ，說明根據本發明的第三範例的參寺電 圖7是-統計圖，說明根據本發明第一範例的讀取 早兀電流分區區段的示範特性； 圖8是一統計圖，說明根據本發 w 豕+赏明罘四範例的1買取電路的 單元電流分區區段的示範特性； 圖9A顯示在-傳統多層式記憶體單元中的單元電流和資 料之間的示範關係； 圖9B顯示在一傳統兩層式記憶體單元中的單元電流和資 料之間的示範關係； 圖10是一電路圖，說明傳統分時感應型讀取電路； 圖11是一電路圖，說明傳統平行感應型讀取電路； 圖12顯示當從一可儲存2位元資料的記憶體單元讀取資 料的時候，該資料和感應放大器輸出之間的示範關係； 圖13顯示接收感應放大器輸出的邏輯電路的示範事實 表； 圖14A是一電路圖，說明具有線性負載特性的讀取電路； 圖14B是一統計圖’說明在圖14 A中顯示的電路示範特 性； 圖15A是一電路圖，說明具有非線性負載特性的讀取電路 :以及 圖1 5 B是一統計圖’說明在圖1 5 A中顯示的電路示範特 性。 87062 -68 - 1226069 【圖式代表符號說明】 1 5，6，6r，45r 10, 11，12, In, 410-r0〜41n_r0, 410-rn 〜41n-rn 20, 21，2n 30, 31，3n，30-r0 40, 41，4n 50, 51，52, 5n 50n〜5nr，60，61，62，6n， 60r〜6nr，61r〜6nr 470-r0〜47n-r0，470-rn〜47n-rn， 70, 71，7n，70-r0 100 101 早元電流分區區段 參考線群組 NMOS電晶體 分區感應電路 電流負載電路 感應放大器 感應線 參考線 PMOS電晶體 電流電壓轉換電路 反相器 110, 120 150 1000, 2000, H100, 200, 300 1500, 2500 WL1, WL2, WL3, WL4 BL1，BL2, BL3, BL4, 8 參考電路 記憶體單元陣列 讀取電路 半導體記憶體裝置 字線 位元線, 61r and 62r PMOS transistors 70-r, 70-r2, 71-r0, 71-r2, 72-rO and 72-rl also become conductive. Therefore, the sub-reference lines (5〇_r〇 to 52-rO) to (50-r2 to 52_r2) and NMOS transistors (ΐ〇-Γ〇 to 12_Γ〇) to (10-r2 to 12-r2) The reference bit lines 8-Γ0 to 8-r2 are charged. When the potential of the bit lines 8-r0 to 8-r2 is increased, a potential difference is generated between the drain and source of each reference element 9_Γ0 to ... r2. Therefore, the reference current flows. When the reference bit lines 8-rO to 8-r2 are charged to a predetermined potential, the inverters 101-r0 included in the current-voltage conversion circuit 100-Γ0 to 100-r2 are added. Potential output to 101-r2. Therefore, the current supply capability of each NMOS transistor (10-rO to 12-rO) to (10-r2 to 12-r2) is reduced. When the potential of the reference bit line 8-rO to 8-r2, the reference current level flowing through the reference element 9-Γ〇 to 9-r2, and the NMOS transistor (丨 〇_r〇 to 丨 2_r) 〇) When the current levels of (10-r2 to 12_r2) reach an equilibrium state, the potential and level of the current in the reference circuit 110 become stable. The reference element 9-Γ〇 is set to obtain the reference current level "Hj" between the data "〇〇" and the data "〇1" (Figure 9A), and the reference element 9_Γΐ is set to obtain the data "〇1" and the data " The reference current level "M" between 10 "and the reference 7G 9 · Γ2 are set to obtain the reference current level" L "between the data" 10 "and the data" u ". Therefore, the potentials of the reference lines 601 :, 61r, and 62r are set to be fairly high, medium, and low, respectively. The PMOS transistor 70 of the partition induction circuit 20 and the PMOS transistor 70-r0 of the reference voltage setting circuit 110_0 in FIG. 1 are connected to each other in a current mirror. The reference voltage output from the reference voltage setting circuit 110_0 (the potential of the reference line 60r in FIG. 4) 87062-51-1226069 is supplied to the partition induction circuit 20. The reference voltage setting circuit 110-0 includes three current load circuits 304 to 32_r0. The current load circuit after removing the current load circuit 3 ^ 0 is connected as shown below to determine the reference voltage, that is, the current load circuit 31-1 &gt; 0 and 32_r0. The current load circuit 31-Γ〇 is connected to the reference line 6 丨, which is then connected to the active current load circuit 31-rl to determine the potential of the reference line 61. The current load circuit 32-rO is connected to the reference line 62, which is then connected to the active current load circuit 32-r2 to determine the potential of the reference line 62. Therefore, the current supply capability of each of the current load circuits 31-rO and 32 ^ 0 is controlled. Similarly, the reference voltages are also supplied through the reference lines 61 and 62 to the current load circuits 31 and 32 included in the partition induction circuits 21 and 22 (FIG. 1), respectively. Therefore, the current supply capability of the current load circuit 31 of the partition induction circuit 21 shown in FIG. 1 and the current load circuit 31-r0 of the reference voltage setting circuit 丨 丨 shown in FIG. 4 are controlled by the reference line 61. Similarly, the current supply capability of the current load circuit 32 of the partition induction circuit 22 shown in FIG. 1 and the current load circuit of the reference voltage setting circuit 110-0 shown in FIG. 4 are controlled by the reference line 62. Therefore, the cell current flowing through the memory cell 9 and the reference current flowing through the reference element 9-Γ0 are substantially affected in the same manner. Especially when the cell current level and the reference current level are equal to each other, the cell current and the reference current are affected in exactly the same way. Such effects are canceled from the read circuit 1000 and the reference circuit U0. Then, the PMOS transistor 70 included in the current load circuit 30 and the pM〇s transistor 70-〇 current mirror included in the current-load Lei Mei circuit 30-r〇 shown in FIGS. 87062-52-1226069 15A Radio connection and display as shown in the figure] ^ ^ Figure 1 5B non-linear load characteristics, which can provide a larger operating limit. Therefore, the sense amplifier 40 in the 'segment sensing circuit 20 can determine whether the cell current level is on the-side of the data "OO" or the data "Qi" with respect to the boundary between the data "〇〇" and the data "〇1". -side. This decision will be made based on the reference voltage of the reference element 9__ set to the reference current level "H". Similarly, the inductive amplifier 分区 in the zone induction circuit 21 can determine whether the unit current level is located on the-side of the data "G1" relative to the boundary between the data "01" and the data "1〇" or the decision This will be performed on the basis of the reference voltage generated by the reference element W of the reference current level "M". The sense amplifier 42 in the zone sensing circuit 22 can determine whether the unit current level is located on the _ side of the data "1G" or the-side of the data "u" with respect to the boundary between the data "10" and the data "U". This decision will be performed on the basis of the reference voltage generated by the reference element 9-Γ2 set as the reference current level%. As mentioned above, the reference circuit of this example can easily generate a diagram] The reference voltage required to read the circuit surface shown in FIG. 5 also allows the transistors included in the read circuit surface and the reference circuit 11G to have the same configuration mode. Therefore, circuits with the same transistor characteristics can be easily produced. Therefore, the reference circuit of this example is quite easy to accept the change of transistor characteristics caused during the manufacturing process, and it is suitable for multilayer memory cells. (Example 3) 87062 -53-1226069 In the third example of the present invention Φ L + A- .L * ^, A »View 1 'will describe a semiconductor memory device including two reference circuits. FIG. 5 schematically shows a structure of a semiconductor memory device 2500 according to a third example of the present invention. The semiconductor memory device 25GG includes a memory cell array 15 and a reading circuit 2000 including a plurality of memory cells for reading data from one of the plurality of memory cells, and a reference circuit 110 and 120, for generating a reference voltage for reading data. In the following description, elements having substantially the same functions as the first and second examples have the same reference numerals, and the same functions will not be described again. The master circuit 2000 includes a plurality of partition induction circuits 20 to 211 and a current-voltage conversion circuit 100. Two reference circuits (reference circuits 110 and 120) supply two types of reference voltages to each of the partition induction circuits 20 to 2n. The reference circuit 120 supplies a type of reference voltage to each of the sense amplifiers 40 to 4n via a first reference line group 5 (including reference lines 50n to 5nr). The reference circuit 110 passes a second reference line group 6 (including reference lines 60 to 6n) provides another type of reference voltage to each of the current load circuits 30 to 3n to control the current supply capability of each of the current load circuits 30 to 311. The reference circuits 110 and 120 can be used as a reference circuit. The reference circuits 110 and 120 are not included in the read circuit 2000 of FIG. 5. The invention is not limited to this structure. The read circuit 2000 may include reference circuits 110 87062 -54 · 1226069 and 120. FIG. 6 is a partial circuit diagram of the reference circuit 120 shown in FIG. 5. As shown in FIG. 6, the reference circuit 120 includes a plurality of reference voltage setting circuits 420-0 to 420-n. The reference voltage setting circuits 420-0 to 420-n provide a reference current through the reference bit lines 408-r0 to 408-rn to the selected reference elements 409-rO to 409-m (in the plurality of reference elements), and then the current The reference currents passing through the reference elements 409-r0 to 409-rn are converted into reference voltages, respectively. For the reference elements 409-r0 to 409-rn, use a reference cell with the same structure and the same characteristics as the memory cell whose limiting voltage is tightly adjusted to obtain an appropriate reference current. The reference voltage setting circuits 420-0 to 420-n include current-voltage conversion circuits 400-rO to 400-rn and a plurality of current load circuits 430-r0 to 43n-r0, 430-r 1 to 43n-rl, and 430- rn to 43n-rn 〇 For simplicity, FIG. 6 does not show the internal structure of the current-voltage conversion circuits 400-rl to 400-rn. The current-voltage conversion circuits 400-rl to 400-m have the same internal structure as the current-voltage conversion circuits 400-r0. The current-voltage conversion circuit 400 · ι · 0 to 400-rn includes reference current division sections 401-rO to 401-m for connecting or separating the sub-reference lines 450 through reference bit lines 408-r0 to 408-rn. -rO to 45n-r0, 450-rl to 45n-rl and 450-rn to 45n-rn and reference units 409-r0 to 409-rn, and also include inverters 501-r0 to 501-rn to control the reference The current partition sections 401-rO to 401-rn. In this example, the reference current partition sections 401-rO to 401-m include a plurality of NMOS transistors (410-r0 to 41n-r0) to (410-rn to 41n-rn), respectively, which have a gate And a source connected to each other via inverters 501-r0 to 501-m 87062-55-1226069. The plurality of sub-reference lines (450-r0 to 45n-rn) to (450-rn to 45n-rn) are respectively composed of NMOS transistors (410-r0 to 41n-r0) to (410-rn to 41n-rn). Connect to the reference bit lines 408-r0 to 408-rn or separate the aforementioned reference bit lines. When these components are electrically connected, the partitioned reference currents are linked together to form a reference current, and are provided to the reference bit lines 408-r0 to 408-rn, respectively. A plurality of sub-reference lines (450-r0 to 45n-r0) ) To (450_rn to 45n-rn) are connected to the current load circuits (430-r0 to 43n-r0) to (430-rn to 43n-rn), respectively, so the partition reference current is provided to the plurality of sub-reference lines. The reference voltage setting circuits 420-0 to 420-n apply a reference voltage to the reference lines 450r to 45nr, respectively. The differences between the reference circuits 110 and 120 are shown below. In the reference circuit 110, the reference voltage output from the reference voltage setting circuit is galvanically connected to at least one current load circuit included in another reference voltage setting circuit. Therefore, at least one current load circuit included in another reference voltage setting circuit is controlled. In the reference circuit 120, the reference voltage is output through the reference lines 450r to 45nr. The reference lines 450r to 45nr will be collectively referred to as "reference line group 45r". The reference line group 45r is schematically shown in the lower right part of FIG. 6. In the reference circuit 120, the current supply capability of the reference voltage setting circuits 420-0 to 420-n is controlled by the reference voltage applied by the reference circuit 110 through the reference lines 60r to 6nr. In this example, the current load circuits (430-γ0 to 43n-r0) to (430-rn to 43n-rn) include PMOS transistors (470-r0 to 47η_ι * 0) to (470-rn 87062 -56) -1226069 to 47π-πι). The PMOS transistor in the at least one current load circuit of the reference voltage setting circuit included in the reference circuit 110 is connected to the PMOS transistor in the current load circuit of the reference voltage setting circuit of the reference circuit 120 by a current mirror. For example, the reference line 60r connected to the PMOS transistor 70-rO in the current load circuit 30-r0 included in the reference voltage setting circuit 110-0 of the reference circuit 110 is connected to the reference voltage setting circuit 420 included in the reference circuit 120. The gates of the PMOS transistors 470-rO to 470-rn in the current load circuits 430-rO to 430-rn of -0 to 420-n are connected in a current mirror. Therefore, the current supply capability of each of the current load circuits 430-1 * 0 to 430-rn is controlled. Similarly, the potentials of the reference lines 61r to 6nr connected to the reference circuit 110 control the current supply capabilities of the current load circuits included in the reference voltage setting circuits 420-0 to 420-n of the reference circuit 120, respectively. Hereinafter, the operation of the reference circuit 120 having the above-mentioned structure will be described. In this example, data is read from a memory cell that stores 2-bit data as shown in Figure 9A. Here, "η" in the reference numerals shown in FIG. 6 is assumed to be 2. Therefore, for example, the following elements will be described as having the following reference numerals. The NMOS transistor 41n-Γ0 contained in the reference current partition section 401-r · 0 is 412-r · 0. The current load circuit 43n-r0 is 432-rO. The sub-reference lines 45n-r0 are 452-rO. The reference line 45nr is 452r. The reference line 46nr is 462r. The PMOS transistors 47n-r0 included in the current load circuit 432-rO are 472-rO. The reference bit line 408-rn is 408-Γ2. The reference element 409-rn is 409-r2. When reading data from a unit that can store m-bit data (m is an integer of 2 or more) 87062 -57-1226069, n is set to. It is also assumed that the reference current level “Η” between the fourth state (FIG. 9A) (corresponding to the data “〇〇”) and the third state (corresponding to the data “01”) is obtained by the reference element 409_r0, and the third state ( The reference current level "M" corresponding to the data "〇i") and the second state (corresponding to the data "10") is obtained by the reference element 409ri, and the second state (corresponding to the data "1〇" ) And the first state (corresponding to the data "11"), the reference current level "L" is obtained by the reference element 409_r2. Therefore, the potentials of the reference lines 45 to 45 included in the reference line group 4 &amp; become potentials equal to the reference lines 60 to 62 included in the reference line group 6, respectively. Assume that in reference circuit 12, PMOS transistors 4701 to 4724, 470-rl to 472-rl, and 470-r2 to 472-r2 have the same transistor size 'and NMOS transistors 410-r0 to 412 -rO, 410-rl to 412-rl, and 410-r2 to 412-r2 also have the same transistor size. (For simplicity, the NMOS transistors 410-rl to 412-rl and 410-1 * 2 to 412-Γ2 are omitted from FIG. 6). When an appropriate voltage is applied to the reference current setting circuit 12 to 12 to 12. When the gate of the reference element 409_r0 to 409_r2 selected in -2 is selected, the potential of the reference bit lines 408-r0 to 408-Γ2 is lowered. Therefore, the output potentials of the inverters 400-r0 to 400-r2 included in the current-voltage conversion circuits 501-r0 to 501-r2 are increased. Therefore, each of the NMOS transistors (410-r0 to 412 · Γ〇) to (410-r2 to 412-r2) included in the reference current partition section 4〇-Γ〇 to 4〇1_γ2 becomes conductive Sex. Then, the potential of the sub-reference 87062 -58-1226069 line (450-r0 to 452-rO) to (450-r2 to 452-1 * 2) is lowered according to the potential of the reference bit lines 408-r0 to 408-Γ2. Then, each of the PMOS transistors (470-r0 to 472_r0) to (470) included in the current load circuits (430-rO to 432-1 * 0) to (430-1 * 2 to 432-1 * 2) -r2 to 472-r2) creates a sufficient potential difference between the source and the drain. Therefore, the PMOS transistors 70-r0, 71-rl, and 72 · ι · 2 included in the reference circuit 110 and operating in substantially the same manner become conductive. Therefore, the PMOS transistors (470-r0 to 472-rO) to (470-r2 to 472-r2) connected to the PMOS transistors 70-rO, 71-rl, and 72-r2, respectively, also become conductive. Therefore, the reference bit lines 408-r0 to 408-r0 through the sub-reference lines (450-rO to 452_r0) to (450_r2 to 452_r2) and NMOS transistors (410_r0 to 412 · γ0) to (410-r2 to 412-r2) 408-r2 charging. When the potential of the reference bit lines 408-rO to 408-r2 is increased, a potential difference is generated between the drain and source of each reference element 409-r0 to 409-Γ2. Therefore, the reference current flows. When the reference bit lines 408-rO to 408-1 * 2 are charged to a prescribed potential, the inverters 501-rO to 501-R included in the current-voltage conversion circuits 400-r0 to 400-r2 are added. r2 output potential. Therefore, the current supply capability of each NMOS transistor (410-Γ0 to 412-rO) to (410-r2 to 412-r2) is reduced. When the potential of the reference bit line 408-r0 to 408-r2, the reference current level flowing through the reference element 409-r0 to 409-r2, and the NMOS transistor (410-r0 to 412-rO) to (410 When the current levels of -r2 to 412-r2) reach equilibrium, the potential and level of the current in the reference circuit 120 become stable. The reference element 409-1 * 0 is set to obtain the reference current level "H" between the data "00" and the data "01" (Figure 9A). The reference element 409-rl is set to 87062 -59-1226069 2: The reference current level "M" between the material "〇1" and the material "10", and the reference element 9-γ2 is set to obtain the data. "Test the current level I. Therefore, the reference ㈣ and ―potential system are set to be equivalent. High, medium, and low. The reference voltage setting circuit connected to the reference circuit 12 is connected to the reference line, and the reference voltage is supplied to the sub-induction circuits 20 to 22 on request. Therefore, 'zone induction The inductive amplification in the circuit plus = 40 can determine whether the single current level is located on the side of the data "〇〇" or the data "〇1" relative to the boundary between the data "〇〇" and &gt; Material 01 ". -Side. This decision is performed by comparing the potential of the reference line 45r with the potential of the induction line 50, which is continuously generated by the reference element set to the reference current level "η" in the reference circuit 120. Similarly, the sense amplifier 41 in the zone sensing circuit 21 determines whether the cell current level is located on the side of the data "01" or the data "1〇" on the boundary between the phase data "Q1" and the data "1 ()". The side. This decision is performed by comparing the potential of the reference line 451r generated by the reference element 409_rl set to the reference current level "M" in the reference circuit 120 to the potential of the sensing line 51. The sense amplifier 42 in the zone sensing circuit 22 determines whether the unit current level is located on the side of the data "10" or the side of the data ru relative to the boundary between the data "1" and the data "U". This decision is performed by comparing the potential of the reference line 452γ generated by the reference element 409-τ2 set to the reference current level "L" in the reference circuit 120 to the potential of the induction line 52. As described above, in the read circuit 2000 of this example, the reference line group 87062 • 60-1226069 45r and the reference line group 6 are separated from each other. This structure has the following effects. In the reading circuit 1000 of FIG. 1, a reference line 60 and a sense line 50 are connected to the input of the sense amplifier 40. The reference line 60 has a gate capacitor and a drain capacitor included in the PMOS transistor 70-r0 of the reference circuit 110, a one-line capacitor of the sub-reference line 50-r0, a gate capacitor of the PMOS transistor 70, and The capacitance of an input terminal of the sense amplifier. The induction line 50 includes a one-line capacitance of the induction line 50, an input terminal capacitance of the induction amplifier, and the like. Therefore, the capacitance of the reference line 60 is generally larger than the capacitance of the induction line 50. The difference in capacitance between the reference line 60 and the induction line 50 will cause, for example, a wobble difference when noise is transmitted to the power supply, and it will not stop until the reference and induced voltages have reached electrical stability. This process is also applicable to other sense amplifiers 41 to 4n. This is considered to significantly affect the time required to read data from the memory cell using the read circuit 1000. In contrast, in the read circuit 2000 of the third example, the reference lines 60 to 6n for controlling the current supply capability of the current load circuit may be the same as the reference lines 45 or to input to the sense amplifiers 40 to 4n. 45 nr separated. Therefore, the capacitance difference between the signals at both ends of the inductive amplifier 40 to 4n, and the above-mentioned influence caused by noise or the like can be reduced. This magnifies the read operation limit. The read circuit 2000 is more suitable for multi-layer memory cells. (Example 4) In the first to second examples, the NMOS transistors 10 to in included in the cell current partition section i are set to have the same transistor size and the same gate potential. Therefore, the NMOS transistor 10 to Dagger has an equivalent current supply capacity of 87062 -61-1226069. Similarly, in the first to third examples, the NMMOS transistors (丨 ^ ... to 丨 ^ ⑴ to (i〇_m to im)) included in the reference current partition section 1-rO to 丨 -⑺ Sighed to have the same transistor size and the same gate potential, so the 'NMOS transistors (10_r0 to ln_r0) to (10-rn to in_rn) have equal current supply capabilities. The invention is not limited to this Such a specific embodiment. In the fourth example of the present invention, the current supply capability of each NMOS transistor is optimized to further enlarge the operating limit. The reading of the fourth example will be explained below with reference to FIGS. 4, 7 and 8. The differences between the fetch circuit and the reference circuit from the first to third examples. In this example, the reading of data from a multi-level memory cell that can store multiple bits of data as shown in FIG. 9A will also be described. Circuit structure. "Η" in the reference number in the figure referenced by this example is assumed to be 2. In this example, a unit current partition section of the read circuit includes NMOS transistors with different transistor sizes. To 12. Every _NM〇s included in the reference circuit 11 The current supply capabilities of the crystals ^^ to i2 r0, 10-rl to 12 ^ 1, and 1042 to 12_γ2 are all set in substantially the same manner as the current supply capabilities of corresponding NMOS transistors. As described above, The potentials of the reference lines 60 to 62 have the relationship of the reference line 60 &gt; reference line 61 &gt; reference line 62. The current supply capability of the current load circuits 30 to 32 has a current load circuit 30 &lt; current load circuit 3 1 &lt; current load circuit The reason for achieving the above relationship is that the voltage applied to the reference line 60 corresponds to 87062 -62-1226069 to the reference current level "Η", and the voltage applied to the reference line 62 corresponds to the reference current level " L "'the latter is a relatively large amount of current. Before describing specific embodiments in which NMOS transistors 10 to 12 have different current supply capabilities, specific examples in which NMOS transistors 10 to 12 have the same current supply capability will be described first. Embodiment 7 FIG. 7 is a statistical diagram illustrating that when NMOS transistors 10 to 12 have the same current supply capability (that is, the same transistor size), the unit power of each NMOS transistor 10 to 12 And source-drain current. The cell current is obtained by combining the divided cell currents flowing through the NMOS transistors 10 to 12. Therefore, the total source-drain current level and the cell current The levels are equal. When the cell current level is near the reference current level rL ", the partition cell current flowing through the NMOS transistor 12 has the highest contribution ratio to the cell current (point c). The cause of this result is the current The load circuits% to w have different current supply capabilities. As shown in FIG. 7, NMOS transistors ⑺ and 丨 丨 cannot provide a current level higher than the current level of the relevant current load circuit. Therefore, the current NMOS transistor 12 which provides the highest level current among the three NMOS transistors 10 to 12 contributes the most to the cell current. In this case, the current contained in the current load circuits 30 to 32 through each of the PMOS transistors 70 to 72 is restricted. Therefore, the NMOS transistors 10 to 12 have substantially no influence on the potentials of the induction lines 50 to 52. When the cell current level is near the reference current level "H" (point eight), the source-drain currents of the NMOS transistors 10 to 12 have substantially the same 87062 -63-1226069 level. The reason is as follows: Although the current load circuits 30 to 32 have different current supply capabilities, the unit current level is low, so the partitioned unit current is not affected by the PMOS transistors 70 to 32 included in the current load circuits 30 to 32. 72 too many restrictions. Therefore, the potentials of the sensing lines 50 to 52 only drop slightly, so they are still high. Therefore, a large potential difference is generated between the source and the drain of each of the NMOS transistors 10 to 12, and the NMOS transistors 10 to 12 operate in a saturation region (a five-pole true moxa region) and substantially The same current level is saturated. Therefore, the divisional cell currents flowing through the NMOS transistors 10 to 12 have substantially the same level, and the unit current level is about 3 times the divisional unit current level. As described above, the unit current level is less than The reference level L ″ or lower is determined by the sense amplifier 42 connected to the drain of the NMOS transistor 12. Whether the cell current level is higher or lower than the reference current level "H" is determined by the sense amplifier 40 connected to the NMOS transistor 10 drain. When the cell current level is high (point c in FIG. 7), the partition induction circuit 22 for determining whether the cell current level is higher or lower than the reference current level "L" contributes the most to the cell current. When the cell current level is low (Figure 8), the contribution of each zone cell circuit to the cell current is only 1/3. / The phase-slope operation limit when the unit current is near the reference current level "L" is different from the relative operation limit when the unitary current is near the reference current level "h". Therefore, in order to achieve even the low unit current level, the zone induction 87062 • 64-1226069 circuit still contributes the most to the unit current to determine the unit current level is higher or lower than the corresponding reference current level, including The current supply capability of each NMOS transistor in the cell current division section 1 is set as shown below. When the current supply capacity of the corresponding circuits of the current load circuits 30 to 32 is high, the current supply capacity of each NMOS transistor 10 to 12 is set to be low, and when the current supply of the corresponding circuits of the current load circuits 30 to 32 is low When the ability is low, set it high. In this example, the current supply capability of the current load circuits 30 to 32 has a relationship of the current load circuit 30 <the current load circuit 3 1 <the current load circuit 32. Therefore, the current supply capability of the NMOS transistors 10 to 12 is set to have a relationship with the NMOS transistor 10 &gt; NMOS transistor 11 &gt; NM0S transistor 12. The current supply capability of the NMOS transistor included in the reference circuit 110 is also set to have NMOS transistor 10-r0 to 10-r2 &gt; NMOS transistor Π-rO to ll-r2 &gt; NMOS transistor 12-rO to 12_r2 relationship. FIG. 8 is a statistical diagram illustrating the relationship between the cell current and the source-polarity current when the current supply capability of the NMOS transistors 10 to 12 has the relationship of the NMOS transistor 10 &gt; NMOS transistor 11 &gt; NMOS transistor 12 relationship. When the unit current level is high, the unit current level is limited by the current supply capability of the current load circuits 30 to 32. Therefore, the operations of the read circuit and the reference circuit are substantially the same as in the case of FIG. 7. When the cell current level is low, the NMOS transistors 10 to 12 reach saturation at different current levels even when the NM transistor 10 to 12 are operating in a saturation region. This situation occurs because the NMOS transistors 10 to 12 have different current supply capabilities, 87062 -65-1226069. For example, the current supply capability level of NMOS transistors 10 to 12 is set to 3 • 2 · 1. When the cell current level is located near the reference current "h" (point a,), the contribution to the single 7G current and 1 'flowing through the partitioned cell current connected to the partitioned sensing circuit 2 &amp; NM〇s transistor 10 is 3/6. As for the cell current, the contribution of the current through the partition cell of the NMMOS transistor connected to the partition induction circuit 2 is 2/6. As for the cell current, the contribution of the partition cell current flowing through the NMOS transistor 12 connected to the partition induction circuit 22 is 1/6. Therefore, even when the unit current level is low, the zone induction circuit 20 for determining whether the unit current level is higher or lower than the reference current level "H" can still contribute the most to a single 70 current. Because of &amp;, the relative operating limit difference caused by the cell current level can be reduced, and a reading circuit capable of high-speed operation and high reading precision can be realized. In the fourth example of the present invention, the current supply capability of the transistor 10 to 12 is described. More specifically, the current supply capability of the NMOS transistor can be adjusted according to the size of the EI body, the gate potential, or both. As described above, the reading circuit according to the present invention combines the following two points: a parallel induction system that has the advantage of operating at a higher reading speed, and a non-linear load characteristic that provides a larger operating limit. Therefore, according to the present invention, The reading circuit of the invention is suitable for a multi-layer memory cell. The reference circuit according to the invention can easily generate a reference voltage required by the reading circuit of the invention, and allows plural included in the reading circuit and the reference circuit. Transistors have the same configuration mode. Therefore, the reference circuit is very tolerant of transistor characteristics changes during the manufacturing process, 87062 • 66 • 1226069 and is suitable for multi-layer memory cells. In each cell current zone Both the segment and the reference current partition section have a plurality of NMOS transistors, and in a specific embodiment in which the current supply capability of each NMOS transistor is optimized, the relative operating limit difference caused by the unit current level can be reduced. Therefore, a reading circuit capable of performing higher-speed operations and having higher reading precision can be provided. The semiconductor memory device of the read circuit and / or the reference circuit can perform higher-speed operations with larger operating limits and higher read precision. Various other modifications are obvious to the experts of the present invention, and The experts of the present invention can proceed immediately without departing from the scope and spirit of the present invention. Therefore, the scope of the accompanying patent application is not intended to be limited to the description provided herein, and such patent application scope should be explained extensively [ Brief description of the drawings] Fig. 1 is a schematic diagram of a semiconductor memory device according to a first example of the present invention, and Fig. 2 is a circuit diagram illustrating a memory cell array of the semiconductor memory device shown in Fig. 1; Fig. 3 system Leaf diagrams illustrating exemplary characteristics of a read circuit according to a first example of the present invention; FIG. 4 is a circuit diagram illustrating a reference circuit according to a second example of the present invention; FIG. 5 is a t diagram illustrating a third circuit according to the present invention. Exemplary semiconductor memory device; 87062 • 67-! 226〇69 Figure 6 is a circuit diagram; FIG. 7 is a statistical diagram illustrating exemplary characteristics of reading an early current zone segment according to the first example of the present invention. FIG. 8 is a statistical diagram illustrating a 1-buying circuit according to the four examples of the present invention. Figure 9A shows an exemplary relationship between cell current and data in a conventional multi-level memory cell. Figure 9B shows the cell current and data in a conventional two-level memory cell. Exemplary relationship between data; Figure 10 is a circuit diagram illustrating a conventional time-sharing inductive reading circuit; Figure 11 is a circuit diagram illustrating a conventional parallel inductive reading circuit; and Figure 12 shows when a 2-bit data can be stored from a slave When the memory unit reads the data, the exemplary relationship between the data and the output of the sense amplifier; Figure 13 shows an exemplary fact table of the logic circuit receiving the output of the sense amplifier; Figure 14A is a circuit diagram illustrating a read with linear load characteristics Take the circuit; Figure 14B is a statistical diagram illustrating the exemplary characteristics of the circuit shown in Figure 14A; Figure 15A is a circuit diagram illustrating a read with non-linear load characteristics Passage: and Figure 1 5 B is a chart 'Laid illustrates an exemplary circuit shown in FIG. 1 5 A. 87062 -68-1226069 [Description of Symbols Representing Drawings] 1 5, 6, 6r, 45r 10, 11, 12, In, 410-r0 ~ 41n_r0, 410-rn ~ 41n-rn 20, 21, 2n 30, 31, 3n, 30-r0 40, 41, 4n 50, 51, 52, 5n 50n ~ 5nr, 60, 61, 62, 6n, 60r ~ 6nr, 61r ~ 6nr 470-r0 ~ 47n-r0, 470-rn ~ 47n- rn, 70, 71, 7n, 70-r0 100 101 Early element current division section reference line group NMOS transistor division induction circuit current load circuit induction amplifier induction line reference line PMOS transistor current voltage conversion circuit inverter 110, 120 150 1000, 2000, H100, 200, 300 1500, 2500 WL1, WL2, WL3, WL4 BL1, BL2, BL3, BL4, 8 reference circuit memory cell array read circuit semiconductor memory device word line bit line

SRC 源極線 87062 -69- 1226069 CELE11 〜CEEL14， CELL21 〜CELL24， CELL31 〜CELL34， CELL41 〜CELL44, 9SRC source line 87062 -69- 1226069 CELE11 ～ CEEL14, CELL21 ～ CELL24, CELL31 ～ CELL34, CELL41 ～ CELL44, 9

Jl, J2，Η 卜 H4，430-r0 〜43n-r0, 430-rn 〜43n-rn J4 J5 450-r0〜45n_rn， 450-rn〜45n-rn，Jl, J2, Η H4, 430-r0 ~ 43n-r0, 430-rn ~ 43n-rn J4 J5 450-r0 ~ 45n_rn, 450-rn ~ 45n-rn,

50-r0, 5n-r0, 5 1-rO 408-r0〜408-rn，8-r0 420-0〜420-n50-r0, 5n-r0, 5 1-rO 408-r0 ~ 408-rn, 8-r0 420-0 ~ 420-n

9-rO9-rO

1-rO 記憶體單元 電流負載電路 第一資料閂鎖電路 第二資料閂鎖電路 子參考線 參考位元線 參考電壓設定電路 參考單元 參考電流分區區段 87062 70-1-rO Memory unit Current load circuit First data latch circuit Second data latch circuit Sub-reference line Reference bit line Reference voltage setting circuit Reference unit Reference current partition section 87062 70-

Claims (1)

1226069 拾、申請專利範圍： 1. 一種讀取電路，用於從複數個記憶體單元的一記憶體單 元讀取資料，該讀取電路包括： 複數個分區感應電路，每一分區感應電路均透過複數 個感應線中對應的一感應線，連接至該一記憶體單元； 以及 一電流電壓轉換電路，用於將流過每一該複數個感應 線的一電流，轉換為代表每一該複數個感應線一電位的 一感應電壓， 其中： 每一該複數個分區感應電路包括一電流負載電路，用 於透過該複數個感應線中的一對應感應線，提供一電流 至該一記憶體單元，以及一感應放大器，用於感應該對 應感應線的電位與複數個參考線的一對應參考線的一 電位之間的一電位差，以及 包含在該複數個分區感應電路中至少一分區感應電 路中的該電流負載電路，具有一電流供應能力，該能力 不同於包含在該複數個分區感應電路中的另一分區感 應電路中的該電流負載電路的電流供應能力。 2·如申請專利範圍第1項之讀取電路，其中該電流電壓轉換 電路包括一單元電流分區區段，用於連接複數個感應線 至該一記憶體單元，或將前述兩者分隔開。 3·如申請專利範圍第丨項之讀取電路，進一步包括一第一參 考電路，用於將代表該複數個參考線中一參考線電位的 87062 1226069 一第一類型參考電壓施加到對應到該複數個感應放大 器中的該一參考線的一感應放大器。 4·如申請專利範圍第1項之讀取電路，其中每一該複數個電 流負載電路的該電流供應能力，均由代表該複數個參考 線中對應的一參考線電位的一第一類型參考電壓所控 制。 5·如申請專利範圍第1項之讀取電路，其中每一該複數個電 流負載電路包括一 PMOS電晶體，其具有透過該複數個 參考線中對應的一參考線施加參考電壓的一閘極。 6·如申請專利範圍第丨項之讀取電路，進一步包括一用於施 加一第二類型參考電壓的一第二參考電路，以控制每一 該複數個電流負載電路的該電流供應能力。 7·如申請專利範圍第6項之讀取電路，其中每一該複數個電 流負載電路包括一PM0S電晶體，具有連接至該第二參 考電路的一閘極。 8.如申請專利範圍第丨項之讀取電路，進一步包括： 一第一參考電路，用於將代表該複數個參考線中一參 考線電位的一第一類型參考電壓施加到對應到該複數 個感應放大器中的該一參考線的一感應放大器；以及 一第二參考電路，用於施加一第二類型參考電壓，以 控制每一該複數個電流負載電路的電流供應能力， 其中該第一參考電路係電連接至該第二參考電路。 9·如申請專利範圍第2項之讀取電路，其中·· 該單元電流分區區段包括複數個NM〇s電晶體，以及 87062 -2 - 1226069 每一該複數個NMOS電晶體包括一閘極以及一源極連 接至該閘極。 ίο. 11. 12. 13. 14. 如申清專利範圍第9項之讀取電路，其中： 每一該複數個NM0S電晶體係連接至該複數個電流負 載電路中對應的一電流負載電路，以及 每一該複數個NM0S電晶體的電流供應能力，係根據 連接至該對應的NM0S電晶體的電流負載電路的電流供 應能力而有所不同。 如申請專利範圍第10項之讀取電路，其中當每一該複數 個NMOS電晶體的電流供應能力較高時，連接至該電流 負載電路的電流供應能力會較低；以及當每一該複數個 NMOS電晶體的電流供應能力較低時，連接至該電流負 載電路的電流供應能力會較高。 如申請專利範圍第1項之讀取電路，其中該複數個分區感 應電路平行操作。 如申請專利範圍第1項之讀取電路，其中每一該複數個記 憶體單元係一多層式記憶體單元。 如申請專利範圍第3項之讀取電路， 其中該第一參考電路包括複數個參考電壓設定電路 ，每一該參考電壓設定電路都包括： 複數個電流負載電路，每一該電流負載電路均透過複 數個子參考線中對應的一子參考線，連接至一參考元件 ’以及 一電流電壓轉換電路，用於將流過該複數個子參考線 87062 1226069 中的一子參考線的— 一子參考線的 ^ ^ ^电况，轉換為代表該 一電位的一參考電壓，以及 其中從該複數個參考電壓設定電路中的一參 設定電路輸出的參考電I，可控制包含在該複數個參考 電壓設定電路中的另—參考電塵設定電路中的至少一 個孩複數個電流負載電路的電流供應能力。 15.如申請專利範圍第8項之讀取電路， 其中該第二參考電路包括複數個參考電壓設定電路 ，每一該參考電壓設定電路都包括： 複數個電流負載電路，每一該電流負載電路均透過複 數個子參考線中對應的—子參考線，連接至—參考元件 ’以及 -電流電壓轉換電路，用於將流過該複數個子參考線 中的一子參考線的一電流，轉換為代表該一子參考線的 一電位的一參考電壓，以及 其中從該第一參考電路輸出的該參考電壓，可控制包 含在該複數個參考電壓設定電路中的一參考電壓設定 電路中的至少一個該複數個電流負載電路的電流供應 能力。 〜 16· —種用於產生一參考電壓的參考電路，用於從複數個記 憶體單元中的一記憶體單元讀取資料，該參考電路包括： 複數個參考電壓設定電路，每一該參考電壓設定電路 包括： 複數個電流負載電路，每一該電流負載電路均透過複 87062 -4 - 1226069 數個子參考線中對應的一子參考線，連接至一參考元件 ’以及 一電流電壓轉換電路，用於將流過該複數個子參考線 中的一子參考線的一電流，轉換為代表該一子參考線的 一電位的一參考電壓， 其中從該複數個參考電壓設定電路中的一參考電恩 ”又疋電路輸出的該參考電壓，可控制包含在該複數個參 考電壓設定電路中的另一參考電壓設定電路中的至少 一個該複數個電流負載電路的電流供應能力。 π·如申請專利範圍第16項之參考電路，其中每一該複數個 電流電壓轉換電路包括一參考電流分區區段，用於連接 該複數個子參考線至該參考元件，或將前述兩者分隔開。 u·如申請專利範圍第17項之參考電路，其中·· 每一該複數個參考電流分區區段包括複數個Nm〇s電 晶體，以及 海一該複數個NMOS電晶體包括一閘極以及一源極連 接至該閘極。 19·如申請專利範圍第18項之參考電路，其中： 每一該複數個NMOS電晶體係連接至該複數個電流負 載電路中對應的一電流負載電路，以及 每一該複數個NMOS電晶體的電流供應能力，係根據 連接至該對應的NMOS電晶體的電流負載電路的電流供 應能力而有所不同。 2〇·如申請專利範圍第19項之參考電路，其中當每一該複數 87062 -5- 1226069 個NMOS電晶體的電流供應能力較高時，連接至該電流 負載電路的電流供應能力會較低；以及當每一該複數個 NMOS電晶體的電流供應能力較低時，連接至該電流負 載電路的電流供應能力會較高。 21. 22. 23. 24. 如申請專利範H第16項之參考電路，其中該參考元件具 有實質上與每-該複數個記憶體單元相同的結構。 如申請專利範圍第16項之參考電路，其中每__該複數個 電流負載電路包括一 PMOS電晶體。 如申請專利範圍第22項之參考電路，其中包含在該複數 個參考電壓設定電路中的一參考電壓設定電路中的該 複數個電流負載電路中的一電流負載電路的該pM〇s電 卵體，係與包含在該複數個參考電壓設定電路中的另一 參考電壓設定電路中的該複數個電流負載電路中的一 電流負載電路的一PMOS電晶體電流鏡射連接。 一種用於產生一參考電壓的參考電路，用於從複數個記 憶體單元中的一記憶體單元讀取資料，該參考電路包括： 一第一參考電路；以及 一第二參考電路， 其中該第一參考電路包括複數個參考電壓設定電路 ’每一該參考電恩設定電路都包括： 複數個電流負載電路，每一該電流負載電路均透過複 數個子參考線中對應的一子參考線，連接至一參考元件 ，以及 一電流電壓轉換電路，用於將流過該複數個子參考線 87062 • 6 - 1226069 中的一子參考線的一電流，轉換為代表該一子參考線的 一電位的一參考電壓， 其中從該複數個參考電壓設定電路中的一參考電壓 設定電路輸出的參考電壓，可控制包含在該複數個參考 電壓設定電路中的另一參考電壓設定電路中的至少一 個該複數個電流負載電路的電流供應能力， 其中該弟一參考電路包括複數個參考電壓設定電路 ’每一該參考電壓設定電路都包括： 複數個電流負載電路，每一該電流負載電路均透過複 數個子參考線中對應的一子參考線，連接至一參考元件 ，以及 一電流電壓轉換電路，用於將流過該複數個子參考線 中的一子參考線的一電流，轉換為代表該一子參考線的 一電位的一參考電壓，以及 其中從該第一參考電路輸出的參考電壓，可控制包含 在該第二參考電流的複數個參考電壓設定電路中的一 參考電壓設定電路中的至少一個該複數個電流負載電 路的電流供應能力。 25. 一種半導體記憶體裝置，該裝置包含： 一包括複數個記憶體單元的記憶體單元陣列；以及 一讀取電路，用於從該複數個記憶體單元中的一記憶 體單元讀取資料， 其中該讀取電路包括： 複數個刀區感應電路，每一該分區感應電路均透過複 87062 1226069 數個感應線中對應的一感應線，連接至該一記憶體單元； 一電流電壓轉換電路，用於將流過每一該複數個感應 線的一電流，轉換為代表每一該複數個感應線的一電位 的一感應電壓， 其中每一該複數個分區感應電路包括一電流負載電 路，用於透過該複數個感應線中的一對應感應線，提供 一電流至該一記憶體單元，以及一感應放大器，用於感 應該對應的感應線的電位與複數個參考線中對應的一 參考線的一電位之間的一電位差，以及 其中包含在該複數個分區感應電路中的至少一分區 感應電路中的電流負載電路，具有一電流供應能力，該 能力不同於包含在該複數個分區感應電路中的另一分 區感應電路中的電流負載電路的電流供應能力。 26. 27. 如申請專利範圍第25項之半導體記憶體裝置，其中每一 該複數個記憶體單元係一多層式記憶體單元。 一種半導體記憶體裝置，該裝置包含： 一包括複數個記憶體單元的記憶體單元陣列；以及 -用於產生-參考電壓的參考電路，用於從該複數個 記憶體單元中的一記憶體單元讀取資料， 其中該參考電路包括複數個參考電壓設定電路，每一 該參考電壓設定電路都包括： 以及 複數個電流負載電路，每一該電流負載電路均透過複 數個子參考線中對應的-子參考線，連接至-參考元件 87062 1226069 電壓轉換電路，用於將流過該複數個子參考線 的子參考線的一電流，轉換為代表該一子參考線的 一電位的-參考電壓，以及 其中從該複數個參考電壓設定電路中的一參考電壓 設定電路輸出的參考電壓，可控制包含在該複數個參考 電壓設定電路中的另—參考電壓設定電路中的至少一 個該複數個電流負載電路的電流供應能力。 87062 9·1226069 Patent application scope: 1. A reading circuit for reading data from a memory unit of a plurality of memory units, the reading circuit includes: a plurality of zone sensing circuits, each zone sensing circuit passes through A corresponding one of the plurality of sensing lines is connected to the memory unit; and a current-voltage conversion circuit for converting a current flowing through each of the plurality of sensing lines to represent each of the plurality of sensing lines. An induction voltage of a potential of the induction line, wherein each of the plurality of partition induction circuits includes a current load circuit for providing a current to the memory unit through a corresponding induction line of the plurality of induction lines, And an inductive amplifier for inducing a potential difference between the potential of the corresponding induction line and a potential of a corresponding reference line of the plurality of reference lines, and included in at least one of the plurality of segmented induction circuits The current load circuit has a current supply capability, which is different from that included in the plurality of partition induction circuits. The other section of the inductor senses the current supply capability of the current load circuit. 2. The reading circuit according to item 1 of the patent application range, wherein the current-voltage conversion circuit includes a unit current partition section for connecting a plurality of sensing lines to the memory unit, or separating the foregoing two. . 3. If the reading circuit of the patent application item 丨 further includes a first reference circuit for applying a reference line potential of 87062 1226069 representing a reference line potential of the plurality of reference lines to a first type reference voltage corresponding to the An induction amplifier of the reference line in the plurality of induction amplifiers. 4. The reading circuit of item 1 in the scope of patent application, wherein the current supply capability of each of the plurality of current load circuits is referenced by a first type of reference that represents a corresponding reference line potential among the plurality of reference lines Voltage controlled. 5. The reading circuit according to item 1 of the patent application range, wherein each of the plurality of current load circuits includes a PMOS transistor having a gate for applying a reference voltage through a corresponding one of the plurality of reference lines . 6. The reading circuit according to item 1 of the patent application scope, further comprising a second reference circuit for applying a second type of reference voltage to control the current supply capability of each of the plurality of current load circuits. 7. The reading circuit of item 6 of the patent application, wherein each of the plurality of current load circuits includes a PMOS transistor having a gate connected to the second reference circuit. 8. The reading circuit according to item 丨 of the patent application scope, further comprising: a first reference circuit for applying a first type reference voltage representing a reference line potential of the plurality of reference lines to a corresponding one of the plurality A sense amplifier of the one reference line among the plurality of sense amplifiers; and a second reference circuit for applying a second type of reference voltage to control the current supply capability of each of the plurality of current load circuits, wherein the first The reference circuit is electrically connected to the second reference circuit. 9. The reading circuit according to item 2 of the patent application scope, wherein the current division section of the unit includes a plurality of NMOS transistors, and 87062 -2-1226069 each of the plurality of NMOS transistors includes a gate And a source is connected to the gate. ίο. 11. 12. 13. 14. If the reading circuit of item 9 of the patent scope is declared, wherein: each of the plurality of NMOS transistor systems is connected to a corresponding one of the plurality of current load circuits, And the current supply capability of each of the plurality of NMOS transistors is different according to the current supply capability of a current load circuit connected to the corresponding NMOS transistor. For example, if the read circuit of claim 10 is applied, when the current supply capability of each of the plurality of NMOS transistors is higher, the current supply capability of the current load circuit connected to the plurality of NMOS transistors is lower; When the current supply capability of an NMOS transistor is low, the current supply capability connected to the current load circuit will be higher. For example, the reading circuit of the patent application No. 1 wherein the plurality of partitioned sensing circuits operate in parallel. For example, the reading circuit of the first patent application range, wherein each of the plurality of memory cells is a multilayer memory cell. For example, the reading circuit of the third patent application range, wherein the first reference circuit includes a plurality of reference voltage setting circuits, and each of the reference voltage setting circuits includes: a plurality of current load circuits, each of the current load circuits passes through A corresponding one of the plurality of sub-reference lines is connected to a reference element 'and a current-voltage conversion circuit for passing a sub-reference line in the plurality of sub-reference lines 87062 1226069 — of a sub-reference line ^ ^ ^ The electrical condition is converted into a reference voltage representing the potential, and the reference voltage I output from a reference setting circuit in the plurality of reference voltage setting circuits can control the plurality of reference voltage setting circuits. Another in the reference—the current supply capability of at least one of the plurality of current load circuits in the reference electric dust setting circuit. 15. The reading circuit according to item 8 of the scope of patent application, wherein the second reference circuit includes a plurality of reference voltage setting circuits, each of the reference voltage setting circuits includes: a plurality of current load circuits, each of the current load circuits Both pass through corresponding sub-reference lines of a plurality of sub-reference lines and are connected to a reference component 'and a current-voltage conversion circuit for converting a current flowing through a sub-reference line in the plurality of sub-reference lines into a representative A reference voltage of a potential of the one sub-reference line and the reference voltage output from the first reference circuit can control at least one of a reference voltage setting circuit included in the plurality of reference voltage setting circuits. Current supply capability of a plurality of current load circuits. ~ 16 · —A reference circuit for generating a reference voltage for reading data from a memory unit in a plurality of memory units, the reference circuit includes: a plurality of reference voltage setting circuits, each of the reference voltages The setting circuit includes: a plurality of current load circuits, each of which is connected to a reference element through a corresponding sub-reference line of a plurality of sub-reference lines of 87062 -4-1226069, and a current-voltage conversion circuit, A current flowing through a sub-reference line of the plurality of sub-reference lines is converted into a reference voltage representing a potential of the sub-reference line, wherein a reference voltage in the reference voltage setting circuit is set from the plurality of reference voltages. The reference voltage output by the circuit can control the current supply capability of the current load circuits of at least one of the other reference voltage setting circuits included in the plurality of reference voltage setting circuits. The reference circuit of item 16, wherein each of the plurality of current-voltage conversion circuits includes a reference current partition , For connecting the plurality of sub-reference lines to the reference element, or separating the foregoing two. U · For example, the reference circuit of the 17th scope of the patent application, wherein each of the plurality of reference current partition sections includes A plurality of NmOs transistors, and Haiyi, the plurality of NMOS transistors includes a gate and a source connected to the gate. 19. The reference circuit of claim 18 in the scope of patent application, wherein: each of the plurality NMOS transistor systems are connected to a corresponding current load circuit of the plurality of current load circuits, and the current supply capability of each of the plurality of NMOS transistors is based on the current load circuits connected to the corresponding NMOS transistors. The current supply capacity is different. 20. For example, the reference circuit of the 19th patent application range, wherein when the current supply capacity of each of the plurality of 87062 -5- 1226069 NMOS transistors is high, connect to the current load. The current supply capability of the circuit will be low; and when the current supply capability of each of the plurality of NMOS transistors is low, the current supply connected to the current load circuit The force will be higher. 21. 22. 23. 24. For example, the reference circuit of item 16 of the patent application, wherein the reference element has substantially the same structure as each of the plurality of memory cells. The reference circuit of 16 items, wherein each of the plurality of current load circuits includes a PMOS transistor. For example, the reference circuit of item 22 of the patent application scope includes a reference voltage setting circuit among the plurality of reference voltage setting circuits. The pM0s electric egg of a current load circuit in the plurality of current load circuits is related to the plurality of current load circuits in another reference voltage setting circuit included in the plurality of reference voltage setting circuits. A PMOS transistor current mirror connection of a current load circuit. A reference circuit for generating a reference voltage is used to read data from a memory cell in a plurality of memory cells. The reference circuit includes: a first reference circuit; and a second reference circuit, wherein the first A reference circuit includes a plurality of reference voltage setting circuits. Each of the reference voltage setting circuits includes: a plurality of current load circuits. Each of the current load circuits is connected to a corresponding one of the plurality of sub-reference lines through a sub-reference line. A reference element and a current-voltage conversion circuit for converting a current flowing through a sub-reference line in the plurality of sub-reference lines 87062 • 6-1226069 into a reference representing a potential of the sub-reference line Voltage, wherein a reference voltage output from a reference voltage setting circuit in the plurality of reference voltage setting circuits can control at least one of the plurality of currents included in another reference voltage setting circuit in the plurality of reference voltage setting circuits. Current supply capability of a load circuit, wherein the reference circuit includes a plurality of reference circuits Each of the reference voltage setting circuits includes: a plurality of current load circuits, each of which is connected to a reference component through a corresponding one of the plurality of sub-reference lines, and a current-voltage conversion circuit A circuit for converting a current flowing through a sub-reference line of the plurality of sub-reference lines into a reference voltage representing a potential of the sub-reference line, and a reference voltage outputted from the first reference circuit , At least one of the reference voltage setting circuits included in the plurality of reference voltage setting circuits of the second reference current can control the current supply capability of the plurality of current load circuits. 25. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells; and a reading circuit for reading data from a memory cell in the plurality of memory cells, The read circuit includes: a plurality of blade area induction circuits, each of which is connected to the memory unit through a corresponding one of the plurality of induction lines of 87062 1226069; a current-voltage conversion circuit, Is used to convert an electric current flowing through each of the plurality of induction wires into an induced voltage representing a potential of each of the plurality of induction wires, wherein each of the plurality of partition induction circuits includes a current load circuit, and A current is supplied to the memory unit through a corresponding one of the plurality of sensing lines, and a sense amplifier is used to sense the potential of the corresponding sensing line and a corresponding one of the plurality of reference lines. A potential difference between a potential and at least one partition induction circuit included in the plurality of partition induction circuits Current load circuit having a current supply capability, which comprises a current supply capability different from another division sensing circuit region in the plurality of partition sensing circuit current in the load circuit. 26. 27. The semiconductor memory device according to claim 25, wherein each of the plurality of memory cells is a multilayer memory cell. A semiconductor memory device includes: a memory cell array including a plurality of memory cells; and a reference circuit for generating a reference voltage from a memory cell in the plurality of memory cells. Read the data, where the reference circuit includes a plurality of reference voltage setting circuits, each of which includes: and a plurality of current load circuits, each of the current load circuits passes through corresponding sub-lines in a plurality of sub-reference lines Reference line, connected to-reference element 87062 1226069 voltage conversion circuit for converting a current flowing through the sub-reference line of the plurality of sub-reference lines into a -reference voltage representing a potential of the one sub-reference line, and among them The reference voltage output from a reference voltage setting circuit in the plurality of reference voltage setting circuits can control at least one of the plurality of current load circuits included in the other reference voltage setting circuit included in the plurality of reference voltage setting circuits. Current supply capability. 87062 9 ·