TWI223865B

TWI223865B - Method of fabricating a shallow trench isolation

Info

Publication number: TWI223865B
Application number: TW90115088A
Authority: TW
Inventors: Ting-Chang Chang; Yi-Shien Mor; Po-Tsun Liu
Original assignee: United Microelectronics Corp
Priority date: 2001-06-21
Filing date: 2001-06-21
Publication date: 2004-11-11

Abstract

A patterned hard mask layer is firmed on a silicon substrate of a semiconductor wafer. An etching process is performed to form a trench in the silicon substrate not covered by the hard mask layer. Following this, a liner oxide layer is formed on the bottom and the sidewalls within the trench. A liquid phase deposition is performed to form a first silicon oxide layer on the liner oxide layer within the trench. Subsequently, a high-density plasma chemical vapor deposition (HDP CVD) is performed to form a second silicon oxide layer on the semiconductor wafer, the second silicon oxide layer filling the trench. Following this, a chemical mechanical polishing (CMP) process is performed to remove portions of the second silicon oxide layer above the hard mask layer, portions of the second silicon oxide layer remaining in the trench being aligned with the surface of the hard mask layer. Finally, the hard mask layer is removed, thereby completing the fabrication of a shallow trench isolation.

Description

1223865 五、發明說明（π 發明領域本發明係提供一種製作淺溝隔離（s h a 1 1 〇 w t r e n c h i s ο 1 a t i ο n， S T I )的方法，尤指一種可以強化淺溝隔離效果之方法。背景說明在目前的半導體製程中，一般是採用區域氧化法 (localized oxidation isolation， LOCOS)或是淺溝隔離法來對半導體晶片上的電子元件進行絕緣隔離，以避免電子元件之間相互干擾而發生短路或寄生電容。然而在積集度逐漸提昇的同時，製程所能容許的線寬也隨著縮小，尤其在線寬0. 2 5// m以下的半導體製程中，傳統之區域氧化法已無法達到完全隔離的效果，因為LOCOS製程中所產生之凹坑（pits)、晶體缺陷（crystal defect)以及鳥缘 (b i r d ’ s b e a k )長度過長等缺點，會大幅地影響半導體晶片的特性，且L 0 C 0 S方法所產生之場氧化層（f i e 1 d〇X i d e layer, FOX)佔據較大的體積，會影響整個半導體晶片的積集度，因此採用淺溝隔離法來做為電子元件間之隔離已漸成時下趨勢。請參考圖一至圖三，圖一至圖三為習知於一半導體片1 0上製作淺溝隔離的方法示意圖。如圖一所示，半導體1223865 V. Description of the invention (π FIELD OF THE INVENTION The present invention provides a method for making shallow trench isolation (sha 1 1 0wtrenchis ο 1 ati ο n, STI), especially a method that can enhance the effect of shallow trench isolation. Background description in In the current semiconductor manufacturing process, localized oxidation isolation (LOCOS) or shallow trench isolation is generally used to isolate and isolate electronic components on semiconductor wafers to avoid short circuits or parasitics caused by mutual interference between electronic components. Capacitor. However, while the accumulation degree is gradually increasing, the line width allowed by the process is also shrinking, especially in semiconductor processes below the line width of 0.2 5 // m, the traditional area oxidation method has been unable to achieve complete isolation. The effect is because the defects such as pits, crystal defects, and bird's sbeaks that are generated in the LOCOS process will greatly affect the characteristics of the semiconductor wafer, and L 0 C 0 The field oxide layer (fie 1 dox ide layer, FOX) produced by the S method occupies a larger volume, which will affect the entire The concentration of conductor wafers, so the use of shallow trench isolation as the isolation between electronic components has become a trend. Please refer to Figures 1 to 3, which are conventionally fabricated on a semiconductor wafer 10 Schematic of shallow trench isolation method. As shown in Figure 1, the semiconductor

第6頁 1223865 五、發明說明（2) 晶片1 0包t 5 一矽基底1 2，一墊氧化層1 4蓋於矽基底1 2表面’以及氮矽層1 6覆蓋於墊氧化層1 4表面。接下來於氮石夕層1 6表面形成_光阻層（未顯示），並進行一黃光製程，以i ^光阻層中定義出淺溝的圖案。之後進行一蝕刻製程，沿著光阻層中的圖案蝕刻氮矽層1 6以及墊氧化層1 4，直至石夕基底12表面。去除光阻層後，剩餘之氮矽層丨6和墊氧化層14即形成一已定義（Patterned)之硬罩幕層（hard mask layer)’用來作為形成淺溝之蝕刻遮罩。如圖一所示，隨後進行一非等向性乾蝕刻製程，去除未被硬罩幕層所覆蓋之矽基底丨2至一預定深度，通常約為數千埃（angstrom, A )，以於矽基底1 2中形成一淺溝1 8。由於在進行乾餘刻製程的過程中，蝕刻氣體會破壞淺溝i 8 内之石夕晶格結構，尤其是淺溝丨8底部之矽基底1 2，因此在形成淺溝1 8之後’必須再將半導體晶片丨〇送入爐管，於淺溝1 8底部以及側壁之石夕基底1 2表面生成一熱氧化層，當作襯氧化（111^1：〇\1(16)層20，用來保護淺溝18底部以及側壁之矽基底12結構，同時修補乾蝕刻製程所造成之晶格結構破壞。之後如圖三所示，進行一高密度電漿化學氣相沉積製程（high density plasma chemical vap〇r dep〇siti〇n， HDP CVD)，先於半導體晶片10表面形成一石夕氧層22，並填滿淺溝18，接著再利用一化學機械研 emicalPage 6 1223865 V. Description of the invention (2) Wafer 10 package t 5 a silicon substrate 1 2, a pad oxide layer 1 4 covers the silicon substrate 1 2 surface and a nitrogen silicon layer 1 6 covers the pad oxide layer 1 4 surface. Next, a photoresist layer (not shown) is formed on the surface of the nitride layer 16 and a yellow light process is performed to define a shallow groove pattern in the photoresist layer. Then, an etching process is performed, and the silicon nitride layer 16 and the pad oxide layer 14 are etched along the pattern in the photoresist layer to the surface of the Shixi substrate 12. After the photoresist layer is removed, the remaining silicon nitride layer 6 and the pad oxide layer 14 form a patterned hard mask layer 'which is used as an etching mask for forming shallow trenches. As shown in FIG. 1, a non-isotropic dry etching process is subsequently performed to remove the silicon substrate not covered by the hard mask layer to a predetermined depth, usually about several thousand angstroms (Angstrom, A). A shallow trench 18 is formed in the silicon substrate 12. During the process of dry-etching, the etching gas will destroy the stone lattice structure in the shallow trench i 8, especially the silicon substrate 12 at the bottom of the shallow trench 8. Therefore, after the shallow trench 18 is formed, it is necessary to The semiconductor wafer is then sent into the furnace tube, and a thermal oxide layer is formed on the bottom of the shallow trench 18 and the surface of the stone wicker substrate 12 on the side wall, which serves as a liner oxide (111 ^ 1: 0 \ 1 (16) layer 20, It is used to protect the silicon substrate 12 structure at the bottom of the shallow trench 18 and the sidewalls, and repair the lattice structure damage caused by the dry etching process. Then, as shown in FIG. 3, a high density plasma chemical vapor deposition process is performed. chemical vap〇r dep〇siti ON, HDP CVD), a silicon oxide layer 22 is formed on the surface of the semiconductor wafer 10, and the shallow trench 18 is filled, and then a chemical mechanical

1223865 五、發明說明（3) mechanical polishing，CMP)製程，進行半導體晶片10表面之平坦化，亦即利用氮矽層1 6作為研磨終點，去除氮矽層1 6表面上之矽氧層2 2，並使填於淺溝1 8内之矽氧層2 2表面約略切齊於氮矽層1 6表面。最後再利用一濕蝕刻製程去除氮矽層1 6，完成習知之淺溝隔離的製作。由於利用HDP CVD製程形成的矽氧層22具有極佳的階梯覆蓋能力以及良好的同形度（conformity)，可輕易克服一般化學沉積法所形成的矽氧層不易填入一高深寬比 (high aspect ratio)之陡山肖地勢（severe topography)的問題’因此被廣泛應用於線見小於〇. 1 5 // m次微米製程。但是利用H D P C V D製程來沉積矽氧層2 2時，矽基底1 2底部必須施加一偏壓，因此使得電漿離子被加速衝向矽基底 1 2，而在淺溝1 8底部造成電漿損害（plasma damage)，如圖三所示。由於電漿損害24區域容易引起漏電流，進而使得淺溝1 8之隔離效果大受影響。發明概述因此，本發明之目的即在提供一種製作淺溝隔離的方法，以避免在淺溝底部形成電漿損害。在本發明之最佳實施例中，首先於一半導體晶片之一矽基底表面形成一已定義圖案之硬罩幕層，接著進行一蝕1223865 V. Description of the invention (3) Mechanical polishing (CMP) process to planarize the surface of the semiconductor wafer 10, that is, using the nitrogen silicon layer 16 as a polishing end point, and removing the silicon oxide layer 2 on the surface of the silicon silicon layer 2 2 The surface of the silicon oxide layer 22 filled in the shallow trench 18 is approximately cut to the surface of the silicon nitride layer 16 approximately. Finally, a wet etching process is used to remove the silicon nitride layer 16 to complete the conventional shallow trench isolation process. Because the silicon oxide layer 22 formed by the HDP CVD process has excellent step coverage and good conformity, it can easily overcome that the silicon oxide layer formed by the general chemical deposition method is not easy to fill a high aspect ratio. ratio) of the steep topography (severe topography) problem is therefore widely used in line see less than 0.1 5 // m order micron process. However, when using the HDPCVD process to deposit the silicon oxide layer 22, a bias must be applied to the bottom of the silicon substrate 12 so that plasma ions are accelerated toward the silicon substrate 12 and plasma damage is caused at the bottom of the shallow trench 18 ( plasma damage), as shown in Figure 3. Because the plasma damages the 24 area, it is easy to cause leakage current, and the isolation effect of the shallow trench 18 is greatly affected. SUMMARY OF THE INVENTION Therefore, the object of the present invention is to provide a method for making shallow trench isolation to avoid the formation of plasma damage at the bottom of the shallow trench. In a preferred embodiment of the present invention, a hard mask layer with a defined pattern is first formed on the surface of a silicon substrate of a semiconductor wafer, and then an etch is performed.

1223865 五、發明說明（4) 刻製程，以於未被該硬罩幕覆蓋之該矽基底中形成一淺溝。然後於該淺溝内之底部表面以及側壁表面形成一襯氧 4匕層，並進4亍一〉夜相沉積〉去(liquid phase deposition， L P D )，以於該淺溝内之該襯氧化層表面形成一第一矽氧層。接著進行一高密度電漿化學氣相沉積（HDP CVD)製程，以於該半導體晶片表面均勻地形成一第二矽氧層並填滿該淺溝。隨後進行一化學機械研磨製程，以去除該硬罩幕表面上之該第二矽氧層，使填入該淺溝内之談第二矽氧層表面約略切齊於該硬罩幕層，並且去除該硬罩幕層，而完成該淺溝隔離製程。1223865 V. Description of the invention (4) The engraving process forms a shallow groove in the silicon substrate not covered by the hard mask. Then, an oxygen-lined layer is formed on the bottom surface and the side wall surface in the shallow trench, and the liquid phase deposition (LPD) is performed on the surface of the liner oxide layer in the shallow trench. A first silicon oxide layer is formed. Then, a high-density plasma chemical vapor deposition (HDP CVD) process is performed to uniformly form a second silicon oxide layer on the surface of the semiconductor wafer and fill the shallow trench. A chemical mechanical polishing process is subsequently performed to remove the second silicon oxide layer on the surface of the hard mask, so that the surface of the second silicon oxide layer filled into the shallow trench is approximately aligned with the hard mask layer, and The hard mask layer is removed to complete the shallow trench isolation process.

I 由於本發明係於進行HDP CVD製程之前，先利用液相沉積法選擇性地於淺溝中成長該第一矽氧層來作為該淺溝底部的保護層，以避免HDP CVD製程破壞該淺溝結構，影響淺溝隔離之絕緣效果。此外，本發明亦可以利用該第一矽氧層來降低該淺溝之深寬比，以利於後續沉積該第二矽氧層時之填洞（g a p - f i 1 1 i n g )能力，進而可以強化淺溝隔離的效果。發明之詳細說明請參考圖四至圖七，圖四至圖七為本發明於一半導體· 晶片3 0上製作一淺溝隔離的方法示意圖。如圖四所示，半導體晶片30包含有一矽基底32，一墊氧化層34蓋於矽基底Since the present invention is performed before the HDP CVD process, the first silicon oxide layer is selectively grown in a shallow trench by a liquid deposition method as a protective layer at the bottom of the shallow trench to avoid the HDP CVD process from damaging the shallow trench. The trench structure affects the insulation effect of shallow trench isolation. In addition, the present invention can also use the first silicon oxide layer to reduce the depth-to-width ratio of the shallow trench, which is beneficial to the subsequent gap-firing ability when the second silicon oxide layer is deposited, and can further strengthen the gap-fi 1 1 ing capability. The effect of shallow trench isolation. Detailed description of the invention Please refer to FIGS. 4 to 7. FIGS. 4 to 7 are schematic diagrams of a method for making a shallow trench isolation on a semiconductor · wafer 30 according to the present invention. As shown in FIG. 4, the semiconductor chip 30 includes a silicon substrate 32, and an oxide layer 34 covers the silicon substrate.

1223865 五、發明說明（5) 3 2表面，以及一氮石夕層36覆蓋於塾氧化層3 4表面。本發明方法是先於氮矽層3 6表面形成一光阻層（未顯示），並利用一黃光製程，以於光阻層中定義出主動區域以及淺溝的圖案。之後進行一蝕刻製程，沿著光阻層中的圖案蝕刻氮矽層3 6以及墊氧化層34，直至矽基底3 2表面。在去除光阻層之後，剩餘之墊氧化層3 4和氮矽層3 6即形成一經過定義之硬罩幕層，用來作為形成淺溝之#刻遮罩。如圖五所示，隨後進行一非等向性乾蝕刻製程，去除未被硬罩幕層覆蓋之矽基底3 2至一預定深度，通常約為數千埃，以於矽基底3 2中形成一淺溝3 8。由於在進行乾蝕刻製程的過程中，蝕刻氣體會破壞淺溝3 8内之矽晶格結構，尤其是淺溝3 8底部之矽基底3 2，因此在形成淺溝3 8之後，必須再將半導體晶片3 0送入爐管，利用熱氧化法於淺溝3 8 底部以及側壁之矽基底3 2表面生成一氧化層，作為襯氧化層4 0，用以於後續製程中保護淺溝3 8底部以及側壁之矽基底3 2結構，同時修補乾蝕刻製程所造成矽基底3 2之晶格結構破壞。之後如圖六所示，把半導體晶片浸泡於一處理溶液 (treatment solution)以使石夕基底3 2表面產生S i Ο Η基。形成Si 0Η基的方法可以參考美國專利第4, 4 78, 9 0 9以及第 5，134，021號，例如利用聚乙烯醇（polyvinyl alcohol)、石夕團（silica nodules)以及有機石夕化合物（organic1223865 V. Description of the invention (5) The surface of 3 2 and a nitrogen oxide layer 36 cover the surface of the hafnium oxide layer 3 4. In the method of the present invention, a photoresist layer (not shown) is formed before the surface of the nitrogen silicon layer 36, and a yellow light process is used to define an active area and a shallow trench pattern in the photoresist layer. Then, an etching process is performed to etch the silicon-silicon layer 36 and the pad oxide layer 34 along the pattern in the photoresist layer to the surface of the silicon substrate 32. After the photoresist layer is removed, the remaining pad oxide layer 34 and the silicon nitride layer 36 form a defined hard mask curtain layer, which is used as a #etched mask for forming shallow trenches. As shown in FIG. 5, a non-isotropic dry etching process is subsequently performed to remove the silicon substrate 32 that is not covered by the hard cover curtain layer to a predetermined depth, usually about several thousand angstroms, so as to form in the silicon substrate 32. A shallow trench 3 8. During the dry etching process, the etching gas will destroy the silicon lattice structure in the shallow trench 38, especially the silicon substrate 32 at the bottom of the shallow trench 38. Therefore, after the shallow trench 38 is formed, the The semiconductor wafer 30 is sent to the furnace tube, and an oxide layer is formed on the bottom of the shallow trench 3 8 and the surface of the silicon substrate 32 on the side wall by thermal oxidation. The oxide layer is used as a liner oxide layer 40 to protect the shallow trench 3 8 in subsequent processes. The silicon substrate 32 structure at the bottom and sidewalls, and the lattice structure of the silicon substrate 32 caused by the dry etching process are repaired at the same time. Then, as shown in FIG. 6, the semiconductor wafer is immersed in a treatment solution so that the surface of the Shi Xi substrate 32 generates a Si Η group. For the method of forming Si 0 fluorene group, refer to U.S. Patent Nos. 4, 4 78, 109 and 5,134, 021. For example, use of polyvinyl alcohol, silica nodules, and organic stone compounds (Organic

第10頁 1223865 五、發明說明（6)Page 10 1223865 V. Description of the invention (6)

s i 1 i con compound)等混合物加以水解來使矽基底32產生 S i 0 Η基。然後再進行一液相沉積法，於淺溝3 8内之底部以及側壁表面形成一由二氧化矽所構成的矽氧層4 2，用來保護淺溝3 8底部，以避免後續於淺溝3 8中沉積介電層時於淺溝3 8底部造成損害。該液相沉積法係利用六氟；ε夕酸 (H i F e)之飽合溶液來作為與矽基底3 2反應之反應溶液，由於此溶液會形成SiFKOH)及SiF2(0H)戎SiF/OiOi等物質中的S i F基，因此可以進一步與矽基底3 2表面的s i 0H基反應生成二氧化碎，其反應式如下：其中’飽和之六氟矽酸溶液之調配則可以在溼度介於 5 5至6 5之間、溫度約為2 2。 C之環境下進行，利用濃度約 3 4 %的六氟碎酸溶液持續地加入二氧化矽粉末，並且持續攪拌2 4小時，以形成六氟矽酸之飽和溶液。如圖七所示，接下來再進行一 HDP CVD製程，於半導體晶片3 0表面形成一介電層4 4，例如二氧化矽層，且介電層4 4填滿淺溝3 8。在本發明之其他實施例中，介電層4 4亦可以利用旋塗式玻璃（spin-on glass, S0G)製程或常壓化 4* 氣相 /儿積（atmospheric pressure chemical vapor deposit ion，APCVD)法形成。隨後進行一化學機械研磨製程’進行半導體晶片3 〇表面之平坦化，亦即利用氮矽層’ 3 6 _ " 作為研磨終點’去除氮矽層3 6表面上之介電層4 4，並使殘 ·s i 1 i con compound) and other mixtures are hydrolyzed to make the Si substrate 32 produce S i 0 fluorene. Then, a liquid phase deposition method is performed to form a silicon oxide layer 42 made of silicon dioxide on the bottom and the surface of the sidewall in the shallow trench 38 to protect the bottom of the shallow trench 38 to avoid subsequent shallow trenches. When the dielectric layer was deposited in 38, damage was caused to the bottom of the shallow trench 38. The liquid phase deposition method uses a saturated solution of hexafluoro; ε eve acid (H i F e) as the reaction solution to react with the silicon substrate 32, because this solution will form SiFKOH) and SiF2 (0H) SiF / S i F groups in OiOi and other materials can further react with si 0H groups on the silicon substrate 32 surface to form dioxide fragments. The reaction formula is as follows: Among them, the configuration of the saturated hexafluorosilicic acid solution can be adjusted in the humidity medium. Between 5 5 and 65, the temperature is about 2 2. Under the environment of C, silicon dioxide powder was continuously added by using a hexafluoric acid solution with a concentration of about 34%, and stirring was continued for 24 hours to form a saturated solution of hexafluorosilicic acid. As shown in FIG. 7, a HDP CVD process is performed next to form a dielectric layer 44, such as a silicon dioxide layer, on the surface of the semiconductor wafer 30, and the dielectric layer 44 fills the shallow trench 38. In other embodiments of the present invention, the dielectric layer 44 can also use a spin-on glass (SOG) process or atmospheric pressure 4 * atmospheric pressure chemical vapor deposit ion (APCVD). ) Law formation. Subsequently, a chemical mechanical polishing process is performed to planarize the surface of the semiconductor wafer 30, that is, to remove the dielectric layer 4 4 on the surface of the nitrogen silicon layer 36 using the nitrogen silicon layer '36_ " as the end point of polishing', and Disability

第11頁 1223865 五、發明說明（Ό 留於淺溝3 8内之矽氧層4 4表面約略切齊於氮矽層3 6表面。最後再利用一濕蝕刻製程去除氮矽層3 6，完成本發明之淺溝隔離的製作。由於利用液相沉積法所形成的矽氧層4 2是在室溫下進行，因此可以有效降低沉積薄膜的應力，避免對淺溝3 8底部結構造成傷害。此外，由於液相沉積法具有比較好的沉積選擇性，可以僅選擇性地於淺溝3 8内成長矽氧層4 2，因此可以降低淺溝3 8之深寬比，以利於後續介電層4 4之填洞 (gap-filling)能力 ° 相較於習知之製作淺溝隔離的方法，本發明係於進行 HDP CVD製程之前，先利用液相沉積法選擇性地於淺溝中成長一矽氧層來作為淺溝底部的保護層，以避免HDP CVD 製程破壞淺溝結構，影響淺溝隔離之絕緣效果。此外，本發明可以利用矽氧層來降低淺溝之深寬比，以利於後續於淺溝内沉積介電層時之填洞能力，進而可以強化淺溝隔離的效果。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。Page 11 1223865 V. Description of the invention (表面 The surface of the silicon oxide layer 4 4 remaining in the shallow trench 3 8 is approximately aligned with the surface of the nitrogen silicon layer 3 6. Finally, a wet etching process is used to remove the nitrogen silicon layer 3 6 to complete the process. The production of the shallow trench isolation of the present invention. Since the silicon oxide layer 42 formed by the liquid phase deposition method is performed at room temperature, the stress of the deposited film can be effectively reduced, and damage to the bottom structure of the shallow trench 38 is avoided. In addition, because the liquid phase deposition method has relatively good deposition selectivity, the silicon oxide layer 4 2 can be grown only in the shallow trenches 38 selectively, so the aspect ratio of the shallow trenches 38 can be reduced to facilitate subsequent dielectrics. The gap-filling ability of layer 4 4 ° Compared with the conventional method for making shallow trench isolation, the present invention is to selectively grow in shallow trenches by liquid phase deposition before performing HDP CVD process. The silicon oxide layer is used as a protective layer at the bottom of the shallow trench to prevent the HDP CVD process from damaging the shallow trench structure and affecting the insulation effect of the shallow trench isolation. In addition, the present invention can use the silicon oxide layer to reduce the shallow trench depth-to-width ratio to facilitate Subsequent deposition of dielectric layers in shallow trenches The ability to fill holes in time can further enhance the effect of shallow trench isolation. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention should be included in the patent Coverage.

第12頁 1223865 圖式簡單說明圖示之簡單說明圖一至圖三為習知製作一淺溝隔離的方法示意圖。圖四至圖七為本發明製作一淺溝隔離的方法示意圖。圖示之符號說明 10 半導體晶片 12 矽基底 14 墊氧化層 16 氮矽層 18 淺溝 20 襯氧化層 22 矽氧層 24 電漿損害 30 半導體晶片 32 6夕基底 34 塾氧化層 36 氮矽層 38 淺溝 40 襯氧化層 42 $夕氧層 44 介電層Page 12 1223865 Brief description of the diagrams Brief description of the diagrams Figures 1 to 3 are schematic diagrams of a conventional method for making a shallow trench isolation. 4 to 7 are schematic diagrams of a method for manufacturing a shallow trench isolation according to the present invention. Explanation of symbols in the diagram 10 Semiconductor wafer 12 Silicon substrate 14 Oxide layer 16 Nitrogen silicon layer 18 Shallow trench 20 Liner oxide layer 22 Silicon oxide layer 24 Plasma damage 30 Semiconductor wafer 32 Silicon substrate 34 Titanium oxide layer 36 Silicon nitrogen layer 38 Shallow trench 40 Lined with oxide layer 42 Oxide layer 44 Dielectric layer

第13頁Page 13

Claims

1223865 ---------------------------------------------------90115088 年月六、申請專利範圍 1. 一種於1223865 ------------------------------------------------- --90115088 Sixth, patent application scope 1. A kind of

曰半導體晶片之一矽基底（silicon substrate)上製作一淺溝隔離（shaii〇w trench isolation，STI)的方法，該方法包含有下列步_ 於該矽基底表面形成一已定義圖案（p a 11 e r n e d )之Ί 罩幕（hard mask)層；進行一蝕刻（e t ch )製程，以於未被該硬罩幕層覆蓋之該矽基底中形成一淺溝（t r e n c h ); 進行一液相沉積法（liquid phase deposition, L P D )，以於該淺溝内之底部表面以及側壁表面形成一第一矽氧層，用以保護該淺溝之底部結構；於該半導體晶片表面均勻地形成一介電層並填滿該淺溝；進行一化學機械研磨製程（chemical mechanical polish，CMP)，以去除該硬罩幕表面上之該介電層’並使填入該淺溝内之該介電層表面約略切齊於該硬罩幕層；以及去除該硬罩幕層，完成該淺溝隔離製程。 2 ·如申請專利範圍第1項之方法’其中該硬罩幕層係由一第一氮矽層以及/第二矽氧層上、下堆疊而成’且形成該已定義圖案之硬罩幕層的方法係包含有下列步驟· 於該矽基底表面形成該第二矽氧層；於該矽氧層表面形成該第一氮矽層；於該第一氮矽層表面形成一光阻層；A method for making a shallow trench isolation (STI) on a silicon substrate of a semiconductor wafer. The method includes the following steps: forming a defined pattern (pa 11 erned) on the surface of the silicon substrate ) Of a hard mask layer; performing an et ch process to form a trench in the silicon substrate not covered by the hard mask layer; and performing a liquid deposition method ( liquid phase deposition (LPD) to form a first silicon oxide layer on the bottom surface and the sidewall surface in the shallow trench to protect the bottom structure of the shallow trench; a dielectric layer is uniformly formed on the surface of the semiconductor wafer and Fill the shallow trench; perform a chemical mechanical polish (CMP) process to remove the dielectric layer on the surface of the hard mask and make the surface of the dielectric layer filled in the shallow trench approximately cut Align with the hard cover curtain layer; and remove the hard cover curtain layer to complete the shallow trench isolation process. 2 · The method according to item 1 of the scope of the patent application, wherein the hard mask layer is formed by stacking a first nitrogen silicon layer and / or a second silicon oxide layer on top and bottom, and forming the hard mask of the defined pattern The layer method includes the following steps: forming the second silicon oxide layer on the surface of the silicon substrate; forming the first silicon nitride layer on the surface of the silicon oxide layer; forming a photoresist layer on the surface of the first silicon nitride layer;

第14頁 1223865 ___________________________________________________案號 90Π5088 ^ J a Ifi ___________________________________________ 六、申請專利範圍 |進行一黃光製程，於該光阻層中定義出該淺溝的圖案； :沿著該光阻層的圖案蝕刻該第一氮矽層以及該第二矽氧層 i直至該矽基底表面；以及 I去除該光阻層，以於該半導體晶片表面形成該已定義圖案 |之硬罩幕層。 3. 如申請專利範圍第1項之方法，其中該方法於形成該第一石夕氧層前另包含有一於該淺溝内形成一概氧化（liner I ox i de )層之製程。 4. 如申請專利範圍第3項之方法，其中該襯氧化層係利用一熱氧.化（t h e r m a 1 ο X i d a t i ο η )法所形成，以消除該# 刻製程對該淺溝底部之該矽基底造成之損害。 5 · 如申請專利範圍第1項之方法，其中於進行該液相沉積法前先將該^夕基底浸泡於一處理溶液（t r e a t m e n t solution)中以使該石夕基底表面產生SiO H基。 6. 如申請專利範圍第1項之方法，其中該液相沉積法係使用六氟矽酸（H 2S i F 6)之飽和溶液作為與該矽基底反應之 |反應溶液。 | ί 7. 如申請專利範圍第1項之方法，其中於該介電層係為一利用旋塗式玻璃（spin-on glass，S0G)製程所形成之Page 14 1223865 ___________________________________________________ Case No. 90Π5088 ^ J a Ifi ___________________________________________ VI. Patent Application Scope | Perform a yellow light process to define the pattern of the shallow trench in the photoresist layer;: Etching along the pattern of the photoresist layer The first silicon nitride layer and the second silicon oxide layer i up to the surface of the silicon substrate; and I removes the photoresist layer to form the hard mask layer of the defined pattern on the surface of the semiconductor wafer. 3. The method according to item 1 of the patent application scope, wherein the method further comprises a process of forming a liner oxide layer in the shallow trench before forming the first stone oxide layer. 4. The method according to item 3 of the patent application, wherein the lining oxide layer is formed using a thermal oxygenation (therma 1 ο X idati ο η) method to eliminate the # etch process from the bottom of the shallow trench. Damage caused by silicon substrate. 5. The method according to item 1 of the patent application scope, in which the substrate is immersed in a treatment solution (t r e a t m en t solution) before the liquid deposition method is performed to generate SiO H groups on the surface of the substrate. 6. The method according to item 1 of the patent application range, wherein the liquid phase deposition method uses a saturated solution of hexafluorosilicic acid (H 2 S i F 6) as the reaction solution that reacts with the silicon substrate. ί 7. The method according to item 1 of the patent application, wherein the dielectric layer is formed by a spin-on glass (S0G) process.

第15頁 1223865 六、申請專利範圍 SOG 層。曰修正 8·如專利範圍第1項之方法，其中於該介電層係為一利用问始、，電漿沉積（high density plasma, HDP)法或一常壓化學氣相沉積（atmospheric pressure chemical vapor deposition, APCVD)法所形成。 9· 一種於一半導體晶片之一矽基底（siiicori substrate)上製作一淺溝隔離（shaii〇w i s ο 1 a ΐ i ο η， S T I )的方法，該方法包含有下列步驟：於5亥石夕基底表面形成一已定義圖案（patterned )之硬罩幕（hard mask)層；進行一钱刻（etch)製程，以於未被該硬罩幕層覆蓋之該石夕基底中形成一淺溝（t r e n c h ); 於該淺溝内之底部表面以及側壁表面形成一襯氧化 (liner oxide)層; 進行一液相沉積法（1 i q u i d p h a s e d e ρ 〇 s i t i 〇 η， LPD)，以於該淺溝内之該襯氧化層表面形成一第一石夕氧層，用以保護該淺溝之底部結構；進行一高密度電漿化學氣相沉積（h i gh den s i t y plasma chemical vapor deposition, HDP CVD)製裎，以於該半導體晶片表面均勻地形成一第二矽氧層並填滿該淺溝；進行一化學機械研磨製程（chemical mechanicalPage 15 1223865 VI. Application scope SOG layer. Amendment 8. The method as described in the first item of the patent, wherein the dielectric layer is a high-pressure plasma (HDP) method or an atmospheric pressure chemical vapor deposition method. vapor deposition (APCVD). 9. A method for fabricating a shallow trench isolation (shaii〇wis ο 1 a ΐ i ο η, STI) on a siiicori substrate of a semiconductor wafer, the method includes the following steps: A patterned hard mask layer is formed on the surface of the substrate; an etch process is performed to form a shallow groove in the stone substrate not covered by the hard mask layer ( trench); forming a liner oxide layer on the bottom surface and the sidewall surface in the shallow trench; performing a liquid phase deposition method (1 liquidphasede ρ 〇siti 〇η, LPD), A first stone oxide layer is formed on the surface of the lining oxide layer to protect the bottom structure of the shallow trench; a high-density plasma chemical vapor deposition (HDP CVD) process is performed to Forming a second silicon oxide layer uniformly on the surface of the semiconductor wafer and filling the shallow trench; and performing a chemical mechanical polishing process

第16頁 1223865 _________________________ 9011互088____________________ 土屋_____________日優正____________________________________________________________ ί六、申請專利範圍 ipolish， CMP)，以去除該硬罩幕表面上之該第二碎氧層， |並使填入該淺溝内之該第二矽氧層表面約略切齊於該硬罩 i幕層；以及 I ! 去除該硬罩幕層，完成該淺溝隔離製程。 ί |10.如申請專利範圍第9項之方法，其中該硬罩幕層係由 I 一第一氮矽層以及一第三矽氧層上、下堆疊而成，且形成 |該已定義圖案之硬罩幕層的方法係包含有下列步驟：於該石夕基底表面形成該第三石夕氧層；於該石夕氧層表面形成該第一氮碎層；於該第一氮石夕層表面形成一光阻層； .進行一黃光製程，於談光阻層中定義出該淺溝的圖案；沿著該光阻層的圖案蝕刻該第一氮矽層以及該第三矽氧層直至該矽基底表面；以及去除該光阻層，以於該半導體晶片表面形成該已定義圖案之硬罩幕層。 1 1 .如申請專利範圍第9項之方法，其中該襯氧化層係利用一熱氧化（t h e r m a 1 ο X i d a ΐ i ο η)法所形成，以消除該I虫刻製程對該淺溝底部之該矽基底造成之損害。 1 2.如申請專利範圍第9項之方法，其中於進行該液相沉積法前先將該碎基底浸泡於一處理溶液（t r e a t m e n t solution)中以使該石夕基底表面產生SiO H基。Page 16 1223865 _________________________ 9011 Mutual 088____________________ Tsuchiya _____________ Riyouzheng ____________________________________________________________ ί6. Patent application scope ipolish (CMP), to remove the second broken oxygen layer on the surface of the hard cover, and make it filled in The surface of the second silicon oxide layer in the shallow trench is approximately aligned with the hard mask i curtain layer; and I! The hard mask curtain layer is removed to complete the shallow trench isolation process. ί | 10. The method according to item 9 of the scope of patent application, wherein the hard mask layer is formed by stacking I-a first nitrogen silicon layer and a third silicon-oxygen layer on top and bottom, and forming the defined pattern The method for hard-covering the curtain layer includes the following steps: forming the third stone oxide layer on the surface of the stone evening substrate; forming the first nitrogen fragment layer on the surface of the stone evening oxygen layer; and forming the first nitrogen stone layer A photoresist layer is formed on the surface of the layer; a yellow light process is performed to define the pattern of the shallow groove in the photoresist layer; the first silicon nitride layer and the third silicon oxide are etched along the pattern of the photoresist layer Layer to the surface of the silicon substrate; and removing the photoresist layer to form the hard mask curtain layer of the defined pattern on the surface of the semiconductor wafer. 1 1. The method according to item 9 of the scope of patent application, wherein the lining oxide layer is formed by a thermal oxidation (therma 1 ο X ida ΐ i ο η) method to eliminate the bottom of the shallow trench by the I insect engraving process. The damage caused by the silicon substrate. 1 2. The method according to item 9 of the scope of patent application, wherein the crushed substrate is immersed in a treatment solution (t r e a t m e n t solution) before the liquid deposition method is performed to generate SiO H groups on the surface of the stone substrate.

第17頁 1223865 ______________________________________ t藍90115088__________________________________#-_______________月曰 __________________優正六、申請專利範圍 il3.如申請專利範圍第9項之方法，其中該液相沉積法係 | |使用六氟矽酸（H2SiF6)之飽和溶液作為與該矽基底反應之 |反應溶液。 !Page 17 1223865 ______________________________________ t blue 90115088 __________________________________ # -_______________ Month __________________ Youzheng VI, patent application scope il3. For the method of patent application scope item 9, where the liquid phase deposition method system | A saturated solution of H2SiF6) is used as a reaction solution for reacting with the silicon substrate. !