1223579 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種半導體封裝基板 構及其製*，具體而言係有關於一種 】口 = 利用電鑛方式形成有圖案化線路層之及t基板中 r先前技術】 /、衣法。 隨著電子產業的蓬勃發展，電子產σ 月& 、高性能的研發方向。為滿足半導體：裝；ΐ =功 Integration)以及微型化（Miniaturizat =二 ，，提供多數主被動元件及線路載接之印刷電 Prated CirCUlt b = ard)亦逐漸由雙層板演變 Γ二二' ’俾於有限的空間下，藉二ί ，技術Unterlayer c〇nnectlon)擴大電路板上可利用^ 电路面積而配合南電子密度之積體電路 circuit)需求。因此這些電子產品之製作便需e :更：&薄的電路；及電子元件，而隨著此縮小化 不同功能之半導體元件鑲嵌在一電路 2 更南密度之需求。 1朝 $電路板製”界，低成本、高可靠度及高佈 一直疋所追求之目私。為達目標，於是發展出一種增^ 術^Ulld-up)。所謂的增層技術基本上是指在—核心^ 板（Core circult board)表面上利用電路增層製程交％ 疊多層絕緣層及線路層，並於絕緣層中制作導+亡孔養 (Vh)以提供各線路層間之電性連接。/中之電增層制 程係為主要影響電路板製程線路密度之關鍵所在，因此κ iiil1223579 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor package substrate structure and a manufacturing method thereof *, and more specifically, it relates to a type] Mouth = a patterned circuit layer is formed by an electric mining method And the prior art in t substrate] /, clothing method. With the vigorous development of the electronics industry, σ month & high-performance R & D directions for electronics production. In order to meet the requirements of semiconductors: packaging; ΐ = work integration) and miniaturization (Miniaturizat = 2), which provides most of the active and passive components and circuit-carrying printed electricity (Prated CirCUlt b = ard) also gradually evolved from double-layer boards Given the limited space, the technology of Unterlayer (cnonectlon) can be used to expand the circuit board to meet the needs of the integrated circuit of the South Electron Density by expanding the circuit board. Therefore, the production of these electronic products requires e: more: & thin circuits; and electronic components, and as this shrinks, the needs of semiconductor components with different functions embedded in a circuit 2 have a higher density. In the world of "circuit board system", low cost, high reliability and high cloth have always been pursued. In order to achieve the goal, an augmentation technology (Ulld-up) has been developed. The so-called layer-up technology is basically It refers to the use of a circuit build-up process on the surface of a core circult board to stack multiple layers of insulating layers and circuit layers, and to make conductive + dead hole (Vh) in the insulating layer to provide electricity between the circuit layers. Electrical connection. / China's electrical build-up process is the key that mainly affects the circuit density of the circuit board process, so κ iiil
17359 全懋.Ptd 第6頁 1223579 五、發明說明（2) 業者主要係利用可形成細線路之半加成法（SAP)與線路電 鍍法（Pattern plating method)，來製作電路板之增層。 請參閱第1 A至1 C圖，所謂半加成法係提供一核心電路 板1 1，並在其表面形成一絕緣層1 2，且利用雷射鑽孔等方 式於該絕緣層1 2中形成有開口 1 2 0以外露出内層線路 1 1 0 (如第1 A圖所示）。再於該絕緣層1 2上形成一導電晶種 層（無電解銅層）1 3，並在該晶種層1 3上形成圖案化阻層1 4 後進行電鍍製程，以在該晶種層1 3上形成一圖案化線路層 1 5 (如第1 B圖所示）。之後將該阻層1 4剝離並進行姓刻以移 除先前覆蓋於該阻層1 4下之晶種層1 3 (如第1 C圖所示）。如 此運用前述方法重複形成絕緣層與增層線路層，俾以完成 一多層電路板。 然而 為電鍍形 層，由於 而在後續 到侵蝕與 度之線路 所示。此 緣層之表 增加絕緣 程之控制 致線路層 細線路與 ，由於採 成線路層 其材料係 蝕刻移除 破壞，此 時，更將 外，於傳 面必需先 層表面與 不易，若 之剝落， 絕緣層有 用上述習知之半加成法增層技術中，作 之電流導通路徑之晶種層，甚或金屬薄 與所形成之線路層相同，倶為金屬銅， 該晶種層時，同時將會造成該線路層受 一情形尤其對於形成細線路且高積集密 造成線路之嚴重收縮與變形，如第2圖 統增層製程中，在形成線路層前，該絕 4亍表面粗4匕（Surface roughening)，以 線路層之結合力，然而此等表面粗化製 未在該絕緣層表面有效粗化，將容易導 尤其對於細線路之電路板而言，由於該 效接合面積減少，而為使該細線路有效17359 Quan 懋 .Ptd Page 6 1223579 V. Description of the Invention (2) The industry mainly uses the semi-additive method (SAP) and the pattern plating method for forming thin circuits to make circuit board additions. Please refer to Figs. 1A to 1C. The so-called semi-additive method provides a core circuit board 1 1 and an insulating layer 12 is formed on the surface, and laser insulating holes 12 are used in the insulating layer 12 The inner layer circuit 1 10 is exposed outside the opening 1 2 0 (as shown in FIG. 1A). Then, a conductive seed layer (electroless copper layer) 13 is formed on the insulating layer 12, and a patterned resist layer 1 4 is formed on the seed layer 13 and then a plating process is performed to form the seed layer. A patterned circuit layer 15 is formed on 13 (as shown in FIG. 1B). Thereafter, the resist layer 14 is peeled off and engraved to remove the seed layer 1 3 previously covered under the resist layer 14 (as shown in FIG. 1C). In this way, the foregoing method is repeatedly used to form the insulating layer and the build-up circuit layer to complete a multilayer circuit board. However, it is an electroplated layer, as shown in the subsequent lines to erosion and corrosion. The surface of this marginal layer increases the control of the insulation process, which results in fine lines on the circuit layer. The material of the circuit layer is removed by etching to remove the damage. At this time, the outer surface must be layered and difficult to pass. If it is peeled off, The insulating layer can use the seed layer of the current conduction path in the conventional semi-additive layer-adding technology, or even the thin metal layer is the same as the circuit layer formed, and the metal layer is copper. When the seed layer is used, It will cause the circuit layer to be affected by a situation, especially for the formation of thin lines and high accumulation density, which will cause severe contraction and deformation of the line. (Surface roughening), based on the bonding force of the circuit layer, however, these surface roughening systems do not effectively roughen the surface of the insulating layer, which will easily lead to the reduction of the bonding area of the circuit, especially for thin circuit boards. To make this fine line effective
i 17359 全懋.ptd 第7頁 1223579 五、發明說明（3) 結合於絕緣層表面，該絕緣層表面之粗化程度勢必造成製 程之困難度。 【發明内容】 鑒於以上所述習知技術之缺點，本發明之主要目的在 提供一種半導體封裝基板之圖案化線路結構及其製法，藉 以避免移除導電晶種層時，亦會對所形成之線路層產生破 壞等問題。 本發明之另一目的係提供一種半導體封裝基板之圖案 化線路結構及其製法，以強化線路層與絕緣層之接合性。 為達成上揭及其他目的，本發明揭露一種半導體封裝 基板之圖案化線路結構製法，其主要製程係包含提供一具 内層線路之基板，以於該基板表面形成一絕緣層，且該絕 緣層形成有複數個開口以外露出内層線路；於該絕緣層及 開口表面形成一金屬導電層，並在該金屬導電層上形成一 圖案化阻層，俾外露出部分該金屬導電層；進行電鍍製程 以在該金屬導電層上形成一圖案化線路層；以及移除該阻 層及其所覆蓋之金屬導電層，其中該金屬導電層之#刻速 率遠大於該圖案化線路層之蝕刻速率。 藉由本發明前述之製法，乃提供一種半導體封裝基板 之圖案化線路結構，其包括有一絕緣層；一圖案化線路 層，係形成於該絕緣層上；以及一金屬導電層，係形成於 該層間線路層及該線路層與該絕緣層之交接面間，且該金 屬導電層之蝕刻速率遠大於該圖案化線路層之蝕刻速率。 由於本發明係先在基板之絕緣層表面上形成一蝕刻速i 17359 懋 .ptd Page 7 1223579 V. Description of the invention (3) Combined with the surface of the insulation layer, the degree of roughening of the surface of the insulation layer will inevitably cause difficulties in the process. [Summary of the Invention] In view of the shortcomings of the conventional techniques described above, the main object of the present invention is to provide a patterned circuit structure of a semiconductor package substrate and a method for manufacturing the same, so as to avoid the removal of the conductive seed layer, it also affects the formation of the conductive seed layer. Problems such as damage to the line layer. Another object of the present invention is to provide a patterned circuit structure of a semiconductor package substrate and a manufacturing method thereof, so as to strengthen the bonding between the circuit layer and the insulating layer. In order to achieve the disclosure and other purposes, the present invention discloses a method for manufacturing a patterned circuit structure of a semiconductor package substrate. The main process includes providing a substrate with an inner layer circuit to form an insulating layer on the surface of the substrate, and the insulating layer is formed. The inner layer circuit is exposed outside the plurality of openings; a metal conductive layer is formed on the insulating layer and the surface of the opening, and a patterned resistive layer is formed on the metal conductive layer, and a part of the metal conductive layer is exposed outside; Forming a patterned circuit layer on the metal conductive layer; and removing the resist layer and the metal conductive layer covered by the metal conductive layer, wherein the #etch rate of the metal conductive layer is much greater than the etching rate of the patterned circuit layer. According to the aforementioned manufacturing method of the present invention, a patterned circuit structure of a semiconductor package substrate is provided, which includes an insulating layer; a patterned circuit layer is formed on the insulating layer; and a metal conductive layer is formed between the layers. The circuit layer and the interface between the circuit layer and the insulating layer, and the etching rate of the metal conductive layer is much greater than the etching rate of the patterned circuit layer. Since the present invention first forms an etching rate on the surface of the insulating layer of the substrate
17359 全懋.ptd 第8頁 1223579 五、發明說明（4) 率遠大於基板圖案化線路結構材質之金屬導電層，以作為 後續在該金屬導電層上電鍍形成圖案化線路層所需之電流 導通路徑，而在電鍍完成圖案化線路層後，移除未為該線 路層所覆蓋之金屬導電層，因該線路層（一般為金屬銅）與 該金屬導電層（例如··鉻（Cr)、鎳（Ni )、錫（Sn)、錫（Sn)/ 鉛（Pb )、鈦（T i )…等材質）之蝕刻選擇性差異極大，因此 蝕刻該金屬導電層不致傷害該線路層，得以保持該線路層 之設計尺寸；再者，由於該金屬導電層係先形成於該絕緣 層上，當金屬導電層為鉻（C r )時，將可用以增強線路層與 絕緣層之附著力，藉以提供後續形成該金屬導電層之線路 層有效接合於該絕緣層上。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 請參閱第3A至第3F圖將詳細說明本發明中半導體封裝 基板之圖案化線路結構製法較佳實施例。其中，須注意的 是，該等圖式均為簡化之示意圖，僅以示意方式說明本發 明之基本架構。因此，在該等圖式中僅顯示與本發明有關 之元件，且所顯示之元件並非以實際實施時之數目、形 狀、及尺寸比例等加以繪製，其實際實施時之數目、形狀17359 Quan 懋 .ptd Page 8 1223579 V. Description of the invention (4) A metal conductive layer with a rate much greater than the material of the patterned circuit structure of the substrate, as a current conduction required for subsequent plating on the metal conductive layer to form a patterned circuit layer Path, and after electroplating the patterned circuit layer, remove the metal conductive layer that is not covered by the circuit layer, because the circuit layer (usually metal copper) and the metal conductive layer (such as chromium (Cr), Nickel (Ni), tin (Sn), tin (Sn) / lead (Pb), titanium (Ti), etc.) have very different etching selectivity, so etching the metal conductive layer will not harm the circuit layer and can be maintained Design dimension of the circuit layer; Furthermore, since the metal conductive layer is first formed on the insulating layer, when the metal conductive layer is chromium (C r), it can be used to enhance the adhesion between the circuit layer and the insulating layer, thereby A circuit layer for subsequently forming the metal conductive layer is effectively bonded to the insulating layer. [Embodiment] The following describes the embodiment of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention may also be implemented or applied by other different specific embodiments, and various details in this specification may also be based on different viewpoints and applications, and various modifications and changes may be made without departing from the spirit of the present invention. Please refer to FIGS. 3A to 3F to describe a preferred embodiment of a method for manufacturing a patterned circuit structure of a semiconductor package substrate in the present invention. It should be noted that these drawings are simplified schematic diagrams, and the basic structure of the present invention is only illustrated schematically. Therefore, in these drawings, only the elements related to the present invention are shown, and the displayed elements are not drawn according to the number, shape, and size ratio of the actual implementation, and the number and shape of the actual implementation
17359 全懋.ptd 第9頁 1223579 五、發明說明（5) - 及尺寸比例為〆種選擇性之設計’且其元件佈局形態可能 更為複雜。 如第3A圖所示，製備一内層基板（Inner SUbStrate)31，該内層基板係由—具預定厚度之樹脂怒層 311及形成於該怒層表面上之内層線路312所構成。立中嗜 樹脂芯層311中町形成有複數個電鍍貫穿孔（ρτΗ)(未圖 示），藉此電性速結該樹脂芯層表面上之内層線路，舍 然，該内層基板亦可為一具多層線路之多層板。 田 如第3Β圖所示，於該内層基板上形成介電絕緣層32, 並於該介電絕緣層32中形成有開口 32〇以顯露出該内層基 板表面之内層線路3 1 2。該絕緣層32可為熱固性樹脂 (Thermosetting resin)或光顯像樹脂 resin) ’若該絕緣層32為熱固性樹脂則以雷射鑽孔形成開 口 3 2 0 ’又絕緣層3 2若為光顯像樹脂則以曝光顯影的方 式成形開口 3 2 0。 ' ” 如第3C圖所示，接著於該絕緣層32及其開口 32〇表面 形成作為電鐘導電層之金屬導電層33，而該金屬導電層可 為鉻（Cr)、鎳（Ni)、錫（Sn)、錫（Sn) /雜（P b)、鈦（T i )所 構成之群組之其中一者，且該金屬導電層3 3係可以物理氣 相沈積、化學氣相沈積、無電電鍵或化學沈積等方式，例 如濺鍍（Sput ter i ng)、蒸鍍（E vapor at i on)、電弧蒸氣沈 積（Arc vapor deposition)、離子束濺鍍(I on beam sputtering)、雷射溶散沈積（Laser ablation deposition)、電漿促進之化學氣相沈積或無電電鍍等方17359 Quan 懋 .ptd Page 9 1223579 V. Description of the invention (5)-and the size ratio is a kind of selective design ', and its component layout may be more complicated. As shown in FIG. 3A, an inner layer substrate (Inner SUbStrate) 31 is prepared. The inner layer substrate is composed of a resin layer 311 having a predetermined thickness and an inner layer circuit 312 formed on the surface of the layer. A plurality of plated through-holes (ρτ 未) (not shown) are formed in Lizhong resinophilic core layer 311 Nakamachi, thereby electrically fasting the inner layer circuit on the surface of the resin core layer. In addition, the inner substrate can also be a Multilayer board with multilayer circuits. As shown in FIG. 3B, a dielectric insulating layer 32 is formed on the inner substrate, and an opening 32 is formed in the dielectric insulating layer 32 to expose the inner layer circuits 3 1 2 on the surface of the inner substrate. The insulating layer 32 may be a thermosetting resin (resin) or a light developing resin. 'If the insulating layer 32 is a thermosetting resin, openings are formed by laser drilling 3 2 0', and if the insulating layer 32 is a light developing The resin forms the opening 3 2 0 by exposure and development. As shown in FIG. 3C, a metal conductive layer 33 as a clock conductive layer is formed on the surface of the insulating layer 32 and its opening 32. The metal conductive layer may be chromium (Cr), nickel (Ni), One of the groups consisting of tin (Sn), tin (Sn) / doped (P b), and titanium (T i), and the metal conductive layer 33 can be physically vapor-deposited, chemical vapor-deposited, Non-electrical bond or chemical deposition, such as sputtering (eputation), evaporation (e vapor at i on), arc vapor deposition (ion vapor deposition), ion beam sputtering (I on beam sputtering), lightning Laser ablation deposition, plasma-assisted chemical vapor deposition or electroless plating, etc.
17359全想.ptd 第10頁 1223579 五、發明說明（6) 法形成。 如第3 D圖所示，再於該金屬導電層上利用印刷、旋塗 或貼合等方式覆蓋有阻層34，該阻層3 4可例如為乾膜或液 態光阻等之光阻層（Photoresist)，並可藉由曝光 (Exposure)及顯影（Development)等圖案化製程使該阻層 3 4形成有複數個開口 3 4 0，藉以顯露出欲形成有圖案化線 路層之部分金屬導電層3 3。其中至少有一阻層開口 3 4 0係 對應至該絕緣層開口 3 2 0，俾供後續於該絕緣層開口 3 2 0中 形成導電盲孔。 如第3 E圖所示，接著進行電鍍製程以在該阻層開口 3 4 0中之該金屬導電層3 3上電鍍形成有圖案化線路層3 5以 及於該絕緣層開口 3 2 0中形成有導電盲孔3 5 1，俾使該圖案 化線路層3 5可透過導電盲孔3 5 1以電性連接至該内層線路 312° 如第3 F圖所示，復將該阻層3 4、與覆蓋於該阻層3 4下 之金屬導電層3 3移除，而由於在移除部分該金屬導電層33 時，因其蝕刻速率遠大於所形成之線路層3 5，所以在以蝕 刻方式去除時並不會破壞該線路層3 5尺寸，進而避免導致 線路收縮等問題。 請參閱第3 F圖所示，本發明亦提供一種半導體封裝基 板之圖案化線路結構，其包括有一絕緣層3 2 ; —圖案化線 路層3 5，係形成於該絕緣層3 2上；以及一金屬導電層33， 係形成於該線路層3 5與該絕緣層3 2之交接面間，且該金屬 導電層33之材質（如鉻（Cr)、鎳（Ni )、錫（Sn)、錫（Sn)/鉛17359 全 想 .ptd Page 10 1223579 V. Description of Invention (6) Method formation. As shown in FIG. 3D, the metal conductive layer is further covered with a resist layer 34 by printing, spin coating or lamination, and the resist layer 34 may be a photoresist layer such as a dry film or a liquid photoresist. (Photoresist), and a plurality of openings 3 4 0 can be formed in the resist layer 3 4 through a patterning process such as exposure and development, so as to reveal that a portion of the metal where a patterned circuit layer is to be formed is conductive Layer 3 3. At least one of the barrier layer openings 3 4 0 corresponds to the insulating layer opening 3 2 0 and is used for subsequent formation of conductive blind holes in the insulating layer opening 3 2 0. As shown in FIG. 3E, a plating process is then performed to form a patterned circuit layer 3 5 on the metal conductive layer 3 3 in the resist opening 3 4 0 and to be formed in the insulating layer opening 3 2 0 There are conductive blind holes 3 5 1 so that the patterned circuit layer 3 5 can be electrically connected to the inner layer circuit 312 ° through the conductive blind holes 3 5 1. As shown in FIG. 3 F, the resist layer 3 4 is repeated. And the metal conductive layer 33 covered under the resistive layer 34 is removed, and since a part of the metal conductive layer 33 is removed, because the etching rate is much higher than the formed circuit layer 35, it is being etched with When the method is removed, the size of the circuit layer 35 will not be destroyed, thereby avoiding problems such as causing circuit shrinkage. Please refer to FIG. 3F. The present invention also provides a patterned circuit structure of a semiconductor package substrate, which includes an insulating layer 3 2; a patterned circuit layer 35 is formed on the insulating layer 32; and A metal conductive layer 33 is formed between the interface between the circuit layer 35 and the insulating layer 32, and the material of the metal conductive layer 33 (such as chromium (Cr), nickel (Ni), tin (Sn), Tin (Sn) / Lead
17359 全懋.ptd 第11頁 1223579 五、發明說明（7) (Pb )、鈦（T i )所構成之群組之其中一者）於適當蝕刻條件 下，其蝕刻速率遠大於該圖案化線路層3 5之材質（銅）。俾 藉由該金屬導電層3 3之形成以避免增層製程中非預期發生 之線路收縮問題。 由於本發明之半導體封裝基板之圖案化線路結構及其 製法係在基板之絕緣層表面上形成一金屬導電層，以作為 後續在該金屬導電層上電鍍形成線路層時所需之電流導通 路徑，而後續在移除未為該線路層所覆蓋之金屬導電層， 因該線路層之材質與該金屬導電層之材質不同，因此透過 蝕刻等製程移除該金屬導電層時不致傷害該線路層，得以 保持該線路層之設計尺寸；再者，由於該金屬導電層係先 形成於該絕緣層上，據業界之習知技藝，當金屬導電層為 鉻（C r )時，亦可用以增強線路層與絕緣層之附著力，藉以 提供後續形成該金屬導電層之線路層有效接合於該絕緣層 上，俾防止習知增層製程中所產生之線路收縮以及線路剝 離等問題。 本發明先前圖式中僅以部分圖案化線路表示，實際上 該圖案化線路之密度，係依實際製程所需而加以設計並分 佈於基板中，且該製程可實施於電路板之單一側面或雙側 面。上述實施例僅為例示性說明本發明之原理及其功效， 而非用於限制本發明。任何熟習此技藝之人士均可在不違 背本發明之精神及範疇下，對上述實施例進行修飾與變 化。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。17359 Quan 懋 .ptd Page 11 1223579 V. Description of the invention (one of the group consisting of (7) (Pb) and titanium (T i)) Under appropriate etching conditions, the etching rate is much larger than the patterned line Material of layer 3 5 (copper).形成 Through the formation of the metal conductive layer 3 3 to avoid unexpected circuit shrinkage during the build-up process. Because the patterned circuit structure of the semiconductor package substrate of the present invention and the manufacturing method thereof form a metal conductive layer on the surface of the insulating layer of the substrate as a current conduction path required when the circuit layer is subsequently plated on the metal conductive layer, In the subsequent removal of the metal conductive layer that is not covered by the circuit layer, the material of the circuit layer is different from that of the metal conductive layer. Therefore, the metal conductive layer is not damaged by removing the metal conductive layer through processes such as etching. The design size of the circuit layer can be maintained; further, since the metal conductive layer is first formed on the insulation layer, according to the industry's conventional technology, when the metal conductive layer is chromium (C r), it can also be used to strengthen the circuit. The adhesion between the layer and the insulating layer provides effective bonding of the circuit layer that subsequently forms the metal conductive layer to the insulating layer, and prevents problems such as circuit shrinkage and circuit peeling that occur during the conventional build-up process. In the previous drawings of the present invention, only part of the patterned lines are used. In fact, the density of the patterned lines is designed and distributed in the substrate according to the actual manufacturing process, and the process can be implemented on a single side of the circuit board or Double sides. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.
17359 全懋.ptd 第12頁 1223579 圖式簡單說明 【圖式簡單說明】 第1 A至1 C圖係顯示習知半加成法之製程剖面示意圖； 第2圖係顯示習知半加成法中線路層受側蝕破壞之剖 面示意圖；以及 第3A至3F圖係顯示本發明之半導體封裝基板之圖案化 線路結構製法剖面示意圖。 11 核心電路板 12 絕緣層 13 晶種層 14 阻層 15 線路層 110 内層線路 120 開口 30 半導體封裝基板 31 内層基板 32 絕緣層 33 金屬導電層 34 阻層 35 線路層 311 芯層 312 内層線路 320 開口 340 阻層開口 351 導電盲孔17359 Quan 懋 .ptd Page 12 1223579 Brief description of the drawings [Simplified description of the drawings] Figures 1 A to 1 C are schematic sectional views showing the process of the conventional semi-additive method; Figure 2 shows the conventional semi-additive method A schematic cross-sectional view of a middle circuit layer damaged by side etching; and FIGS. 3A to 3F are schematic cross-sectional views showing a method for manufacturing a patterned circuit structure of a semiconductor package substrate of the present invention. 11 Core circuit board 12 Insulating layer 13 Seed layer 14 Resistive layer 15 Circuit layer 110 Inner circuit 120 Opening 30 Semiconductor package substrate 31 Inner substrate 32 Insulating layer 33 Metal conductive layer 34 Resistive layer 35 Circuit layer 311 Core layer 312 Inner circuit 320 Opening 340 resist opening 351 conductive blind hole
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