TWI223426B - Electric connection structure of semiconductor package substrate and method for fabricating the same - Google Patents
Electric connection structure of semiconductor package substrate and method for fabricating the same Download PDFInfo
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- TWI223426B TWI223426B TW92134979A TW92134979A TWI223426B TW I223426 B TWI223426 B TW I223426B TW 92134979 A TW92134979 A TW 92134979A TW 92134979 A TW92134979 A TW 92134979A TW I223426 B TWI223426 B TW I223426B
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五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種半 構及其製法，具體而言係有 形成圖案化線路層，並在其 電性連接蟄之外露表面電錢 之結構及其製法。 【先前技術】 導體封裝基板之電性連接端結 關一種在半導體封裝基板表面 打線墊、凸塊銲墊或錫球墊等 形成一可為鎳/金金屬保護層 ^ ^者電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、南性能的研發方向。為滿足半導體封裝件高積集度（ Integration)以及微型化（Miniaturizati〇n)的封裝需求 ，提供多數主被動元件及線路載接之印刷電路板（printed circuit board)亦逐漸由雙層板演變成多層板（心1七1一 layer board) ’俾於有限的空間下，藉由層間連接技術（ Interlayer connection)擴大電路板上可利用的電路面積 而配合高電子密度之積體電路（lntegrated circuit)需 求。因此這些電子產品之製作便需要使用比以前更小、更 薄的電路板及電子元件，而隨著此縮小化之趨勢，各種不 同功能之半導體元件鑲嵌在一電路板上則有朝更高密度之 需求。 由於電子產業之相關技術快速提昇，且伴隨電子產品 輕小化之趨勢’半導體封裝基板制造業者亦面臨著製程上 許多關鍵處。其中，用於半導體封裝基板之表面即形成有 多數例如由銅材質所組成之導電線路，並由其加以延伸而 成之電性連接墊，以作為傳輸電子訊號或電源，同時，通V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semi-structure and a manufacturing method thereof. Specifically, the invention relates to a method for forming a patterned circuit layer and exposing the surface of the electric money on the surface of its electrical connection. Structure and method of making it. [Previous technology] The electrical connection end of the conductive package substrate is a type of wire pad, bump pad or solder ball pad on the surface of the semiconductor package substrate to form a protective layer of nickel / gold metal. Electronic products are also gradually entering the direction of multi-functional and southern performance research and development. In order to meet the packaging requirements for high integration and miniaturization of semiconductor packages, printed circuit boards that provide most of the active and passive components and lines have gradually evolved from double-layer boards to Multilayer board (heart 171 layer board) 'Confined to a limited space, the interlayer connection technology (Interlayer connection) is used to expand the circuit area available on the circuit board to match the high electron density integrated circuit (lntegrated circuit) demand. Therefore, the production of these electronic products requires the use of smaller and thinner circuit boards and electronic components than before. With this trend of reduction, semiconductor components with different functions are embedded in a circuit board with a higher density. Demand. Due to the rapid advancement of related technologies in the electronics industry, along with the trend toward miniaturization of electronic products, semiconductor package substrate manufacturers are also facing many key points in the manufacturing process. Among them, the surface of the substrate for semiconductor packaging is formed with a plurality of conductive wirings made of copper, for example, and an electrical connection pad formed by extending the conductive wirings, which is used to transmit electronic signals or power.
17555 全懋.ptd 第9頁 1223426 五、發明說明（2) 常會在該電 之金屬層， 錫或銲球與 境影響而導 該電性 性耦合之凸 pad)；該電 電性耦合之 電性耦合之 外露表面形 屬層内之電 而氧化，以 連接墊之電 性連接墊之外露表面开彡 ”士… 衣Φ ^成有一如鎳/金（Ni/Au; 以有效提供其與導電亓杜 B u ^ ，、守电7^件如金線、凸塊、預銲 :，電路板之電性耦合，亦可避免因外界環 致該電性連接墊本體之氧化。 $接墊可例如為半導體覆晶封裝基板與晶片電 塊銲墊（Bump pad)或預銲錫銲墊（pres〇Uer 性連接整亦可為打線式半導體封裳基板與晶片 銲墊（Finger)，以及例如封裝基板與電路板作 銲球墊（Ball pad)。藉由在該電性連接墊本體 成有一鎳/金金屬層，以提供包覆於該鎳/金金 性連接墊（通常為金屬銅）不易因外界環境影響 提咼金線、凸塊 '預銲錫或銲球等植設於電性 性連接品質。 請參閱第1 A至1 Η圖，為習知技藝中採用可製你4 # 之丰加成法（SAP )以形成圖案化線路層之結構，以及利 無電鍍導線（NPL)電鍍製程以在該線路層之電性連接塾2 電鍍形成有鎳/金金屬層之方法示意圖。其係在一美板李 面絕緣層1 1上形成一導電膜i 2，再於該導電獏丨形成二 第一圖案化阻層1 3 (如第1 A圖所示），俾使該圖案化阻層i 3 形成複數開口 1 3〇以外露出該導電膜1 2，之後再進行電\ 製程，以在該阻層開口 1 3 0中之導電膜1 2上形成—圖案化 線路層1 4 (如第丨B圖所示）。之後將該阻層1 3剝離並進行餘 刻以移除先前覆蓋於該阻層1 3下之導電膜1 2 (如第丨(：圖 示）。17555 Quan 懋 .ptd Page 9 1223426 V. Description of the invention (2) The electrical pads that often lead to the electrical coupling in the metal layer of the electricity, tin or solder balls and the environment); the electrical properties of the electrical electricity coupling The exposed surface of the coupling is oxidized in the shape of the layer, and the exposed surface of the electrical connection pad of the connection pad is opened. The coat is made of nickel / gold (Ni / Au; to effectively provide it with conductive 亓). Du B ^, 7 ^ pieces of electricity, such as gold wires, bumps, pre-soldering :, the electrical coupling of the circuit board, can also avoid the oxidation of the electrical connection pad body due to external loops. For semiconductor flip-chip packaging substrates and wafer pads (bump pads) or pre-soldering solder pads (pres solder joints) can also be wire-type semiconductor sealing substrates and wafer pads (Finger), and for example, packaging substrates and The circuit board is used as a ball pad. By forming a nickel / gold metal layer on the body of the electrical connection pad, the nickel / gold metal connection pad (usually metal copper) is provided so as not to be easily affected by the outside world. Environmental impacts: gold wires, bumps, 'pre-solder or solder balls, etc. Quality. Please refer to the first 1 to 1 drawings, the structure of patterned circuit layer is formed by using the additive addition method (SAP) that can make you 4 # in the conventional technique, and the non-plated wire (NPL) plating process A schematic diagram of a method of electroplating a nickel / gold metal layer by electrically connecting the circuit layer 2 to the circuit layer. The method is to form a conductive film i 2 on a U.S. board insulating layer 1 1 and then form the conductive layer 丨Two first patterned resist layers 1 3 (as shown in FIG. 1A), the patterned resist layer i 3 is formed to form a plurality of openings 1 30 and the conductive film 12 is exposed, and then an electrical process is performed to Formed on the conductive film 12 in the resist opening 1 30-a patterned circuit layer 14 (as shown in FIG. 丨 B). Then the resist layer 13 is peeled off and left to remove the previous cover. The conductive film 1 2 under the resist layer 13 (as shown in the figure).
17555 全懋.ptd 第10頁 1223426 五、發明說明（3) 如上述製程即完成所需之前段製程而在封裝基板之表 面上形成有圖案化之線路層1 4，之後，再利用無電錢導線 (N P L)電鍵製程以在該線路層1 4之電性連接整1 4 〇上電鐘形 成有錄/金金屬層。首先係在該基板表面之線路層1 4上形 成一導電膜1 5，以作為後續進行電鍍之電流傳導路徑，並 在該導電膜1 5上形成一第二圖案化阻層1 6，並使該第二阻 層16具有複數個弟一開口 以露出該開口下方為導電 膜1 5所覆蓋作為電性連接墊1 40區域之部分線路層（如第i D 圖所示）。接著移除未被該第二阻層所覆蓋之導電膜i 5， 此時該第二阻層之開口區底緣處殘露有部分之導電膜1 5 ( 如第1 E圖所示）。再於該第二阻層1 6上形成一第三圖案化 阻層1 7，並使該第三阻層1 7覆蓋住外露於該第二阻層之開 口區之導電膜1 5，且該電性連接墊1 4 〇係外露出於該第三 阻層1 7 (如第1 F圖所示）。然後，進行電鍍製程，以在電性 連接墊140之外露表面上，電鍍形成一如鎳/金之金 層1 8 (如第1 G圖所示）。之後，將該第三圖案化阻層丨7盥第 ::案:匕：層16剝•，並進行蝕刻以移除先前覆蓋於該阻 ίΐϋ膜15, U成金屬保護層覆蓋於該電性接觸墊 二第1Γ所示）。最後，可再於該半導體封裝 “ ί:i Ϊ 巨銲層，並使該拒銲層形成有開孔，以 外路出该電性連接墊之金屬保護層，該 供與晶片或電路板作為電性連接之介面（未圖連:塾即了k 然而’上述習知在基板上電鍍形丁 構與電性連接墊表面t^有圖案化之線路結 安墊表面之金屬保4層時，係於該基板表面之17555 全懋 .ptd Page 10 1223426 V. Description of the invention (3) As the above process is completed, the required previous process is completed, and a patterned circuit layer 14 is formed on the surface of the package substrate, and then, a non-money wire is used (NPL) A keying process is performed to form a recording / gold metal layer on the electrical clock of the circuit layer 14 for the electrical connection. First, a conductive film 15 is formed on the circuit layer 14 on the surface of the substrate as a current conduction path for subsequent electroplating, and a second patterned resist layer 16 is formed on the conductive film 15 and The second resistive layer 16 has a plurality of openings to expose part of the circuit layer covered by the conductive film 15 as an electrical connection pad 1 40 under the opening (as shown in FIG. I D). Then, the conductive film i 5 not covered by the second resistance layer is removed. At this time, a part of the conductive film 15 is left at the bottom edge of the opening area of the second resistance layer (as shown in FIG. 1E). A third patterned resist layer 17 is formed on the second resist layer 16, and the third resist layer 17 covers the conductive film 15 exposed in the opening area of the second resist layer, and the The electrical connection pad 14o is exposed to the third resist layer 17 (as shown in FIG. 1F). Then, a plating process is performed to form a gold layer 18 as shown in FIG. 1G on the exposed surface of the electrical connection pad 140 by electroplating. After that, the third patterned resist layer is removed: and the case: layer: layer 16 is peeled and etched to remove the previously covered resist film 15, U forming a metal protective layer covering the electrical property. Contact pad 2 (shown 1Γ). Finally, the semiconductor package “ί: i 巨 giant solder layer can be formed, and the solder resist layer can be formed with an opening, and the metal protective layer of the electrical connection pad can be routed out. The interface of the sexual connection (not shown in the picture: 塾 就 k, but when the above-mentioned conventional plating on the substrate and the surface of the electrical connection pad t ^ patterned circuit junction pad surface of the metal security layer, the system On the surface of the substrate
ϋ 厶 J4·!·厶 U 五、發明說明（4) _ 絕緣層上先杆费— 圖案化阻層盍一導電膜，並在該導電膜上形成〜第一 並於該圖案化*義出圖案化線路層，之後移除5亥第〜阻層 電膜上形成_ =路層上覆蓋一第二導電膜，再於該第二導 口而顯露出二圖案化阻層，藉該第二圖案化阻層之開 露於該第二图崇接墊並為避免後續之電鑛製程時將殘 金金屬保護芦^ 層之開口區之第二導電膜亦電鍍有鎳 需形成一第^圖吏八與基板之線路層造成短路之情形，則 層之開口區之第案，阻層以覆蓋住外露於該第二圖案化阻 導通路禋以於該;；，膜，俾透過該第二導電膜作為電流 佳電性連接品質之入 ' 接墊表面上以電鍍之方式形成具較 。 、 至屬保護層。然而上述之製程過於繁複 雲此’業界發展屮 ^ 直接在基板表面之用二次阻層覆蓋之製程，以 ，如第形；有錄/金金屬層 第-圖案化阻層23,二所；V;再導電膜22上形成-以外露出該導電膜22:Λ 9ϊ 2具有第—開口 23° 23。内電鑛形成1=2= V妾著於該第-開口 間茶化線路層2 4 (如第2 C圖所千、· h 於該形成有圖案化線路層24之基板表面上覆甚二上，然後 化阻層25’以使該第二阻層25具有第;第二圖案 該線路層之電性連接塾部分240,其中，m =外露出 24 0處之該弟二開口 25〇尺寸係小於對 連接墊 第所示)’·接著進行電鑛製程，以於顯：出了二厶 4J4 ·! · 厶 U V. Description of the invention (4) _ First charge on the insulating layer — a patterned resist layer 盍 a conductive film, and formed on the conductive film ~ the first and patterned * Pattern the circuit layer, and then remove the resist film from the 5th layer to form _ = a second conductive film is covered on the circuit layer, and then two patterned resist layers are exposed at the second guide port, and the second The opening of the patterned resist layer is exposed on the second picture, and the second conductive film of the opening area of the reed layer is also plated with nickel in order to avoid the subsequent electro-mine production process. In the case of a short circuit between the circuit layer of the substrate and the substrate, the first layer of the layer's opening area, the resistance layer to cover the second patterned conductive path exposed to the film; The conductive film serves as a good quality of electrical connection. The surface of the pad is formed by electroplating. , To the protective layer. However, the above process is too complicated. This industry development is a process of directly covering the surface of the substrate with a second resistance layer, such as the shape; there are recorded / gold metal layer-patterned resistance layer 23, two; V; formed on the conductive film 22-the conductive film 22 is exposed outside: Λ 9ϊ 2 has a first opening 23 ° 23. The internal electricity ore is formed 1 = 2 = V and is attached to the teatified circuit layer 2 of the first-opening (as shown in FIG. 2C,... H is superimposed on the surface of the substrate on which the patterned circuit layer 24 is formed. Then, the resistive layer 25 'is formed so that the second resistive layer 25 has a first; the second pattern of the electrical connection portion 240 of the circuit layer, where m = the size of the second opening 25 exposed at 24 o Is less than that shown on the connection pad) '· Then proceed to the electric mining process to show:
17555 全懋.ptd 第12頁 1223426 五、發明說明（5) 口 2 5 0内之該電性連接墊2 4 0上電鑛形成有第一金屬保護層 2 6 1 (如鎳金屬層）及第二金屬保護層2 6 2 (如金金屬層）（如 第2 E圖所示）；之後移除該第二阻層2 5、第一阻層2 3及其 所覆蓋之導電膜22 (如第2F圖所示）。 上述習知製程中，雖可簡化該SAP與NPL電鐘製程，惟 該電性連接墊表面之金金屬層係僅覆蓋於該鎳金屬層之上 表面，而在後續蝕刻去除該導電膜時將無法提供該鎳金屬 層側邊有效保護，導致該鎳金屬易受蝕刻溶液之側蝕而析 出，甚而造成蝕刻溶液污染等問題，嚴重影響後續之蝕刻 品質與速度，同時造成該電性連接墊與外界電性連接之可 靠度下降。再者，係由於該第二圖案化阻層中供顯露電性 連接墊之第二開口係小於對應處之第一開口 ，即令該第二 圖案化之阻層開口之尺寸相對變小，使形成該第二圖案化 阻層時所需之曝光精度較高，導致所需製程時間較長且繁 瑣。 【發明内容】 鑒於以上所述習知技術之問題，本發明之主要目的係 在提供一種半導體封裝基板之電性連接端結構及其製法， 以減化製程步驟，進而提高該半導體封裝基板之生產效率 〇 本發明之另一目的係在提供一種半導體封裝基板之電 性連接端結構及其製法，以避免鎳金屬保護層受蝕刻溶液 破壞析出所導致蝕刻品質及速率下降等問題。 為達成上揭及其他目的，本發明揭露一種半導體封裝17555 Quan 懋 .ptd Page 12 1223426 V. Description of the invention (5) The electrical connection pad 2 4 0 in the port 2 5 0 is formed with a first metal protective layer 2 6 1 (such as a nickel metal layer) and The second metal protective layer 2 6 2 (such as a gold metal layer) (as shown in FIG. 2E); thereafter, the second resistive layer 25, the first resistive layer 23, and the conductive film 22 covered by it are removed ( (As shown in Figure 2F). In the above conventional manufacturing process, although the SAP and NPL electric clock manufacturing processes can be simplified, the gold metal layer on the surface of the electrical connection pad only covers the upper surface of the nickel metal layer, and will be removed when the conductive film is subsequently etched to remove the conductive film. Failure to provide effective protection of the side of the nickel metal layer, causing the nickel metal to be susceptible to precipitation from the side of the etching solution, and even causing problems with the etching solution, which seriously affects subsequent etching quality and speed, and also causes the electrical connection pad and the The reliability of the external electrical connection is reduced. Furthermore, because the second opening of the second patterned resistive layer for exposing the electrical connection pad is smaller than the corresponding first opening, the size of the opening of the second patterned resistive layer is relatively small, so that The exposure accuracy required for the second patterned resist layer is relatively high, resulting in a long and complicated process. [Summary of the Invention] In view of the problems of the conventional technology described above, the main object of the present invention is to provide an electrical connection terminal structure of a semiconductor package substrate and a method for manufacturing the same, so as to reduce the number of process steps and thereby improve the production of the semiconductor package substrate. Efficiency. Another object of the present invention is to provide an electrical connection terminal structure of a semiconductor package substrate and a method for manufacturing the same, so as to avoid problems such as degradation of etching quality and rate caused by the nickel metal protective layer being damaged and precipitated by the etching solution. In order to achieve the disclosure and other objectives, the present invention discloses a semiconductor package
Π555 全懋.ptd 第13頁 1223426 五、發明說明（6) 基板之電性連接端結構之製法，其主要製程係包含：於一 基板表面之絕緣層上覆蓋一導電膜，且在該導電膜上形成 第一圖案化阻層，俾使該第一阻層具有第一開口以外露出 該導電膜；於該第一開口内電鍍形成一圖案化線路層；於 該形成有圖案化線路層之基板表面上覆蓋第二圖案化阻層 ，俾使該第二阻層具有第二開口以外露出欲作為電性連接 墊區域之部分線路層，且該第二開口尺寸係大於該電性連 接墊處之該第一開口尺寸；在該第一開口中之電性連接墊 上電鍍形成有第一金屬保護層，並使該第一金屬保護層外 露出該第一開口 ，以及在該第一金屬保護層上電鍍形成有 第二金屬保護層，俾使該第二金屬保護層形成一蓋狀結構 以覆蓋住該第一金屬保護層之上表面與側邊部分；之後再 移除該第二、第一阻層及其所覆蓋之導電膜。 藉由前述本發明之較佳實施例之製法，本發明亦揭露 一種半導體封裝基板之電性連接端結構，其包括一電性連 接墊；一第一金屬保護層，係形成於該電性連接墊之上表 面；以及一第二金屬保護層，係形成於第一金屬保護層上 ，俾覆蓋該第一金屬保護層之上表面與側邊部分。 相較於習知依序採用SAP與NPL電鍍製程等方式於半導 體封裝基板上形成圖案化線路層以及電性連接墊上之金屬 保護層，本發明所揭露之半導體封裝基板之電性連接端結 構及其製法，係在形成第一圖案化阻層而定義出該圖案化 線路層之後，直接於該具圖案化線路層之基板上形成一第 二圖案化阻層，俾藉該第二圖案化阻層之開口顯露部分之Π555 全懋 .ptd Page 13 1223426 V. Description of the invention (6) The manufacturing method of the electrical connection structure of the substrate, the main process includes: covering an insulating layer on the surface of a substrate with a conductive film, and the conductive film A first patterned resist layer is formed thereon so that the conductive film is exposed outside the first resist layer with a first opening; a patterned circuit layer is formed by electroplating in the first opening; and the substrate on which the patterned circuit layer is formed A second patterned resist layer is covered on the surface, so that the second resist layer has a part of the circuit layer outside the second opening that is to be used as an electrical connection pad area, and the size of the second opening is larger than that of the electrical connection pad. The size of the first opening; a first metal protective layer is electroplated on the electrical connection pad in the first opening, and the first metal protective layer is exposed outside the first opening, and on the first metal protective layer A second metal protective layer is formed by electroplating, and the second metal protective layer is formed into a cap-like structure to cover the upper surface and side portions of the first metal protective layer; and then the second and first resists are removed. And covered with the conductive film. According to the manufacturing method of the foregoing preferred embodiment of the present invention, the present invention also discloses an electrical connection terminal structure of a semiconductor package substrate, which includes an electrical connection pad; a first metal protective layer is formed on the electrical connection The upper surface of the pad; and a second metal protective layer, which is formed on the first metal protective layer and covers the upper surface and side portions of the first metal protective layer. Compared to the conventional method of sequentially forming SAP and NPL plating processes on a semiconductor package substrate to form a patterned circuit layer and a metal protective layer on an electrical connection pad, the electrical connection terminal structure and the semiconductor package substrate disclosed in the present invention and The method is to form a first patterned resist layer and define the patterned circuit layer, and then directly form a second patterned resist layer on the substrate with the patterned circuit layer, and then borrow the second patterned resist. Exposed part of the layer
17555 全懋.ptd 第14頁 丄223426 五、發明說明（7) ~ " ----- ®案化線路層以定義出雷地 ' 查 二阻屉門口肉夕：2 接墊區域，以於後續在該第 ^ ^I 电’連接墊之表面上得以電鍍形成一金屬 = , = 知般需藉由第-、第二及第三圖案: 裝基板=性一導！膜之方式而形成半導體封 ^ φ. 而、，，D構，俾藉由本發明之製法而簡化習 之U步驟，同時提高半導體封裝基板之生產效率。 開口中先電在該電性連接塾上之該第-阻層 出該電性、車=執夕Ϊ苐一金屬保護層（如鎳），再藉由顯露 阻層二阻層開口尺寸係大於對應處之第- 成第二金屬伴1 #二以繼續在該第一金屬保護層上電鍍形 口中之ί ί ϊ ΐ 金）時’得以使電鍍形成於該第二開 上表面及it:t成—蓋體結構’藉以包覆該鎳金屬層之 ，因金屬層大部分為該金金屬層所包覆 避免錦金屬受姓刻溶害該錄金屬層，有效 污染等問題，同時亦得以，進而導致蚀刻溶液 接塾與外界之電性連接σ:持：：有金屬保護層之電性連 圖案化阻層上供顯露電：i接塾：黛由於本發明在該第二 將進-步簡化半導體需之曝光精度較低，俾 成本。同丰“封裝基板之生產效率及大幅降低生產之17555 Quan 懋 .ptd Page 14 丄 223426 V. Description of the invention (7) ~ " ----- ® The circuit layer is defined to define the minefield '. Check the second block of the drawer door meat evening: 2 pad area, to In the subsequent process, a metal can be formed on the surface of the ^ ^ I electrical 'connection pad by electroplating =, = It is necessary to use the first, second, and third patterns: the mounting substrate = conductive! The method of forming a semiconductor package by means of a film ^ φ. Moreover, the D structure, the U step is simplified by the manufacturing method of the present invention, and the production efficiency of the semiconductor package substrate is improved. In the opening, the first resistance layer on the electrical connection pad is firstly provided with the electrical property. A metal protective layer (such as nickel) is exposed, and then the size of the opening of the second resistance layer is greater than that by exposing the resistance layer. Corresponding to the first-into the second metal companion 1 # 2 to continue plating on the first metal protective layer (ί ϊ ΐ ΐ gold) when the plating can be formed on the second open upper surface and it: t The formation-cover structure is used to cover the nickel metal layer, because most of the metal layer is covered by the gold metal layer to prevent the bronzing metal from dissolving the metal recording layer by the last name and effectively contaminating the metal layer. At the same time, This further leads to the electrical connection between the etching solution and the outside world. Σ: hold :: The electrical connection patterned resistive layer with a metal protective layer is used to expose electricity: i. Simplified semiconductors require lower exposure accuracy and lower costs. Tongfeng's “Production Efficiency of Package Substrates and Significantly Reduced Production
Π555全懋.ptdΠ555Full 懋 .ptd
第15頁Page 15
五、發明說明（8) 【實施方式】 以下係藉 ，熟習此技藝 解本發明之其 具體貫施例加 基於不同觀點 修飾與變更。 請參閱第 基板之電性連 的是，該等圖 發明之基本架 關之元件，且 狀、及尺寸比 及尺寸比例為 更為複雜。 之實施方式 容輕易地瞭 其他不同的 項細節亦可 下進行各種 半導體封裝 中，須注意 方式說明本 與本發明有 之數目、形 數目、形狀 局形態可能 特疋的具體實施例說明本發明 之人士可由本說明書所揭示之内 ，，點與功效。本發明亦可藉由 =知行或應用，本說明書中的各 ，…用 在不丨孛離本發明之精神 3 A至第3 F圖將詳細說明本發明中 接端結構製法之較佳實施例。其 式均為簡化之示意圖，僅以示意 構。因此，在該等圖式中僅顯示 所顯示之元件並非以實際實施時 例等加以繪製，其實際實施時之 一種選擇性之設計，且其元件佈 如第3A圖所示，首先提供一半導體封裝基板，並於該 封裝基板表面之絕緣層3丨上形成一導電膜3 2。其中，該絕 緣層31可例如為環氧樹脂（Epoxy resin)、聚乙酿胺（V. Description of the Invention (8) [Embodiment] The following is borrowed to familiarize yourself with this technique and to understand the specific implementation examples of the present invention plus modifications and changes based on different perspectives. Please refer to the electrical connection of the substrate. The basic components of these inventions are more complex in shape, size ratio and size ratio. The implementation can be easily carried out in other different details, and can also be carried out in various semiconductor packages. It should be noted that the specific examples of the number, shape, and shape of the present invention may be specific. Persons can discover the points, effects, and functions within this manual. The present invention can also be understood by the knowledge or application. Each of the descriptions in this specification is used without departing from the spirit of the present invention. Figures 3A to 3F will explain in detail the preferred embodiment of the method for manufacturing the terminal structure in the present invention. . The formulas are simplified diagrams, which are only for schematic structure. Therefore, in these drawings, it is only shown that the displayed elements are not drawn based on actual implementation examples, etc., and an optional design during actual implementation, and the component layout is shown in FIG. 3A. First, a semiconductor is provided. The substrate is packaged, and a conductive film 32 is formed on the insulation layer 3 丨 on the surface of the package substrate. Wherein, the insulating layer 31 may be, for example, epoxy resin, polyethylene amine (
Polyimide)、氰脂（cyanate ester)、玻璃纖維（Giass fiber)、雙順丁烯二酸醯亞胺/三氮阱（BT，Bismaleimide tr iazine)、混合環氧樹脂與玻璃纖維（FR5)或ABF ( Ajinomoto Build-up Film,日商味之素公司出產）等材質 所構成，而該導電膜2 3可為金屬銅，其係作為後述進行電 鍍線路層所需之電流傳導路徑。其中，該封裝基板係可為Polyimide), cyanate ester, glass fiber, Giss fiber, Bisaleimide tr iazine (BT), mixed epoxy resin and glass fiber (FR5) or ABF (Ajinomoto Build-up Film, manufactured by Nissho Ajinomoto Co., Ltd.) and other materials, and the conductive film 23 may be metallic copper, which is used as a current conduction path required for the plating circuit layer described later. The package substrate may be
17555 全懋.ptd 第16頁 1223426 五、發明說明（9) 覆晶式（Fl ip Chip)封裝基板，亦可為打線式（wire bonding)封裝基板，該封裝基板係可由一具預定厚度之 樹脂芯層’甚或包含有形成於該芯層表面上之内層線路所 構成（未圖示）。此外，該封裝基板亦可為一具多層線路之 多層板。 如第3 B圖所示，接著在於該導電膜3 2上利用印刷、旋 塗或貼合等方式覆蓋有第一阻層3 3，該第一阻層3 3可例如 為藍漆、乾膜或液態光阻等之光阻層（Photoj^sist)，並 可藉由曝光（Exposure)及顯影（Development)等圖案化製17555 Quan 懋 .ptd Page 16 1223426 V. Description of the invention (9) A flip chip package substrate can also be a wire bonding package substrate. The package substrate can be made of a resin with a predetermined thickness. The core layer may even include an inner layer circuit (not shown) formed on the surface of the core layer. In addition, the package substrate can also be a multilayer board with multilayer circuits. As shown in FIG. 3B, the conductive film 32 is then covered with a first resist layer 3 3 by printing, spin coating, or lamination. The first resist layer 3 3 may be, for example, a blue paint or a dry film. Or liquid photoresist layer (Photoj ^ sist), and can be patterned by exposure and development
私使该阻層3 3形成有第一開口 3 3 0，俾以顯露出欲形成圖 案化線路層之部分導電膜3 2，當然亦可藉由雷射鑽孔等技 術形成該些開口。 如第3C圖所示，接著進行電鍍製程以在該第一阻層開 口 3 3 0中之該導電膜32上電鍍形成有圖案化線路層^。曰其 中，該圖案化線路層34亦包含有複數個欲進行電0鑛如鎳 金之金屬保護層之電性連接墊3 4 0。 又 ’、 如第3D圖所示，復在該形成有圖案化線路層^之某板 士覆二第：阻層35,該第二阻層35可如藍•、“態 光阻專之光阻層（Photoresist)，其可藉由曝光The first opening 3 3 0 is formed in the resist layer 3 3 so as to expose a part of the conductive film 3 2 to form a patterned circuit layer. Of course, the openings can also be formed by a technique such as laser drilling. As shown in FIG. 3C, a plating process is subsequently performed to form a patterned circuit layer on the conductive film 32 in the first resist opening 3030. In other words, the patterned circuit layer 34 also includes a plurality of electrical connection pads 3 4 0 which are to be protected by a metal, such as nickel and gold. Also, as shown in FIG. 3D, the second layer of a certain board with the patterned circuit layer formed thereon is: a resist layer 35, and the second resist layer 35 may be blue, “state photoresistor light Photoresist, which can be exposed by
(Exposure)及顯影（Development)等圖案化制 、 衣括' 4吏言亥声 3 5形成有第二開口 3 5 0以顯露欲進行電鍍如鎳/ △ 八曰 保護層之電性連接墊340。其中，該供顯露有二^ f 3 4 0之第二開口 3 5 0之尺寸係大於對應處之第— 俾使於該電性連接墊340處之第一開口得以顯露#出大第小二’(Exposure) and development (Development) and other patterning, clothing, '4 official speech Haisheng 3 5 is formed with a second opening 3 50 0 to expose the electrical connection pad 340, such as nickel / △ eight protective layer . Among them, the size of the second opening 3 50 that exposes two ^ f 3 4 0 is larger than the corresponding one — so that the first opening at the electrical connection pad 340 can be exposed # 出 大 第 小 二'
12234261223426
五、發明說明（ίο) 開口 3 5 0 〇 於 結 時 如第3E圖所示，進行電鍍製程，以在該第一阻声 中之該電性連接墊上電鍍形成有第一金屬保護層曰'口 並使該第一金屬保護層外露出於該第一開口 ，之可、择 該^ 一金屬保護層上之該第二阻層開口中有= ί = 欠金)，俾使？第二金屬保護層形 雷性連接塾上之電鑛錦/金金屬保護 電性連接墊與外部之晶片或電路板之有效之電性：以 錄/金如Λ3Γ屬所;電性連接塾28之上表面形成有如 之後可於該封#其4 ^先刖復盍於該阻層下之導電膜32。 37，例如綠漆广=反、，覆盍上一拒銲層（s〇lder mask) 壞，該拒銲層並$以保羞该封襄基板免受外在環境污染破 金屬保護層之電^成有複數個開孔，使該完成電鍍形成有 ，該拒銲層開孔之==二以顯露於拒銲層之開孔，其中 小，以藉由該電性、可大於或小於該電性連接墊之大 性連接端結構鱼& j接塾顯露之金屬保護層以提高基板電 透過前述製程，本：J J °σ貝。 電性連接端結構，复=义月亦提供一種半導體封裝基板之 保護層361，係形成於:電‘丨生連接塾340; —第一金屬 第二金屬保護層3 6 2 :兒性連接墊3 4 0之上表面；以及一 " ’係為—形成於該第一金屬保護層上V. Description of the Invention (ίο) The opening 3 5 0 0 is subjected to an electroplating process at the end as shown in FIG. 3E, so that a first metal protective layer is formed on the electrical connection pad in the first sound barrier by electroplating. Opening and exposing the first metal protective layer to the first opening, optionally, the second resistive layer opening on the metal protective layer has 有 = owing gold), so? The second metal protective layer is a thunder-type connection. The electrical resistance of the electromechanical brocade / gold metal protection electrical connection pad on the external chip or circuit board is effective: the recording / gold as Λ3Γ belongs to; electrical connection 塾 28 The upper surface is formed with a conductive film 32 which can be subsequently laminated on the seal layer under the resist layer. 37. For example, green paint can be reversed, and a solder mask is damaged. The solder mask is not used to protect the substrate from external environmental pollution. There are a plurality of openings, so that the completed electroplating is formed, == two of the openings of the solder resist layer are exposed in the openings of the solder resist layer, which is small in order to make the electrical resistance larger or smaller than the electrical resistance. The large connection end structure of the electrical connection pad is connected with the exposed metal protective layer to improve the substrate's electrical transmission. The above process: JJ ° σ shell. Electrical connection structure, Yi = Yue also provides a protective layer 361 for a semiconductor package substrate, which is formed in: electrical connection 340;-first metal second metal protective layer 3 6 2: child connection pad 3 4 0 upper surface; and a " 'system is-formed on the first metal protective layer
第18頁 1223426 五、發明說明（11) 之蓋狀結構，俾以覆蓋該第一金屬保護層3 6 1之上著 為 側邊部分，其中，該第一與第二金屬保^層較佳者& 金金屬層。俾藉由該第二金屬保護層（金金屬層）之芸壯处 構以覆蓋住該第一金屬保護層（鎳金屬層），以在後二二 刻製程中避免傷害該鎳金屬層，與造成蝕刻溶液污.，， ^ Γ ^持形成有金屬保護層之電性連接墊與外界之電性連 =較於習知採用SAP與NPL電鍍製程等方式形成半 ί ί ί ί之圖案化線路結構與電性連接墊上之金屬保ΐ ί Γ i卸 明所揭露之半導體封裝基板之電性連接端^ 構及i法，係在形成第一圖案化阻層而定 ^ 線：層之，，直接於該圖案化線路 ：】㊁匕 電性連使後續在該第二阻層開口内之 習知般需藉由第： 形成金屬保護層，而並非如 而形成半導體封裝圖案化阻層與另一導電膜 製程之簡化步驟以i高半；體封j=f構，俾藉由本發明 再者，士八 封a基板之生產效率。 係大於對應iim露出電性連接塾之第二開。 接塾上形成有錄ί屬π全ππ錢方式以於該電性連 口内之金金屬，，得以藉由^層’使形成於該第二開 該鎳金屬芦till . μ弟一開口之較大尺寸而包覆 ^ 上表面及其側邊部分·之抬腺泌士仏持攸总 之弟二圖案化阻層、第一圖安儿刀，之後將形成於線路層 乐圖案化阻層剝離，並在後續以蝕Page 18 1223426 V. Description of the invention (11) The cover-like structure covers the first metal protective layer 3 6 1 as a side portion, wherein the first and second metal protective layers are preferred. &Amp; gold metal layer.构 Cover the first metal protective layer (nickel metal layer) with the strong structure of the second metal protective layer (gold metal layer) so as to avoid damaging the nickel metal layer in the second and second etch process, and Causes the etching solution to become dirty. ^ Γ ^ The electrical connection pad with a metal protective layer is electrically connected to the outside world. Compared to the conventional method of forming a patterned line using SAP and NPL plating processes, etc. Structure and metal protection on the electrical connection pads Γ Γ 卸 卸 卸 明 明 Disclose the electrical connection terminals of the semiconductor package substrate disclosed by the ^ structure and the i method are determined by forming the first patterned resist layer ^ Line: layer, Directly on the patterned circuit:] Electrically, the subsequent practice in the opening of the second resistance layer needs to be formed by the first: rather than forming a semiconductor package patterned resistance layer and another The simplified steps of a conductive film manufacturing process are i half as high; the body seal is j = f structure, and according to the present invention, the production efficiency of Shibafeng a substrate. It is larger than the second opening of the corresponding iim exposed electrical connection. A gold metal in the electrical connection is formed on the electrical connection, which can be formed on the nickel metal reed till by the layer ^. Large size and cover ^ The upper surface and its side parts are the second patterned resist layer and the first figure An Erdao, and then the patterned resist layer formed on the circuit layer is peeled off. And subsequent eclipse
^^426 五、發明說明（12) 〜 ^------〜·»-- ίπ阻層下之導電膜時，因該錄金屬層已 導電膜時不：傷m 3丄因此透過蝕刻等製程移除該 錦金屬受蚀刻溶；之錄金屬層’得以減少 等問題，同時亦污染”溶液 與外界之電性連接口質ϋ有金屬保護層之電性連接墊 =形成供顯露電性連接塾之第二開口係小於對 曝光；：：t在形成圖案化阻層時需採用四象限；割之 第:口 ：：發明之較佳實施例中，“該第二 。相對變ϊ 處Γ第，，即第二之開 匕曝光J數減少，可降低曝光曝 生產效率及大幅降低生產之成本。 土板 本：：中所應用之電性連接#，係如半導體 、t ϊ ί ί凸塊銲墊或錫球墊’圖中所示僅以部“性 連，〒’實際上電性連接塾之數目及作為遮罩之二 糸^際製程所需而加以設計並分佈於基板中^ :可貫施於電路板之單一側面或雙側自。除本發明實 佯$:電=接墊之外’只要是基板需進行電鍍形成全屬 :;:=為一錄/金金屬保護層之部分，皆可藉本發 月:斤揭不之製程以形成其電鍍有金屬保護層之結構^ 广明亦可運用於供第二階層組農電子元件之 電路板（printed Circult Board)之製作。上述之實又施例^^ 426 V. Description of the invention (12) ~ ^ ------ ~ · »-ίπ When the conductive film under the resist layer, because the metal recording layer has a conductive film does not: hurt m 3 丄 so through the etching The process removes the brocade metal by etching; the metal layer is reduced and other problems are contaminated. At the same time, the electrical connection between the solution and the outside world is poor. The electrical connection pad with a metal protective layer is formed to provide electrical conductivity. The second opening of the connection line is smaller than the pair exposure; :: t needs to use four quadrants when forming the patterned resist layer; and the first: port: In the preferred embodiment of the invention, "the second. The relative change in the number Γ, that is, the second number of open exposures, reduces the number of exposures, which can reduce the production efficiency of exposure and significantly reduce the cost of production. Soil board :: The electrical connection # used in :, such as semiconductors, t ί ί 焊 bump pads or solder ball pads' shown in the figure is only "sexually connected," 'actually electrically connected' It is designed and distributed in the substrate as the number of masks required for the second manufacturing process. It can be applied to a single side or both sides of the circuit board. Except for the invention, $: 电 = 接 垫 的Outside 'as long as the substrate needs to be plated to form all:;: = is part of a recording / gold metal protective layer, which can be borrowed from this month: a process that can not be removed to form a structure with a metal protective layer electroplated ^ 广The Ming Dynasty can also be used for the production of printed Circult Boards for second-tier agricultural electronic components.
]7555 全懋.ptd 第20頁 1223426 五、發明說明（13) 僅為例示性說明本發明之原理及其功效，而非用於限制本 發明。任何熟習此技藝之人士均可在不違背本發明之精神 及範疇下，對上述實施例進行修飾與變化。因此，本發明 之權利保護範圍，應如後述之申請專利範圍所列。] 7555 全懋 .ptd Page 20 1223426 V. Description of the Invention (13) It is only for illustrative purposes to explain the principle and effect of the present invention, but not for limiting the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.
17555 全懋.ptd 第21頁 1223426 圖式簡單說明 【圖式簡單說明】 第1 A至1 Η圖係顯示習知半加成法（SAP )與無電鍍導線 (N P L )電鍍製程之剖面示意圖； 第2A至2F圖係顯示習知形成基板線路結構與電性連接 墊上之金屬保護層之製程剖面示意圖；以及 第3A至3F圖係顯示本發明之半導體封裝基板之電性連 接端結構之製法剖面示意圖。 11 絕緣層 12 導電膜 13 阻層 130 開口 14 線路層 140 電性連接墊 15 導電膜 16 第二阻層 160 開口 17 第三阻層 18 金屬保護層 21，31 絕緣層 22, 32 導電膜 23, 33 第一阻層 230, 330 開口 24, 34 線路層 24 0, 34 0 電性連接墊 25,35 第二阻層 250, 350 開口 261， 361 第一金屬保護層 2 6 2, 3 6 2 第二金屬保護層 37 拒鲜層17555 Quan 懋 .ptd Page 21 1223426 Simple illustration of the drawings [Simplified illustration of the drawings] The first 1 to 1 drawings are cross-sectional schematic diagrams showing the conventional semi-additive (SAP) and electroless plated wire (NPL) plating process; Figures 2A to 2F are schematic cross-sectional views showing a conventional process for forming a substrate circuit structure and a metal protective layer on an electrical connection pad; and Figures 3A to 3F are cross-sectional views showing a method for manufacturing an electrical connection terminal structure of a semiconductor package substrate of the present invention. schematic diagram. 11 Insulating layer 12 Conductive film 13 Resistive layer 130 Opening 14 Circuit layer 140 Electrical connection pad 15 Conductive film 16 Second resistive layer 160 Opening 17 Third resistive layer 18 Metal protective layer 21, 31 Insulating layer 22, 32 Conductive film 23, 33 First resistive layer 230, 330 Opening 24, 34 Circuit layer 24 0, 34 0 Electrical connection pad 25, 35 Second resistive layer 250, 350 Opening 261, 361 First metal protective layer 2 6 2, 3 6 2 Two metal protective layer 37
17555 全懋.ptd 第22頁17555 懋 .ptd Page 22
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8901729B2 (en) | 2011-12-21 | 2014-12-02 | Siliconware Precision Industries Co., Ltd. | Semiconductor package, packaging substrate and fabrication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8901729B2 (en) | 2011-12-21 | 2014-12-02 | Siliconware Precision Industries Co., Ltd. | Semiconductor package, packaging substrate and fabrication method thereof |
| US9269677B2 (en) | 2011-12-21 | 2016-02-23 | Siliconware Precision Industries Co., Ltd. | Fabrication method of packaging substrate |
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