1220305 五、發明說明（1) 【發明所屬之技術領域】 本發明與三維晶片堆疊構 種熱傳增益之三維晶片堆疊構 【先前技術】 近年來半導體隨著電腦與 昇，、多元化、可攜性與輕巧化 上，不斷地努力以減少半導體 片的半導體元件密度一直增加 向於小而高速，且高密集的元 已脫離了傳統的技術而朝高功 化等高精密度製程發展，目前 有、提供電子訊號與電力之傳 路）、散熱與保護構裝結構等 (Electronic Packaging)需要 製造成本等必要特性，同時隨 能越來越繁複，所以目前有許 疊的方式，在有限的空間内， 性和構裝的尺寸大小都是重要 源主要來自晶片本體，其散熱 與熱對流（Convec t i on )為主， 本身的厚度有關，也跟堆疊構 提供一種三維晶片堆疊構裝架 較佳散熱效果及製造簡單等優 相關的專利技術例如有美 裝架構有關’特別是關於一 裝架構。 通訊等產品功能的急速提 的需求，在積體電路的製造 元件的大小，使每單位矽晶 ，積體電路（1C)的技術已傾 件，並且其晶片構裝製程業 率、高密度、輕、薄與微小 一般而言構裝之主要功用 輸（輸入與輸出積體電 項’，所以，電子構裝 有高可靠度、散熱性佳、低 著半導體是越來越輕巧，功 多研究都傾向以三維晶片堆 整合不同的晶片，其中散熱 的因素，電子構裝元件之熱 途徑以熱傳導（Conduction: 而構裝後尺寸的大小跟晶片 裝方式有關。因此，本發明 構，有較佳堆疊構裝尺寸、 點。 國專利第6, 49 8, 3 8 1號；美1220305 V. Description of the invention (1) [Technical field to which the invention belongs] Three-dimensional wafer stacking structure with heat transfer gain of the present invention and three-dimensional wafer stacking structure [Prior technology] In recent years, with the advancement of computers and computers, semiconductors have been diversified and portable. In terms of performance and lightweight, continuous efforts have been made to reduce the density of semiconductor elements. The density of semiconductor elements has been increasing toward small and high-speed, and high-density elements have been separated from traditional technologies and developed toward high-precision processes such as high power. At present, there are , Providing electronic signals and power transmission), heat dissipation and protective packaging structures (Electronic Packaging) need the necessary characteristics such as manufacturing cost, and at the same time can be more and more complicated, so there are many ways to do so in a limited space. Both the performance and the size of the structure are important sources mainly from the chip body. Its heat dissipation is mainly based on thermal convection (Convec ti on), which is related to its thickness and also provides a three-dimensional wafer stacking structure for better heat dissipation. The patented technology related to the effect and the simplicity of manufacture are related to the US installation architecture, in particular, to the one installation architecture. The demand for the functions of products such as communications is rapidly increasing. The size of the integrated circuit manufacturing components has made the technology of integrated circuit (1C) per unit silicon crystal, and its wafer fabrication process rate, high density, Light, thin and tiny. Generally speaking, the main functions of the structure are input and output (input and output integrated electrical items'). Therefore, electronic structures are becoming more and more reliable, with good heat dissipation and low semiconductors. All tend to integrate different wafers with three-dimensional wafer stacks, among which the heat dissipation factor and the thermal path of the electronic structured components are heat conduction (Conduction: and the size of the structure after the structure is related to the way of the wafer. Therefore, the structure of the present invention has better Stacking structure dimensions and points. National Patent No. 6, 49 8, 3 8 1;
1220305 五、發明說明（2) 國專利第6，3 2 2，9 0 3號；美國專利第6，1 8 4，0 6 0號；日本專 利jp2 0 0 1 2 0 8 4 7 8號；日本專利jp20 0 1 1 4444 1號；日本專利 j pi 1 2 24 9 74號；日本專利jp2 0 0 2 2 8 0 3 8 6號及中華民國專利 號479337等等。 美國專利第6, 49 8, 3 8 1號；美國專利第6, 1 84, 0 6 0號曰 本專利jp2 0 0 1 2 0 8478號；日本專利jp2 0 0 1 1 4444 1號；日本 專利；j p 2 0 0 2 2 8 0 3 8 6號，分別都揭露晶片穿孔方式，其中並 無提:到以穿孔方式進行晶片堆疊構裝，也沒有散熱增益效 果，美國專利第6，3 2 2，9 0 3號和日本專利j p 1 1 2 2 4 9 7 4號揭 露三維穿孔堆疊構裝架構，然而其中並無提及有散熱增益 效果。 如第1圖所示，為一習知技術（中華民國專利號 4 7 9 3 3 7 )之一實施例，其中揭露了一種高散熱效能之堆疊 式球柵陣列型晶片封裝結構，主要特徵有一基板3 0 0，一 散熱塊3 3 0，具有一頂部3 3 2，與一支撐部3 3 1，一第一晶 片3 1 0，一第二晶片3 2 〇，一封裝膠體3 5 〇，複數條銲線 3 4 0，3 4 5及複數個銲球3 6 0，其中該第二晶片3 2 0之非電路 面3 2 0 b係導熱性接置於該散熱塊3 3 0之頂部3 3 2，而該散熱 塊3 3 0之頂部3 3 2係導熱性的接置於該第一晶片3丨〇非電路 面310b，該第一晶片310之電路面31〇a係藉由覆晶技術電 性耗接至該基板3 0 0的正面3 0 0 a，該複數條銲線3 4 〇，3 4 5 係從該第&二晶片3.20的電路面32〇a穿過該散熱塊33〇之頂部 3 3 2—上之穿線孔而打線至該基板3 〇 〇的正面3 〇 〇 &上，用以將 。亥弟一曰曰片3 2 0電性|禺接至該基板3 〇 〇，該封裝膠體3 & 〇包' 1220305 五、發明說明（3) |覆住該基板3 0 0之正面3 0 0 a、該第一晶片3 1 〇、該散熱塊 33〇、該第二晶片3 2 0、及該等銲線3 4 0、34 5,該^婁^個鮮 |球3 6 0，其次球柵陣列形態植於該基板3〇〇之背面3〇〇b上了 I 如以上所述，該高散熱效能之堆疊式球柵陣列却曰 封裝結構，其中該堆疊結構為該散熱塊33〇夹在哕B曰曰片 |片3 1 〇與該第二晶片3 2 0之間，社據曰H R办 以弟 日日 丨疊社槿尺+直埤埶，八"?佔據晶片間空間，增加該堆 匕、=構尺寸，其散熱述彼為該第一晶片w 、隹 所產生的熱，皆傳至該散熱掄 弟一日日片320 3 3 1，至基板3 0 0或外露部導出。丁、邛3 3 2經由支撐部 上例較佳之熱傳效果及構裂 舍明之目的即為提供較 構裝（Electronic Packagf 、、’亚且製造簡單，使電子 |造成本等優點。 有散熱性佳、輕巧化、低製 發明内容】 鑒於以上習知技術的 /ΤΛ ' 缺點，月焱7 ,4· (Electronic Packaging)有 μ 钩〔使電子構裝 |等優點，因此本發明的主要政熱性佳、輕巧化及製造簡單 晶片堆疊構裝架構，擁有較^的為提供一種熱傳增益三維 下會簡單說明如何得到上^土 =熱傳效果及構裝尺寸。以 術的缺點，較詳細的敘壤二，，點及如何改善以上習知 I依據本發明之目的，二在實施方式中。 t> f 的製造方法：提供一基板:二較廣的實施例描述本發明 晶片，形成一銲料凸塊扒^ i複數個穿孔於一預製之第 穿孔中，以形成一電性連接孔上並回流填充於該第— 個電性連接凸塊與該基柘立ϋ塊，將該第一晶μ之兮、—如 土板表面電性弟日日片之遠復數 1 連…，有另一預製之第1220305 V. Description of the invention (2) National patent No. 6,3 2 2,9 0 3; U.S. patent No. 6,1 4 4,0 6 0; Japanese patent jp 2 0 0 1 2 0 8 4 7 8; Japanese patent jp20 0 1 1 4444 1; Japanese patent j pi 1 2 24 9 74; Japanese patent jp 2 0 2 2 8 0 3 8 6 and Republic of China patent number 479337 and so on. US Patent No. 6,49 8, 3 8 1; US Patent No. 6, 1 84, 0 60; Japanese Patent No. jp2 0 0 1 2 0 8478; Japanese Patent No. jp 2 0 0 1 1 4444 1; Japanese Patent ; Jp 2 0 0 2 2 8 0 3 8 6 each disclose the wafer perforation method, which is not mentioned: the stacking structure of the wafer by the perforation method has no heat dissipation gain effect. US Patent No. 6, 3 2 2 No. 903 and Japanese Patent No. jp 1 1 2 2 4 9 7 4 disclose a three-dimensional perforated stacking structure, but there is no mention of a heat dissipation gain effect. As shown in FIG. 1, it is an embodiment of a conventional technology (Republic of China Patent No. 4 7 9 3 3 7), which discloses a stacked ball grid array chip package structure with high heat dissipation efficiency. The main features are as follows: The substrate 300, a heat sink 3 3 0, has a top 3 3 2 and a supporting portion 3 3 1, a first wafer 3 1 0, a second wafer 3 2 0, a packaging gel 3 5 0, A plurality of bonding wires 3 4 0, 3 4 5 and a plurality of solder balls 3 6 0, wherein the non-circuit surface 3 2 0 of the second wafer 3 2 0 is thermally conductively placed on top of the heat sink 3 3 0 3 3 2 and the top 3 3 2 of the heat sink 3 3 0 is thermally conductively connected to the non-circuit surface 310b of the first chip 310, and the circuit surface 31〇a of the first chip 310 is covered by The crystal technology is electrically connected to the front surface 3 0 0 a of the substrate 3 0 0, and the plurality of bonding wires 3 4 0, 3 4 5 pass from the circuit surface 32 0a of the & second wafer 3.20 through the heat dissipation. The top 3 3 2-of the block 33 is threaded to the front surface of the substrate 300 for wiring. Hai Di said that the film 3 2 0 is electrically connected to the substrate 3 00, the encapsulant 3 & 0 package '1220305 V. Description of the invention (3) | Covering the front surface of the substrate 3 0 0 3 0 0 a, the first wafer 3 1 0, the heat sink 33 0, the second wafer 3 2 0, and the bonding wires 3 4 0, 34 5, the ^ Lou ^ a fresh | ball 3 6 0, followed by The shape of the ball grid array is implanted on the back of the substrate 300. As described above, the stacked ball grid array with high heat dissipation efficiency is called a package structure, and the stacked structure is the heat dissipation block 33. Sandwiched between 哕 B said film | slice 3 1 〇 and the second wafer 3 2 0, according to the HR office, the younger day 丨 stacked company hibiscus + straight, eight "quotes? Occupy space between the wafers Increase the size of the stack, and the heat dissipation is the heat generated by the first wafer w and 隹, which are all transmitted to the heat sink's day-to-day film 320 3 3 1 to the substrate 3 0 0 or exposed. Export. Ding, 邛 3 3 2 through the support example of the better heat transfer effect and the purpose of framing is to provide a more structured (Electronic Packagf, 'Asia and simple manufacturing, so that electronics | cause this and other advantages. There is heat dissipation In view of the disadvantages of the above-mentioned conventional technology, the Λ7,4 · (Electronic Packaging) has the advantages of the μ hook [to make the electronic structure | etc.]. Therefore, the main features of the present invention are: It is simple, lightweight, and simple to manufacture. It has a relatively simple stacking structure. To provide a heat transfer gain in three dimensions, it will simply explain how to get the heat transfer effect and the size of the structure. The disadvantages of the technique are more detailed. The second aspect, points and how to improve the above-mentioned conventional knowledge I in accordance with the purpose of the present invention, two in the embodiment. T > f manufacturing method: provide a substrate: two broader embodiments describe the wafer of the present invention, forming a solder The bumps ^ i a plurality of perforations in a prefabricated first perforation to form an electrical connection hole and reflow filling the first electrical connection bump and the base standing block, the first crystal μ 之 西 、 —such as soil The number of far-reaching electric and electronic films on the surface of the board is 1 consecutive ...
1220305 五、發明說明（4) 二晶片，形成複數個第二穿孔於該第二晶片，形成一銲料 凸塊於該穿孔上並回流填充於該第二穿孔中，以形成一電 性連接凸塊，接著將該第二晶片之複數個電性連接凸塊， 與對應的位在該第一晶片之該第二電性連接凸塊電性接 觸，最後將每個晶片接觸之該複數個電性連接凸塊，同時 電性導通連結至該基板表面以形成一多晶片堆疊結構。至 少一導熱裝置，用以導熱性安置於該基板表面上，位於該 多晶片堆疊結構旁，至少一晶片有一導熱部件，其一端與 該晶片形成一導熱性接觸，該導熱部件另一端則導熱性連 結於該導熱裝置，形成一熱傳增益三維晶片堆疊構裝架 構，復可有一散熱部件與該導熱裝置一端導熱性連結，用 以增益散熱效能。 上述之實施例，僅為清楚表達本發明之特徵，不限制 本發明僅應用於兩晶片堆疊構裝。 本發明熱傳增益三維晶片堆疊構裝架構之特點，在於 至少一晶片有一導熱部件與該晶片形成一導熱性接觸，且 該導熱部件與一導熱裝置導熱性連結以散熱，其散熱途徑 短，有較佳之散熱效能，且不佔據多晶片之間堆疊空間， 可減少構裝尺寸，另外多晶片構裝係以銲接製程，經過該 晶片穿孔一次電性連結導通至該基板表面上，可簡化製造 流程。 【實施方式】 以下即配合所附圖示第2圖至第5圖，詳細揭露說明本 發明之一實施例。1220305 V. Description of the invention (4) Two wafers, forming a plurality of second through holes in the second wafer, forming a solder bump on the through hole and refilling the second through hole to form an electrical connection bump Then, the plurality of electrical connection bumps of the second wafer are electrically contacted with the second electrical connection bumps corresponding to the first wafer, and finally the plurality of electrical connections of each wafer are contacted. The bumps are connected and electrically connected to the substrate surface to form a multi-chip stacked structure. At least one thermally conductive device is disposed on the surface of the substrate with thermal conductivity, and is located beside the multi-chip stack structure. At least one of the wafers has a thermally conductive member, one end of which is in thermal contact with the wafer, and the other end of the thermally conductive member is thermally conductive. The heat conduction device is connected to the heat conduction device to form a heat transfer gain three-dimensional chip stacking structure. A heat dissipation component may be thermally connected to one end of the heat conduction device to increase heat dissipation performance. The above-mentioned embodiments are only for clearly expressing the features of the present invention, and the present invention is not limited to being applied to a two-wafer stacked structure. The heat transfer gain three-dimensional wafer stacking structure of the present invention is characterized in that at least one wafer has a thermally conductive member forming a thermally conductive contact with the wafer, and the thermally conductive member is thermally connected to a thermally conductive device to dissipate heat. Better heat dissipation performance, and does not occupy stacking space between multiple chips, which can reduce the size of the structure. In addition, the multi-chip structure is made by a welding process, which is electrically connected to the substrate surface through the wafer perforation once, which can simplify the manufacturing process. . [Embodiment] An embodiment of the present invention will be described in detail below with reference to Figures 2 to 5 of the accompanying drawings.
1220305 五、發明說明（5) 如弟2A圖至弟2D圖所不’為一晶片穿孔構裝之流程 圖，有一預製完成之一第一晶片1 0 0，以電感耦合電漿式 矽蝕刻系統（I . C . P )或是雷射，於該第一晶片1 〇 〇上鑽孔， 形成複數個穿孔1 0 1，接著於該穿孔壁及該第一晶片1 0 0背 面，鍍上一絕緣層，該絕緣層可為二氧化矽，可以化學氣 相沉積（CVD )的方式沉積該絕緣層，再於該穿孔1 〇 1壁上之 該絕緣層上，鍍上一金屬層，接著在該第一晶片1 0 0該穿 孔1 0 1上，形成一錫料凸塊1 0 2，經過回流製程（R e f 1 〇 w ) 後，使該錫料凸塊1 0 2，填充於該穿孔1 0 1中以形成一電性 連接凸塊1 0 3，該電性連接凸塊1 0 3凸出於該第一晶片 1 00 〇 :如第3圖所示，將該第一晶片1 0 0上之該複數個電性連 接凸塊1 0 3，電性接置於一預製基板1 0 6表面，另有一預製 之第二晶片2 0 0，以電感耦合電漿式矽蝕刻系統（I. C. P )或 是雷射，於該第二晶片2 0 0上鑽孔，形成複數個穿孔，接 著於該穿孔壁及該第二晶片2 0 0背面，鍍上一絕緣層，該 絕緣層可為二氧化矽，可以化學氣相沉積（CVD )的方式沉 積該絕緣層，再於該穿孔壁上之該絕緣層上，鍍上一金屬 層，接著在該第二晶片2 0 0該穿孔上，形成一錫料凸塊 2 0 3，經過回流製程（Ref low)後，使該錫料凸塊2 0 3，填充 於該穿孔中以形成一電性連接凸塊2 0 3，該電性連接凸塊 2 0 3凸出於該第二晶片2 0 0，接下來，將該第二晶片2 0 0上 之該複數個電性連接凸塊2 0 3，與該第一晶片對應之電性 連接凸塊1 0 3電性連接，接著即進行一銲接程序，將連接1220305 V. Description of the invention (5) As shown in Figure 2A to Figure 2D, it is a flow chart of a wafer perforation structure. There is a prefabricated first wafer 100, which is an inductively coupled plasma silicon etching system. (I.C.P.) or laser, drilling holes in the first wafer 100 to form a plurality of perforations 101, and then plating the perforation wall and the back of the first wafer 100 with one An insulating layer. The insulating layer may be silicon dioxide. The insulating layer may be deposited by chemical vapor deposition (CVD), and then a metal layer is plated on the insulating layer on the 1001 wall of the perforation. A tin material bump 102 is formed on the first wafer 100 and the through hole 101. After the reflow process (Ref 1 0w), the tin material bump 102 is filled in the through hole. 1 0 1 to form an electrical connection bump 1 0 3, the electrical connection bump 1 0 3 protrudes from the first wafer 100: as shown in FIG. 3, the first wafer 1 0 The plurality of electrical connection bumps 103 on 0 are electrically connected to the surface of a prefabricated substrate 106 and another prefabricated second wafer 2 0 0 is used to inductively couple the plasma silicon Engraving system (IC P) or laser, drilling holes on the second wafer 2000 to form a plurality of perforations, and then plating an insulating layer on the perforation wall and the back of the second wafer 2000, the The insulating layer may be silicon dioxide. The insulating layer may be deposited by chemical vapor deposition (CVD), and then a metal layer is plated on the insulating layer on the perforated wall, and then the second wafer 200 A solder bump 203 is formed on the perforation. After the reflow process (Ref low), the solder bump 203 is filled in the via to form an electrical connection bump 203. The electrical connection bumps 2 0 3 protrude from the second chip 2 0. Next, the plurality of electrical connection bumps 2 0 3 on the second chip 2 0 and the first chip 2 The corresponding electrical connection bumps are electrically connected, and then a welding process is performed to connect
第10頁 1220305 五、發明說明（6) --- 該第一晶片1〇〇及該第二晶片2 0 0之該複數個電 塊，電性連結至5亥基板1 0 6表面，形成_多晶田社 構。接著將兩導熱裝置105,以導熱膠108黏@置ζ3芙口 1 0 6表面且位於該多晶片堆疊結構之兩侧，右；以土 部件109，該第一導熱部件1〇9之一端以導熱膠 歹第、 晶片1 00—端相連，形成一導熱性接觸， ，、及弟 可位於该弟一晶片100之晶面、晶背、晶側政 與該導熱裝置112以導熱膠110連、结，另有— -、件 111，該第二導熱部件111的一端以導熱膠1〇桃該第、二卩曰牛 片2 0 0—端相連，形成一導熱性接觸’該導熱性接觸;: 於該第二晶片2 0 0之晶面、晶背、晶侧复由一 /、丫 一處，並鱼該 導熱裝置1〇5以，熱膠U0連結’複可將—散熱 〇、 導熱膠U3與該導熱裝置105之一端連結。該散埶 1〇7、該導熱裝置1〇5及該導熱部件1〇9皆係由高'、導敎1 料組成，例如銅。 ▼…、I王歼 上述之實施例，僅為清楚表達本發明 本發明僅應用於兩晶片堆疊構裝。 4 ’不限制 如第4圖所示，為本發明之另一實施例，豆曰 構裝之流程圖如第2Α圖至第2D圖所示。有一繁、一曰曰/牙孔 40 9,广端以導熱膠404與該第一晶片1〇〇一端-相導連熱部件 有一第二導熱部件4 1 1，其一端以導熱膠4〇4盥嗲曰 2。0-端相連，接著將同—側之該第一：二：；片, 二導熱部件411以導熱膠41〇連結，複可將—散熱 以導熱膠4 1 3連結於該第二導熱部件4丨丨的上方:掸2散 1220305 五、發明說明（7) 熱，該散熱部件4 0 7及該導熱部件4 1 1皆係由高導熱性材料 組成，如銅。 上述之實施例，僅為清楚表達本發明之特徵，不限制 本發明僅應用於兩晶片堆疊構裝。 如第5圖所示，為本發明之再一實施例，其晶片穿孔 構裝之流程圖如第2 A圖至第2 D圖所示，將兩導熱裝置 5 0 5，分別以導熱膠5 0 8黏置於該基板1 0 6表面，且位於該 多晶片堆疊結構之兩側，該導熱裝置5 0 5具有至少一支部 509，以導熱膠50 4與任一晶片連結以形成一導熱性接觸， 該導熱性接觸係可位於該晶片之晶面、晶背、晶側其中一 處，複可將一散熱部件5 0 7以導熱膠5 1 3與該導熱裝置5 0 5 之一端連結，用以增益散熱效果。該散熱部件5 0 7、該導 熱裝置5 0 5皆係由高導熱性材料組成，例如銅。 :上述之實施例，僅為清楚表達本發明之特徵，不限制 本發期僅應用於兩晶片堆疊構裝。 如第3圖所示，本發明之再一實施例，係於前述實施 例上之該複數個導熱部件1 0 9，局部延伸形成一外露部 1 1 4，可進一步提升散熱效能。 綜而言之，本發明提供了一種三維晶片堆疊構裝技 術，相較於習知技術，本發明有以下特點，任一晶片所產 生的熱，可經由該晶片個別之該導熱部件，傳導至該導熱 裝置以將熱逸散至外面，提供較短之熱傳導途徑，因此有 較佳散熱功能，且因該導熱部件非置於該晶片之間，可減 少三維晶片堆疊構裝的大小，因此本發明較習知技術具有Page 10 1220305 V. Description of the invention (6) --- The plurality of electric blocks of the first wafer 100 and the second wafer 200 are electrically connected to the surface of the substrate 50 to form _ Takada Corporation. Next, the two heat-conducting devices 105 are adhered to the surface of the multi-chip stacking structure with a heat-conducting adhesive 108 and located on both sides of the multi-chip stacking structure, right; with a soil member 109, one end of the first heat-conducting member 109 The thermal conductive adhesive is connected to the 100-side end of the wafer to form a thermally conductive contact, and the thermal conductive adhesive can be located on the crystal surface, crystal back, and crystal side of the thermal conductive adhesive wafer 112 of the thermal conductive adhesive 112, Knot, and in addition--, piece 111, one end of the second thermally conductive member 111 is connected with the thermal conductive adhesive 10 peach, the second and second beef chips 200-ends to form a thermally conductive contact 'the thermally conductive contact; : One, one, and one of the crystal surface, crystal back, and crystal side of the second wafer 200 are connected to the heat conduction device 105, and the thermal glue U0 is connected to the heat sink to dissipate heat and heat. The glue U3 is connected to one end of the heat conducting device 105. The loose particles 107, the heat-conducting device 105, and the heat-conducting component 109 are all made of high-temperature, high-conducting materials such as copper. ▼ ..., I Wang Jian The above-mentioned embodiments are only for expressing the present invention clearly. The present invention is only applied to a two-wafer stacked structure. 4 'is not limited. As shown in FIG. 4, it is another embodiment of the present invention, and the flow chart of the bean structure is shown in FIGS. 2A to 2D. There is a fan, a tooth / tooth hole 40 9, and a wide end is connected to one end of the first wafer 100 with a thermally conductive adhesive 404. The thermal component has a second thermally conductive component 4 1 1 and one end thereof is thermally conductive adhesive 4. The 4 bathroom is connected to the 2.0-end, and then the first side of the same side: the two, the two, the thermally conductive member 411 is connected with the thermally conductive adhesive 41o, and the heat can be connected with the thermally conductive adhesive 4 1 3 Above the second thermally conductive member 4 丨 丨: 掸 2 散 1220305 V. Description of the invention (7) The heat, the heat dissipation member 407 and the thermally conductive member 4 1 1 are all made of a material with high thermal conductivity, such as copper. The above-mentioned embodiments are only for clearly expressing the features of the present invention, and the present invention is not limited to being applied to a two-wafer stacked structure. As shown in FIG. 5, it is another embodiment of the present invention. The flow chart of the wafer perforation structure is shown in FIG. 2A to FIG. 2D. 0 8 is adhered to the surface of the substrate 1 06, and is located on both sides of the multi-chip stack structure. The heat-conducting device 5 5 has at least a portion 509, which is connected to any one of the chips with a thermally conductive adhesive 50 4 to form a thermal conductivity. The thermally conductive contact may be located on one of the crystal plane, the crystal back, and the crystal side of the wafer, and a heat dissipating component 5 0 7 may be connected with one end of the thermally conductive device 5 5 5 by a thermally conductive adhesive 5 1 3. Used to gain heat dissipation. The heat-dissipating component 507 and the heat-conducting device 505 are all made of a material with high thermal conductivity, such as copper. The above-mentioned embodiment is only for clearly expressing the features of the present invention, and it is not limited that this issue period is only applied to a two-chip stacked structure. As shown in Fig. 3, yet another embodiment of the present invention is based on the plurality of thermally conductive members 1 0 9 in the previous embodiment, partially extending to form an exposed portion 1 1 4, which can further improve heat dissipation performance. To sum up, the present invention provides a three-dimensional wafer stacking assembly technology. Compared with the conventional technology, the present invention has the following characteristics. The heat generated by any wafer can be transmitted to the heat conduction member of the wafer to The heat conducting device can dissipate heat to the outside and provide a short heat conduction path, so it has better heat dissipation function. Since the heat conducting member is not placed between the wafers, the size of the three-dimensional wafer stacking structure can be reduced. Invention has more than conventional technology
1220305 五、發明說明（8) 進步性及實用性。 所述者，僅為本發明其中的較佳實施例而已，並非用 來限定本發明的實施範圍；即凡依本發明申請專利範圍所 作的均等變化與修飾，皆為本發明專利範圍所涵蓋。1220305 V. Description of the invention (8) Progressiveness and practicality. The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention; that is, all equivalent changes and modifications made in accordance with the scope of patent application for the present invention are covered by the scope of patent of the present invention.
第13頁 1220305 圖式簡單說明 第1圖為一習知技術代表圖； 第2A圖至第2D圖為一晶片穿孔構裝之流程圖； 第3圖為本發明之一實施例側面圖； 第4圖為本發明之另一實施例侧面圖；及 第5圖為本發明之再一實施例側面圖。 【圖式符號說明】 100 第一晶片 101 穿孔 10 2 錫料凸塊 103 第一電性連接凸塊 104 導熱膠 105 導熱裝置 106 基板 107 散熱部件 108 導熱膠 109 第一導熱部件 110 導熱膠 111 第二導熱部件 113 導熱膠 2 〇 0 第二晶片 2 0 3 第二電性連接凸塊 3 0 0 基板 3 0 0 a 基板正面 3 0 0b 基板背面1220305 on page 13 Brief description of the diagram. Figure 1 is a representative diagram of a conventional technology; Figures 2A to 2D are flowcharts of a wafer perforation structure; Figure 3 is a side view of an embodiment of the present invention; FIG. 4 is a side view of another embodiment of the present invention; and FIG. 5 is a side view of still another embodiment of the present invention. [Illustration of Symbols] 100 First wafer 101 Perforation 10 2 Tin bump 103 First electrical connection bump 104 Thermal conductive adhesive 105 Thermal conductive device 106 Substrate 107 Radiating component 108 Thermal conductive material 109 First thermal conductive component 110 Thermal conductive adhesive 111 Two thermally conductive components 113 Thermally conductive adhesive 2 〇2 Second wafer 2 0 3 Second electrical connection bump 3 0 0 Substrate 3 0 0 a Substrate front 3 0 0b Substrate back
第14頁 1220305 圖式簡單說明 305 接地墊 310 第一晶片 310a 弟一晶片 之電路 面 3 10b 弟一晶片 之非電 路面 311 銲料凸塊 320 弟二晶片 3 2 0 a 弟二晶片 之電路 面 3 2 0 b 弟二晶片 之非電 路面 321 黏膠層 330 散熱塊 331 散熱塊之支撐部 332 散熱塊之頂部 335 導電膠 340 銲線 360 球柵陣列 404 導熱膠 407 散熱部件 408 導熱膠 409 第一導熱部件 410 導熱膠 411 第二導熱 部件 413 導熱膠 504 導熱膠 50 5 導熱裝置Page 14 1220305 Brief description of the diagram 305 Ground pad 310 First chip 310a Circuit board 3 of the first chip 3 10b Non-circuit surface of the board 1 311 Solder bump 320 Second chip 3 2 0 a Circuit board 3 of the second chip 3 2 0 b Non-circuit surface of the second chip 321 Adhesive layer 330 Thermal block 331 Support block of thermal block 332 Top of thermal block 335 Conductive adhesive 340 Welding wire 360 Ball grid array 404 Thermal adhesive 407 Thermal component 408 Thermal adhesive 409 First Thermally conductive component 410 Thermally conductive adhesive 411 Second thermally conductive component 413 Thermally conductive adhesive 504 Thermally conductive adhesive 50 5 Thermally conductive device
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