591781591781
【發明所屬之技術領域】 本發明係有關於一種用於量測同時切換雜1 (Simultaneous Switch Noise)之基板，更特"別有關於一 種基板’具有接地墊及電源墊選擇性分別電性連接^至接地 層及電源層，藉此量測各種不同的封裝構造之同切換雜 訊。 、 、 【先前技術】 半導體封裝主要具有四個功能，包括：訊號的連接、 電源的連接、熱量的散發、以及保護。一般而言，半導體 晶片係先形成一包封體（encl〇sure)，例如單_晶片模組 (SCM)或晶片承載器（chip carrier )，稱為第一階段的封 裝’亦即半導體封裝。這些封裝後的晶片，伴隨著其他的 元件，諸如電容、電阻、電桿、濾波器、開關、光學元 件、及RF元件等等，係於第二階段封裝中，組裝在一印刷 電路板上。[Technical field to which the invention belongs] The present invention relates to a substrate for measuring Simultaneous Switch Noise at the same time, and more particularly " specially to a substrate 'which has a ground pad and a power pad selectively and electrically Connect ^ to the ground plane and the power plane to measure the switching noise of various package structures. [Previous technology] Semiconductor packages mainly have four functions, including: signal connection, power connection, heat dissipation, and protection. Generally speaking, a semiconductor wafer is first formed into an enclosing body, such as a single-chip module (SCM) or a chip carrier, which is referred to as a first-stage package, that is, a semiconductor package. These packaged chips, along with other components, such as capacitors, resistors, poles, filters, switches, optical components, and RF components, are packaged in a second-stage package and assembled on a printed circuit board.
隨著半導體晶片之工作頻率的增高、元件密度的增 加，以及工作電壓的下降，半導體封裝所產生的雜訊問題 越趨嚴重。更明確而言，當半導體晶片上的元件在開啟 (on)與關閉（〇 f f)間切換時，基板間的電源及接地面所產 生的同時切換雜訊（Simultaneous Switch Noise ;SSN)便 會大幅度的降低整體半導體封裝構造的效益，亦即降低整 個系統的效益。為了解決上述同時切換雜訊的問題，半導 體封裝構造之同時切換雜訊必須被量測以及分析，以改良 半導體封裝構造以及其基板之設計，進一步將該半導體封As the operating frequency of semiconductor wafers increases, the density of components increases, and the operating voltage decreases, the problem of noise generated by semiconductor packages becomes more serious. More specifically, when the components on the semiconductor wafer are switched between on (off) and off (off), the simultaneous switching noise (SSN) generated by the power and ground planes between the substrates will increase. Decrease the benefit of the overall semiconductor package structure, that is, the benefit of the entire system. In order to solve the above-mentioned problem of simultaneous switching noise, the switching noise of the semiconductor package structure must be measured and analyzed to improve the semiconductor package structure and the design of the substrate, and further the semiconductor package
第9頁 591781 五、發明說明（2) 裝構造之同時切換雜訊降至最低 傳統上，為了量測半導體封裝構造之同時切換雜訊， 必須提供特定設計之量測板，以與不同的半導體封裝構造 相配合。因此，同時切換雜訊之量測係相當難以處理的^ 有鑑於此，便有需要提供一種用於量測同時切換雜訊 之萬用測試基板，能夠適用於各種不同的封裝構造。 【發明内容】 本發 之測試基 為達 體封裝構 地層、一 墊、以及 置於該介 配置於該 層中，且 半導體封 一連接墊 一連接墊 二連接墊 綜前 或供給電 換雜訊。 封裝構造 明之一 板，能 上述目 造之同 電源層 複數個 電層之 介電層 分別電 裝構造 或該第 選擇性 選擇性 所述， 源，而 該基板 相配合 目的在 夠適用 的，本 時切換 Λ —複 導電通 頂部表 之底部 性連接 具有複 二連接 地電性 地電性 該半導 可便利 之連接 ，而可 於各種 發明提 雜訊。 數個第 孔。該 面，且 表面。 該第一 數個接 墊上。 連接至 連接至 體封裝 的量測 墊係陣 適用於 一種用於量測同時切換雜訊 不同的封裝構造。 供一種基板用於量測一半導 該基板包含一介電層、一接 一連接墊、複數個第二連接 接地層及該 該電源層及 該導電通孔 連接墊及該 點係個別地 複數個導電 该接地層， 該電源層。 構造之接點 該半導體封 列分佈，如 里測不同的 第一連接墊係配 該第二連接墊係 係配置於該介電 第二連接墊。該 電性連接至該第 膠可用以將該第 且可用以將該第 可選擇性的接地 裝構造之同時切 此便可與不同的 半導體封裝構Page 9591781 V. Description of the invention (2) Switching noise while mounting structure is minimized Traditionally, in order to measure semiconductor package structure and switch noise at the same time, a measurement board with a specific design must be provided to compare with different semiconductors. The package structure is matched. Therefore, it is quite difficult to switch the measurement of noise at the same time. In view of this, it is necessary to provide a universal test substrate for measuring and switching noise at the same time, which can be applied to various package structures. [Summary of the invention] The test base of the present invention is a body package structure layer, a pad, and a semiconductor package, a connection pad, a connection pad, a connection pad, and a power supply noise. . The package structure shows a board that can make the above-mentioned dielectric layers of the same power layer and a plurality of electrical layers, respectively, the electrical structure or the first selective selective source, and the matching purpose of the substrate is sufficient. Time Switching Λ — The bottom connection of the top table of the complex conductor has a complex second connection. The semiconductor can be conveniently connected, and can raise noise in various inventions. Several holes. The surface, and the surface. The first number of pads. The measurement pad array connected to the connection to the body package is suitable for a kind of package structure for measuring and switching noise at the same time. A substrate for measuring half-conductivity. The substrate includes a dielectric layer, connection pads, a plurality of second connection ground layers, the power supply layer, the conductive via connection pads, and the points are individually plural. The ground layer and the power layer are conductive. The junction of the structure. The semiconductor package is distributed. For example, different first connection pads are matched with the second connection pads and are arranged on the dielectric second connection pads. The electrical connection to the first adhesive can be used to connect the first and second selective grounding structures at the same time.
第10頁 591781 五、發明說明（3) 。 為了讓本發明之上述和其他目的、特徵、和優點能更 明頒’下文特舉本發明較佳實施例，並配合所附圖示，作 詳細說明如下。 【實施方式】 芩考第1 - 3圖，其顯示根據本發明之一基板10 0，用於 i測一半導體封裝構造之同時切換雜訊（Simu 1 taneous Switch Noise ;SSN)。該基板loo具有一介電層120，係由 介電材料（dielectric material)所製造。一電源層 (Power Plane)132 及一接地層（Ground Plane)142 係分別 配置於該基板1〇〇之該介電層12〇之頂部及底部表面上。舉 例而言’如圖所示，該電源層丨3 2係配置於該介電層丨2 〇之 底部表面，且該接地層丨42係配置於該介電層丨2〇之頂部表 面。勿庸贅述，該電源層132亦可配置於該介電層12〇之頂 部表面，且該接墊層142亦可配置於該介電層12〇之底部表 面。 如第2及3圖所示，複數個連接墊14〇及連接墊丨3〇分別 配置於該基板100之該介電層120之頂部及底部表面，並夢 由複數個導電通孔（V i a ) 1 2 2個別的相互連接。一防焊声 (Solder Mask)144係配置於該介電層12〇之頂部表面〔 部分地覆蓋該連接墊140及該接地層142。該連接塾14〇 2 體上具有較大的面積，且配置於該連接塾1 4 〇上之今防產曰 層144具有一接墊開口146，用以界定一接塾148。^ 鮮 舉例而言，請參考第4-6圖，其顯示根據本發明之該 591781 五、發明說明（4) 基板10 0係量測一球格陣列封裝構造2 〇〇。該球格陣列封裝 構造200具有一基板210、一封膠體212配置於該基板210 上用以包封一半導體晶片（圖中未示）、及複數個錫球 220固定於該基板2 1 〇上。該複數個錫球22〇係電性至 該半導體晶片。 於量測時’該半導體封裝構造2 G〇之該錫球2 2〇係可藉 由已知的表面固定技術（Surface M〇unt Technique)，電 性連接並固定至該基板丨00之該接墊148上。當該球格陣列 封裝構造2 0 0之該錫球2 2 0 a需要接地時，一導電膠，諸如 $膠230a，係塗佈於該接地層142與該連接墊H〇a之間， 藉此該錫球220a係電性連接至該接地層142。當該球格陣 列封裝構造2 0 0之該錫球2 2 0 b需要供給電源時，一導電 膠，諸如銀膠230b，係塗佈於該電源層132與該連接墊 1 30b之間，藉此該錫球22〇b係經由該導電通孔丨22及該連 接墊140b，電性連接至該電源層132。勿庸贅述，該連 墊130及140與該電源層132及該接地層142間亦可保持絕 緣，如此使得該錫球220將不致於接地或被供給電源。巴 如圖所不，該基板1〇〇之該接墊丨48係以陣列分佈 此以便與不同的半導體封裝構造相配合。再者，該接如 1 4 8可以固定的或變化的間距分佈，藉以配合不同 體封裝構造。 ¥ 如前所述，該半導體封裝構造之錫球可選擇性的接( 或供給電源，而可便利的量測該半導體封裝構造之同日士 換雜訊。精於本技藝者將可瞭解，根據本發明之基板】= ΓΙ 第12頁 591781Page 10 591781 V. Description of Invention (3). In order to make the above and other objects, features, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described below, and the accompanying drawings will be described in detail below. [Embodiment] Figs. 1-3 show a substrate 100 according to the present invention, which is used to measure a semiconductor package structure while switching noise (Simu 1 taneous Switch Noise; SSN). The substrate loo has a dielectric layer 120, which is made of a dielectric material. A power plane 132 and a ground plane 142 are respectively disposed on the top and bottom surfaces of the dielectric layer 120 of the substrate 100. For example, as shown in the figure, the power supply layer 3 2 is disposed on the bottom surface of the dielectric layer 2 20, and the ground layer 42 is disposed on the top surface of the dielectric layer 2 20. Needless to say, the power supply layer 132 can also be disposed on the top surface of the dielectric layer 120, and the pad layer 142 can also be disposed on the bottom surface of the dielectric layer 120. As shown in FIGS. 2 and 3, a plurality of connection pads 14 and 30 are disposed on the top and bottom surfaces of the dielectric layer 120 of the substrate 100, respectively, and a plurality of conductive vias (V ia ) 1 2 2 Individual interconnections. A solder mask (Solder Mask) 144 is disposed on the top surface of the dielectric layer 120 [partially covering the connection pad 140 and the ground layer 142. The connection 142 has a large area on the body, and the present production-prevention layer 144 disposed on the connection 142 has a pad opening 146 for defining a connection 148. ^ For example, please refer to Figs. 4-6, which show the 591781 according to the present invention. 5. Description of the Invention (4) The substrate 100 measures a ball grid array package structure 2000. The ball grid array package structure 200 has a substrate 210, a colloid 212 disposed on the substrate 210 for encapsulating a semiconductor wafer (not shown), and a plurality of solder balls 220 fixed on the substrate 2 10. . The plurality of solder balls 2220 are electrically connected to the semiconductor wafer. During the measurement, the semiconductor package structure 2 G0 and the solder ball 2 2 0 can be electrically connected and fixed to the connection of the substrate by a known surface mounting technique (Surface Mount Technique). On the pad 148. When the solder ball 2 2 0 a of the ball grid array package structure 2 0 0 needs to be grounded, a conductive adhesive, such as $ glue 230 a, is applied between the ground layer 142 and the connection pad H 0a. The solder ball 220a is electrically connected to the ground layer 142. When the solder ball 2 2 0 b of the ball grid array package structure 200 needs to supply power, a conductive adhesive, such as silver adhesive 230 b, is applied between the power supply layer 132 and the connection pad 1 30 b. The solder ball 22b is electrically connected to the power supply layer 132 via the conductive via 22 and the connection pad 140b. Needless to say, insulation can also be maintained between the pads 130 and 140 and the power supply layer 132 and the ground layer 142, so that the solder ball 220 will not be grounded or supplied with power. As shown in the figure, the pads 48 of the substrate 100 are distributed in an array so as to cooperate with different semiconductor package structures. Furthermore, the connection can be distributed at a fixed or variable pitch to match different package structures. ¥ As mentioned earlier, the solder balls of the semiconductor package structure can be selectively connected (or supplied with power), and the semiconductor package structure can be easily measured for noise. The person skilled in the art will understand that according to Substrate of the invention] = ΓΙ Page 12 591781
僅限於畺測球袼陣列封裝構造，根據本發明之基板可以提 供各種不同型式之接墊，諸如插槽或銲墊，用以電性連 至不同型式之封裝構造之接點，諸如針狀格陣列（p i η Grid Array ;PGA)或四方平坦封裝構造（Quad Flat Package ； QFP)。 雖然丽述的描述及圖示已揭示本發明之較佳奋 必須瞭解到各種增添、修改和取 1^， 貝施例，而不會脫離如所附申請專 f<土 原理之精神及範圍。熟悉該枯 靶圍所界疋的本發明 用於很多形式、結構:者將可體會本發明可能使 修改。因此，本文於此所揭示的=、材料、兀件和組件的 視為用以說明本發明，而非用以焉施例於所有觀點，應被 圍應由後附申請專利範圍所界定限制本發明。本發明的範 並不限於先前的描述。 1疋’並涵蓋其合法均等物， 591781 圖式簡單說明 【圖式簡單說明】 第1圖：為根據本發明之一用於量測同時切換雜訊之基板 之橫剖面示意圖。 第2圖：為第1圖所示之該基板之上平面示意圖。 第3圖：為第1圖所示之該基板之下平面示意圖。 第4-6圖：為根據本發明之該基板，量測一球格陣列封裝 構造之橫剖面示意圖。 圖號說明： 100 基板 120 介電層 122 導電通孔 130 連接墊 130b 連接墊 132 電源層 140 連接墊 140a 連接墊 142 接地層 144 防銲層 146 接墊開口 148 接墊 200 球格陣列封裝構造 210 基板 212 封膠體 220 錫球 220a 錫球 22 0b 錫球 23 0a 銀膠 2 3 0b 銀膠It is only limited to the test ball array package structure. The substrate according to the present invention can provide various types of pads, such as sockets or solder pads, for electrically connecting to contacts of different types of package structures, such as pin grids. Array (Pi n Grid Array; PGA) or Quad Flat Package (QFP). Although the description and illustrations of Lishu have revealed the best practices of the present invention, it is necessary to understand various additions, modifications, and examples, without departing from the spirit and scope of the principle of earth as described in the attached application. The invention, which is familiar with the boundaries of the target, is used in many forms and structures: those who will appreciate that the invention may make modifications. Therefore, the materials, components, and components disclosed herein are to be used to illustrate the present invention, not to illustrate the point of view in all aspects, and should be bounded by the scope of the attached patent application. invention. The scope of the invention is not limited to the foregoing description. 1 疋 ’and its legal equivalents are covered. 591781 Brief Description of Drawings [Simplified Description of Drawings] Figure 1: A schematic cross-sectional view of a substrate for measuring and simultaneously switching noise according to one of the present invention. FIG. 2 is a schematic plan view of the substrate shown in FIG. 1. FIG. 3 is a schematic plan view below the substrate shown in FIG. 1. 4-6 are schematic cross-sectional views of a ball grid array package structure measured for the substrate according to the present invention. Description of drawing number: 100 substrate 120 dielectric layer 122 conductive via 130 connection pad 130b connection pad 132 power supply layer 140 connection pad 140a connection pad 142 ground layer 144 solder mask 146 pad opening 148 pad 200 ball grid array package structure 210 Substrate 212 Sealant 220 Tin ball 220a Tin ball 22 0b Tin ball 23 0a Silver glue 2 3 0b Silver glue
第14頁Page 14