TW587317B - Construction and manufacturing of a chip package - Google Patents

Construction and manufacturing of a chip package Download PDF

Info

Publication number
TW587317B
TW587317B TW091137813A TW91137813A TW587317B TW 587317 B TW587317 B TW 587317B TW 091137813 A TW091137813 A TW 091137813A TW 91137813 A TW91137813 A TW 91137813A TW 587317 B TW587317 B TW 587317B
Authority
TW
Taiwan
Prior art keywords
layer
glass substrate
scope
patent application
item
Prior art date
Application number
TW091137813A
Other languages
Chinese (zh)
Other versions
TW200411862A (en
Inventor
Chi-Hsing Hsu
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW091137813A priority Critical patent/TW587317B/en
Application granted granted Critical
Publication of TW587317B publication Critical patent/TW587317B/en
Publication of TW200411862A publication Critical patent/TW200411862A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Construction and manufacturing of a chip package which is composed of a glass substrate, at least one chip, an adhesive layer, a stiff layer and an interconnection layer. The glass substrate with a first surface on which the chip is located is opposite to an active surface of the chip. In addition, the adhesive layer covers the first surface and the chip fully. The stiff layer is located on the adhesive layer, moreover, first conductive vias pass through the glass substrate to be electrically coupled to the chip pad of the chip. The interconnection layer with several bonding pads which are located on the second surface of the glass substrate and electrically coupled to those first conductive vias.

Description

587317587317

發明所屬之技術領城 本發明是有關於一種晶片封裝結構及其製程，且特別 疋有關於一種應用玻璃基板（glass substrate)作為介 電層（dielectric layer )之晶片封裝結構及其製程。 先前枯術 覆晶接合技術（Flip Chip Interconnect Technology，簡稱FC )乃是利用面陣列（area array )的 方式’將多個晶片墊（d i e pad )配置於晶片（d i e )之主 動表面（active surface)上，並在晶片墊上形成凸塊 (bump)，接著將晶片翻覆（nip)之後，再利用這些凸 塊來分別電性及機械性連接晶片之晶片墊至承載器 (carrier)上的接點（contact )，使得晶片可經由凸塊 而電性連接至承載器，並經由承載器之内部線路而電性連 接至外界之電子裝置。值得注意的是，由於覆晶接合技術 (FC)係可適用於高腳數pin count )之晶片封裝 、’、《構並同時具有縮小晶片封裝面積及縮短訊號傳輸路徑 等諸多優點，所以覆晶接合技術目前已經廣泛地應用於晶 片封裝領域，常見應用覆晶接合技術之晶片封裝結構例如 有覆晶球格陣列型（Flip Chip Ball Grid Array， FC/BGA )及覆晶針格陣列型（FHp Chip Pin Grid ·The invention belongs to a technology leader. The present invention relates to a chip packaging structure and a manufacturing process thereof, and particularly to a chip packaging structure and a process using a glass substrate as a dielectric layer. Previously, Flip Chip Interconnect Technology (FC) was a method of using an area array to 'position multiple die pads on the active surface of a die. And bumps are formed on the wafer pad, and after the wafer is overturned (nip), these bumps are used to electrically and mechanically connect the wafer pad of the wafer to the contacts on the carrier ( contact), so that the chip can be electrically connected to the carrier through the bump, and electrically connected to the external electronic device through the internal circuit of the carrier. It is worth noting that, because the flip-chip bonding technology (FC) is applicable to chip packages with high pin counts, it has many advantages such as reducing chip package area and shortening signal transmission paths. Bonding technology has been widely used in the field of chip packaging. Common chip packaging structures that use flip-chip bonding technology include Flip Chip Ball Grid Array (FC / BGA) and FHp. Chip Pin Grid

Affay ’ FX/PGA )等型態之晶片封裝結構。 曰 喷參考第1圖，其繪示習知之一種覆晶球格陣列型之 晶片封裝結構的剖面示意圖。晶片封裝結構1 〇〇包括基板 (substrate ) 11〇、多個凸塊12〇、晶片13〇、及多個銲球Affay ’FX / PGA) and other types of chip packaging structure. Refer to FIG. 1, which is a schematic cross-sectional view of a conventional flip chip lattice array type chip package structure. The chip package structure 100 includes a substrate 11, a plurality of bumps 120, a wafer 13, and a plurality of solder balls.

587317 五、發明說明（2) 140。其中，基板11〇具有一頂面112及對應之一底面114 , 且基板110更具有多個凸塊墊（bump pad) 116a及多個銲 球墊（bal 1 pad ) 11 6b。此外，晶片1 30具有一主動表面 (active surface) 132及對應之一背面134，其中晶片 130之主動表面132係泛指晶片130之具有主動元件 (active device)(未繪示）的一面，並且晶片130更具 有多個晶片墊136，其配置於晶片130之主動表面132 ,用 以作為晶片1 3 0之訊號輸出入的媒介，其中這些凸塊墊 116a之位置係分別對應於這些晶片墊丨36之位置。另外， 這些凸塊120則分別電性及機械性連接這些晶片墊丨36之一 至其所對應之這些凸塊墊116a之一。並且，這些録球14〇 則分別配置於這些銲球墊11 6 b上，用以電性及機械性連接 至外界之電子裝置。587317 V. Description of the invention (2) 140. The substrate 110 has a top surface 112 and a corresponding bottom surface 114, and the substrate 110 further includes a plurality of bump pads 116a and a plurality of bal 1 pads 11 6b. In addition, the chip 130 has an active surface 132 and a corresponding back surface 134. The active surface 132 of the chip 130 refers to the side of the chip 130 with an active device (not shown), and The wafer 130 further has a plurality of wafer pads 136, which are arranged on the active surface 132 of the wafer 130 and serve as a medium for the signal input and output of the wafer 130. The positions of the bump pads 116a correspond to the wafer pads, respectively. 36 position. In addition, the bumps 120 are electrically and mechanically connected to one of the wafer pads 36 to one of the corresponding bump pads 116a, respectively. In addition, these recording balls 14 are respectively arranged on the solder ball pads 11 6 b for electrically and mechanically connecting to external electronic devices.

請同樣參考第1圖，底膠（underfill) 150係可填充 於基板110之頂面112及晶片130之主動表面132所圍成的空 間，用以保護凸塊墊116a、晶片墊136及凸塊120所裸露出 之部分，並同時緩衝基板11〇與晶片13〇之間在受熱時所產 生的熱應變（thermal strain)之不匹配的現象。因此， 晶片130之晶片墊136將可經由凸塊120而電性及機械性連 接至基板11 0之凸塊墊11 6a，再經由基板11〇之内部線路 118而向下繞線（routing)至基板11〇之底面114的銲球墊 116b，最後經由銲球墊11 6b上之銲球14〇而電性及機械性 連接至外界之電子裝置。值得注意的是，習知晶片1 3 〇與 基板110之材質不同，因此其熱膨脹係數（c〇efficientPlease refer to FIG. 1 as well. Underfill 150 can fill the space surrounded by the top surface 112 of the substrate 110 and the active surface 132 of the wafer 130 to protect the bump pad 116a, the wafer pad 136, and the bump. The exposed part of 120 and at the same time buffer the thermal strain mismatch between the substrate 11 and the wafer 13 when heated. Therefore, the wafer pad 136 of the wafer 130 will be electrically and mechanically connected to the bump pad 116a of the substrate 110 through the bump 120, and then routed down to the inner wiring 118 of the substrate 110 to The solder ball pad 116b on the bottom surface 114 of the substrate 110 is finally electrically and mechanically connected to the external electronic device through the solder ball 14o on the solder ball pad 116b. It is worth noting that the material of the conventional wafer 130 is different from that of the substrate 110, so its thermal expansion coefficient (coefficient)

587317 五、發明說明（3) of Thermal Expansion, CTE)亦不相同，而凸塊120在長 時間受到晶片130與基板11〇之間的熱應變的反覆作用之 下’凸塊120之本身極易產生疲勞（fatigue)而發生橫向 斷裂的現象。另外，習知之晶片封裝製程係完成基板11 〇 之内部線路118、凸塊墊11 6a以及銲球墊11 6b之後，再將 晶片130組裝於基板11〇之表面上。由於晶片13〇暴露於基 板11 0之表面，因此晶片1 30很容易受到外力所破壞，且晶 片1 3 0很容易受到外界溼度影響及雜塵污染等。 再者，目前作為覆晶球格陣列型（FC/BGA )或覆晶針 格陣列型（FC/PGA )之基板的常見材質包括有陶瓷 (ceramic)及有機材料（organic materiai)等，其中 又以有機材料作為材質之有機基板（organic substrate )最為常見。由於有機基板在製程良率上的限制，使得目 刖可大規模量產之有機基板的導線其線寬及線距僅可達到 25微米。值得注意的是，隨著晶片之晶片墊的密度逐漸地 升高’而現有之有機基板的接點密度無法相對地向上提升 的情況下，如何利用具有更高密度接點及微細線路之基板 來取代現有之有機基板，此乃目前晶片封裝領域所亟待解 決的重大課題。 發明内容 有鑑於此，本發明之目的係在於提出一種晶片封裝結 構及其製程，主要是利用玻璃基板來取代習知之有機基 板，並可提供咼密度接點及微細線路，用以封裝具有高密 度晶片墊之晶片，並提高晶片封裝之性能。 间587317 V. Description of the invention (3) of Thermal Expansion (CTE) is also different, and the bump 120 is subject to repeated effects of thermal strain between the wafer 130 and the substrate 110 for a long time. The bump 120 itself is extremely easy Fatigue occurs and lateral fracture occurs. In addition, the conventional chip packaging process is to complete the internal circuit 118 of the substrate 110, the bump pad 116a, and the solder ball pad 116b, and then assemble the wafer 130 on the surface of the substrate 110. Since the wafer 130 is exposed on the surface of the substrate 110, the wafer 130 is easily damaged by external forces, and the wafer 130 is easily affected by external humidity and dust pollution. Furthermore, common materials currently used as substrates for flip-chip ball grid array (FC / BGA) or flip-chip pin grid array (FC / PGA) include ceramics and organic materiai. Among them, Organic substrates using organic materials as materials are the most common. Due to the limitation of the organic substrate in the process yield, the wire width and the pitch of the wires of the organic substrate, which can be mass-produced at present, can only reach 25 microns. It is worth noting that, as the density of the wafer pads of the wafers gradually increases, and the contact density of existing organic substrates cannot be relatively increased upwards, how to use substrates with higher density contacts and fine lines to Replacing the existing organic substrates is a major issue urgently to be solved in the field of chip packaging. SUMMARY OF THE INVENTION In view of this, the object of the present invention is to propose a chip packaging structure and a manufacturing process thereof, which mainly uses a glass substrate instead of a conventional organic substrate, and can provide a high-density contact and a fine circuit for packaging with high density. Wafer wafers and improve the performance of chip packaging. between

587317 發明說明（4) 本發明之另一目的係在於提出一種晶片封裝結構及其 製程’其玻璃基板與晶片之表面具有一膠材層以及一支撐 層’用以防止晶片之表面受到外力所破壞，進而使晶片得 到最佳之保護。 為達本發明之上述目的，本發明提出一種晶片封裝製 程’包括下列步驟：（a)提供一玻璃基板，其中玻璃基 板具有一第一表面及對應之一第二表面；（b)提供多個 晶片’其中晶片分別具有一主動表面及對應之一背面，且 晶片更分別具有多個晶片墊，而晶片墊係分別配置於其所 對應之這些晶片之一的主動表面，且經由晶片之主動表 面，而將這些晶片配置於玻璃基板之第一表面；（c)全 面性形成一膠材層於玻璃基板之第一表面，且膠材層覆蓋 晶片之背面；（d)配置一支撐層於膠材層上；（e)形成 多個第一導電插塞於玻璃基板上，其中第一導電插塞係分 別連接於晶片之晶片墊；（f )形成一内連線層於玻璃基77 板之第二表面，其中内連線層更具有多個接合墊，其位於 内連線層之遠離第二表面的一面，且内連線層之内部線路 係電性連接於這些導電插塞；以及（g)單顆化這些封 後之晶片。 為達本發明之上述目的，本發明提出一種晶片封装社 構，包括一玻璃基板、至少一晶片、一膠材層、一支樓^ 以及一内連線層。其中，玻璃基板具有一第一表面及對廉 之一第二表面，而晶片具有一主動表面及對應之_背面了 且晶片更具有多個晶片墊，其分別配置於晶片之主動表587317 Description of the invention (4) Another object of the present invention is to propose a chip packaging structure and its process, "the surface of the glass substrate and the wafer has an adhesive layer and a support layer" to prevent the surface of the wafer from being damaged by external forces. , So that the chip is best protected. In order to achieve the above object of the present invention, the present invention proposes a chip packaging process including the following steps: (a) providing a glass substrate, wherein the glass substrate has a first surface and a corresponding second surface; (b) providing a plurality of Wafer 'wherein the wafer has an active surface and a corresponding back surface, and the wafer further has a plurality of wafer pads, and the wafer pads are respectively disposed on the active surface of one of these wafers and pass through the active surface of the wafer. These wafers are arranged on the first surface of the glass substrate; (c) a glue layer is comprehensively formed on the first surface of the glass substrate, and the glue layer covers the back of the wafer; (d) a support layer is arranged on the glue (E) forming a plurality of first conductive plugs on a glass substrate, wherein the first conductive plugs are respectively connected to a wafer pad of a wafer; (f) forming an interconnecting layer on a glass-based 77 board A second surface, wherein the interconnect layer further has a plurality of bonding pads, which are located on a side of the interconnect layer that is away from the second surface, and the internal wiring of the interconnect layer is electrically connected to the conductive plugs; And (g) singulate these sealed wafers. In order to achieve the above object of the present invention, the present invention provides a chip packaging structure, which includes a glass substrate, at least one wafer, an adhesive material layer, a building, and an interconnect layer. Among them, the glass substrate has a first surface and a second surface, and the wafer has an active surface and a corresponding back surface, and the wafer further has a plurality of wafer pads, which are respectively arranged on the active surface of the wafer.

587317587317

五、發明說明（5) 面，且晶片係以主動表面配置於玻璃基板之第一表面。此 外，膠材層係全面性覆蓋玻璃基板之第一表面，且覆蓋晶 片之背面。支撐層係配置於膠材層之上，而第一導電插^ 係貫穿玻璃基板，而分別電性連接晶片之晶片塾。另外= 内連線層係配置於玻璃基板之第二表面，並具有多個接人 墊，其位於内連線層之遠離基板之第二表面的一面，且; 連線層之内部線路係電性連接至這些第一導電插塞。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： ^ 實施方式5. Description of the invention (5), and the wafer is arranged on the first surface of the glass substrate with an active surface. In addition, the adhesive layer covers the first surface of the glass substrate and covers the back of the wafer. The supporting layer is disposed on the adhesive material layer, and the first conductive plug ^ penetrates the glass substrate and is electrically connected to the wafer 塾 of the wafer. In addition = the interconnect layer is disposed on the second surface of the glass substrate and has a plurality of access pads, which are located on the side of the interconnect layer that is away from the second surface of the substrate, and the internal wiring of the interconnect layer is electrically To the first conductive plugs. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: ^ Embodiments

第2A〜2F圖依序繪示本發明之較佳實施例的一種晶片 封裝製程的剖面流程圖。請先參考第2A圖，先提供一玻璃 基板210，某具有一第一表面212以及對應之一第二表面 214，接著提供多個晶片220，而每一晶片220具有一主動 表面222以及對應之一背面224，且每一晶片220還具有多 個晶片墊226，其配置於晶片220之主動表面222上，而晶 片220係以覆晶（FC)接合的方式，將晶片220之主動表面 222貼附於玻璃基板210之第一表面212上。其中，晶片220 與玻璃基板21 0之間例如以一黏著層2 3 0 a而貼合，而黏著 層230a可以薄膜貼附的方式形成在玻璃基板21〇之上，接 著晶片220經由黏著層230a而貼附於玻璃基板210上。值得 注意的是’由於玻璃基板21〇與晶片220之材質均為矽化 物’所以兩者之熱膨脹係數相近，使得玻璃基板2 1 〇與晶Figures 2A to 2F sequentially show a cross-sectional flowchart of a chip packaging process according to a preferred embodiment of the present invention. Please refer to FIG. 2A first, a glass substrate 210 is provided, a certain surface has a first surface 212 and a corresponding second surface 214, and then a plurality of wafers 220 are provided, and each wafer 220 has an active surface 222 and a corresponding surface. A back surface 224, and each wafer 220 also has a plurality of wafer pads 226, which are arranged on the active surface 222 of the wafer 220, and the wafer 220 is bonded to the active surface 222 of the wafer 220 by means of flip-chip (FC) bonding It is attached to the first surface 212 of the glass substrate 210. Wherein, the wafer 220 and the glass substrate 21 0 are bonded by, for example, an adhesive layer 2 3 0 a, and the adhesive layer 230 a can be formed on the glass substrate 21 0 by a thin film, and then the wafer 220 is passed through the adhesive layer 230 a. It is attached to the glass substrate 210. It ’s worth noting that because the materials of the glass substrate 21 and the wafer 220 are silicides, the thermal expansion coefficients of the two are similar, so that the glass substrate 21 and the crystal

587317587317

片2 2 0之熱應變可以相互匹配。 ^, "〇^Λ^22βΓ2," ： ： ： ί 2：Γ"230 " ^ 220，Α展：J 材層230係完全覆蓋晶片 220 S厚度可大於等於晶片22G之厚度，如此膠材声⑽ 可在晶片220之表面形成一層保護膠膜，使得晶片二以及 Ϊ: i =力之/;表面212不會暴露出來，所以晶片220 ^二到外力所破壞。此外，谬材層230之材質例如為環 虱樹月曰（epoxy resin)等有機材料，而 :配；：支撐綱，且支撑侧之材質可為曰強=還 用以提咼晶片封裝結構的硬度，且支撐層24〇亦可為一高 散熱性之導熱板，其包括金屬或石墨等材質，用以#將晶片 220胃所產胃生之熱能快速地傳導至晶片封裝結構的表面，藉 以提南晶片封裝結構之散熱效能。 ,接著請參考第2C圖，從玻璃基板210之第二表面214來 薄化玻璃基板21 0。由於上述之支擇層24()具有足夠的強度 以及硬度，所以支樓層240更可作為曰曰曰片22〇以及玻璃基板 210之底部的支撐結構。因此，當從玻璃基板21〇之第二表 面214來薄化玻璃基板21〇時，晶片220以及膠材層230較不 會受到研磨機台之施力，而有損傷或斷裂之可能性。 接著請參考第2D圖，形成多個第一導電插塞21〇a於玻 璃基板210上，其方法例如先在玻璃基板21Q上進行雷射燒 孔（laser ablation )、蝕刻穿孔或超音波成孔，以使玻 璃基板210之第二表面214上形成多個開口 21〇a，之後再分 別填入一導電材質於每一開口 21〇a之内，而形成上述之多The thermal strain of the plates 2 2 0 can be matched with each other. ^, " 〇 ^ Λ ^ 22βΓ2, "::: ί 2: Γ Γ 230 & ^ 220, Α exhibition: J material layer 230 completely covers the thickness of wafer 220 S can be greater than or equal to the thickness of wafer 22G, so glue The material sound can form a protective film on the surface of the wafer 220, so that the second wafer and the second wafer: i = force /; the surface 212 will not be exposed, so the wafer 220 is damaged by external force. In addition, the material of the absurd material layer 230 is, for example, an organic material such as a ring louse, epoxy resin, and the like: and the supporting platform, and the material on the supporting side may be strong = also used to improve the chip packaging structure. Hardness, and the support layer 240 can also be a high heat-dissipating heat conductive plate, which includes a material such as metal or graphite, which is used to quickly conduct the heat generated by the stomach 220's stomach to the surface of the chip packaging structure, thereby The heat dissipation performance of the chip package structure is improved. Then, referring to FIG. 2C, the glass substrate 210 is thinned from the second surface 214 of the glass substrate 210. Since the above-mentioned optional layer 24 () has sufficient strength and hardness, the branch floor 240 can be used as a supporting structure for the bottom sheet 22 and the bottom of the glass substrate 210. Therefore, when the glass substrate 21 is thinned from the second surface 214 of the glass substrate 21o, the wafer 220 and the adhesive material layer 230 are less likely to be damaged or broken by the force of the polishing machine. Next, referring to FIG. 2D, a plurality of first conductive plugs 21a are formed on the glass substrate 210. For example, a method such as laser ablation, etching perforation, or ultrasonic hole formation on the glass substrate 21Q is performed first. So that a plurality of openings 21a are formed on the second surface 214 of the glass substrate 210, and then a conductive material is filled in each opening 21aa separately to form as many as described above.

587317 五、發明說明（7) 個第一導電插塞2 5 〇。其中開口 21 〇 a的位置亦對應晶片2 2 〇 之，片，226的位置，且開口2i〇a係貫穿玻璃基板210 ,以 暴露出每一晶片墊226，如此導電插塞250係可與晶片墊 226作電性連接，且晶片22〇之每一晶片墊226上具有一第 一導電插塞25 0。另外，在後續形成導線層252於玻璃基板 上的同時，可一併將導電材質250b填入每一開口2l〇a之 内，而形成這些第一導電插塞25(),使得第一導電插塞25〇 可與圖案化之導線層252—體成型。 接著同樣如第2D圖所示，再形成一圖案化之内連線層 260於玻璃基板21〇之第二表面214上，而内連線層“ο係電 性連接於第一導電插塞250，且内連線層26〇可為單層導線 層結構或多層導線層結構。單層導線層結構之内連線層 260係指在玻璃基板21〇之第二表面214上，形成圖案化之 一導線層252，而導線層252之材質可為銅、鋁及該等之合 金，且此導線層252具有多個接合墊252a以及線路252b , 且接合墊252a藉由線路252b而電性連接於第一導電插塞 250，最後可再形成一抗銲層258於此導線層託2上並暴 露出接合墊252a ,如此即構成單層導線層託2之内連線層 260，如第4圖所示之内連線層26〇 ,其僅包括一單層導線 層。 < 如第2E圖所不，多層導線層結構之内導線層係指 在玻璃基板210之第二表面214上，形成以圓案化之導線 層252、25 6以及η-1層介電層254，其中n可為自然數㈠列 如2,3,4···#’但1除外），而相鄰二圖案化之導線層 10035twf.ptd 第11頁 587317 五、發明說明（8) 252 : 256與一介電層254交替疊合，且多個第二導線插塞 251係0以上述之雷射燒孔、蝕刻穿孔或超音波成孔的方 式，貫穿介電層2 54 ,而電性連接於相鄰二圖案化之導線 層252及^導線層256之間。其中介電層254之材質可為氮化 矽或二氧化矽等材質，其與晶片22〇、玻璃基板21〇的熱膨 脹係數相近，故可與晶片2 2 〇、玻璃基板21 〇之熱應變相互 匹配。 :請再參考第2E圖，内導線層26 0之遠離玻璃基板21〇的 最頂層還具有多個接合塾2 5 6a以及線路256b，且接合墊 2 5 6a藉由線路256b而電性連接於第一、第二導電插塞 2 5 0、251 ’最後再形成一抗銲層258於最頂層之導線層256 上，並暴露出接合墊2 5 6a。其中，接合墊2 5 6a之表面上還 可配置多個接點270 ’用以連接外部之電子裝置，且接點 270可為一銲球（ball)或一針腳（pin)，用以形成覆晶 球格陣列型（FC/BGA)或覆晶針格陣列型（FC/PGA)之晶 片封裝結構。 接著如第2F圖所示’利用切割機將上述具有多個晶片 220之玻璃基板210切單，以得到單顆化之晶片封裝結構 200其中，晶片220之數目非侷限於單顆。由於玻璃基板 之佈線密度高，其導線層之線寬及線距（pi tch )可達到 1 · 5微米’遠小於有機基板之導線層之線寬及線距（約2 5 微米）。因此，可配置多個晶片22()於一玻璃基板21〇中， 故可應用於多晶片模組（Multi ple-Chip Module，MCM ) 或系統於單一封裝（System In Package, SIP )等晶片封587317 V. Description of the invention (7) First conductive plugs 2 5 0. The position of the opening 21 〇a also corresponds to the position of the wafer 2 2 0, the position of the sheet 226, and the opening 2 ioa penetrates the glass substrate 210 to expose each wafer pad 226, so the conductive plug 250 can communicate with the wafer. The pads 226 are electrically connected, and each wafer pad 226 of the chip 220 has a first conductive plug 250. In addition, at the same time that the conductive layer 252 is subsequently formed on the glass substrate, a conductive material 250b may be filled into each of the openings 21a to form these first conductive plugs 25 (), so that the first conductive plug The plug 25 can be formed integrally with the patterned wire layer 252. Then, as shown in FIG. 2D, a patterned interconnect layer 260 is formed on the second surface 214 of the glass substrate 21, and the interconnect layer is electrically connected to the first conductive plug 250. In addition, the interconnect layer 26 may be a single-layer wire layer structure or a multilayer wire layer structure. The interconnect layer 260 of the single-layer wire layer structure refers to a patterned pattern formed on the second surface 214 of the glass substrate 21 A wire layer 252, and the material of the wire layer 252 may be copper, aluminum, and alloys thereof, and the wire layer 252 has a plurality of bonding pads 252a and lines 252b, and the bonding pads 252a are electrically connected to the bonding layer 252a through the lines 252b. The first conductive plug 250 can finally form a solder resist layer 258 on the wire layer holder 2 and expose the bonding pad 252a, so as to form the inner wiring layer 260 of the single layer wire layer holder 2, as shown in FIG. 4 The interconnect layer 26 shown, which includes only a single wire layer. ≪ As shown in FIG. 2E, the inner wire layer of the multilayer wire layer structure refers to the second surface 214 of the glass substrate 210, formed Rounded wire layers 252, 256, and n-1 dielectric layer 254, where n can be a natural number queue 2,3,4 ... ## except 1), and two adjacent patterned wire layers 10035twf.ptd page 11 587317 5. Description of the invention (8) 252: 256 and a dielectric layer 254 are alternately superposed In addition, a plurality of second wire plugs 251 through 0 pass through the dielectric layer 2 54 in the manner of laser burning holes, etched holes or ultrasonic holes, and are electrically connected to adjacent two patterned wire layers. Between 252 and ^ wire layer 256. The material of the dielectric layer 254 may be silicon nitride or silicon dioxide, which has a thermal expansion coefficient similar to that of the wafer 22 and the glass substrate 21, so it can be similar to the wafer 2 2 〇 The thermal strains of the glass substrate 21 〇 match each other.: Please refer to Figure 2E again. The top layer of the inner conductor layer 26 0 far from the glass substrate 21 〇 also has a plurality of bonding pads 2 5 6a and wiring 256b, and the bonding pad 2 5 6a is electrically connected to the first and second conductive plugs 2 5 0, 251 through the line 256b. Finally, a solder resist layer 258 is formed on the topmost wire layer 256, and the bonding pad 2 5 6a is exposed. . Among them, a plurality of contacts 270 ′ can also be arranged on the surface of the bonding pad 2 5 6a to connect external electronic devices, and The point 270 may be a solder ball or a pin, which is used to form a flip chip array (FC / BGA) or flip chip array (FC / PGA) chip package structure. As shown in FIG. 2F, the glass substrate 210 having a plurality of wafers 220 is singulated using a cutting machine to obtain a singulated wafer packaging structure 200. The number of wafers 220 is not limited to a single piece. Because of the wiring of the glass substrate The density is high, and the line width and line pitch (pi tch) of the lead layer can reach 1 · 5 microns', which is much smaller than the line width and line pitch of the lead layer of the organic substrate (about 25 microns). Therefore, multiple wafers 22 () can be arranged in a glass substrate 21, so they can be applied to wafer packages such as Multiple-Chip Modules (MCM) or systems in a single package (System In Package, SIP).

10035twf.ptd 第12頁 587317 五、發明說明（9) 裝結構。 第3圖繪示本發明之較佳實施例之一種晶片封裝結 構，其内連線層具有單層導線層的剖面示意圖。經過切單 之後之晶片封裝結構202主要包括一玻璃基板210、至少一 晶片220、一膠材層230、一支撐層240、多個第一導電插 塞250以及一内連線層260。其中，玻璃基板210具有一第 一表面212及對應之一第二表面214，而晶片220具有一主 動表面222及對應之一背面224，且晶片220更具有多個晶 片墊226，其分別配置於晶片220之主動表面222，且晶片 220係以主動表面222配置於玻璃基板210之第一表面212 , g 膠材層230係全面性覆蓋玻璃基板2 10之第一表面212，且 覆蓋晶片220之背面224，支撐層240係配置於膠材層230之 上’而第一導電插塞250係貫穿玻璃基板21〇 ,而分別電性 連接晶片220之晶片墊226。内連線層260係配置於玻璃基 板210之第二表面214，且内連線層26〇具有一導線層252 , 其電性連接至這些第一導電插塞25〇，並且内連線層26〇之 遠離玻璃基板210之一面具有多個接合墊託。。另外，抗 婷層258係配置於導線層252以及玻璃基板21〇上並暴露 出接合墊252a，而接點270 (例如銲球或針腳）則分別配 置於每一接合墊252a上。 · 緣示本發明之較佳實施例之一種晶片封裝結 内連線層具有多層導線層的剖面示意圖。經過切單 f ^晶片封裝結構2G4主要包括—玻璃基板21()、至少一 明片220、一膠材層230、-支撐層240、多個第一導電插10035twf.ptd Page 12 587317 V. Description of the invention (9) Installation structure. FIG. 3 is a schematic cross-sectional view of a chip packaging structure according to a preferred embodiment of the present invention, in which the interconnect layer has a single wire layer. After the singulation, the chip packaging structure 202 mainly includes a glass substrate 210, at least one wafer 220, an adhesive material layer 230, a support layer 240, a plurality of first conductive plugs 250, and an interconnect layer 260. The glass substrate 210 has a first surface 212 and a corresponding second surface 214, and the wafer 220 has an active surface 222 and a corresponding back surface 224, and the wafer 220 further has a plurality of wafer pads 226, which are respectively disposed on The active surface 222 of the wafer 220 is arranged on the first surface 212 of the glass substrate 210 with the active surface 222, and the g glue layer 230 comprehensively covers the first surface 212 of the glass substrate 210 and covers the first surface 212 of the glass substrate 210. The back surface 224, the support layer 240 is disposed on the adhesive material layer 230, and the first conductive plug 250 penetrates the glass substrate 210, and is electrically connected to the wafer pad 226 of the wafer 220, respectively. The interconnect layer 260 is disposed on the second surface 214 of the glass substrate 210, and the interconnect layer 26 has a wire layer 252, which is electrically connected to the first conductive plugs 25, and the interconnect layer 26 There is a plurality of bonding pads on one side of the surface away from the glass substrate 210. . In addition, the anti-tin layer 258 is disposed on the wire layer 252 and the glass substrate 21 and exposes the bonding pads 252a, and the contacts 270 (such as solder balls or pins) are respectively disposed on each bonding pad 252a. · A schematic cross-sectional view of a chip package junction in which the interconnecting layer has a plurality of wire layers in a preferred embodiment of the present invention. After singulation, the chip package structure 2G4 mainly includes—a glass substrate 21 (), at least one clear sheet 220, an adhesive material layer 230, a support layer 240, and a plurality of first conductive plugs.

587317 五、發明說明（ίο) 塞250以及一内連線層260。其中，玻璃基板210具有一第 一表面212及對應之一第二表面214，而晶片220具有一主 動表面222及對應之一背面224，且晶片220更具有多個晶 片墊226，其分別配置於晶片220之主動表面222，且晶片 220係以主動表面222配置於玻璃基板210之第一表面212， 膠材層230係全面性覆蓋玻璃基板21〇之第一表面212，且 覆蓋晶片220之背面224，支撐層240係配置於膠材層230之 上’而第一導電插塞2 5 0係貫穿玻璃基板2 1 0，而分別電性 連接晶片220之晶片墊226。内連線層260係配置於玻璃基 板2 10之第二表面214，且内連線層260具有多層導線層 252、256、至少一介電層254以及多個第二導電插塞251， 其中導線層252、256係依序配置於玻璃基板21〇之第二表 面212，且最接近玻璃基板21〇之導線層252係電性連接於 第一導電插塞250，而最遠離玻璃基板21〇之導線層256係 形成接合墊256a，且介電層254係配置二相鄰之導線層 252、256之間’而第二導線插塞251係貫穿介電層254，而 電性連接相鄰之導線層252、256。另外，抗銲層258係配 置於最遠離玻璃基板210之導線層256及介電層254上，並 暴露出接合墊256a，且接點270 (銲球或針腳）係分別配 置於每一接合墊256a上。 綜上所述，本發明之晶片封裝結構及其製程至少具有 下列優點： 1 ·本發明之晶片封裝結構及其製程，其中 包覆於膠材層之中’故晶片可得到最佳的保護 M7317 五、發明說明（11) 晶片受到濕氣影響或雜塵污染等。 2 ·本發明之晶片封裝結構及其製程，其中晶片之背面 具有=支撐層如強化玻璃或導熱板，其材質可為金屬或石 墨’進而提高整體晶片封裝結構之抗破壞性。 、3 ·本發明之晶片封裝結構及其製程，係利用玻璃基板 从及=線路層來提供高密度接點及微細導線層，用以封裝 具有咼密度晶片墊之晶片，以提高晶片封裝之性能。 、雖然本發明已以一較佳實施例揭露如上，然其並非用 以限=本發明，任何熟習此技藝者，在不脫離本發明之精 ，^範圍内’當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 μ587317 V. Description of the invention (plug) 250 and an interconnecting layer 260. The glass substrate 210 has a first surface 212 and a corresponding second surface 214, and the wafer 220 has an active surface 222 and a corresponding back surface 224, and the wafer 220 further has a plurality of wafer pads 226, which are respectively disposed on The active surface 222 of the wafer 220 is arranged on the first surface 212 of the glass substrate 210 with the active surface 222, and the adhesive layer 230 comprehensively covers the first surface 212 of the glass substrate 21 and covers the back surface of the wafer 220. 224, the support layer 240 is disposed on the adhesive material layer 230, and the first conductive plug 250 is penetrated through the glass substrate 210, and is electrically connected to the wafer pad 226 of the wafer 220, respectively. The interconnect layer 260 is disposed on the second surface 214 of the glass substrate 2 10, and the interconnect layer 260 has a plurality of conductive layers 252, 256, at least one dielectric layer 254, and a plurality of second conductive plugs 251. The layers 252 and 256 are sequentially disposed on the second surface 212 of the glass substrate 21o, and the conductive wire layer 252 closest to the glass substrate 21o is electrically connected to the first conductive plug 250, and is farthest from the glass substrate 21o. The wire layer 256 forms a bonding pad 256a, and the dielectric layer 254 is arranged between two adjacent wire layers 252 and 256. The second wire plug 251 penetrates the dielectric layer 254 and electrically connects the adjacent wires. Layers 252, 256. In addition, the solder resist layer 258 is disposed on the wire layer 256 and the dielectric layer 254 farthest from the glass substrate 210, and the bonding pad 256a is exposed, and the contact 270 (solder ball or pin) is disposed on each bonding pad separately. 256a. To sum up, the chip packaging structure and the manufacturing process of the present invention have at least the following advantages: 1 · The chip packaging structure and the manufacturing process of the present invention, wherein the wafer packaging structure and the manufacturing process are covered in a plastic layer, so the wafer can be optimally protected. M7317 V. Description of the invention (11) The wafer is affected by moisture or dust. 2 · The chip packaging structure and manufacturing process of the present invention, wherein the back surface of the chip has a support layer such as reinforced glass or a thermally conductive plate, and the material thereof can be metal or graphite ', thereby improving the destructive resistance of the overall chip packaging structure. 3 · The chip packaging structure and manufacturing process of the present invention use glass substrates and circuit layers to provide high-density contacts and fine wire layers for packaging wafers with a high-density wafer pad to improve the performance of chip packaging. . 2. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the essence of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. μ

10035twf.ptd 第15頁 587317 圖式簡單說明 第1圖繪示習知之一種覆晶球格陣列型之晶片封裝結 構的剖面示意圖； 第2 A〜2F圖依序繪示本發明之較佳實施例的一種晶片 封裝製程的剖面流程圖； 構 構 第3圖繪示本發明之較佳實施例之一種d 其内連線層具有單層導線層的剖面示意 第4圖繪示本發明之較佳實施例之一種d 其内連線層具有多層導線層的剖面示意 圖式之標示說明 100 :晶片封裝結構 110 ： :基板 112 : :頂面 114 ： :底面 116a :凸塊墊 116b :鲜球塾 118 導線層 120 凸塊 130 晶片 132 主動表面 134 背面 136 晶片塾 140 鲜球 150 底膠 200 、 202 、 204 :晶片 封裝結構 210 玻璃基板 210a :開口 212 第一表面 214 第二表面 220 晶片 222 主動表面 224 背面 226 晶片塾 230 膠材層 230a :黏著層 240 支撐層 250 、 _ 251 :第- 252 ’ • 256 :導線層 252a 、256a :去 〇10035twf.ptd Page 15 587317 Brief Description of Drawings Figure 1 shows a cross-sectional schematic diagram of a conventional flip-chip ball grid array chip package structure; Figures 2 A to 2F sequentially show the preferred embodiment of the present invention A cross-sectional flow chart of a chip packaging process; FIG. 3 shows a cross-sectional view of a preferred embodiment of the present invention. D The cross-sectional view of the interconnect layer having a single wire layer. FIG. 4 shows a preferred implementation of the present invention. An example of a type d is a schematic diagram of a cross-section diagram of a multilayer wiring layer in an interconnecting layer 100: chip package structure 110: substrate 112: top surface 114: bottom surface 116a: bump pad 116b: fresh ball 塾 118 wire Layer 120 bump 130 chip 132 active surface 134 back 136 chip 塾 140 fresh ball 150 primer 200, 202, 204: chip package structure 210 glass substrate 210a: opening 212 first surface 214 second surface 220 wafer 222 active surface 224 back 226 Wafer 塾 230 Adhesive material layer 230a: Adhesive layer 240 Support layer 250, _251: No. -252 '• 256: Wire layer 252a, 256a: Go.

10035twf.ptd 第16頁 587317 圖式簡單說明 258 :抗銲層 270 :銲球 252b、256b :導線 2 6 0 :内連線層 10035twf.ptd 第17頁10035twf.ptd page 16 587317 Brief description of the drawings 258: Solder resist 270: Solder balls 252b, 256b: Wire 2 6 0: Interconnect layer 10035twf.ptd Page 17

Claims (1)

587317 六、申請專利範圍 1. 一種晶片封裝製程 (a)提供一玻璃基板 表面及對應之一第二表面； (b )提供複數個晶片 至少包括下列步驟·· 其中該玻璃基板具有一第 其中該些晶片分別具有 二* /1 7j /j^\ 財L 一—幸 動表面及對應之一背面，且該也曰W # π θ 、 Η . ^ ^ a u ^ . 乂 一日日片更分別具有複數個晶 片墊’而该些明片墊係分別配置於其所對應之該些晶片之 -的該主動表®’且經由該些晶片之該主動表面而將該 些晶片配置於该玻璃基板之該第一表面； 〇 (C)全面性形成一膠材層於該玻璃基板之該第一表 面，且該膠材層覆蓋該晶片之該背面； (d) 配置一支撐層於該膠材層上； (e) 形成複數個第一導電插塞於該玻璃基板上，其 中該些第一導電插塞係分別連接於該些晶片之該些晶片 墊； (f)形成一内連線層於該玻璃基板之該第二表面， 其中該内連線層更具有複數個接合墊，其位於該内連線層 之遠離該玻璃基板的一面，且該内連線層之内部線路係電 性連接於該些導電插塞；以及 (g)早顆化該些晶片。587317 VI. Application for Patent Scope 1. A chip packaging process (a) providing a glass substrate surface and a corresponding second surface; (b) providing a plurality of wafers including at least the following steps ... wherein the glass substrate has a first These chips each have two * / 1 7j / j ^ \ L L a-Fortunately, the moving surface and the corresponding one of the back, and it should also be W # π θ, Η. ^ ^ Au ^. A plurality of wafer pads', and the wafer pads are respectively disposed on the active watch of the corresponding wafers-and the wafers are disposed on the glass substrate via the active surfaces of the wafers. The first surface; (C) forming an adhesive layer on the first surface of the glass substrate, and the adhesive layer covering the back surface of the wafer; (d) configuring a support layer on the adhesive layer (E) forming a plurality of first conductive plugs on the glass substrate, wherein the first conductive plugs are respectively connected to the wafer pads of the wafers; (f) forming an interconnect layer on the glass substrate; The second surface of the glass substrate, wherein the interconnect It further has a plurality of bonding pads, which are located on a side of the interconnect layer that is far from the glass substrate, and the internal circuits of the interconnect layer are electrically connected to the conductive plugs; and (g) the particles are formed early. These chips. 2 ·如申請專利範圍第1項所述之晶片封裝製程，其中 該膠材層之材質包括環氧樹脂。 3 ·如申請專利範圍第1項戶斤述之晶片封裝製程，其中 該支撐層之材質包括玻璃、金屬及石墨其中之一。 4 ·如申請專利範圍第1項户斤述之晶片封裝製程’於步2. The chip packaging process according to item 1 of the scope of patent application, wherein the material of the adhesive layer includes epoxy resin. 3. The chip packaging process described in item 1 of the patent application scope, wherein the material of the supporting layer includes one of glass, metal and graphite. 4 · The chip packaging process as described in the first patent application scope in the first step 10035twf.ptd 第18頁 58731710035twf.ptd Page 18 587317 更包括從該玻璃基板之該第二表面來薄化 驟（e )之前 該玻璃基板^ 牌Λ ΐΐ請ΐ利範圍第1項所述之晶片封裝製程，於步 驟（e)之時，包括先形成複數個 於該 後，再分別填入一導電材f &兮此μ σ $ Λ ;基板上之 第-導電插塞。 質於该些開之内，而形成該些 晶片封裝製程，其中 、姓刻穿孔以及超音 6.如申請專利範圍第5項所述之 形成δ亥些開口之方式係採用雷射燒孔 波成孔其中之"一。It also includes the step of thinning the glass substrate from the second surface of the glass substrate (e) before the step (e). The wafer packaging process described in item 1 of the scope is included. In step (e), After forming a plurality of them, a conductive material f & μ μ σ $ Λ; and a first conductive plug on the substrate are respectively filled. The quality is within these openings, and the chip packaging processes are formed. Among them, the last name is perforation and supersonic. 6. The method of forming delta openings as described in item 5 of the scope of patent application is to use laser burning hole waves. One of the holes " One. 7·如申請專利範圍第1項所述之晶片封裝製程，其中 該内連線層至少包括圖案化之_導線層’丨配置於該玻璃 基板之該第二表面，且電性連接於該些第一導 且該導線層係形成該些接合塾。 8·如申請專利範圍第7項所述之晶片封裝製程，其中 該導線層與該些第一導電插塞係同時形成。 9·如申請專利範圍第7項所述之晶片封裝製程，其中 該内連線層更具有一抗銲層，其配置於該内連線層之遠離 該玻璃基板的表面上，並暴露出該些接合墊。7. The chip packaging process as described in item 1 of the scope of the patent application, wherein the interconnect layer includes at least a patterned _conductor layer, which is disposed on the second surface of the glass substrate, and is electrically connected to the The first conductor and the wire layer form the bonding pads. 8. The chip packaging process according to item 7 of the scope of patent application, wherein the wire layer is formed simultaneously with the first conductive plugs. 9. The chip packaging process as described in item 7 of the scope of the patent application, wherein the interconnect layer further has a solder resist layer disposed on a surface of the interconnect layer away from the glass substrate and exposing the Some bonding pads. 10·如申請專利範圍第7項所述之晶片封裝製程，其 中該導線層之材質係選自於鋼、鋁、該等合金及該等之組 合所組成族群的一種材質。 11·如申請專利範圍第1項所述之晶片封裝製程，其 中該内連線層至少包括圖案化之複數個導線層、至少一介 電層及複數個第二導電插塞，其中該些導線層係依序配置10. The chip packaging process described in item 7 of the scope of the patent application, wherein the material of the wire layer is a material selected from the group consisting of steel, aluminum, the alloys, and combinations thereof. 11. The chip packaging process according to item 1 of the scope of the patent application, wherein the interconnect layer includes at least a patterned plurality of wire layers, at least one dielectric layer, and a plurality of second conductive plugs, wherein the wires Hierarchical configuration 587317 六、申請專利範圍 於該玻璃基板之該第二表面，且該些導線層之最接近該玻 璃基板者係電性連接於該些第一導電插塞，而該些導線層 之最遠離該些玻璃基板者係形成該些接合墊，且該介電層 係配置二相鄰之該些導線層之間，而該些第二導線插塞係 貫穿該介電層，而電性連接相鄰之該些導線層。 12·如申請專利範圍第1 1項所述之晶片封裝製程，其 中該些導線層之最接近該玻璃基板者與該些第一導電插塞 係同時形成。 13·如申請專利範圍第11項所述之晶片封裝製程，其 中該内連線層更具有一抗銲層，其配置於該導線層之最遠 離該玻璃基板者及該介電層，並暴露出該些接合墊。 14·如申請專利範圍第11項所述之晶片封裝製程，其 中該導線層之材質係選自於銅、鋁、該等合金及該等之組 合所組成族群的一種材質。 15·如申請專利範圍第11項所述之晶片封裝製程，其 中該介電層之材質係選自於由氧化矽及氮化矽所組成族群 的一種材質。 16·如申請專利範圍第1項所述之晶片封裝製程，於 步驟（f)之後，且於步驟（g)之前，更包括形成複數個 接點分別於該些接合墊之上。 17·如申請專利範圍第1 6項所述之晶片封裝製程，其 中該些接點係採用銲球或針腳其中之一。 、 18· 一種晶片封裝結構，至少包括： 一玻璃基板，具有一第一表面及對應之一第二表面；587317 6. The scope of the patent application is on the second surface of the glass substrate, and the conductor layers closest to the glass substrate are electrically connected to the first conductive plugs, and the conductor layers are farthest away from the Those glass substrates form the bonding pads, and the dielectric layer is disposed between two adjacent wire layers, and the second wire plugs penetrate the dielectric layer and are electrically connected to adjacent ones. The wire layers. 12. The chip packaging process as described in item 11 of the scope of patent application, wherein the conductor layers closest to the glass substrate are formed simultaneously with the first conductive plugs. 13. The chip packaging process as described in item 11 of the scope of patent application, wherein the interconnect layer further has a solder resist layer, which is disposed on the wire layer farthest from the glass substrate and the dielectric layer, and is exposed Remove the bonding pads. 14. The chip packaging process as described in item 11 of the scope of patent application, wherein the material of the wire layer is a material selected from the group consisting of copper, aluminum, these alloys, and combinations thereof. 15. The chip packaging process according to item 11 of the scope of the patent application, wherein the material of the dielectric layer is a material selected from the group consisting of silicon oxide and silicon nitride. 16. The chip packaging process described in item 1 of the scope of patent application, after step (f) and before step (g), it further includes forming a plurality of contacts on the bonding pads, respectively. 17. The chip packaging process according to item 16 of the scope of patent application, wherein the contacts are one of solder balls or pins. 18. A chip packaging structure, comprising at least: a glass substrate having a first surface and a corresponding second surface; 587317 六、申請專利範圍 至少一晶片’具有一主動表面及對應之一背面，且該 晶片更具有複數個晶片墊，其分別配置於該晶片之該主動 表面’且該晶片係以該主動表面配置於該玻璃基板之該第 一表面； 一膠材層’全面性覆蓋該玻璃基板之該第一表面，且 覆蓋該晶片之該背面； 一支撐層，配置於該膠材層之上； 複數個第一導電插塞，貫穿該玻璃基板，而分別電性 連接該晶片之該些晶片墊；以及 一内連線層’配置於該玻璃基板之該第二表面，並具 有複數個接合墊’其位於該内連線層之遠離該玻璃基板的 一面’且該内連線層之内部線路係電性連接至該些第一導 電插塞。 1 9 ·如申請專利範圍第1 8項所述之晶片封裝結構，其 中該膠材層之材質包括環氧樹脂。 20·如申請專利範圍第18項所述之晶片封裝結構，其 中該支樓層之材質包括玻璃、金屬及石墨其中之一。 21·如申請專利範圍第18項所述之晶片封裝結構，其 中該内連線層至少包括圖案化之一導線層，其配置於該玻 璃基板之該第二表面，且電性連接於該些第一導電插塞，〇 並且該導線層係形成該些接合墊。 22·如申請專利範圍第21項所述之晶片封裝結構，其 中該導線層與該些第一導電插塞同時形成。 23·如申請專利範圍第以項所述之晶片封襞結構，其587317 VI. Patent application scope At least one wafer 'has an active surface and a corresponding back surface, and the wafer further has a plurality of wafer pads, which are respectively arranged on the active surface of the wafer' and the wafer is configured with the active surface On the first surface of the glass substrate; an adhesive material layer 'comprehensively covers the first surface of the glass substrate and covers the back surface of the wafer; a support layer disposed on the adhesive material layer; a plurality of A first conductive plug penetrates the glass substrate and is electrically connected to the wafer pads of the wafer, respectively; and an interconnect line layer is disposed on the second surface of the glass substrate and has a plurality of bonding pads. The side of the interconnecting layer that is far from the glass substrate and the internal wiring of the interconnecting layer are electrically connected to the first conductive plugs. 19 · The chip packaging structure described in item 18 of the scope of patent application, wherein the material of the adhesive layer includes epoxy resin. 20. The chip packaging structure as described in item 18 of the scope of patent application, wherein the material of the branch floor includes one of glass, metal and graphite. 21. The chip package structure according to item 18 of the scope of the patent application, wherein the interconnect layer includes at least one patterned wire layer, which is disposed on the second surface of the glass substrate and is electrically connected to the The first conductive plug is 0, and the wire layer forms the bonding pads. 22. The chip package structure according to item 21 of the scope of patent application, wherein the wire layer is formed simultaneously with the first conductive plugs. 23. The wafer sealing structure described in item 1 of the scope of patent application, which 第21頁 587317 六、申請專利範圍 中該内連線層更具有一抗銲層，其配置於該内連線層之最 遠離該玻璃基板的表面，並暴露出該些接合塾。 24. 如申請專利範圍第2 1項所述之晶片封裝結構’其 中該導線層之材質係選自於銅、鋁、該等合金及該等之組 合所組成族群的一種材質。 25. 如申請專利範圍第1 8項所述之晶片封裝結構，其 中該内連線層至少包括圖案化之複數個導線層、至少一介 電層及複數個第二導電插塞，其中該些導線層係依序配置 於該玻璃基板之該第二表面，且該呰導線層之最接近該玻 璃基板者係電性連接於該些第一導電插塞，而該些導線層| 之最遠離該些玻璃基板者係形成該些接合塾’且該介電層 係配置二相鄰之該些導線層之間，而該些第二導線插塞係 貫穿該介電層，而電性連接相鄰之該些導線層。 26·如申請專利範圍第25項所述之晶片封裝結構.，其 中該些導線層之最接近該玻璃基板者與該些第一導電插塞 係同時形成。 27·如申請專利範圍第25項所述之晶片封裝結構，更 包括一抗銲層，其配置於該内連線層之最遠離該玻璃基板 的表面’並暴露出該些接合墊。 2 8 ·如申請專利範圍第2 5項所述之晶片封裝結構，其 中該導線層之材質係選自於銅、鋁、該等合金及該等之組 合所組成族群的一種材質。 2 ·如申請專利範圍第2 5項所述之晶片封裝結構，其 中5亥；1電層之材質係選自於由氧化矽及氮化矽所組成族群Page 21 587317 6. In the scope of the patent application, the interconnecting layer further has a solder resist layer, which is arranged on the surface of the interconnecting layer farthest from the glass substrate, and exposes the bonding pads. 24. The chip package structure described in item 21 of the scope of the patent application, wherein the material of the wire layer is a material selected from the group consisting of copper, aluminum, these alloys, and combinations thereof. 25. The chip package structure described in item 18 of the scope of the patent application, wherein the interconnect layer includes at least a plurality of patterned wire layers, at least one dielectric layer, and a plurality of second conductive plugs, wherein The wire layers are sequentially arranged on the second surface of the glass substrate, and the closest to the glass substrate of the 呰 wire layer is electrically connected to the first conductive plugs, and the wire layers are farthest away The glass substrates form the junctions, and the dielectric layer is disposed between two adjacent wire layers, and the second wire plugs penetrate the dielectric layer, and electrically connect the phases. Adjacent to these wire layers. 26. The chip package structure according to item 25 of the scope of the patent application, wherein the conductor layers closest to the glass substrate are formed simultaneously with the first conductive plugs. 27. The chip package structure described in item 25 of the scope of patent application, further comprising a solder resist layer disposed on the surface of the interconnect layer that is furthest from the glass substrate 'and exposing the bonding pads. 2 8 · The chip package structure described in item 25 of the scope of patent application, wherein the material of the wire layer is a material selected from the group consisting of copper, aluminum, these alloys, and combinations thereof. 2 · The chip package structure described in item 25 of the scope of the patent application, in which the 50 Ohm; 1 The material of the electrical layer is selected from the group consisting of silicon oxide and silicon nitride 第22頁 587317 六、申請專利範圍 的一種材質。 30. 如申請專利範圍第1 8項所述之晶片封裝結構，更 包括複數個接點，其分別配置於該些接合墊之上。 31. 如申請專利範圍第1 8項所述之晶片封裝結構，其 中該些接點係為銲球或針腳其中之一。 I 4Page 22 587317 VI. A material for patent application. 30. The chip package structure described in item 18 of the scope of patent application, further includes a plurality of contacts, which are respectively disposed on the bonding pads. 31. The chip package structure described in item 18 of the scope of the patent application, wherein the contacts are one of solder balls or pins. I 4 10035twf.ptd 第23頁10035twf.ptd Page 23
TW091137813A 2002-12-30 2002-12-30 Construction and manufacturing of a chip package TW587317B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW091137813A TW587317B (en) 2002-12-30 2002-12-30 Construction and manufacturing of a chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091137813A TW587317B (en) 2002-12-30 2002-12-30 Construction and manufacturing of a chip package

Publications (2)

Publication Number Publication Date
TW587317B true TW587317B (en) 2004-05-11
TW200411862A TW200411862A (en) 2004-07-01

Family

ID=34058095

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091137813A TW587317B (en) 2002-12-30 2002-12-30 Construction and manufacturing of a chip package

Country Status (1)

Country Link
TW (1) TW587317B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI596678B (en) * 2016-03-08 2017-08-21 南茂科技股份有限公司 Semiconductor package structure and manufacturing method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI824414B (en) * 2022-02-16 2023-12-01 矽品精密工業股份有限公司 Electronic package and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI596678B (en) * 2016-03-08 2017-08-21 南茂科技股份有限公司 Semiconductor package structure and manufacturing method thereof

Also Published As

Publication number Publication date
TW200411862A (en) 2004-07-01

Similar Documents

Publication Publication Date Title
US7847415B2 (en) Method for manufacturing a multichip module assembly
TWI229890B (en) Semiconductor device and method of manufacturing same
JP4594934B2 (en) Integrated electronic chip and interconnect device, and method for manufacturing the same
US7361972B2 (en) Chip packaging structure for improving reliability
TWI335658B (en) Stacked structure of chips and wafer structure for making same
US20090294947A1 (en) Chip package structure and manufacturing method thereof
TWI595613B (en) Semiconductor package and fabrication method thereof
TW200826265A (en) Semiconductor package assembly and silicon-based package substrate
JP2006319243A (en) Memory module and its manufacturing method
KR20020043188A (en) Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same
TW200931628A (en) Stacking die package structure for semiconductor devices and method of the same
TW200816435A (en) Semiconductor device and method of manufacturing the same
TW200818439A (en) Stacked structures and methods of forming the same
JP2007180529A (en) Semiconductor device and method of manufacturing the same
US20100140801A1 (en) Device
JP2004048048A (en) Semiconductor device and method of manufacturing the same
US20070267738A1 (en) Stack-type semiconductor device having cooling path on its bottom surface
TW200527557A (en) Semiconductor package and method for manufacturing the same
JPWO2008087701A1 (en) Three-dimensional semiconductor integrated circuit device and manufacturing method thereof
TW200901396A (en) Semiconductor device package having chips
TW202230711A (en) Semiconductor package
JP2005005632A (en) Chip-like electronic component, its manufacturing method, and its packaging structure
JP2007142026A (en) Interposer and method of manufacturing same, and semiconductor device
TW587317B (en) Construction and manufacturing of a chip package
TW200536074A (en) Chip package structure and process for fabricating the same

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent