TW584951B

TW584951B - Decoupling capacitor circuit with dynamic control

Info

Publication number: TW584951B
Application number: TW92109808A
Authority: TW
Inventors: Wen-Tai Wang; Chang-Fen Hu
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2003-04-25
Filing date: 2003-04-25
Publication date: 2004-04-21
Also published as: TW200423366A

Abstract

The present invention provides a decoupling capacitor circuit with dynamical control. This circuit comprises a transistor switch that may cut off the decoupling capacitor circuit in accordance with the usage situation to reduce the gate leakage current.

Description

584951584951

- __ 一五、發明說明（1) 【發明所屬之技術領威】本發明是有關於一種電去耦合電容電路結構，且特別是有關於一種可動態調整之去耦合電容電路結構。【先前技術】由於半導體技術的快速發展’在一很小的面積上常常是由數百個以上的電晶體以及電容器來組成整合電路。這4b元件最基本的組成如：MOS電晶體’透過這些MOS電晶體來护^ 制閘極動作，組成一系列的邏輯訊號等。 " 傳統上，當外加電壓低於1伏後，於整合電路之周邊會需要一些去耦合電容（decoupling capacitor )電路用以抑制雜訊，其傳統電路架構如第一A圖與第一B圖所示，於外加高電壓（VDD )與低電壓（VSS )間，利用源極與集極相連接之PM0S電晶體101或NM0S電晶體102串接電阻100來形成去耦合電容電路。或是如第一c圖所示，使用耦接之PM〇s電晶體103與NM0S電晶體1〇4形成。然而，隨著製程的精進，元件的要求也跟著變窄，尤其當製晶體之閘極氧化層亦隨之變薄並使得去耦合電容電路用以抑一方面，積體電路上漏電流的源’造成線路負載過重，使得密集度也越來越增加，線寬程進步到0· 13微米後，M0S電 ’造成閘極漏電流之產生，制雜訊之功能大為降低。另情形將會耗去大部分的電元件的驅動電壓將不足，元-__ V. Explanation of the invention (1) [Technical power to which the invention belongs] The present invention relates to an electric decoupling capacitor circuit structure, and particularly to a dynamically adjustable decoupling capacitor circuit structure. [Previous Technology] Due to the rapid development of semiconductor technology, an integrated circuit is often composed of hundreds of transistors and capacitors on a small area. The most basic components of this 4b element are as follows: MOS transistors' protect gate action through these MOS transistors and form a series of logic signals. " Traditionally, when the applied voltage is lower than 1 volt, some decoupling capacitor circuits are needed around the integrated circuit to suppress noise. The traditional circuit architecture is as shown in Figures A and B. As shown, a decoupling capacitor circuit is formed between a high-voltage (VDD) and a low-voltage (VSS) by using a PM0S transistor 101 or an NMOS transistor 102 with a source and a collector connected in series with a resistor 100. Alternatively, as shown in FIG. 1c, a PMMOS transistor 103 and a NMOS transistor 104 are coupled to each other. However, with the advancement of the process, the requirements for components have become narrower, especially when the gate oxide layer of the crystal is thinned and the decoupling capacitor circuit is used to suppress the source of leakage current on the integrated circuit. 'As a result of the overload of the line, the density has also increased. After the line width has been increased to 0.13 micrometers, the M0S voltage has caused the gate leakage current and greatly reduced the noise suppression function. In other cases, the driving voltage of most of the electrical components will be insufficient.

第4頁 584951 五、發明說明（2) 件無法正常運作發明内容】本發明能抑制本發明此架構本發明容電路本發明體開關區塊運生漏電電流，耗，並的主要目漏電流之的另一目可根據整的再一目架構，藉較佳實施元件，其作情形，流亦僅有遠小於電提高隔離的就是在提供產生。的就是在提供合電路之工作的就是在提供以降低電源之例之去耦合電中此開關元件而動態截斷去電晶體開關之容元件之閘極雜訊效能。一種去耦合電容電路架構，一種去耦合電容電路架構，狀態進行動態調整。一種可動態調整之去耦合電消耗。谷電路架構至少包括一曰电曰曰可根據對應之整合電路功能耦合電容電路，因此即使2 源極與集極和通道戴止之漏漏電流，因此可降電源消【實施方式】在不限制本發明之精例，介紹本發明之實明之精神後，當可應種不同之整合電路中可根據整合電路之工神及應用範圍之下施；熟悉此領域技用本發明之去輕合。其中本發明之去作狀態進行動態調 ’以下即以一實施藝者，在瞭解本發電容電路架構於各耦合電容電路架構整以抑制漏電流之Page 4 584951 V. Description of the invention (2) The item does not work normally. Summary of content] The present invention can suppress the leakage current, current consumption, and main leakage current of the body switch block of the present invention. The other project can be based on the structure of the whole project, and with better implementation components, its operation situation, the flow is only much smaller than the electrical improvement isolation is generated. The purpose is to provide the switching circuit. The purpose is to provide the switching element in the decoupling circuit to reduce the power supply, for example, to dynamically cut off the gate noise performance of the capacitive element of the transistor switch. A decoupling capacitor circuit architecture, a decoupling capacitor circuit architecture, and the state is dynamically adjusted. A type of decoupling power consumption that can be dynamically adjusted. The valley circuit architecture includes at least one electrical circuit, which can be coupled to the capacitor circuit according to the corresponding integrated circuit function. Therefore, even if the source and collector and the channel and the leakage current of the channel are stopped, the power consumption can be reduced. The precise example of the present invention, after introducing the practical spirit of the present invention, can be applied in different integrated circuits according to the working spirit and application scope of the integrated circuit; familiar with the technology of the field to use the invention. Among them, the working state of the present invention is dynamically adjusted. The following is an implementation artist who understands the capacitor circuit architecture in the coupling capacitor circuit architecture to reduce the leakage current.

584951 五，發明說明（3) f生，並降低電源之消耗。參閱第二A Μ _ 構 —w所示為本發明較佳實施例之去耦合電容電路架本發明’之本:構明利用一電晶體開關，取代傳統之電阻。根據之去巍:一ί容元件201串接一電晶體開關202形成本發明源極與路架構，其中本發明之電容元件201可使用 f曰_ pW。連接之PM〇S電晶體或·05電晶體來形成，而電:體開關202可為一 M0S電晶體。 ΐΐ參？第二A圖所示’電晶體開關2°2之間極引出-控制體開關202之導通或切斷，當本 f日日導通之狀況時，其功能就有如V，曰體開關202處於示。八力月匕就有如—電阻203，如第二B圖所 =二A圖’當電晶體開關2〇2處其可此產生之電流僅為電晶體呵炙狀况時，截止下之漏電流，此漏構下電容元件產生之閘極漏電流於傳，、先去麵合電容電路架根據上述說明，本發明電晶體開線路，可根據積體電路之使用壯 3極所5丨出之控制導通或切斷。一般而言，於整個馨2控制電晶體開關202之個功能區塊’而每一個功能區塊會；：：： =常會包括數路來隔離外界之雜訊，當整合電去耦合電容電區塊均會動作。換句話說，當未=作時，並非所有功能統之去耦合電容電路來隔離外之=能區若是使用傳 1雜訊’由於閘極漏電流之 584951 五、發明說明（4) - 關係，仍繼續消耗電源，反之，本發明之電路架構，當所連接之功能區塊未動作時，其會送出一控制信號，將本發明去耦合電容電路架構20 0之電晶體開關202切斷，亦即: 此時去耦合電容電路架構20 0所可能產生之漏電流，僅為電晶體開關2 0 2之源極與集極和通道間逆偏下之漏電流，^小於電容元件之閘極漏電流，因此可降電源消耗，同時提$高降低雜訊效能。 n584951 V. Description of the invention (3) F production and reduce power consumption. Referring to the second AM structure, w shows a decoupling capacitor circuit frame according to a preferred embodiment of the present invention. The present invention's structure: the use of a transistor switch to replace a conventional resistor. According to it: a capacitor element 201 is connected in series with a transistor switch 202 to form the source and circuit structure of the present invention, wherein the capacitor element 201 of the present invention can use f _ pW. The connected PMOS transistor or .05 transistor is formed, and the electric body switch 202 may be a MOS transistor. Pompano? As shown in the second figure A, the pole switch between 2 ° 2 and the control body switch 202 is turned on or off. When it is turned on every day, its function is like V, and the body switch 202 is shown. . The eight force moon dagger is like-the resistance 203, as shown in the second diagram B = two diagram A 'When the transistor switch 202 can generate only the current of the transistor, the leakage current at the cutoff In this drain structure, the gate leakage current generated by the capacitive element is passed. First, the capacitor circuit frame is first connected. According to the above description, the transistor of the present invention can be opened according to the use of integrated circuits. Control on or off. Generally speaking, the entire functional block of the transistor switch 202 is controlled throughout Xin2, and each functional block will ::: = will often include several channels to isolate external noise, when integrated electrical decoupling capacitor electrical area The blocks will all move. In other words, when it is not working, not all functions are decoupling capacitor circuits to isolate the external = energy range. If it is used to pass 1 noise 'because of gate leakage current 584951 V. Description of the invention (4)-relationship, It still consumes power. On the contrary, the circuit structure of the present invention sends a control signal when the connected functional block is not activated, and cuts off the transistor switch 202 of the decoupling capacitor circuit structure 200 of the present invention. That is: the leakage current that may be generated by the decoupling capacitor circuit architecture 200 at this time is only the leakage current under the reverse bias between the source and collector and the channel of the transistor switch 202, which is less than the gate leakage of the capacitor element. Current, so it can reduce power consumption and increase noise at the same time. n

以第一A圖之較佳實施例而言，使用源極與集極相連接之 PMOS電晶體作為本發明電容元件2〇1，其中PM〇s電晶體之通道長度約為2um，而通道寬度約為2 X i〇5um，其電容大小約為3· 6nF，此時閘極漏電流約為91lUA。一NM〇s電晶體作為本發明電晶體開關2 0 2，採用NMOS係因為其電子之飄移速度大於PMOS電晶體，因此使用NM0S電晶體可有較快之切換速" 度’然值得注意的是本發明之電路結構亦可使用pM〇s電晶體控制，而所選用之NMOS電晶體通道長度約為〇. 26um，而通道寬度約為105um，此時源極與集極和通道截止下之漏電流約為7uA。一般而言，本發明之電晶體開關設計，通常採用較長之通道設計，藉以降低漏電流。Taking the preferred embodiment of FIG. 1A as an example, a PMOS transistor with a source and a collector connected is used as the capacitor element 201 of the present invention. The channel length of the PMMOS transistor is about 2um, and the channel width It is about 2 X 〇5um, and its capacitance is about 3.6nF. At this time, the gate leakage current is about 91lUA. An NMOS transistor is used as the transistor switch 202 of the present invention. NMOS is used because its electron drift speed is faster than PMOS transistor. Therefore, using NMOS transistor can have a faster switching speed. The circuit structure of the present invention can also be controlled by using pMOS transistor, and the selected NMOS transistor channel length is about 0.26um, and the channel width is about 105um. At this time, the source and collector and the channel are cut off. The leakage current is about 7uA. Generally speaking, the transistor switch design of the present invention usually adopts a longer channel design to reduce leakage current.

參閱第三圖所示，為將本發明之電路架構應用於一雙電晶體之去搞合電容電路300中。其中nm〇S電晶體301與PMOS電晶體302可接收一控制信號以切斷去柄合電容電路3〇〇導通。例如當去搞合電容電路3〇〇所連接之整合電路未動作時’此時會送出一控制信號將電晶體3 〇 1與電晶體3 〇 2導通，以將高電壓信號（VDD )與低電壓信號（vss )分別傳Referring to the third figure, in order to apply the circuit architecture of the present invention to a capacitor circuit 300 for an electric double crystal. Among them, the nmOS transistor 301 and the PMOS transistor 302 can receive a control signal to cut off the decoupling capacitor circuit 300. For example, when the integrated circuit connected to the capacitor circuit 300 is not activated, a control signal will be sent at this time to turn on the transistor 3 〇1 and the transistor 3 〇2 to connect the high-voltage signal (VDD) to low. The voltage signal (vss) is transmitted separately

第頁Page

584951 五、發明說明（5) 遞給PMOS電晶體303與題⑽電晶體3 晶體。閘極來截斷此兩電由於本發明之去耦合電容電路架構可話說當對應之整人雷政# Ab p^订動恶控制，換句 i 口冤路功能區塊未進行 ^ ^ 斷去耦合電容電路，因此即使產；；：：，可動悲截之閘極漏電流，因此可降電：消Ά時；1:電容元：能。 U時提南降低雜訊效雖然本發明已以—/4. ^ 定本發明，钮h較佳實揭路如J"，然其並非用以限疋不知月，任何熟習此技藝者，範圍内，當可作爭叙獻Μ ^不脫離本發明之精神和圍·視德附_，因此本發明之保護範圍田視後附之申請專利範圍所界定 584951584951 V. Description of the invention (5) Pass to PMOS transistor 303 and title transistor 3 crystal. The gates are used to cut off the two power sources. Because of the decoupling capacitor circuit architecture of the present invention, it can be said that when the corresponding person is Lei Zheng # Ab p ^ subscribe to evil control, in other words, the functional block of the wrong way is not performed ^ ^ Decoupling Capacitor circuit, so even if it is produced; ::, movable and tragic gate leakage current, so it can reduce power: when dying out; 1: capacitor element: Yes. U Titinan reduces the noise effect. Although the present invention has been settled with-/ 4. ^, The button h is better to reveal the road like J ", but it is not used to limit the unknown months, anyone who is familiar with this skill, within the scope It can be argued that it does not depart from the spirit and scope of the present invention, and is attached to the German patent. Therefore, the scope of protection of the present invention is defined by the scope of the patent application attached to Tianshi 584951.

圖式簡單說明【圖式簡單說明】為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：第一A圖至第一C圖所示為傳統之去耦合電容電路。第二A圖繪示根據本發明第一較佳實施例之去耦合電容電路概略圖。第二B圖繪示根據本發明第一較佳施例之去耦合電容電路你對等電路圖。第三圖繪示根據本發明之第二較佳實施例之去耦合電容電路概略圖。【元件代表符號簡單說明】 100和203電阻 1 0 1和20 1源極與集極相連接pM〇s電晶體 102源極與集極相連接NM〇s電晶體 103、 303 和302 PMOS 電晶體 104、 202、301 和304 NMOS 電晶體 200和300去耦合電容電路Brief Description of the Drawings [Simplified Description of the Drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows : Figures A through C show the traditional decoupling capacitor circuits. FIG. 2A is a schematic diagram of a decoupling capacitor circuit according to the first preferred embodiment of the present invention. The second diagram B shows a circuit diagram of a decoupling capacitor circuit according to the first preferred embodiment of the present invention. The third figure shows a schematic diagram of a decoupling capacitor circuit according to a second preferred embodiment of the present invention. [A brief description of the symbols of the components] 100 and 203 resistors 1 0 1 and 20 1 The source is connected to the collector pM0s transistor 102 The source is connected to the collector NM0s transistor 103, 303 and 302 PMOS transistor 104, 202, 301, and 304 NMOS transistors 200 and 300 decoupling capacitor circuits

Claims

584951 六、申請專利範圍 1· 一種可動態調整之去耦合電容電路’連接於一整合電路用以隔離外來雜訊影響該整合電路，該電路至少包含：一電容，耦接於第一電魘源；以及一開關元件，轉接於該電容’而該電容可經由該開關元件轉接於第二電壓源。 2 ·如申請專利範圍第1項所述之可動態調整之去耦合電容電路，其中該第一電壓源為一高電壓源，而該第二電壓源為一低電壓源。 Q •如申請專利範圍第1項所述之可動態調整之去耦合電容電路’其中該第一電壓源為一低電壓源，而該第二電壓源為一高電壓源。 4路如申請專利範圍第1項所述之可動態調整之去耦合電容電 ’其中該電容為一源極與集極相連接pM〇s電晶體。 5路如Πί利範圍第1項所述之可動態調整之去耦合電容電 ’、I電容為一源極與集極相連接NMOS電晶體。 6·如申請專利範圍第丨項所路，其中該開關元件為一電晶體了動癌、调整之去搞合電容電 584951 六、申請專利範圍 7. 如申請專利範圍第1項所述之可動態調整之去耦合電容電路，其中該開關元件與該電容串連。 8. 如申請專利範圍第1項所述之可動態調整之去耦合電容電路，其中當該連接之整合電路未運作時，該開關元件會切斷該電容與該第二電壓源之連接。 9. 一種可動態調整之去耦合電容電路，連接於一整合電路用以隔離外來雜訊影響該整合電路，該電路至少包含：一電容元件，耦接於一第一電壓源與第二電壓源；以及第一與第二個開關元件，分別耦接於該電容元件，其中該電容元件可透過該第一開關元件耦接於該第一電壓源，並透過該第二開關元件耦接於該第二電壓源。 1 0.如申請專利範圍第9項所述之可動態調整之去耦合電容電路，其中該第一電壓源為一高電壓源，而該第二電壓源為一低電壓源。 11.如申請專利範圍第9項所述之可動態調整之去耦合電容電路，其中該第一電壓源為一低電壓源，而該第二電壓源為一高電壓源。 1 2.如申請專利範圍第9項所述之可動態調整之去耦合電容電路，其中該電容元件係由複數個電晶體組成。584951 6. Scope of patent application 1. A dynamically adjustable decoupling capacitor circuit is connected to an integrated circuit to isolate external noise from affecting the integrated circuit. The circuit includes at least: a capacitor coupled to a first power source And a switching element connected to the capacitor 'and the capacitor can be connected to the second voltage source through the switching element. 2. The dynamically adjustable decoupling capacitor circuit according to item 1 of the scope of the patent application, wherein the first voltage source is a high voltage source and the second voltage source is a low voltage source. Q • The dynamically adjustable decoupling capacitor circuit described in item 1 of the scope of the patent application, wherein the first voltage source is a low voltage source and the second voltage source is a high voltage source. The 4-way dynamically adjustable decoupling capacitor as described in item 1 of the scope of patent application, wherein the capacitor is a pM0s transistor with a source and a collector connected. The five-way dynamically adjustable decoupling capacitor as described in the first item of the 范围 Li range, I capacitor is a NMOS transistor with a source and a collector connected. 6 · As described in item 丨 of the scope of patent application, in which the switching element is a transistor to move the cancer, adjust it to engage the capacitor 584951 6. Application for patent scope 7. As described in item 1 of the scope of patent application A dynamically adjusted decoupling capacitor circuit, wherein the switching element is connected in series with the capacitor. 8. The dynamically adjustable decoupling capacitor circuit as described in item 1 of the patent application scope, wherein when the connected integrated circuit is not operating, the switching element cuts off the connection between the capacitor and the second voltage source. 9. A dynamically adjustable decoupling capacitor circuit, connected to an integrated circuit to isolate external noise from affecting the integrated circuit, the circuit at least includes: a capacitive element coupled to a first voltage source and a second voltage source And first and second switching elements are respectively coupled to the capacitive element, wherein the capacitive element can be coupled to the first voltage source through the first switching element and coupled to the first voltage source through the second switching element Second voltage source. 10. The dynamically adjustable decoupling capacitor circuit according to item 9 of the scope of the patent application, wherein the first voltage source is a high voltage source and the second voltage source is a low voltage source. 11. The dynamically adjustable decoupling capacitor circuit according to item 9 of the scope of the patent application, wherein the first voltage source is a low voltage source and the second voltage source is a high voltage source. 1 2. The dynamically adjustable decoupling capacitor circuit as described in item 9 of the scope of the patent application, wherein the capacitor element is composed of a plurality of transistors.

第11頁 584951 六、申請專利範圍 3 路專請中如亥士0> 中其容合耦去之整調。態體動晶可電之I 述為所件項元 9關第1 開圍一 II第 14·如申請專利範圍第9項所述之可動態調整之去耦合電容電路，其中該第二開關元件為一電晶體。 1 5·如申請專利範圍第9項所述之可動態調整之去耦合電容，路，其中當該連接之整合電路未運作時，該第一開關元件會切斷該電容元件與第/電壓源之連接。 16·如申請專利範圍第9項所述之可動態調整之去耦合電容 f路，其中當該連接之整合電路未運作時，該第二開關元件會切斷該電容元件與第二電壓源之連接。 17·種動良、調整去輕合電容電路方法，其中該去搞合電容電路/、整口電路連接以隔離外來雜訊影響該整合電路，該去耦合電容電路$ ,丨、a & ^ ^ t ，吟至 > 包含一電容元件血一開關7G件，而該電容元件可經由哕„ M 4 Μ /、「 _ /h β 田这開關兀件耦接於一電壓源，該方法至 ^包3 · 產生一控制訊號並值& 運作後；以及傳适給該開關元件，當該整合電路停止控制訊號控制該開關^ μ 1關疋件切斷該電容元件與該電壓源之連Page 11 584951 VI. Scope of patent application Three channels are specially requested for adjustments such as the capacity and coupling in the Haishi 0 >. The state I of the dynamic body can be described as 9 items of the first element, 1st of the opening, II, 14th, and a dynamically adjustable decoupling capacitor circuit as described in item 9 of the patent application scope, wherein the second switching element It is a transistor. 15. The dynamically adjustable decoupling capacitor as described in item 9 of the scope of patent application, wherein when the connected integrated circuit is not operating, the first switching element will cut off the capacitor element and the voltage source Of connection. 16. The dynamically adjustable decoupling capacitor f as described in item 9 of the scope of the patent application, wherein when the connected integrated circuit is not operating, the second switching element will cut off the capacitance element and the second voltage source. connection. 17. A good method for adjusting and closing a light-capped capacitor circuit, wherein the capacitor circuit / and the entire circuit are connected to isolate external noise from affecting the integrated circuit. The decoupling capacitor circuit $, 丨, a & ^ ^ t, yin > Contains a capacitor element blood 7G switch, and the capacitor element can be coupled to a voltage source via the switch element 哕 M 4 Μ /, _ / h β field, the method to ^ Pack 3 · Generate a control signal and value & after operation; and pass it to the switching element, when the integrated circuit stops controlling the signal to control the switch ^ μ 1 The switch shuts off the connection between the capacitive element and the voltage source

第12頁 584951 六、申請專利範圍 18·如申請專利範圍第I?項所述之動態調整去麵合電容電路方法，其中該電壓源為一高電麼源。 19.如申請專利範圍第17項所述之動態調整去柄合電容電路方法，其中該電壓源為一低電壓源。 20·如申請專利範圍第17項所述之動態調整去耦合電容電路方法，其中該電容元件為〆源極與集極相連接P Μ 0 S電晶 21·如申請專利範圍第項所述之動態調整去耦合電容電路方法，其中該電容元件為ζ源極與集極相連接NMOS電晶體。 2 2 ·如申請專利範圍第丨7項所述之動態調整去耦合電容電路方法，其中該電容元件係由複數個電晶體組成。 2 3.如申請專利範圍第17項所述之動態調整去耦合電容電路方法’其中該開關元件為一電晶體。 24·如申請專利範圍第17項所述之動態調整去耦合電容電路方法，其中該開關元件與該電容元件串連。Page 12 584951 VI. Scope of patent application 18. The method for dynamically adjusting a capacitor circuit as described in item I of the scope of patent application, wherein the voltage source is a high-power source. 19. The method for dynamically adjusting a decoupling capacitor circuit according to item 17 of the scope of patent application, wherein the voltage source is a low voltage source. 20 · The method for dynamically adjusting a decoupling capacitor circuit as described in item 17 of the scope of the patent application, wherein the capacitor element is a 〆 source and collector connected P Μ 0 S transistor 21 · as described in the scope of the patent application A method for dynamically adjusting a decoupling capacitor circuit, wherein the capacitor element is a NMOS transistor with a zeta source connected to a collector. 2 2 · The method for dynamically adjusting a decoupling capacitor circuit according to item 7 of the patent application scope, wherein the capacitor element is composed of a plurality of transistors. 2 3. The method for dynamically adjusting a decoupling capacitor circuit according to item 17 of the scope of the patent application, wherein the switching element is a transistor. 24. The method for dynamically adjusting a decoupling capacitor circuit according to item 17 of the scope of the patent application, wherein the switching element is connected in series with the capacitor element.