584903 A7 --SL____ 一— 五、發明說明（\ ) 發明領域 本發明係關於一半導體裝置，更具體而言，係關於具有 低差排密度（dislocation density)磊晶成長的一發光半導 體裝置。 發明背景 以氮化銘銦鎵(AlInGaN)爲基底之化合物半導體，是常 用於生產如藍綠色發光二極體、以及雷射二極體等發光半 導體裝置的材料。這些材料通常係成長於氧化鋁(Al2〇3)或 者碳化矽（SiC)等基板上。 由於晶格常數的差異，半導體材料很難直接成長於基 板上。舉例來說，氮化鎵結晶層（a=3.189人）很難成長在 氧化鋁（a=4.758 A)基板上，因爲他們的晶格常數差異超 過 16% 〇584903 A7 --SL ____ I. V. Description of the Invention (\) Field of the Invention The present invention relates to a semiconductor device, and more specifically, to a light-emitting semiconductor device having epitaxial growth with low dislocation density. BACKGROUND OF THE INVENTION Compound semiconductors based on indium gallium nitride (AlInGaN) are materials commonly used in the production of light-emitting semiconductor devices such as blue-green light-emitting diodes and laser diodes. These materials are usually grown on substrates such as alumina (Al203) or silicon carbide (SiC). Due to the difference in lattice constants, it is difficult for semiconductor materials to grow directly on substrates. For example, GaN layers (a = 3.189 people) are difficult to grow on alumina (a = 4.758 A) substrates because their lattice constants differ by more than 16%.
Akasaki等人首先於美國專利案案號4,855,249中提 出，在氧化鋁基板上以低溫成長非晶性的氮化鋁（A1N) 緩衝層，以緩和氧化鋁基板與氮化鎵層之間晶格常數差異 太大的問題。Nakamura等人於美國專利案案號5,290,393 中揭露以氮化鎵（GaN)或氮化鋁鎵(AlGaN)等材料爲緩衝： 層的作法。首先在氧化鋁基板上以成長溫度範圍400至 °c成長一非晶性氮化鎵緩衝層。接著在此氮化鎵緩衝 以1000至l2〇0°C的溫度範圍，成長氮化鎵磊晶層。此_ 化鎵聶晶層之品質與效能皆優於以氮化錦爲緩衝層;^ ~ & 鎵磊晶層。 4EPITAXY/200006TW ^ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 訂---------線_---1 經濟部智慧財產局員工消費合作社印製 584903 A7 B7 五、發明說明（>) 傳統上，在基板與緩衝層之間成長單一種晶核，以 平衡晶格常數的差異。然而基板上的單一種晶核仍然顯出 更多差排缺陷的發生機會。請參照圖1a到圖ld，其描述 根據先前技術差排缺陷是如何發生的。在圖la中’晶核 101成長於基板1上。然後，如圖lb所示，一緩衝層103 漸漸成長在基板1與晶核101上。完成緩衝層1〇3之後， 如圖lc所示，差排缺陷104大多沿著兩個晶核1〇1的邊發 生。在圖Id中，在成長一磊晶層105之後，差排缺陷104 更進一步延伸到磊晶層105內。差排缺陷1〇4減低發光二 極體的光電效能。 由於晶格常數的差異造成磊晶層的差排缺陷，並甚至 會減低所生產之半導體裝置的效能，因此一直有需求要減 低磊晶層與基板間，如氮化鎵磊晶層與氧化鋁基板之間的 晶格常數差異。 發明簡要說明 本發明提供一種半導體裝置，其包含一單晶基板、單 晶基板上的多重晶核、多重晶核上的一差排抑制層、以及 差排抑制層上的一磊晶層。多重晶核由至少兩種具有不同 晶格常數的材料所構成。多重晶核是分別隔開的。多重晶 核較佳的厚度在10人到100 A。 圖式之簡單說明 圖la到Id詳細圖示根據先前技術發生在一半導體裝置中 4EPITAXY/200006TW 〇 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） (請先閱讀背面之注意事項再填寫本頁)Akasaki et al. First proposed in U.S. Patent No. 4,855,249 that an amorphous aluminum nitride (A1N) buffer layer was grown on an alumina substrate at low temperature to relax the lattice constant between the alumina substrate and the gallium nitride layer. The difference is too big. Nakamura et al., In US Patent No. 5,290,393, disclose the use of gallium nitride (GaN) or aluminum gallium nitride (AlGaN) and other materials as a buffer: layer approach. An amorphous gallium nitride buffer layer is first grown on an alumina substrate at a growth temperature range of 400 to ° C. Then, in this gallium nitride buffer, a gallium nitride epitaxial layer is grown at a temperature range of 1000 to 12O ° C. The quality and performance of this gallium nitride layer are better than using nitride bromide as a buffer layer; ^ ~ & gallium epitaxial layer. 4EPITAXY / 200006TW ^ This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Printed by the Intellectual Property Bureau Staff Consumer Cooperatives --- ------ Line _--- 1 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 584903 A7 B7 V. Description of the invention (>) Traditionally, a single crystal nucleus was grown between the substrate and the buffer layer to Differences in equilibrium lattice constants. However, a single type of crystal nucleus on the substrate still shows more opportunities for the occurrence of poorly aligned defects. Please refer to FIG. 1a to FIG. 1d, which describe how the difference defect occurs according to the prior art. In FIG. 1a ', the crystal nuclei 101 are grown on the substrate 1. Then, as shown in FIG. 1b, a buffer layer 103 is gradually grown on the substrate 1 and the crystal core 101. After the buffer layer 103 is completed, as shown in FIG. 1c, most of the differential defects 104 occur along the edges of the two crystal nuclei 101. In FIG. Id, after growing an epitaxial layer 105, the differential defect 104 further extends into the epitaxial layer 105. Differential defect 104 reduces the photoelectric efficiency of the light emitting diode. Due to the difference in lattice constants, the defection of the epitaxial layer causes defects and even reduces the efficiency of the semiconductor devices produced. Therefore, there has been a need to reduce the epitaxial layer and the substrate, such as the gallium nitride epitaxial layer and alumina. Lattice constant difference between substrates. Brief Description of the Invention The present invention provides a semiconductor device including a single crystal substrate, multiple crystal nuclei on the single crystal substrate, a differential emission suppression layer on the multiple crystal nuclei, and an epitaxial layer on the differential emission suppression layer. Multiple crystal nuclei are composed of at least two materials with different lattice constants. Multiple nuclei are separated. The thickness of the multiple crystal nuclei is preferably from 10 to 100 A. Brief description of the drawings Figures la to Id are detailed illustrations that occur in a semiconductor device according to the prior art. 4EPITAXY / 200006TW 〇 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297 public love) (Please read the back first (Notes to fill out this page)
訂---------線I 584903 A7 _B7__ 五、發明說明（3 ) 的差排缺陷。 圖2a到2d詳細圖示根據本發明在一半導體裝置中較少之 差排缺陷。 圖3爲根據本發明之一半導體裝置的示意圖。 圖4爲根據本發明第一較佳實施例之半導體裝置的示意 圖。 圖5爲根據本發明第二較佳實施例之半導體裝置的示意 圖。 圖6爲根據本發明第三較佳實施例之半導體裝置的示意 圖。 -----------^丨裝—— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 圖7爲根據本發明第四較佳實施例之半導體裝置的示意 圖。 圖8爲根據本發明第五較佳實施例之半導體裝置的示意 圖。 圖9爲根據本發明第六較佳實施例之發光半導體裝置的 Tp：意圖。 圖10爲根據本發明第七較佳實施例之發光半導體裝置的 示意圖。 圖11爲根據本發明第八較佳實施例之發光半導體裝置的 示意圖。 圖式之元件符號說明 1基板 103緩衝層Order --------- Line I 584903 A7 _B7__ V. The difference in the description of the invention (3). Figs. 2a to 2d illustrate in detail the fewer difference defects in a semiconductor device according to the present invention. FIG. 3 is a schematic diagram of a semiconductor device according to the present invention. Fig. 4 is a schematic diagram of a semiconductor device according to a first preferred embodiment of the present invention. Fig. 5 is a schematic diagram of a semiconductor device according to a second preferred embodiment of the present invention. Fig. 6 is a schematic diagram of a semiconductor device according to a third preferred embodiment of the present invention. ----------- ^ 丨 Installation—— (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 7 is the fourth preferred implementation according to the present invention Example of a schematic diagram of a semiconductor device. Fig. 8 is a schematic diagram of a semiconductor device according to a fifth preferred embodiment of the present invention. FIG. 9 is a Tp: intention of a light emitting semiconductor device according to a sixth preferred embodiment of the present invention. FIG. 10 is a schematic diagram of a light emitting semiconductor device according to a seventh preferred embodiment of the present invention. Fig. 11 is a schematic diagram of a light emitting semiconductor device according to an eighth preferred embodiment of the present invention. Explanation of the symbols of the drawings 1 substrate 103 buffer layer
4EPITAXY/200006TW 訂 101晶核 104差排缺陷 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 584903 A7 B7 五 發明說明（今） 105嘉晶層 201、202多重晶核 204差排缺陷 2多重晶核層 203差排抑制層 205嘉晶層 差排抑制層、氮化鎵差排抑制層、氮化鋁鎵寒排 磊晶層、氮化鎵磊晶層 4 η型氮化鎵包覆層、p型氮化鎵包覆層 5 6多重量子井結構 7 Ρ型氮化鋁鎵包 9鎳/金歐姆接觸層 11鈦/鋁歐姆接觸層^ 1〇多重晶核半導體裝置 20、30、40、50、60氮化鎵半導體裝置 70、80、90發光半導體裝置 221、 232、251、253、272、281 氮化銦晶核 222、 231、252、271氮化鋁晶核 241氮化鎵晶核 242、262、292氮化鋁銦晶核 261、282氮化鋁鎵 層4EPITAXY / 200006TW Order 101 crystal nuclei 104 differential arrangement defect This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 584903 A7 B7 Five invention description (present) 105 Jiajing layer 201, 202 multiple crystal nuclei 204 Differential row defect 2 Multiple nucleation layer 203 Differential row suppression layer 205 Jiajing layer Differential row suppression layer, GaN differential row suppression layer, AlGaN cold row epitaxial layer, GaN epitaxial layer 4 η-type nitrogen Gallium cladding layer, p-type gallium nitride cladding layer 5 6 multiple quantum well structure 7 P-type aluminum gallium nitride package 9 nickel / gold ohmic contact layer 11 titanium / aluminum ohmic contact layer ^ 10 multiple crystal core semiconductors Devices 20, 30, 40, 50, 60 GaN semiconductor devices 70, 80, 90 Light-emitting semiconductor devices 221, 232, 251, 253, 272, 281 Indium nitride nuclei 222, 231, 252, 271 Aluminum nitride crystals Core 241 gallium nitride crystal core 242, 262, 292 aluminum indium nitride crystal core 261, 282 aluminum gallium nitride layer
(請先閱讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 發明之詳細說明 本發明提供位於基板上，且由至少兩種材料$_、 多重晶核’以解決基板與嘉晶層之間因晶格不匹配所造$ 的差排缺陷問題，特別是在氧化鋁（a = 4.7S8 A)基板與氮 化鎵（a = 3.189 A)磊晶層之間。若不減少差排缺陷，對於 發光半導體裝置的光電效能會有重大影響。 請參閱圖2a到2d，其描述如何根據本發明減少差排缺(Please read the notes on the back before filling this page) Detailed description of the invention printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This invention is provided on the substrate and is composed of at least two materials The problem of misalignment between the substrate and the Jiajing layer due to lattice mismatch, especially between the alumina (a = 4.7S8 A) substrate and the gallium nitride (a = 3.189 A) epitaxial layer. If the differential defect is not reduced, the photoelectric performance of the light-emitting semiconductor device will be greatly affected. Please refer to Figures 2a to 2d, which describe how to reduce the difference in exclusion according to the present invention
4EPITAXY/200006TW 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) W----訂----------線------------- 584903 A7 B7 五、發明說明（5) 陷。首先請參照圖2a。多重晶核201與202成長於於基板 1上。多重晶核201與2〇2係由兩種不同晶格常數的材料 所構成，供減少因基板1與之後成長於其上之磊晶層205 的晶格常數差異所造成之應力。多重晶核201與202分別 隔開，以允許差排抑制層203成長。接著’請參閱圖2b。 差排抑制層203成長在基板1與多重晶核201與202上。 圖2c圖示在成長完成後的差排抑制層203。由於阻止無法 承受之應力發生在晶核201與202之間的邊上，差排缺陷 204較少產生。這是因爲磊晶成長可以不同速率與方向實 施，而且差排被抑制或者被強迫沿著側邊成長。如圖2d 所示，在磊晶層205的成長之後，則產生一半導體裝置， 其一直向上延伸到磊晶層205的差排缺陷比較少。 晶核201與202較好各是由AlxIriyGa^N所構成，其 中（^^卜〇^01，而〇^+01。有較大晶格常數的 材料，如 InN ( a=3.544 A)與 GaN ( a=3.189 A)，兩者擇 一地與較小晶格常數材料，如AIN ( a=3.1lA)混合，以構 成多重晶核201與202。相隔一段距離的晶核201與202， 由至少兩種材料構成，其藉著幫助以不同的晶核形成速率 與方向成長磊晶層205，以減少差排缺陷。 經濟部智慧財產局員工消費合作社印製 差排抑制層203較好是由AlxIriyGa^yN所構成，其中 OSx^l，OSy^l，而O^x+y^l，而且更好是由以氮化 鎵爲基礎的材料所構成，如氮化鎵、氮化鋁以及氮化鋁鎵。 差排抑制層2〇3幫助進一步減少在多重晶核201與202以 及磊晶層205之間的差排缺陷。 4EPITAXY/200006TW ^ 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） 經濟部智慧財產局員工消費合作社印製 584903 A7 B7 五、發明說明（G ) 任何化合物半導體層根據以下方法成長於基板上。一 化合物半導體層，藉由氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)、有機金屬氣相嘉晶（organometallic vapor phase epitaxy，OMVPE)或分子束嘉晶（molecular beam epitaxy，MBE)，直接或間接地形成於基板上。對於 III-氮族化合物半導體而言爲AlxIriyGarx-yN層，·其中OSx ‘l，〇$y$l，而 〇$ χ+y $ 1。鎵來源是 TMGa 或 TEGa 〇 鋁來源是TMA1與TEA卜銦來源是TMIn或TEIn。氮來源 是 NH3 或二甲基聯氨（Dimethylhydrazine，DMeNNH2 )。而 P型摻質係選自包含Zn、Cd、Be、Mg、Ca、Ba與Sb的 群組。n型摻質係選自包含Si、Ge與Sn的群組。p型與n 型摻質也適用於以下實施例。 爲簡化起見，在以下圖式中多重晶核不以真實比例的 層來例示。請參閱圖3。在基板1上，1〇 A至1〇〇 A厚的 多重晶核層2在成長溫度400至1000°C下成長。可調整 鋁、銦以及鎵化合物在氣相中的流速與成長溫度，以決定 多重晶核層2的適當構成。爲進一步減少差排缺陷，以成 長溫度 400 至 1000t 成長 AUInyGa^yN ( 0‘xS 1，OSy ^ 1，而0$ x+yg 1 )差排抑制層3在多重晶核層2上，厚 度在100 A至500A之間。然後再以成長溫度l〇〇〇°C至1200 °C，成長以氮化鎵爲基底的（GaN-based)化合物半導體磊晶 層4在差排抑制層3上。 藉由以下示範性的方式成長多重晶核層2,以減少差排 缺陷。 4EPITAXY/200006TW 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------- · ------— — — — — — — · (請先閱讀背面之注意事項再填寫本頁) 584903 A7 B7 五、發明說明（ο ) (1) 在基板1上成長多重晶核層2。其成長方式爲先在基板 上成長氮化銦（InN)晶核，然後再成長氮化鋁（A1N) 晶核。氮化銦與氮化鋁晶核大約10到1〇〇 A厚。晶核 分別隔開以在其表面具有許多的孔洞，以便減少差排缺 陷。AlJriyGarx-yN (OSx^l，O^y^l，而 OS x+yS 1 ) 差排抑制層3接著成長在多重晶核層2上。差排抑制層 3厚度約介於100 A至500 A之間。 (2) 在基板1上成長多重晶核層2。其成長方式爲在基板上 先成長氮化鋁晶核，然後再成長氮化銦晶核。氮化鋁與 氮化銦晶核總厚度約爲10到100 A。晶核分別隔開以在 其表面具有眾多的孔洞，以便減少差排缺陷產生。 AlxInyGa卜x-yN (OSxgl，Ogygl，而 OSx+ygl)差 排抑制層3接著成長在多重晶核層2上。差排抑制層3 厚度約介於.1〇〇人至500 A之間。 (3) 在基板上1成長多重晶核層2。成長方式係在基板上首 先成長氮化銦晶核，然後成長氮化鎵晶核。氮化銦與氮 化鎵的厚度約介於10至100 A之間。晶核分別隔開以 在其表面具有眾多的孔洞，以便減少差排缺陷。 AlxInyGa 卜 x_yN (OSx^l，〇gy$l，而 0$ χ+y g 1 )差 排抑制層3接著成長在多重晶核層2上。差排抑制層3 厚度約介於1〇〇 A至500人之間。 (4) 在基板1上成長多重晶核層2。其成長方式在基板上先 成長氮化鎵晶核，然後再成長氮化銦晶核。氮化鎵與氮 化銦晶核的厚度約介於10至100 A之間。晶核分別隔 4EPITAXY/200006TW 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------#-裝 (請先閱讀背面之注意事項再填寫本頁) W ----訂---------· 經濟部智慧財產局員工消費合作社印製 584903 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（公） 開以在其表面具有眾多的孔洞，以便減少差排缺陷。 AlxInyGaH-yN ( OgxS 1，1，而 1)差 排抑制層3接著成長在多重晶核層2上。差排抑制層3 厚度約介於100人至500 A之間。 (5) 在基板1上成長多重晶核層2。其成長方式在基板上先 成長氮化銦鎵晶核，然後再成長氮化鎵晶核。氮化銦鎵 與氮化鎵晶核的厚度約介於10至100 A之間。晶核分 別隔開以在其表面具有眾多的孔洞，以便減少差排缺 陷。AlxIiiyGai (O^x^l，’ 而 〇Sx+yg 1) 差排抑制層3接著成長在多重晶核層2上。差排抑制層 3厚度約介於1〇〇 A至500 A之間。 (6) 在基板1上成長多重晶核層2。其成長方式在基板上先 成長氮化鎵晶核，然後再成長氮化鋁銦晶核。氮化鎵與 氮化鋁銦晶核的厚度約介於10至100人之間。晶核分 別隔開以在其表面具有眾多的孔洞，以便減少差排缺 陷。AlxInyGai_x_yN (OSxSl，OSy^l，而 OS x+y ^ 1 ) 差排抑制層3接著成長在多重晶核層2上。差排抑制層 3厚度約介於100 A至500 A之間。 (7) 在基板1上成長多重晶核層2。其成長方式在基板上先 成長氮化鋁銦晶核，然後再成長氮化鎵晶核。氮化鋁銦 與氮化鎵晶核的厚度約介於10至100 A之間。晶核分 別隔開以在其表面具有眾多的孔洞，以便減少差排缺 陷。AlxInyGa卜x_yN (O^x^l，O^y^l，而 0$ x+y S 1 ) 差排抑制層3接著成長在多重晶核層2上。差排抑制層 4EPITAXY/200006TW 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂--- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 584903 A7 B7 五、發明說明（g) 3厚度約介於100 A至500 A之間。 (8) 在基板1上成長多重晶核層2。其成長方式在基板上先 成長氮化銦晶核，然後再成長氮化鋁鎵晶核。氮化銦與 氮化鋁鎵晶核的厚度約介於10至100 A之間。晶核分 別隔開以在其表面具有眾多的孔洞，以便減少差排缺 陷。AUnyGarx-yN ( OSxS 1，1，而 1 ) 差排抑制層3接著成長在多重晶核層2上。差排抑制層 3厚度約介於100 A至500 A之間。 (9) 在基板1上成長多重晶核層2。其成長方式在基板上先 成長氮化鋁鎵晶核，然後再成長氮化銦晶核。氮化鋁鎵 與氮化銦晶核的厚度約介於1〇至1〇〇 A之間。晶核分 別隔開以在其表面具有眾多的孔洞，以便減少差排缺 陷。AlJiiyGa^x-yN (Ogx^l，〇$y‘l，而 0€ x+yS 1 ) 差排抑制層3接著成長在多重晶核層2上。差排抑制層 3厚度約介於100 A至500 A之間。 (10) 在基板1上成長多重晶核層2。其成長方式在基板 上先成長氮化鋁晶核，然後再成長氮化銦鎵晶核。氮化 鋁與氮化銦鎵晶核的厚度約介於10至100 A之間。晶 核分別隔開以在其表面具有眾多的孔洞，以便減少差排 缺陷。AUInyGak-yN ( OgxS 1，OSyS 卜而 0$x+y S1)差排抑制層3接著成長在多重晶核層2上。差排 抑制層3厚度約介於100 A至500 A之間。 (11) 在基板1上成長多重晶核層2。其成長方式在基板 上先成長氮化銦鎵晶核，然後再成長氮化鋁晶核。氮化 4EPITAXY/200006TW 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------AWI ^--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 584903 A7 —____B7___ _ 五、發明說明（（〇 ) 銦鎵與氮化鋁晶核的厚度約介於10至100 A之間。晶 核分別隔開以在其表面具有眾多的孔洞，以便減少差排 缺陷。AlxInyGamN ( 1，1，而 〇gx+y S 1 )差排抑制層3接著成長在多重晶核層2上。差排 抑制層3厚度約介於100 A至500 A之間。 (12) 在基板1上成長多重晶核層2。其成長方式在基板 上先成長氮化鋁銦鎵晶核，然後再成長氮化銦鎵晶核。 氮化鋁銦鎵與氮化銦鎵晶核的厚度約介於10至100 A 之間。晶核分別隔開以在其表面具有眾多的孔洞，以便 減少差排缺陷。AlxInyGai_x_yN (OSxgl，OSySl，而 OS x+yS1)差排抑制層3接著成長在多重晶核層2上。 差排抑制層3厚度約介於1〇〇 A至500 A之間。 (13) 在基板1上成長多重晶核層2。其成長方式在基板 上先成長氮化銦鎵晶核，然後再成長氮化鋁銦晶核。氮 化銦鎵與氮化鋁銦晶核的厚度約介於10至100 A之 間。晶核分別隔開以在其表面具有眾多的孔洞，以便減 少差缺陷。AlxInyGabx.yN (OSxSl，o^y^l，而 〇 Sx+yS 1)差排抑制層3接著成長在多重晶核2上。差 排抑制層3厚度約介於100 A至500 A之間。 以下將進一步描述本發明之較佳實施例。 第一實施例 請參考圖4，其爲氮化鎵半導體裝置20的示意圖。將 一可晶晶成長之氧化錦基板(epitaxy-ready AI2O3 )1，如一^ 4EPITAXY/200006TW 1 〇 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------AWI ^--- (請先閱讀背面之注意事項再填寫本頁) 訂· 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 584903 A7 B7 五、發明說明（π ) 晶圓，首先置於一有機金屬氣相磊晶成長反應器(未顯示） 中。先於1150°c的溫度下，將氧化鋁基板1預熱’導入流 速爲10 Ι/min的氫氣淸洗晶片表面。然後將氧化鋁基板溫 度降低至400°C至l〇〇〇°C之間的範圍，導入包含TMIn 55 μιηοΐ/min及氨氣3 1/min的混合氣體，以成長氮化銦晶核 221。氮化銦晶核221的較佳成長溫度爲62(TC。然後導入 包含TMA1 50 μπιοΐ/min及氨氣2 Ι/min的混合氣體，以 成長氮化鋁晶核222。氮化鋁晶核222的較佳成長溫度爲 530°C。多重晶核氮化銦與氮化鋁221與222厚約45A。然 後，將溫度降至400°C至1000°C之間的範圍，導入包含 TMGa 30 μηιοΐ/min及氨氣2.5 Ι/min的氣體，以成長氣 化鎵差排抑制層3，其厚度約在100 A至500A之間。差排 抑制層3較佳成長溫度與較佳的厚度分別是500 °C與 200A。然後，再升溫至1120°C，導入包含TMGa 52 μιηοΐ/mm 及氨氣3 Ι/miri的混合氣體，以在氮化鎵差排抑制層3上 成長厚2 μιη未摻雜之氮化鎵磊晶層4。藉由霍爾效應測纛 (Hall effect measurement)量測磊晶層4。結果顯示在 300K下，遷移率(mobility)爲430 cm2/V-s，載子濃度 (carrier concentration)爲-3el6/cm3 ;在 77 K 下，遷移率 爲 1250 cm2/V-s，載子濃度爲 _7.04el5/cm3。 第二實施例 請參考圖5，其爲氮化鎵半導體裝置30的示意圖。將 一可嘉晶成長之氧化錦基板1，如一晶圓，首先置於一^有 4EPITAXY/200006TW n ^^尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ----------裝--------訂——— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 584903 A7 ____Β7_____ 五、發明說明（丨工） 機金屬氣相磊晶成長反應器(未顯示）中。先於1150°C的溫 度下，將氧化銘基板1預熱，導入10 Ι/min的氣氣淸洗晶 片表面。然後將氧化鋁基板溫度降低至40CTC至l〇〇〇°C之 間的範圍，導入包含TMA1 50 μπιοΐ/min及氨氣2 1/min 的混合氣體，以成長氮化鋁晶核231。氮化鋁晶核231的 較佳成長溫度爲530°C。然後導入幫含TMIn 55 μπιοΐ/min 及氨氣3 1/min的混合氣體，以成長氮化銦晶核232。氮 化銦晶核232的較佳成長溫度爲620°C。多重晶核氮化銦 與氮化鋁231與232厚約45人。然後，將溫度降至400°C 至1000°C之間的範圍，導入包含TMGa 30 μπιοΐ/min及氣 氣2.5 Ι/min的混合氣體，以成長氮化鎵差排抑制層3， 其厚度約在1〇〇 A至500A之間。差排抑制層3之較佳成 長溫度與較佳厚度分別是500 °C與200A。然後，再升溫 至 1120°C，導入包含 TMGa 52 μπιοΐ/min 及氨氣 3 1/min 的混合氣體，以在氮化鎵差排抑制層3上成長厚2 μηι未 摻雜之氮化鎵磊晶層4。 第三實施例 請參考圖6，其爲氮化鎵半導體裝置40的示意圖。將 一可磊晶成長之氧化鋁基板1，如一晶圓，首先置於一有 機金屬氣相磊晶成長反應器（未顯示）中。先於1150°C的溫 度下，將氧化鋁基板1預熱，導入流速爲10 Ι/min的氫氣 淸洗晶片表面。然後將氧化鋁基板溫度降低至5〇〇°C至600 °C之間的範圍，導入包含TMGa 50 μιηοΐ/min及氨氣1.5 4EPITAXY/200006TW 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --I------ i —訂！！！ - (請先閱讀背面之注意事項再填寫本頁) 584903 A7 B7 五、發明說明（\3) l/min的混合氣體，以成長氮化鎵晶核241。晶核241的較 佳成長溫度爲510°C。然後導入包含TMA1 25 μπιοΐ/min、 TMIn20 l/min以及氨氣2.5 l/min的混合氣體，以成長氮 化鋁銦晶核242。氮化鋁銦晶核242的較佳成長溫度爲580 °C。多重晶核241與242厚約65A。然後，將溫度降至500 。(：，導入包含 TMGa 30 μηιοΐ/min、TMA1 25 μπιοΐ/min 以 及氨氣3 l/min的混合氣體，以在氮化鋁銦晶核2上成長 200 A厚的氮化鋁鎵差排抑制層3。然後，再升溫至1120 °C，導入包含TMGa 52 μπιοΐ/min及氨氣3 l/min的混合氣 體，以在氮化鋁鎵差排抑制層3上成長厚2 μηι未摻雜之 氮化錄嘉晶層4。 第四實施例 請參考圖7，其爲氮化鎵半導體裝置50的示意圖。將 一可磊晶成長之氧化鋁基板1，如一晶圓，首先置於一有 機金屬氣相磊晶成長反應器（未顯示）中。先於115〇°C的溫 度下，將氧化鋁基板1預熱，導入流速爲10 l/min的氫氣 淸洗晶片表面。然後將氧化鋁基板溫度降低至400°C至 1000°C之間的範圍，導入包含TMIn 55 μπιοΐ/min及氨氣 3 l/min的混合氣體，以成長氮化銦晶核251。氮化銦晶核 251的較佳成長溫度爲620°C。然後導入包含TMA1 50 μηιοΐ/min以及氨氣2 l/min的混合氣體，以成長氮化銘晶 核252。氮化鋁晶核252的較佳成長溫度爲530t。然後， 導入包含ΤΜΙη 55μπιο1/ιηίη以及氨氣3 l/min的混合氣 4EPITAXY/200006TW 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------II——•-裝 (請先閱讀背面之注意事項再填寫本頁) ----訂--- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 584903 A7 B7 五、發明說明（\<V) 體，以成長氮化銦晶核253。晶核253之較佳成長溫度是 620°C。多重晶核251、252與253厚約50A。然後，將溫 度降至400°C至l〇〇〇°C的範圍，導入包含TMGa 30 μηιοΐ/πιίη、TMA1 25 μπιοΐ/min 以及氛氣 2.5 1/min 的混 合氣體，以在多重晶核2上成長100人至500 A厚的氮化 鋁鎵差排抑制層3。差排抑制層3之較佳成長溫度與較佳 厚度分別是500 °C與200A。然後，再升溫至1120°C，導 入包含TMGa 52 μπιοΐ/min及氨氣3 Ι/min的混合氣體，以 成長厚2 μιη未摻雜之氮化鎵磊晶層4在氮化鋁鎵差排抑 制層3上。 第五實施例 請參考圖8，其爲氮化鎵半導體裝置60的示意圖。將 一可磊晶成長之氧化鋁基板1，如一晶圓，首先置於一有 機金屬氣相磊晶成長反應器(未顯示）中。先於1150°C的溫 度下，將氧化鋁基板1預熱，導入流速爲10 Ι/min的氫氣 淸洗晶片表面。然後將氧化鋁基板溫度降低至500°C至600 °C之間的範圍。當溫度到達500°C，導入包含TMGa 30 μπιοΐ/min、TMA1 25μιηο1/πτάη 以及氛氣 3 1/min 的混合氣 體，以成長氮化鋁鎵晶核261。接著調整溫度到580°C，導 入包含 TMA1 25 μπιοΐ/min、20pmol/minTMIn 以及氨氣 2.5 Ι/min的混合氣體，以成長氮化鋁銦晶核262。多重晶核261 與262厚約65人。然後，將溫度調整至400t至1000°C的 範圍，導入包含TMGa 30 μιηοΐ/min以及氛氣2 Ι/min的 4EPITAXY/200006TW 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------— 丨裝 -------訂·! (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 584903 A7 B7 五、發明說明（丨占） 混合氣體，以在多重晶核2上成長200 A厚的氮化鎵差排 抑制層3。然後，再升溫至1120°C，導入包含TMGa 52 μπιοΐ/min及氨氣3 1/min的混合氣體，以在氮化鋁鎵差排 抑制層3上成長厚2 μιη未摻雜之氮化鎵嘉晶層4。 第六實施例 請參考圖9，其爲發光半導體裝置7〇的示意圖。此發 光半導體裝置70係爲，舉例來說，一發光二極體（LED)。 將一可磊晶成長之氧化鋁基板1裝載於一有機金屬氣相磊 晶成長反應器（未顯示）中。基板1可爲氧化鋁、碳化矽 或砷化鎵材料。在1150°C的溫度下，導入5 Ι/min氫氣 淸洗晶片表面10分鐘。然後將溫度降低至溫度範圍爲約 400°C 至 1000X：之間，_導入包含 TMA1 50 μιηοΐ/min 及氨 氣2 Ι/min的混合氣體，以成長氮化鋁晶核271。晶核271 的較佳成長溫度爲530°C。然後導入包含TMIn 55 μιηοΐ/min及氨氣3 1/min的混合氣體，以成長氮化銦晶核 272。氮化銦晶核272的較佳成長溫度爲620°C。多重晶核 271與272厚約45A。然後，將晶片溫度降至溫度範圍約 4〇〇°C 至 1000°C 之間，導入包含 TMGa 20 μιηοΐ/πιίη、TMA1 25μηιο1/πήη及氨氣2.5 1/min的混合氣體，以在多重晶 核2上成長厚度約介於100 A至500A之間的氮化鋁鎵 (AlyGai_yN，OSyS 1)差排抑制層3。差排抑制層3的較佳 成長溫度與較佳厚度分別爲570 °C與320A。然後，將溫 度升高至1130°C，並導入包含TMGa 52 μπιοΐ/min及3·5 4EPITAXY/200006TW 15 ^5長尺度適用中國國家標準（CNS)A4規格（210 X 297公釐1 ----------裝--------訂--------- (請先閱讀背面之注音？事項再填寫本頁) 584903 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（\(α ) 1/min氨氣及100 ppm SiH4/H2的混合氣體，在差排抑 制層3上成長4 μιη厚之η型氮化鎵包覆層(cladding layer)5。包覆層 5 的一實施例爲 AlwInzGai-w-zN ， l，0Sz$l，0$ w+z $ 1 〇 然後再溫度調整至約850°C，並導入包含TMGa 30 μπιοΐ/min、TMIn 30 μπιοΐ/min 以及 3.5 1/min 氨氣的 混合氣體。藉由控制TMIn的輸出，在η型氮化鎵包覆層 5上形成包含多對（例如5對）氮化銦鎵/氮化鎵之多重 量子井結構(multiple quantum well-MQW)層6，當作發光 活性層（light emitting active layer )。然後再將溫度升高至 約 1100°C，並導入包含 TMGa 42 μπιοΐ/min、TMA1 20 μηιοΐ/min、氨氣 3.5 Ι/min 以及 DCpMg 52 nmol/min 的混合氣體，以在多重量子井結構層6上成長約0.2 μιη厚 的Ρ型氮化鋁鎵包覆層7。包覆層7的一實施例爲 AlsIntGai+tN，OgsS 1，1，OSs+tS 1。 然後再將晶片升溫至約1130°C，並導入包含TMGa 52 μΓΠθΙ/min、氨氣 3.5 Ι/min 以及 DCpMg 52 nmol/ min的混合氣體，以在ρ型氮化鋁鎵包覆層7上成長約0.3 μιη厚的ρ型氮化鎵電極層8。電極層8的一實施例爲 AluInvGa^u-vN，其中 OSuSl，OSvSl，OS u+vS 1 〇 — LED結構磊晶片以此方式完成。 將上述磊晶片，經活化處理之後，然後依據下列步驟 製作成晶粒（chip )。 步驟一：將部分P型電極層8、ρ型包覆層7以及多重量子 4EPITAXY/200006TW 16 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----I-----J^wi I --------^ ·11111111 . (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 584903 A7 B7 五、發明說明（㈧） 井結構層6移除，以將η型氮化鎵包覆層5的表面暴露出 來。 步驟二：沉積一鎳/金（Ni/Au)歐姆接觸金屬層（ohmic contact metal layer) 9在p型氮化鎵電極層8上。 步驟三：沉積一鈦/鋁（Ti/Al)歐姆接觸金屬層11於n 型氮化鎵包覆層5上。 步驟四：將晶圓鋸切成複數個350 μιη X 350 μπι之正方形 晶粒。 上述之發光二極體晶粒，在20mA時的順向電壓 (forward voltage)約爲 3.5 伏特（voltage)。 第七實施例 請參考圖10，其爲一發光半導體裝置80的示意圖。 此發光半導體裝置80，舉例來說，可爲一發光二極體。將 一可嘉晶成長之氧化錦基板1裝載於一有機金屬氣相嘉晶 成長反應器（未顯示）中。基板1可爲氧化鋁、碳化矽或 砷化鎵材料。在ll5〇°C的溫度下，導入5 Ι/min氫氣淸 洗晶片表面10分鐘。然後將溫度降低至約400°C至1000 C之間的温度範圍，並導入包含TMIn 25 μπιοΐ/min以及 氨氣3 Ι/min的混合氣體，以成長氮化銦晶核281。此晶核 281的較佳成長溫度爲620°C。然後導入包含TMGa 45 μιηοΐ/min、TMA1 35 μηιοΐ/min 以及氨氣 3 1/min 的混合氣 體，以成長氮化鋁鎵晶核282。晶核282的較佳成長溫度 爲550°C。多重晶核281與282厚約60A。然後，將晶片 4EPITAXY/200006TW ι7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) .裝--— — — — — — 訂·111 584903 Α7 Β7 五、發明說明（α) (請先閱讀背面之注意事項再填寫本頁) 溫度調整至400°c至1000°C之間的溫度範圍’並導入包含 TMGa 35 μπιοΐ/min以及氨氣2·5 Ι/min的混合氣體，以 在多重晶核2上成長厚度介於1〇〇 A至500A之間的氮化 鎵差排抑制層3 ( AlyGa!_yN、0‘yS 1)。差排抑制層3的 較佳成長溫度與較佳厚度分別爲510 °C與250A。然後將 溫度升高至約1130°C，並導入包含TMGa 52 μηιοΐ/min、 氨氣3.5 1/min以及DCpMg 52 nmol/min的混合氣體， 以在差排抑制層3上成長4 μπι厚之p型氮化鎵包覆層5。 包覆層5的一實施例爲AUIrizGa^w-zN，其中0$ w‘ 1，0 ‘ z g 1，以及 0 S w+z S 1。 經濟部智慧財產局員工消費合作社印製 然後，再將溫度降低至約850°C，並導入包含TMGa 30 μπιοΐ/min、TMIn 30 μιηοΐ/min 以及氨氣 3·5 1/min 的混 合氣體。藉由控制TMIri的輸出，可於p型氮化鎵包覆層 5上成長包含多對(例如5對)氮化銦鎵/氮化鎵之多重量 子井結構層6，以當作發光活性層。然後再將晶片升溫至 1130°C，並且導入包含 TMGa 52 μιηοΐ/min、3.5 1/min 氨氣以及100 ppm SiH4/H2的混合氣體，以在多重量子井 結構層6上成長0.5 μπι厚之η型氮化鎵層8。此η型氮 化鎵層8兼作爲多重量子井結構層6之包覆層以及此發光 二極體80之電極層。一 LED結構磊晶片以此方式完成。 將上述嘉晶片，經活化處理之後，然後依據下列步驟 製作成晶粒（chip)。 步驟一：將部分η型氮化鎵層8以及多重量子井結構層6 移除，以將Ρ型氮化鎵包覆層5的表面暴露出來。 4EPITAXY/200006TW ι〇 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 584903 A7 __B7 五、發明說明（q) 步驟二：沉積一鎳/金歐姆接觸金屬層9在p型氮化鎵包 覆層5上。 (請先閱讀背面之注意事項再填寫本頁) 步驟三：沉積一鈦/鋁歐姆接觸金屬層11於η型氮化鎵層 8上。 步驟四：將晶圓鋸切成複數個350 μιη X 350 μιη之正方形 晶粒。 上述之發光二極體晶粒，在20mA時的順向電壓約爲 3.5伏特。 第八實施例 經濟部智慧財產局員工消費合作社印製 請參考圖11，其爲一發光半導體裝置90的示意圖。此 發光半導體裝置90，舉例來說，可爲一發光二極體。首先 將一可嘉晶成長之氧化鋁基板1裝載於一有機金屬氣相磊 晶成長反應器（未顯示）中。基板1可爲氧化鋁、碳化矽 或砷化鎵材料。在1150°C的溫度下，導入5 Ι/min氫氣 淸洗晶片表面10分鐘。然後將溫度降低至約40(TC至1000 C之間的溫度範圍，並導入包含TMGa 45 μπιοΐ/min、TMIn 40μπΐ()1/ιηίη以及氨氣3 1/min的混合氣體，以成長氮化銦 鎵晶核291。此晶核291的較佳成長溫度爲57(TC。然後導 入包含 TMA1 50 μπιοΙ/min'TMIn 40 μπιοΐ/min以及氨氣 3 Ι/min的混合氣體，以成長氮化鋁銦晶核292。晶核292的 較佳成長溫度爲570°C。多重晶核291與292厚約50A。 然後，將晶片溫度調整至400°C至1000°C之間的溫度範 圍，並導入包含 TMGa 20 μιηοΐ/min、TMA1 25 μπιοΐ/min 4EPITAXY/200006TW 19 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 584903 Α7 Β7 五、發明說明Uo ) 以及氨氣2.5 l/min的混合氣體，以在多重晶核2上成長 厚度介於100 A至500A之間的氮化鋁鎵差排抑制層3。差 排抑制層3的較佳成長溫度與較佳厚度分別爲550 °C與 320人。然後將溫度升高至約ll3〇°C’並導入包含TMGa 52 pmol/inin、氨氣 3·5 l/min 以及 SiH4/H2 l〇〇ppm/min 的混合氣體，以在差排抑制層3上成長4 μιη厚之n型氮 化鎵包覆層5。 然後，再將溫度降低至約850。。，並導入包含TMGa 30 μπιοΐ/min、TMIn 30 μπιοΐ/min 以及 3·5 l/min 氨氣的 混合氣體。藉由控制ΤΜΙιι的輸出，可於η型氮化鎵包覆 層5上形成包含多對(例如5對)氮化銦鎵/氮化鎵之多重 量子井結構層6，以當作發光活性層。然後再將溫度升高 至 1100°C，並且導入包含 TMGa 42 μηιοΐ/min、ΤΜΑ1 20 μπιοΐ/min、氨氣 3·5 l/min 以及 DCpMg 52nmol/min 的混 合氣體，以在多重量子井結構層6上成長0.2 μιη厚之p 型氮化鋁鎵包覆層7。 然後將溫度高至約1130°C，並導入包含TMGa 52 μηιοί /min、氨氣 3·5 l/min 以及 DCpMg 52nmol/min 的混合氣 體，以在p型氮化鋁鎵包覆層7上成長0.3 μιη厚之p型 氮化鎵電極層8。一 LED結構磊晶片以此方式完成。 將上述嘉晶片，經活化處理之後，然後依據下列步驟 製作成晶粒。 步驟一：將部分P型電極層8、p型包覆層7以及多重量子 井結構層6移除，以將n型氮化鎵包覆層5的表面暴露出4EPITAXY / 200006TW This paper size applies to China National Standard (CNS) A4 specification (210 X 297 male f) W ---- Order ---------- Line ----------- -584903 A7 B7 V. Description of the invention (5). Please refer to FIG. 2a first. Multiple crystal nuclei 201 and 202 are grown on the substrate 1. The multiple crystal nuclei 201 and 202 are composed of two materials with different lattice constants, so as to reduce the stress caused by the difference in the lattice constants of the substrate 1 and the epitaxial layer 205 grown thereon. The multiple crystal nucleuses 201 and 202 are spaced apart to allow the differential discharge suppressing layer 203 to grow. Next ', please refer to Figure 2b. The differential suppression layer 203 is grown on the substrate 1 and the multiple crystal nuclei 201 and 202. FIG. 2c illustrates the difference suppression layer 203 after the growth is completed. Since the unsustainable stress is prevented from occurring on the edge between the crystal cores 201 and 202, the differential defect 204 is rarely generated. This is because epitaxial growth can be performed at different rates and directions, and the differential row is suppressed or forced to grow along the side. As shown in FIG. 2d, after the epitaxial layer 205 is grown, a semiconductor device is generated, which has a relatively small number of differential defects extending up to the epitaxial layer 205. The nuclei 201 and 202 are each preferably composed of AlxIriyGa ^ N, where (^^ 卜 〇 ^ 01, and 〇 ^ + 01. Materials with larger lattice constants, such as InN (a = 3.544 A) and GaN (a = 3.189 A), either mixed with a smaller lattice constant material, such as AIN (a = 3.1lA), to form multiple crystal nuclei 201 and 202. The crystal nuclei 201 and 202 separated by a distance, by It is composed of at least two materials, which helps to grow the epitaxial layer 205 at different rates and directions of nucleation to reduce the defect of differential discharge. The employee of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the differential emission suppression layer 203. AlxIriyGa ^ yN, among which OSx ^ l, OSy ^ l, and O ^ x + y ^ l, and more preferably composed of gallium nitride-based materials, such as gallium nitride, aluminum nitride, and nitrogen Aluminum gallium. The differential emission suppression layer 203 helps to further reduce the differential emission defects between the multiple crystal nucleus 201 and 202 and the epitaxial layer 205. 4EPITAXY / 200006TW ^ This paper size applies the Chinese National Standard (CNS) A4 specification ( 21〇X 297 Public Love) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 584903 A7 B7 V. Description of Invention (G) Any The semiconductor layer is grown on the substrate according to the following method. A compound semiconductor layer is formed by hydride vapor phase epitaxy (HVPE), organometallic vapor phase epitaxy (OMVPE), or molecular beam. A molecular beam epitaxy (MBE) is formed directly or indirectly on the substrate. For the III-nitrogen compound semiconductor, it is an AlxIriyGarx-yN layer, where OSx 'l, 〇 $ y $ l, and 〇 $ χ + y $ 1. The source of gallium is TMGa or TEGa. The source of aluminum is TMA1 and the source of indium is TMIn or TEIn. The source of nitrogen is NH3 or Dimethylhydrazine (DMeNNH2). The P-type dopant is selected from The group containing Zn, Cd, Be, Mg, Ca, Ba, and Sb. The n-type dopant is selected from the group containing Si, Ge, and Sn. The p-type and n-type dopants are also applicable to the following examples. For the sake of simplicity, the multiple nuclei are not exemplified by layers in true proportions in the following diagrams. Please refer to FIG. 3. On the substrate 1, a 10A to 100A thick multiple nuclei layer 2 is grown at a temperature of 400. Grow to 1000 ° C. Adjustable aluminum, indium and gallium compounds in the gas phase Growth rate and growth temperature to determine the proper composition of the multiple nucleation layer 2. To further reduce the differential defect, grow AUInyGa ^ yN (0'xS 1, OSy ^ 1, and 0 $ x + yg 1 at a growth temperature of 400 to 1000t ) The differential emission suppression layer 3 is on the multiple nucleus layer 2 and has a thickness between 100 A and 500 A. Then, a gallium nitride-based (GaN-based) compound semiconductor epitaxial layer 4 is grown on the differential emission suppression layer 3 at a growth temperature of 1000 ° C to 1200 ° C. The multiple crystal nuclei layer 2 is grown in the following exemplary manner to reduce the defect of the differential discharge. 4EPITAXY / 200006TW 6 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ---------- · ------— — — — — — — — (Please (Please read the notes on the back before filling this page) 584903 A7 B7 V. Description of the invention (ο) (1) Grow multiple nuclei layer 2 on the substrate 1. The growth method is to first grow indium nitride (InN) nuclei on the substrate, and then grow aluminum nitride (A1N) nuclei. Indium nitride and aluminum nitride nuclei are about 10 to 100 A thick. The crystal nuclei are spaced apart to have many holes on their surface in order to reduce the defect of the defective row. AlJriyGarx-yN (OSx ^ l, O ^ y ^ l, and OS x + yS 1) The difference suppression layer 3 is then grown on the multi-nucleus layer 2. The thickness of the differential emission suppression layer 3 is between about 100 A and 500 A. (2) A multiple crystal nuclei layer 2 is grown on the substrate 1. The growth method is to first grow aluminum nitride crystal nuclei on the substrate, and then grow indium nitride crystal nuclei. The total thickness of aluminum nitride and indium nitride nuclei is about 10 to 100 A. The nuclei are spaced apart to have a large number of holes on their surfaces in order to reduce the occurrence of differential defects. The AlxInyGa and x-yN (OSxgl, Ogygl, and OSx + ygl) differential suppression layer 3 is then grown on the multiple crystal nuclei layer 2. The thickness of the differential emission suppression layer 3 is between about 100 and 500 A. (3) Grow multiple nuclei layer 2 on the substrate 1. The growth method is to first grow indium nitride nuclei on the substrate, and then grow gallium nitride nuclei. The thickness of indium nitride and gallium nitride is between 10 and 100 A. The nuclei are spaced apart to have a large number of holes on their surface, so as to reduce the difference in row defects. The AlxInyGa and x_yN (OSx ^ l, 0gy $ l, and 0 $ x + yg1) difference row suppression layer 3 is then grown on the multi-nucleus layer 2. The thickness of the differential emission suppression layer 3 is between 100 A and 500 persons. (4) A multiple crystal nuclei layer 2 is grown on the substrate 1. The growth method is to first grow gallium nitride crystal nuclei on the substrate, and then grow indium nitride crystal nuclei. The thickness of the nuclei of gallium nitride and indium nitride is about 10 to 100 A. The crystal nuclei are separated by 4EPITAXY / 200006TW 7 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- #-pack (Please read the precautions on the back before (Fill in this page) W ---- Order --------- · Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 584903 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (public) Open to have a large number of holes in its surface in order to reduce the difference in row defects. The AlxInyGaH-yN (OgxS 1, 1, and 1) differential suppression layer 3 is then grown on the multiple nucleus layer 2. The thickness of the differential emission suppression layer 3 is between about 100 and 500 A. (5) A multiple crystal nuclei layer 2 is grown on the substrate 1. The growth method firstly grows an indium gallium nitride crystal nucleus on a substrate, and then grows a gallium nitride crystal nucleus. The thickness of indium gallium nitride and gallium nitride nuclei is between about 10 and 100 A. The nuclei are separated to have a large number of holes on their surface in order to reduce the defect of the defective row. The AlxIiiyGai (O ^ x ^ l, 'and 〇Sx + yg 1) differential-row suppression layer 3 is then grown on the multiple crystal nuclei layer 2. The thickness of the differential emission suppression layer 3 is between 100 A and 500 A. (6) A multiple crystal nuclei layer 2 is grown on the substrate 1. The growth method is to first grow gallium nitride nuclei on the substrate, and then grow aluminum indium nitride nuclei. The thickness of the nuclei of gallium nitride and aluminum indium nitride is about 10 to 100 people. The nuclei are separated to have a large number of holes on their surface in order to reduce the defect of the defective row. AlxInyGai_x_yN (OSxSl, OSy ^ l, and OSx + y ^ 1) The difference suppression layer 3 is then grown on the multiple nucleus layer 2. The thickness of the differential emission suppression layer 3 is between about 100 A and 500 A. (7) A multiple crystal nuclei layer 2 is grown on the substrate 1. The growth method firstly grows an aluminum indium nitride crystal nucleus on a substrate, and then grows a gallium nitride crystal nucleus. The thickness of the indium aluminum nitride and gallium nitride nuclei is about 10 to 100 A. The nuclei are separated to have a large number of holes on their surface in order to reduce the defect of the defective row. AlxInyGa and x_yN (O ^ x ^ l, O ^ y ^ l, and 0 $ x + yS1) The differential suppression layer 3 is then grown on the multi-nucleus layer 2. Differential emission suppression layer 4EPITAXY / 200006TW 8 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- installation -------- order-- -(Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 584903 A7 B7 V. Invention Description (g) 3 The thickness is between 100 A and 500 A. (8) A multiple crystal nuclei layer 2 is grown on the substrate 1. The growth method is to first grow indium nitride crystal nuclei on the substrate, and then grow aluminum gallium nitride crystal nuclei. The thickness of the indium nitride and aluminum gallium nitride nucleus is between about 10 and 100 A. The nuclei are separated to have a large number of holes on their surface in order to reduce the defect of the defective row. The AUnyGarx-yN (OSxS 1, 1, and 1) differential-row suppression layer 3 is then grown on the multi-nucleus layer 2. The thickness of the differential emission suppression layer 3 is between about 100 A and 500 A. (9) A multiple crystal nuclei layer 2 is grown on the substrate 1. The growth method is to first grow aluminum gallium nitride crystal nuclei on the substrate, and then grow indium nitride crystal nuclei. The thickness of the aluminum gallium nitride and indium nitride nuclei is between about 10 and 100 A. The nuclei are separated to have a large number of holes on their surface in order to reduce the defect of the defective row. AlJiiyGa ^ x-yN (Ogx ^ l, 〇 $ y'l, and 0 € x + yS 1) The difference suppression layer 3 is then grown on the multiple crystal nuclei layer 2. The thickness of the differential emission suppression layer 3 is between about 100 A and 500 A. (10) A multiple crystal nuclei layer 2 is grown on the substrate 1. The growth method firstly grows aluminum nitride crystal nuclei on the substrate, and then grows indium gallium nitride crystal nuclei. The thickness of the aluminum nitride and indium gallium nitride nuclei is about 10 to 100 A. The nuclei are spaced apart to have a large number of holes on their surface, in order to reduce the defect of the defect. The AUInyGak-yN (OgxS 1, OSyS and 0 $ x + y S1) differential row suppression layer 3 is then grown on the multiple crystal nucleus layer 2. The thickness of the differential suppression layer 3 is about 100 A to 500 A. (11) A multiple crystal nuclei layer 2 is grown on the substrate 1. The growth method is to grow indium gallium nitride crystal nuclei on the substrate, and then to grow aluminum nitride crystal nuclei. Nitrid 4EPITAXY / 200006TW 9 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----------- AWI ^ -------- Order --- ------ Line (Please read the precautions on the back before filling this page) 584903 A7 —____ B7___ _ V. Description of the invention ((〇) The thickness of the nuclei of indium gallium and aluminum nitride is between 10 and 100 A The nuclei are separated to have a large number of holes on the surface, so as to reduce the defect of differential rows. The AlxInyGamN (1, 1, and 0gx + y S 1) differential row suppressing layer 3 is then grown on the multiple crystal nuclei layer 2 The thickness of the differential suppression layer 3 is between about 100 A and 500 A. (12) A multiple crystal nucleus layer 2 is grown on the substrate 1. The growth method firstly grows aluminum indium gallium nitride nucleus on the substrate, and then Then grow indium gallium nitride nuclei. The thickness of the aluminum indium gallium nitride and indium gallium nitride nuclei is between about 10 and 100 A. The nuclei are separated to have a large number of holes on their surfaces in order to reduce the difference. Defects. AlxInyGai_x_yN (OSxgl, OSySl, and OS x + yS1) The differential emission suppression layer 3 is then grown on the multiple nucleus layer 2. The thickness of the differential emission suppression layer 3 is between 100 A and 500 A. ( 13) Grow multiple nucleus layer 2 on substrate 1. The growth method is to grow indium gallium nitride crystal nucleus on the substrate first, and then to grow aluminum indium nitride crystal nucleus. The thickness is between 10 and 100 A. The crystal nuclei are separated to have a large number of holes on their surface in order to reduce poor defects. AlxInyGabx.yN (OSxSl, o ^ y ^ l, and 0Sx + yS 1) is poor The row suppression layer 3 is then grown on the multiple crystal nuclei 2. The thickness of the difference row suppression layer 3 is between about 100 A and 500 A. The preferred embodiment of the present invention will be further described below. For the first embodiment, please refer to FIG. 4 , Which is a schematic diagram of a gallium nitride semiconductor device 20. A crystal-growable oxide bromide substrate (epitaxy-ready AI2O3) 1, such as a ^ 4EPITAXY / 200006TW 1 〇 This paper standard applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) ----------- AWI ^ --- (Please read the notes on the back before filling out this page) Order · Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Cooperatives, Printing Wisdom of the Ministry of Economic Affairs Printed by the Consumer Affairs Cooperative of the Property Bureau 584903 A7 B7 V. Description of the invention (π) Wafer, first placed in an organic In a metal vapor phase epitaxial growth reactor (not shown), the alumina substrate 1 is preheated at a temperature of 1150 ° C, and the surface of the wafer is rinsed by introducing hydrogen gas at a flow rate of 10 l / min. Then, the alumina substrate is washed. The temperature was lowered to a range between 400 ° C. and 1000 ° C., and a mixed gas containing TMIn 55 μιηοΐ / min and ammonia gas 3 1 / min was introduced to grow indium nitride crystal nuclei 221. The preferred growth temperature of the indium nitride nuclei 221 is 62 ° C. Then a mixed gas containing TMA1 50 μποι / min and ammonia gas 2 1 / min is introduced to grow the aluminum nitride nuclei 222. The aluminum nitride nuclei 222 The preferred growth temperature is 530 ° C. The multicrystalline nuclei of indium nitride and aluminum nitride 221 and 222 are about 45A thick. Then, the temperature is reduced to a range between 400 ° C and 1000 ° C, and TMGa 30 μηιοΐ is introduced. / min and ammonia gas at 2.5 I / min to grow the gallium vaporized differential emission suppression layer 3 with a thickness of about 100 A to 500 A. The preferred growth temperature and the preferred thickness of the differential emission suppression layer 3 are 500 ° C and 200A. Then, the temperature was raised to 1120 ° C, and a mixed gas containing TMGa 52 μιηοΐ / mm and ammonia 3 Ι / miri was introduced to grow 2 μm thick on the gallium nitride differential emission suppression layer 3. Hybrid GaN epitaxial layer 4. The epitaxial layer 4 was measured by Hall effect measurement. The results show that at 300K, the mobility is 430 cm2 / Vs and the carrier concentration ( carrier concentration) is -3el6 / cm3; at 77 K, the mobility is 1250 cm2 / Vs, and the carrier concentration is _7.04el5 / cm3. Second implementation Please refer to FIG. 5, which is a schematic diagram of a gallium nitride semiconductor device 30. An oxide brominated substrate 1 such as a wafer, which is grown by Jiajiajing, is first placed on a 4EPITAXY / 200006TW n ^^ standard applicable to Chinese national standards ( CNS) A4 specification (210 X 297 public love) ---------- install -------- order ------ (Please read the precautions on the back before filling this page) Wisdom of the Ministry of Economy Printed by the Consumer Cooperative of the Property Bureau 584903 A7 ____ Β7 _____ 5. Description of the Invention (丨 Work) In a metal-metal vapor phase epitaxial growth reactor (not shown). Preheat the oxidation substrate 1 at a temperature of 1150 ° C. The wafer surface was cleaned by introducing 10 Ι / min gas, and then the temperature of the alumina substrate was reduced to a range between 40CTC and 1000 ° C, and a mixture including TMA1 50 μποΐ / min and ammonia gas 2 1 / min was introduced. Gas to grow aluminum nitride nucleus 231. The preferred growth temperature of aluminum nitride nucleus 231 is 530 ° C. Then introduce a mixed gas containing TMIn 55 μπιοΐ / min and ammonia 3 1 / min to grow nitrogen Indium crystal nucleus 232. The preferred growth temperature of indium nitride crystal nucleus 232 is 620 ° C. Multicrystalline nucleus indium nitride and nitride Aluminum 231 and 232 are about 45 people thick. Then, the temperature is reduced to a range between 400 ° C and 1000 ° C, and a mixed gas containing TMGa 30 μπιοΐ / min and gas 2.5 Ι / min is introduced to grow gallium nitride. The differential emission suppression layer 3 has a thickness between about 100 A and 500 A. The preferred growth temperature and the preferred thickness of the differential emission suppression layer 3 are 500 ° C and 200A, respectively. Then, the temperature was raised to 1120 ° C, and a mixed gas containing TMGa 52 μπιοΐ / min and ammonia 3 1 / min was introduced to grow a 2 μηι undoped gallium nitride on the gallium nitride differential emission suppression layer 3.晶 层 4。 Crystal layer 4. Third Embodiment Please refer to FIG. 6, which is a schematic diagram of a gallium nitride semiconductor device 40. An epitaxially grown alumina substrate 1, such as a wafer, is first placed in an organic metal vapor phase epitaxial growth reactor (not shown). Prior to the temperature of 1150 ° C, the alumina substrate 1 was preheated, and the wafer surface was rinsed by introducing hydrogen gas at a flow rate of 10 l / min. Then reduce the temperature of the alumina substrate to a range between 500 ° C and 600 ° C, and introduce TMGa 50 μιηοΐ / min and ammonia gas 1.5 4EPITAXY / 200006TW 12 This paper applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) --I ------ i --Order! !! !! -(Please read the precautions on the back before filling this page) 584903 A7 B7 V. Description of the invention (\ 3) l / min mixed gas to grow gallium nitride nuclei 241. The preferred growth temperature of the crystal nuclei 241 is 510 ° C. Then, a mixed gas containing TMA1 25 μποΐ / min, TMIn 20 l / min, and ammonia 2.5 l / min was introduced to grow the aluminum indium nitride crystal core 242. The preferred growth temperature of the aluminum indium nitride core 242 is 580 ° C. The multiple crystal nuclei 241 and 242 are approximately 65A thick. Then, reduce the temperature to 500 ° C. (: A mixed gas containing TMGa 30 μηιοΐ / min, TMA1 25 μπιοΐ / min, and ammonia 3 l / min is introduced to grow a 200 A-thick aluminum gallium nitride differential emission suppression layer on the aluminum indium nitride core 2 3. Then, the temperature was increased to 1120 ° C, and a mixed gas containing TMGa 52 μπιοΐ / min and ammonia gas 3 l / min was introduced to grow 2 μηι undoped nitrogen on the aluminum gallium nitride differential emission suppression layer 3. Carbide crystal layer 4. Please refer to FIG. 7 for a fourth embodiment, which is a schematic diagram of a gallium nitride semiconductor device 50. An epitaxially grown alumina substrate 1, such as a wafer, is first placed in an organic metal gas A phase epitaxial growth reactor (not shown). The alumina substrate 1 was preheated at a temperature of 115 ° C, and the wafer surface was purged by introducing hydrogen gas at a flow rate of 10 l / min. Reduce the temperature to 400 ° C to 1000 ° C, and introduce a mixed gas containing TMIn 55 μπιοΐ / min and ammonia 3 l / min to grow indium nitride crystal core 251. Indium nitride crystal core 251 is preferred The growth temperature is 620 ° C. Then a mixed gas containing 50 μηιοΐ / min of TMA1 and 2 l / min of ammonia is introduced. In order to grow nitride crystal core 252. The preferred growth temperature of aluminum nitride crystal core 252 is 530t. Then, a mixed gas containing TIM 1 55 μπι 1 / ιηίη and ammonia 3 l / min is introduced 4EPITAXY / 200006TW 13 This paper is applicable to the standard China National Standard (CNS) A4 Specification (210 X 297 mm) ------ II—— • -Installation (Please read the precautions on the back before filling this page) ---- Order --- Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative printed by the Ministry of Economic Affairs ’Intellectual Property Bureau employee consumer cooperative printed by 584903 A7 B7 V. Description of the invention (\ <V) body to grow indium nitride crystal nucleus 253. Better growth temperature of crystal nucleus 253 It is 620 ° C. The multiple crystal nuclei 251, 252, and 253 are about 50A thick. Then, the temperature is lowered to a range of 400 ° C to 1000 ° C, and TMGa 30 μηιοΐ / πιίη, TMA1 25 μπιοΐ / min, and A mixed gas with an atmosphere of 2.5 1 / min to grow 100 people to 500 A thick aluminum gallium nitride differential emission suppression layer 3 on the multiple crystal nuclei 2. The preferred growth temperature and the preferred thickness of the differential emission suppression layer 3 are respectively 500 ° C and 200A. Then, the temperature was raised to 1120 ° C, and TMGa 52 μπιοΐ / m was introduced. In and ammonia gas 3 Ι / min to grow a 2 μm undoped gallium nitride epitaxial layer 4 on the aluminum gallium nitride differential emission suppression layer 3. For a fifth embodiment, please refer to FIG. 8, which It is a schematic diagram of a gallium nitride semiconductor device 60. An epitaxially grown alumina substrate 1, such as a wafer, is first placed in an organic metal vapor phase epitaxial growth reactor (not shown). Prior to the temperature of 1150 ° C, the alumina substrate 1 was preheated, and the wafer surface was rinsed by introducing hydrogen gas at a flow rate of 10 l / min. The temperature of the alumina substrate is then reduced to a range between 500 ° C and 600 ° C. When the temperature reaches 500 ° C, a mixed gas containing TMGa 30 μπιοΐ / min, TMA1 25 μιηο1 / πτάη and atmosphere 3 1 / min is introduced to grow the aluminum gallium nitride crystal core 261. Next, the temperature was adjusted to 580 ° C, and a mixed gas including TMA1 25 μπιοΐ / min, 20 pmol / minTMIn, and ammonia gas 2.5 I / min was introduced to grow the aluminum indium nitride nuclei 262. The multiple crystal nuclei 261 and 262 are about 65 people thick. Then, adjust the temperature to the range of 400t to 1000 ° C, and introduce 4EPITAXY / 200006TW including TMGa 30 μιηοΐ / min and the atmosphere 2 Ι / min. 14 This paper is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm). (Li) ---------— 丨 Loading ------- Ordering! (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 584903 A7 B7 V. Description of the invention (Introduction) Mix gas to grow 200 A thick gallium nitride differential emission suppression layer 3 on the multiple crystal nuclei 2. Then, the temperature was raised to 1120 ° C, and a mixed gas containing TMGa 52 μπιοΐ / min and ammonia 3 1 / min was introduced to grow a 2 μιη undoped gallium nitride on the aluminum gallium nitride differential emission suppression layer 3.嘉 晶 层 4。 Jia crystal layer 4. Sixth Embodiment Please refer to FIG. 9, which is a schematic diagram of a light emitting semiconductor device 70. The light emitting semiconductor device 70 is, for example, a light emitting diode (LED). An epitaxially grown alumina substrate 1 is loaded in an organometallic vapor phase epitaxial growth reactor (not shown). The substrate 1 may be made of alumina, silicon carbide or gallium arsenide. At a temperature of 1150 ° C, 5 l / min hydrogen gas was introduced to rinse the wafer surface for 10 minutes. Then reduce the temperature to a temperature range of about 400 ° C to 1000X :, introduce a mixed gas containing TMA1 50 μιηοΐ / min and ammonia 2 Ι / min to grow the aluminum nitride crystal core 271. The preferred growth temperature of the crystal nuclei 271 is 530 ° C. Then, a mixed gas containing TMi 55 μηηΐ / min and ammonia 3 1 / min is introduced to grow indium nitride crystal nuclei 272. The preferred growth temperature of the indium nitride crystal core 272 is 620 ° C. The multiple crystal nuclei 271 and 272 are approximately 45A thick. Then, the temperature of the wafer was lowered to a temperature range of about 400 ° C to 1000 ° C, and a mixed gas including TMGa 20 μιηοΐ / πιίη, TMA1 25 μηιο1 / πήη and ammonia gas at 2.5 1 / min was introduced to multiplex the nuclei. The upper layer 2 has an aluminum gallium nitride (AlyGai_yN, OSyS 1) differential emission suppression layer 3 with a thickness between about 100 A and 500 A. The preferred growth temperature and preferred thickness of the differential emission suppression layer 3 are 570 ° C and 320A, respectively. Then, raise the temperature to 1130 ° C and introduce TMGa 52 μπιοΐ / min and 3 · 5 4EPITAXY / 200006TW 15 ^ 5 long scale to apply Chinese National Standard (CNS) A4 specification (210 X 297 mm 1 --- ------- Installation -------- Order --------- (Please read the note on the back? Matters before filling out this page) 584903 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Production of A7 B7 V. Description of the invention (\ (α) 1 / min ammonia gas and 100 ppm SiH4 / H2 mixed gas, grow 4 μm thick η-type gallium nitride cladding layer on the differential emission suppression layer 3 ) 5. An example of the cladding layer 5 is AlwInzGai-w-zN, 1, 0Sz $ l, 0 $ w + z $ 1, and then the temperature is adjusted to about 850 ° C, and TMGa 30 μπιοΐ / min is introduced. , TMIn 30 μπιοΐ / min and 3.5 1 / min ammonia gas mixture. By controlling the output of TMIn, multiple pairs (for example, 5 pairs) of indium gallium nitride / nitrogen are formed on the n-type gallium nitride coating 5 The multiple quantum well-MQW layer 6 of gallium is used as a light emitting active layer. Then the temperature is increased to about 1100 ° C, and TMGa is introduced. A mixed gas of 42 μπιοΐ / min, TMA1 20 μηιοΐ / min, ammonia 3.5 Ι / min, and DCpMg 52 nmol / min was coated with a P-type aluminum gallium nitride with a thickness of about 0.2 μηη on the multiple quantum well structure layer 6 Layer 7. An example of the cladding layer 7 is AlsIntGai + tN, OgsS 1,1, OSs + tS 1. Then the wafer is heated to about 1130 ° C and introduced with TMGa 52 μΓΠθΙ / min, ammonia gas 3.5 Ι / min and DCpMg 52 nmol / min mixed gas to grow a p-type gallium nitride electrode layer 8 with a thickness of about 0.3 μm on the p-type aluminum gallium nitride cladding layer 7. An example of the electrode layer 8 is AluInvGa ^ u-vN, among which OSuSl, OSvSl, OS u + vS 1 0— LED structure epitaxial wafer is completed in this way. After the above epitaxial wafer is activated, it is then made into chips according to the following steps. Step one: Part of the P-type electrode layer 8, the ρ-type cladding layer 7, and the multiple quantum 4EPITAXY / 200006TW 16 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ---- I ----- J ^ wi I -------- ^ · 11111111. (Please read the Zhuyin on the back? Please fill out this page again) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 584903 A7 B7 V. Description of the invention (ii) The well structure layer 6 is removed to expose the surface of the n-type gallium nitride coating layer 5. Step 2: deposit a nickel / gold (Ni / Au) ohmic contact metal layer 9 on the p-type gallium nitride electrode layer 8. Step 3: Deposit a Ti / Al ohmic contact metal layer 11 on the n-type gallium nitride cladding layer 5. Step 4: Saw the wafer into a plurality of 350 μm X 350 μm square grains. The forward voltage of the above-mentioned light-emitting diode grains at 20 mA is about 3.5 volts. Seventh Embodiment Please refer to FIG. 10, which is a schematic diagram of a light emitting semiconductor device 80. The light emitting semiconductor device 80 may be, for example, a light emitting diode. An oxidized brominated substrate 1 for growth of keraxite was loaded in an organometallic vapor phase growth reactor (not shown). The substrate 1 may be made of alumina, silicon carbide or gallium arsenide. At a temperature of 150 ° C, 5 l / min hydrogen was introduced to rinse the wafer surface for 10 minutes. Then, the temperature was lowered to a temperature range between about 400 ° C. and 1000 C, and a mixed gas containing 25 μπιπ / min of TMIn and 3 1 / min of ammonia gas was introduced to grow the indium nitride crystal core 281. The preferred growth temperature of the crystal nuclei 281 is 620 ° C. Then, a mixed gas containing TMGa 45 μιηοΐ / min, TMA1 35 μηιοmin / min, and ammonia 3 1 / min was introduced to grow the aluminum gallium nitride nuclei 282. The preferred growth temperature of the crystal nuclei 282 is 550 ° C. The multiple crystal nuclei 281 and 282 are about 60A thick. Then, the chip 4EPITAXY / 200006TW ι7 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page). Install --- — — — — — Order · 111 584903 Α7 Β7 V. Description of the invention (α) (Please read the precautions on the back before filling this page) Adjust the temperature to the temperature range between 400 ° C and 1000 ° C 'and import TMGa 35 μπιοΐ / min And an ammonia gas mixture of 2.5 I / min to grow a gallium nitride differential suppression layer 3 (AlyGa! _YN, 0'yS 1) with a thickness of 100A to 500A on the multiple crystal nuclei 2. ). The preferred growth temperature and the preferred thickness of the differential emission suppression layer 3 are 510 ° C and 250A, respectively. Then raise the temperature to about 1130 ° C and introduce a mixed gas containing TMGa 52 μηιοΐ / min, ammonia gas 3.5 1 / min, and DCpMg 52 nmol / min to grow a 4 μπι thick p on the differential emission suppression layer 3. Type gallium nitride cladding layer 5. An example of the cladding layer 5 is AUIrizGa ^ w-zN, where 0 $ w ′ 1, 0 ′ z g 1, and 0 S w + z S 1. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, the temperature was lowered to about 850 ° C, and a mixed gas containing TMGa 30 μπιοΐ / min, TMIn 30 μιηοΐ / min, and ammonia 3.5 · 1 / min was introduced. By controlling the output of TMIri, a multiple quantum well structure layer 6 including multiple pairs (for example, 5 pairs) of indium gallium nitride / gallium nitride can be grown on the p-type gallium nitride cladding layer 5 as a light emitting active layer . Then the wafer was heated up to 1130 ° C, and a mixed gas containing TMGa 52 μιηοΐ / min, 3.5 1 / min ammonia gas and 100 ppm SiH4 / H2 was introduced to grow 0.5 μπι thick η on the multiple quantum well structure layer 6. Type gallium nitride layer 8. The n-type gallium nitride layer 8 also serves as a cladding layer of the multiple quantum well structure layer 6 and an electrode layer of the light emitting diode 80. An LED structure wafer is completed in this way. After the above-mentioned Jia wafer is subjected to activation treatment, a chip is formed according to the following steps. Step 1: Remove a part of the n-type gallium nitride layer 8 and the multiple quantum well structure layer 6 to expose the surface of the p-type gallium nitride cladding layer 5. 4EPITAXY / 200006TW 〇 This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 584903 A7 __B7 V. Description of the invention (q) Step 2: Deposit a nickel / gold ohmic contact metal layer 9 in p-type On the gallium nitride cladding layer 5. (Please read the precautions on the back before filling this page) Step 3: Deposit a Ti / Al ohmic contact metal layer 11 on the n-type GaN layer 8. Step 4: Saw the wafer into a plurality of 350 μm × 350 μm square grains. The above-mentioned light-emitting diode grains have a forward voltage of about 3.5 volts at 20 mA. Eighth Embodiment Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economics Please refer to FIG. 11, which is a schematic diagram of a light-emitting semiconductor device 90. The light emitting semiconductor device 90 may be, for example, a light emitting diode. First, an alumina substrate 1 grown by a regal crystal is loaded in an organometallic vapor phase epitaxial growth reactor (not shown). The substrate 1 may be made of alumina, silicon carbide or gallium arsenide. At a temperature of 1150 ° C, 5 l / min hydrogen gas was introduced to rinse the wafer surface for 10 minutes. Then reduce the temperature to about 40 ° C to 1000 ° C, and introduce a mixed gas containing TMGa 45 μπιοΐ / min, TMIn 40 μπΐ () 1 / ιηίη, and ammonia 3 1 / min to grow indium nitride Gallium nuclei 291. The preferred growth temperature of this nuclei 291 is 57 ° C. Then a mixed gas containing TMA1 50 μπιοΙ / min'TMIn 40 μπιοΐ / min and ammonia gas 3 Ι / min is introduced to grow aluminum indium nitride. Crystal nucleus 292. The preferred growth temperature of the crystal nucleus 292 is 570 ° C. The multiple crystal nucleus 291 and 292 are approximately 50A thick. Then, the wafer temperature is adjusted to a temperature range between 400 ° C and 1000 ° C, and introduced TMGa 20 μιηοΐ / min, TMA1 25 μπιοΐ / min 4EPITAXY / 200006TW 19 This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 584903 Α7 Β7 V. Invention Explain Uo) and a mixed gas of 2.5 l / min of ammonia gas to grow an aluminum gallium nitride differential emission suppression layer 3 with a thickness between 100 A and 500 A on the multiple crystal nuclei 2. The better of the differential emission suppression layer 3 is better The growth temperature and the preferred thickness are 550 ° C and 320 persons, respectively. After that, the temperature was increased to about 130 ° C 'and a mixed gas containing TMGa 52 pmol / inin, ammonia gas 3.5 l / min, and SiH4 / H2 100 ppm / min was introduced to the differential emission suppression layer 3 A 4 μm thick n-type gallium nitride cladding layer 5 was grown thereon. Then, the temperature was lowered to about 850 ° C. and introduced with TMGa 30 μπιοΐ / min, TMIn 30 μπιοΐ / min, and 3.5 l / min ammonia. By controlling the output of TMI, a multiple quantum well structure layer 6 including multiple pairs (for example, 5 pairs) of indium gallium nitride / gallium nitride can be formed on the n-type gallium nitride cladding layer 5 to As a light-emitting active layer. Then raise the temperature to 1100 ° C and introduce a mixed gas containing TMGa 42 μηιοΐ / min, TM1 20 μπιοΐ / min, ammonia 3.5 · l / min, and DCpMg 52nmol / min. A 0.2 μm thick p-type aluminum gallium nitride cladding layer 7 was grown on the multiple quantum well structure layer 6. Then, the temperature was raised to about 1130 ° C, and TMGa 52 μηι / min, ammonia gas 3.5 · / min and DCpMg 52nmol / min mixed gas to grow 0.3 μm thick p-type on p-type aluminum gallium nitride cladding layer 7 Gallium electrode layer 8. An LED structure wafer is completed in this way. After the above Chia wafer is subjected to an activation treatment, a crystal grain is formed according to the following steps. Step 1: Remove part of the P-type electrode layer 8, the p-type cladding layer 7 and the multiple quantum well structure layer 6 to expose the surface of the n-type gallium nitride cladding layer 5
4EPITAXY/200006TW 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------裝--------訂--------- MT (請先閱讀背面之注意事項再填寫本頁) 584903 A7 B7 五、發明說明（J) 來。 (請先閱讀背面之注咅？事項再填寫本頁) 步驟二：沉積一鎳/金歐姆接觸金屬層9在p型氮化鎵電 極層8上。 步驟三：沉積一鈦/鋁歐姆接觸金屬層11於η型氮化鎵包 覆層5上。 步驟四：將晶圓鋸切成複數個350 μπι X 350 μηι之正方形 晶粒。 上述之發光二極體晶粒，在20mA時的順向電壓約爲 3.5伏特。 以上所述僅爲本發明之較佳實施例。凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明所涵蓋之 範圍。 經濟部智慧財產局員工消費合作社印製 4EPITAXY/200006TW 21 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）4EPITAXY / 200006TW This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ---------- installation -------- order -------- -MT (Please read the notes on the back before filling this page) 584903 A7 B7 V. Description of the invention (J). (Please read the note on the back? Matters before filling out this page) Step 2: Deposit a nickel / gold ohmic contact metal layer 9 on the p-type GaN electrode layer 8. Step 3: Deposit a titanium / aluminum ohmic contact metal layer 11 on the n-type gallium nitride coating layer 5. Step 4: Saw the wafer into a plurality of 350 μm X 350 μm square grains. The above-mentioned light-emitting diode grains have a forward voltage of about 3.5 volts at 20 mA. What has been described above are only preferred embodiments of the present invention. All equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4EPITAXY / 200006TW 21 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)