TW582090B - Structure with tapered landing and method of fabrication - Google Patents
Structure with tapered landing and method of fabrication Download PDFInfo
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- TW582090B TW582090B TW090121454A TW90121454A TW582090B TW 582090 B TW582090 B TW 582090B TW 090121454 A TW090121454 A TW 090121454A TW 90121454 A TW90121454 A TW 90121454A TW 582090 B TW582090 B TW 582090B
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- 238000004519 manufacturing process Methods 0.000 title description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 27
- 210000000746 body region Anatomy 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 230000000630 rising effect Effects 0.000 claims abstract description 3
- 238000000059 patterning Methods 0.000 claims abstract 2
- 239000004020 conductor Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 2
- 238000003860 storage Methods 0.000 claims description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims 2
- 229910052697 platinum Inorganic materials 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 description 26
- 239000002184 metal Substances 0.000 description 26
- 239000012212 insulator Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- -1 copper) Chemical class 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- ZHPNWZCWUUJAJC-UHFFFAOYSA-N fluorosilicon Chemical compound [Si]F ZHPNWZCWUUJAJC-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- WQLQSBNFVQMAKD-UHFFFAOYSA-N methane;silicon Chemical compound C.[Si] WQLQSBNFVQMAKD-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
582090 A7 B7582090 A7 B7
五、發明説明（1 ) 發明領域 一般而言，本發明用於半導體製造並且，進一步特別 地，有關一積體電路和一相關的製造方法。 ’ 發明背景 在任何製造過程中，簡單化為一優點。因而，一半導體 製造方法十分偏好可達到相同或較佳品質產品以相同= 料成本而使用較少步驟，特別是當減少製造步驟而減少 人工成本和製造時間。這特別是真的，當導入一新的妗 構到一製造過程需要額外的遮罩運作。遮罩運作的數目 的減少可使設備上的投資能有進一步高的產出率。 電容器廣泛地使用在電子裝置内供電荷儲存。該電容器 必要地包括二導電板，由一絕緣體分離。該電容量，戈 該電容器每應用電壓所持有的電荷量，視薄板的面積， 該薄板之-間的距離，和該絕緣體的介電質值而定。使用 電容器在濾波器，類比至數位轉換器，數位記憶體裝 置，和各種控制應用。 在積體電路中加入電容器需要额外的遮罩運作。特別 疋’當金屬技術從負金屬蚀刻（傳統用於形成銘線）過渡到 嵌刻（Damascene)系統（使用例如銅等的金屬），若不施加 額外的遮罩運作的話，整合電容器變得因難。故偏好提 供一較簡單的方法供電容器整合，以便減少製造成本。 發明之簡要說明 現在提供一多層結構’在該發明的一種形式，包括一基 材，一元件形成於該基材之上和一連接元件。該元件包 •5- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 582090 A7 _ B7 五、發明説明（2~" --- 括一主體區域及一具有一厚部份鄰接該主體區域錐形連 接’一薄部份從遠厚部份延件出以及在該厚部份和該薄 部份之上表面。該連接元件與錐形連接的表面有實體的 接觸並且從該錐形連接延伸出來。 在本發明之一替代形式中，一元件形成於一基材上包括 一主體區域和一錐形連接，具有一厚部份鄰接該主體區 域，一薄部份從該厚部份延伸出以及在該厚部份和該薄 部份之上表面^ 在一相關方法中，形成一實例結構透過將第一層材料沉 積於一第一表面之上，將該層圖樣化以定義一特色並且 I虫刻該層以定義該特色之第一區域具有第一厚度和一第 二區域鄰接該第一區域，以及從該第一區域延伸出厚度 遞減的第二區域直到該第二區域終止。在本發明之一具 體實施例中，可能在該第一層上形成額外的層，以形成 一導體結構。 附圖之簡要說明 閱讀下列詳細的描述與相關附圖時，本發明之優點將很 明顯，其中： -圖1到5圖示，本發明之一具體實施例，在一半導體裝 置内形成一導體結構；及 圖6圖示本發明實例應用中金屬層厚度和連接角度的關 係。 詳細的敘述 參考圖1 ’本發明敘述相關於在一半導體裝置内範例的 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 582090V. Description of the Invention (1) Field of the Invention Generally, the present invention is used in semiconductor manufacturing and, more particularly, relates to an integrated circuit and a related manufacturing method. BACKGROUND OF THE INVENTION Simplification is an advantage in any manufacturing process. Therefore, a semiconductor manufacturing method is very likely to achieve the same or better quality products with the same material cost and use fewer steps, especially when reducing the manufacturing steps to reduce labor costs and manufacturing time. This is especially true when introducing a new structure into a manufacturing process that requires additional masking operations. The reduction in the number of mask operations allows for a further higher yield on investment in equipment. Capacitors are widely used in electronic devices for charge storage. The capacitor necessarily includes two conductive plates separated by an insulator. The capacitance, the amount of charge held by the capacitor per applied voltage, depends on the area of the sheets, the distance between the sheets, and the dielectric value of the insulator. Use capacitors in filters, analog-to-digital converters, digital memory devices, and various control applications. Adding capacitors to integrated circuits requires additional masking operations. In particular, when metal technology transitions from negative metal etching (conventionally used to form inscription lines) to Damascene systems (using metals such as copper), the integration of capacitors becomes a problem if no additional masking is used difficult. Therefore, it is preferred to provide a simpler method for power container integration in order to reduce manufacturing costs. Brief Description of the Invention A multilayer structure 'is now provided in one form of the invention including a substrate, an element formed on the substrate, and a connecting element. This component package • 5- This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 582090 A7 _ B7 V. Description of the invention (2 ~ " --- Including a main area and a thick part Adjacent to the main body area, a thin portion extends from the far thick portion and a surface above the thick portion and the thin portion. The connecting element has a physical contact with the surface of the tapered connection and starts from The tapered connection extends. In an alternative form of the invention, a component formed on a substrate includes a body region and a tapered connection, having a thick portion adjacent to the body region, and a thin portion extending from the The thick portion extends and the surface above the thick portion and the thin portion ^ In a related method, an example structure is formed by depositing a first layer of material on a first surface to pattern the layer To define a feature and to inscribe the layer to define the feature, the first region has a first thickness and a second region is adjacent to the first region, and a second region of decreasing thickness extends from the first region until the first region. Termination of two zones. In the present invention In a specific embodiment, an additional layer may be formed on the first layer to form a conductor structure. Brief Description of the Drawings The advantages of the present invention will be apparent when reading the following detailed description and related drawings, among which: -Figures 1 to 5 illustrate a specific embodiment of the present invention to form a conductor structure in a semiconductor device; and Figure 6 illustrates the relationship between the thickness of the metal layer and the connection angle in the application of the example of the present invention. 1 'The description of the present invention is related to the example of a semiconductor device-6-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 582090
電容器結構形成於一多層互連系統的形成及連接。圖示 積目这包路結構1 〇心相關部份的部份橫斷面以提供有關 將本發明併人_金屬化結構中的細節。在此實例中，該 金屬化結構形成於-半導體層之上（未圖示），通常會有複 數個甩谷器/口著其表面形成。在所圖示的具體實施例 中，根據一標準且週知的雙嵌刻（t)amascene)製造程序， 銅互連的數個較上階層形成於一半導體層。有關嵌刻 (Damascene)結構的形成細節為，例如，cw Kaanta及其 他所敘述之”雙嵌刻（Dual Damascene ): A ULSI繞線技術， ” 1991年國際電機及電子工程師協會超大型積體電路多階 層互連會議，第144頁。也請參考於2〇〇〇年國際互連技術 會議中，E. Barth及其他所著，第219頁”整合銅及氟化矽 玻璃以0.18微米互連’·。 如圖1所示，該積體電路結構1 〇原本包括嵌刻 (Damascene)金屬的二階層。一金屬的下階層2〇包括一實 例導體元件22形成於一通孔部份24之上。金屬的第二階 層30包括一導體元件32形成於一通孔部份34之上。該通 孔部份3 4穿透一矽氮阻隔層3 6，以元件2 2連接元件3 2。 氮化矽的第二層3 8形成於該金屬的第二階層3 〇之上 介電質層40隔離導體元件22及通孔部份24從形成在相同 的階層20的其它金屬區域。類似地，一介電質層42電予 地隔離該導體元件32及通孔部份34從在階層30的其它金 屬結構。 參考圖2，一金屬-絕緣體-金屬堆疊4 4係沉積於氮化令The capacitor structure is formed during the formation and connection of a multilayer interconnection system. A cross section of the relevant part of the package structure 10 is shown in the figure to provide details on incorporating the invention into a metallized structure. In this example, the metallization structure is formed on the -semiconductor layer (not shown), and usually a plurality of threshing devices / mouths are formed along its surface. In the illustrated embodiment, several higher-level copper interconnects are formed in a semiconductor layer according to a standard and well-known dual-amascene manufacturing process. Details of the formation of the Damascene structure are, for example, cw Kaanta and other described "Dual Damascene: A ULSI winding technology," 1991 International Institute of Electrical and Electronics Engineers ultra-large integrated circuit Multi-level Interconnection Conference, p. 144. Please also refer to the 2000 International Conference on Interconnection Technology, E. Barth and others, page 219, "Integrating Copper and Fluoro-Silicon Glass to Interconnect at 0.18 microns". As shown in Figure 1, this The integrated circuit structure 10 originally included two levels of Damascene metal. The lower level 20 of a metal includes an example conductor element 22 formed on a through-hole portion 24. The second level 30 of metal includes a conductor The element 32 is formed on a through-hole portion 34. The through-hole portion 34 penetrates a silicon-nitrogen barrier layer 36, and is connected to the element 32 by the element 22. A second layer 38 of silicon nitride is formed on the The second layer 30 of the metal above the dielectric layer 40 isolates the conductive element 22 and the via portion 24 from other metal regions formed in the same layer 20. Similarly, a dielectric layer 42 electrically isolates the The conductor element 32 and the through-hole portion 34 are from other metal structures at the level 30. Referring to Fig. 2, a metal-insulator-metal stack 4 4 is deposited in a nitrided order
本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582090 A7 B7This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 582090 A7 B7
層38之上，並且與光阻層48_起圖樣化以定義—*容器 結構。該堆疊包括第一導電層5〇沉積在氮化碎層"Μ之 上，一絕緣層52沉積在導電層5〇之上及—第二導電居w 沉積在絕緣體層52之上。堆叠可能從一不同材料的^人 變化所形L導電層50及54可能是2〇〇毫微米二 濺鍍銘，及絕緣體層52可能是從矽甲烷氣體藉由低壓化 學氣相沉積（LPCVD)的25 to 40毫微米的氧化矽沉積。可 選擇地，該鋁層50可能是3 6 0毫微米（nm)厚及該層“可 能是以40毫微米（nm)的氮化鈦（TiN)所形成的。代換的 材料也可選擇作為絕緣體層52，譬如氧化钽（Ta〇5)。 將該光阻層48圖樣化以定義每一個電容器薄板的有效 區域及插進的介電質。由於光阻在適當的位置，該堆叠 4 4以一南聚合物金屬蚀刻化學較佳地被姓刻，光阻層4 $ 所定義在該堆疊之外的區域產生錐形特色。請參考圖3所 做的說明，在移除該光阻，一範例的電容器結構6 〇在一 絕緣體層64之上及在一下導電層66之上具有一上導電層 62。該整個層62充作該較高電容器薄板。該層66的一部 伤’稱為68 ’延仲出該層62 ’而該層66的内部薄板區域 7 0實質上係與該·層6 2共同延伸。該薄板區域7 〇充作該層 66的一部份，其功能係與層62 —起儲存電荷。從圖3中 可看該區域6 8係延件自薄板區域7 0，起先有一厚的部份 7 2，然後逐漸縮小成相對薄部份7 4，並且在那之後終 止。 一般而言，該區域68可視為一錐形連接。一表面區域 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 582090 A7 B7Above layer 38 and patterned with photoresist layer 48 to define— * container structure. The stack includes a first conductive layer 50 deposited on the nitrided layer " M, an insulating layer 52 deposited on the conductive layer 50 and a second conductive layer w deposited on the insulator layer 52. The stack may be changed from a different material. The L conductive layers 50 and 54 may be 2000 nanometers, and the insulator layer 52 may be a silicon methane gas by low pressure chemical vapor deposition (LPCVD). 25 to 40 nm silicon oxide deposition. Alternatively, the aluminum layer 50 may be 360 nanometers (nm) thick and the layer "may be formed of 40 nanometers (nm) titanium nitride (TiN). Substituted materials may also be selected As the insulator layer 52, such as tantalum oxide (TaO5). The photoresist layer 48 is patterned to define the effective area of each capacitor thin plate and the dielectric substance inserted. Since the photoresist is in place, the stack 4 4 The polymer etch chemistry of a polymer is preferably engraved by the last name. The photoresist layer 4 $ defines a tapered feature outside the stack. Please refer to the description made in Figure 3 to remove the photoresist. An exemplary capacitor structure 60 has an upper conductive layer 62 above an insulator layer 64 and above the lower conductive layer 66. The entire layer 62 serves as the higher capacitor sheet. A portion of this layer 66 is injured ' Called 68 'extend the layer 62' and the inner sheet area 70 of the layer 66 is essentially coextensive with the layer 62. The sheet area 70 serves as a part of the layer 66 and its function The system and the layer 62 store the charge together. From this figure, it can be seen that the area 6 and 8 are extended from the sheet area 70, and there is an The part 7 2 is then gradually reduced to a relatively thin part 7 4 and ends after that. Generally speaking, the area 68 can be regarded as a conical connection. A surface area -8- This paper size applies to Chinese national standards (CNS) A4 size (210X 297 mm) 582090 A7 B7
76從該厚部份延伸出，並且在該薄部份終止，定義_錐 形連接表面。該錐形連接表面7 6從氮化矽層3 8的較高表 面78升起，並且直到或超過該厚部份72。隨著該表面78 上升至該表面76，其可變斜率的特徵為從終止於該表面 78上位置80的錐形連接與直到最大厚度的該區域82之間 的平均上升角度。相對於氮化碎表面78，該表面76的斜 率將影響是否該表面76能適於充當與尚未形成元件接觸 的連接區域。 改良一各向異性的蝕刻化學以分授一傾斜輪廓至該蝕刻 金屬而達成該表面76的偏妤斜率。可應用表1的該錐形蚀 刻公式以定義如在圖中所示的該整個電容器結構6 〇 ^或 者，該蝕刻可為如表1中所說明的二步騾順序。亦即，可 能使用一實例的主要（垂直）蝕刻來定義具有相當直的邊牆 (未圖示）的該導體薄板層62，一旦穿透至該絕緣層64内 或在#刻該層6 4期間，在該情況下該公式被改良成該錐 形蚀刻公式。然而，若該蚀刻情況在材料從該絕緣體6 4 移除期間改良成該範例的錐形蝕刻，則一旦穿透，該整 層66又依循表1的錐形蚀刻。 表176 extends from the thick portion and terminates at the thin portion, defining a conical connection surface. The tapered connection surface 76 is raised from the higher surface 78 of the silicon nitride layer 38, and reaches or exceeds the thick portion 72. As the surface 78 rises to the surface 76, its variable slope is characterized by an average rising angle from a conical connection terminating at position 80 on the surface 78 to the region 82 up to the maximum thickness. The slope of the surface 76 relative to the nitrided surface 78 will affect whether the surface 76 can be adapted to serve as a connection area with which a component has not yet been formed. An anisotropic etching chemistry is modified to impart a slanted profile to the etched metal to achieve the skew slope of the surface 76. The tapered etching formula of Table 1 can be applied to define the entire capacitor structure as shown in the figure, or the etching can be a two-step 骡 sequence as illustrated in Table 1. That is, it is possible to use an example of a main (vertical) etch to define the conductor sheet layer 62 with a fairly straight side wall (not shown), once it penetrates into the insulating layer 64 or #etches the layer 6 4 Meanwhile, in this case, the formula is modified to the tapered etching formula. However, if the etching condition is modified to the tapered etch of this example during the removal of the material from the insulator 64, the entire layer 66 follows the tapered etch of Table 1 once it penetrates. Table 1
主要（垂直的） 錐形蝕刻 10 16 mtorr 80 60 C12 40 60 BC13 7 15 N2 500 W 400W 150 W 200W -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂Main (vertical) tapered etching 10 16 mtorr 80 60 C12 40 60 BC13 7 15 N2 500 W 400W 150 W 200W -9- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding
k 582090 A7 -------- Β7 五、發明説明（6 ) 在過去，已知鋁蝕刻化學會產生在垂直方向上輪廓的偏 差。與如本發明之較佳輪廓相較的話，此偏差已相當 小，並且已視為較不想要的特色，特別是在互連結構中 形成導電元件時。請參考：1996年6月1 8到2 0曰VMIC研 討會論文集中由Mautz所著之”單一晶圓及批次金屬蝕刻 製造程序的特色 ”（ISMICM06/96/0524(c)) ; SPIE 第 2875 冊’第301到311頁Gonzales及其他所著之”次微米金屬 蚀刻整合研究”；及SPIE第2875冊，第3 1 2到3 2 1頁由 Youn及其他所著之”在次半微米鋁蝕刻内微載 (Microloading)上程序參數的效果”。 連接意義為一材料的區域適合以一其它材料的不連續區 段供接受實體的接觸。在此所使用的名詞連接角度意義 為該表面7 6的整個斜面相對於該氮化梦層3 8的表面的平 均角度。-進一步進一步，連接角度意義為一斜率表面相 對於其相對地水平表面的底層的平均角度。 以電容器60所定義，介電質的第三層84是完全沉積於 其上。參考圖4。其次，如標準雙嵌刻（Duai Damasane) 程序（參考圖5 )，該層8 4係圖樣化及蝕刻以定義一金屬階 層90，金屬階層90包括導體部份92a和92b和一通孔部 份9 4。圖5也圖示整個形成於該一雙嵌刻（Duai Damascene ) 金屬階層90内的該已完成電容器結構60。 一氮化矽層96形成在金屬階層90之上和額外通孔部份 98的覆蓋其上的金屬階層延件通過該氮化碎層96的開口 以接觸導體部份92a和92b。每一個通孔部份98連接覆蓋 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) A7 B7k 582090 A7 -------- B7 V. Description of the invention (6) In the past, it is known that aluminum etching chemistry will produce deviations in the profile in the vertical direction. This deviation is already relatively small compared to the preferred profile of the invention, and has been considered a less desirable feature, especially when forming conductive elements in interconnect structures. Please refer to: "Features of Single Wafer and Batch Metal Etch Manufacturing Process" by Mautz, June 18-20, 1996, VMIC Conference Papers (ISMICM06 / 96/0524 (c)); SPIE Chapter Book 2875, "Gonzales and others," Research on the Integration of Submicron Metal Etching, "pages 301 to 311; and SPIE Book 2875, pages 3 1 2 to 3 21," by Youn and others " "Effects of program parameters on microloading in aluminum etching." The meaning of connection is that a region of one material is suitable for contacting a receiving entity with a discontinuous section of another material. The term "joint angle" as used herein means the average angle of the entire slope of the surface 76 with respect to the surface of the nitride nitride layer 38. -Further, the connection angle means the average angle of a slope surface relative to the bottom layer of its relatively horizontal surface. As defined by capacitor 60, a third layer 84 of dielectric is completely deposited thereon. Refer to Figure 4. Secondly, as in the standard Duai Damasane procedure (refer to Figure 5), this layer 8 4 is patterned and etched to define a metal layer 90, which includes conductor portions 92a and 92b and a via portion 9 4. FIG. 5 also illustrates the completed capacitor structure 60 formed entirely within the Duai Damascene metal layer 90. A silicon nitride layer 96 is formed on the metal layer 90 and a metal layer extension covering the additional via portion 98 passes through the opening of the nitride layer 96 to contact the conductor portions 92a and 92b. Each through hole part 98 connection cover -10- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) A7 B7
582090 五、發明説明（7 其上的導體元件（未圖示）。 在元成結構1 0該上導電層6 2 (該上端電容器薄板）連接 經過導體部份92b和一通孔部份98以提供對該電容器的 第一接觸。金屬階層90的通孔部份94是一導電元件接觸 該錐形連接區域68(圖3)以連接該導電層66(下電容器薄 板）經由導醴部份92a和一通孔部份98(另一導電元件）以 提供第二接觸供該電容器結構6〇。 該導電層66的薄板區域70可能的厚度範圍是介於2〇〇 及400毫微米（nm)之間及可能是以鋁形成。圖6說明該鋁 的厚度範圍相當的連接角度以適合供蝕刻一通孔部份接 點，亦即；如圖5的通孔部份9 4，以1 0 〇亳微米（n m )的 完全覆蓋容忍度。典型上，該通孔部份導電元件的直徑 可能範圍介於200毫微米（nm)及300毫微米（nm)之間。 特別地，_用200毫微米（nm)厚度的薄板區域70需要該錐 形區域68的連接角度範圍介於60度及65度之間。當該薄 板部份70的厚度是400毫微米（nm)，該連接角度範圍增 至大約在75度。一大約70度的連接角度，亦即，適於該 4 0 0毫微米（n m )厚的實例，能以表1的主要蝕刻化學所達 成。該表1的錐形蝕刻化學提供一較小的連接角度，亦 即，以達到較大的連接表面7 6。這很有用對於在薄的金 屬層内建立足夠的連接表面。 該說明的較佳具體實例的特色是以單一遮罩階層所形成 的電容器結構。亦即，透過建立一錐形連接是可能以一 整合的錐形連接部份在遮罩和蝕刻步騾中同時地定義該 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 装 訂582090 V. Description of the invention (7 conductor elements (not shown) thereon. In the element structure 10, the upper conductive layer 6 2 (the upper capacitor thin plate) is connected through the conductor portion 92b and a through hole portion 98 to provide First contact to the capacitor. The through-hole portion 94 of the metal layer 90 is a conductive element contacting the tapered connection region 68 (FIG. 3) to connect the conductive layer 66 (lower capacitor plate) via the conductive portion 92a and A through hole portion 98 (another conductive element) to provide a second contact for the capacitor structure 60. The possible thickness of the thin plate region 70 of the conductive layer 66 is between 200 and 400 nanometers (nm) It may be formed of aluminum. Fig. 6 illustrates that the thickness range of the aluminum is equivalent to the connection angle suitable for etching a contact portion of a through hole, that is, the through hole portion 94 of Fig. 5 is 100 micrometers. (Nm) full coverage tolerance. Typically, the diameter of the conductive element of the through hole may range between 200 nanometers (nm) and 300 nanometers (nm). In particular, 200 nanometers ( nm) thickness of the thin plate region 70 requires a connection angle range of the tapered region 68 Between 60 degrees and 65 degrees. When the thickness of the thin plate portion 70 is 400 nanometers (nm), the connection angle range is increased to about 75 degrees. A connection angle of about 70 degrees, that is, suitable for This 400 nanometer (nm) thick example can be achieved with the main etch chemistry of Table 1. The tapered etch chemistry of Table 1 provides a smaller connection angle, that is, to achieve a larger connection surface 7 6. This is useful for establishing a sufficient connection surface in a thin metal layer. The preferred specific example of this description features a capacitor structure formed by a single mask layer. That is, by establishing a tapered connection is It is possible to define the -11 simultaneously in the mask and the etching step with an integrated tapered connection part-this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) binding
582090 A7 B7 五、發明説明（8 ) 薄板區域而同時形成一接觸至該上端電容器的薄板。雖 然該說明是基於一個雙嵌刻（Dual Damascene )金屬架構及 範例的電容器材料，數種其它金屬技術及材料同樣適 合。此外，以一進一步普通的形式，本發明提供形成一 結構具有一主體區域的一結構和一方法，亦即，薄板區 域7 0，連接至一單獨定義的元件，亦即，一通孔部份， 透過一錐形區域。此結構可能很有用對其它的電子連接 和機械連接。 已說明一架構與其相關製造方法，這對形成具有簡化遮 罩步騾的結構很有用。如較佳具體實施例，應用這些原 理將確保能以簡化方式形成機械或電子結構。雖已說明 本發明之特定應用，在此所揭露之原理提供以各種方法 將本發明實現於包括半導體裝置之各種結構之基礎，並 且很明顯、也會有許多種應用。因而，其它不偏離本發明 範疇之架構，雖然未特別地在此敘述，也將受到以下申 請專利範圍所限制。 圖式元件符號說明 10積體電路結構 20金屬的較低的階層 22導體元件 24通孔部份 30金屬的第二階層 32導體元件 34通孔部份 36矽氮阻隔層 38第二層 40介電質層 42介電質層 44金屬-絕緣體-金屬堆疊582090 A7 B7 V. Description of the invention (8) A thin plate area is simultaneously formed with a thin plate contacting the upper capacitor. Although the description is based on a dual damascene metal structure and exemplary capacitor materials, several other metal technologies and materials are equally suitable. In addition, in a further general form, the present invention provides a structure and a method of forming a structure with a body region, that is, a thin plate region 70, connected to a separately defined element, that is, a through-hole portion, Through a conical area. This structure may be useful for other electrical and mechanical connections. An architecture and its associated manufacturing methods have been described, which are useful for forming structures with simplified mask steps. As in the preferred embodiment, the application of these principles will ensure that mechanical or electronic structures can be formed in a simplified manner. Although specific applications of the present invention have been described, the principles disclosed herein provide the basis for implementing the present invention in various structures including semiconductor devices in a variety of ways, and it is clear that there are many applications. Therefore, other structures that do not depart from the scope of the present invention, although not specifically described herein, will also be limited by the scope of the following patent applications. Graphical component symbol description 10 Integrated circuit structure 20 Lower metal layer 22 Conductor element 24 Through hole portion 30 Second layer of metal 32 Conductor element 34 Through hole portion 36 Silicon nitrogen barrier layer 38 Second layer 40 Dielectric layer 42 dielectric layer 44 metal-insulator-metal stack
裝 訂Binding
k -12- 本紙張尺度適用中國國家標準(CNS) A4規格(21〇x 297公釐) 582090 A7 B7 五、發明説明（9 ) 48光阻層 76錐形連接表面 50第一導電層 78上表面 52絕緣體層 80位置 54第二導電層 82區域 60電容器結構 84第三層 62上導電層 90金屬階層 64絕緣體層 92a導體部份 66下導電層 92b導體部份 68區域 94通孔部份 70薄板區域 96氮化矽層 72厚部份 74相對薄部份 98通孔部份 -13- 本紙張尺度適用中國國家標準(CNS) A4規格(21〇x 297公釐）k -12- This paper size applies Chinese National Standard (CNS) A4 specification (21 × 297 mm) 582090 A7 B7 V. Description of the invention (9) 48 Photoresist layer 76 Tapered connection surface 50 First conductive layer 78 Surface 52 insulator layer 80 position 54 second conductive layer 82 area 60 capacitor structure 84 third layer 62 conductive layer 90 metal layer 64 insulator layer 92a conductor portion 66 lower conductive layer 92b conductor portion 68 area 94 through hole portion 70 Thin plate area 96 Silicon nitride layer 72 Thick portion 74 Relatively thin portion 98 Through hole portion -13- This paper size applies to China National Standard (CNS) A4 specification (21〇x 297 mm)
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US65349200A | 2000-08-31 | 2000-08-31 |
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| TW090121454A TW582090B (en) | 2000-08-31 | 2001-08-30 | Structure with tapered landing and method of fabrication |
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| JP (1) | JP2002124576A (en) |
| KR (1) | KR20020018606A (en) |
| GB (1) | GB2371408B (en) |
| TW (1) | TW582090B (en) |
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| JP4949656B2 (en) * | 2005-08-12 | 2012-06-13 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US11869725B2 (en) | 2021-11-30 | 2024-01-09 | Texas Instruments Incorporated | Multi-stacked capacitor |
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| US5838605A (en) * | 1996-03-20 | 1998-11-17 | Ramtron International Corporation | Iridium oxide local interconnect |
| US6114766A (en) * | 1997-12-18 | 2000-09-05 | Advanced Micro Devices, Inc. | Integrated circuit with metal features presenting a larger landing area for vias |
-
2001
- 2001-08-30 TW TW090121454A patent/TW582090B/en not_active IP Right Cessation
- 2001-08-31 JP JP2001262668A patent/JP2002124576A/en not_active Abandoned
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| GB2371408B (en) | 2004-12-22 |
| GB0121205D0 (en) | 2001-10-24 |
| GB2371408A (en) | 2002-07-24 |
| JP2002124576A (en) | 2002-04-26 |
| KR20020018606A (en) | 2002-03-08 |
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