TW581912B - Active matrix substrate, method of manufacturing same, and flat-panel image sensor - Google Patents

Abstract

In an active matrix substrate, a glass substrate is provided with TFTs having gate electrodes connected to scanning lines also provided on the glass substrate. The glass substrate is further provided with auxiliary capacitance lines, formed on the same layer as the scanning lines. Further, pixel electrodes connected to drain electrodes of the TFTs are formed on the same layer as signal lines connected to source electrodes of the TFTs. An insulating layer is provided between the layer forming the signal lines and pixel electrodes and the layer forming the drain and source electrodes. Since the insulating film is present between the signal lines and the scanning and auxiliary capacitance lines, influence on the auxiliary capacitance value can be reduced, as can a signal line capacitance value. As a result, even when the auxiliary capacitance value is increased, the signal line capacitance value remains small.

Description

581912 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（1 ) 發明之領域 本發明係有關一種以液B縣一姑 ☆ 使明顯不裝置烏代表之畫像顯示裝 置，及平板畫像感測器等之佥德 ▼〈旦像攝矽裝置，以及此等裝置 中所用之主動矩陣基板及其製法。 發明之背景 王動矩陣基板，具有大面積、薄型、輕量等優異之特 性，不僅可用於以液晶顯示裝置爲代表之畫像顯示裝置， 同時可用於平板型X線畫像感測器等之畫像攝影裝置。 習用主動矩陣基板之構造，係佐以圖6〜圖8説明如下， 圖6係習用主動矩陣基板之平面圖，其中表示該主動矩陣 基板中所形成之許多晝素中之一者。此一主動矩陣基板， 例如係在日本公開特許公報特開昭58_172685號1983年工〇 月1 1日公開）、美國專利第5,953,084號（發行日1999年9月 14日）等中所揭示的液晶顯示體裝置中，基於提高開口率 之目的而使用，其目的係如下所示。 玻璃基板51 (參見圖7或圖8)上，以彼此成格子狀之方 式配置有複數條掃描線5 2及複數條信號線5 6，與其各交 叉部份對應，配置有開關元件晝素電極5 7。作爲開關元 件’係採用薄膜電晶體（以下稱爲T F Τ ) 6 0，其閘極5 5係 接續於掃描線5 2，源極6 1係接續於信號線5 6，没極6 3係 介以没配線6 3 a及接觸孔5 7 a接續於圖素電極5 7。又，接 觸孔57a之下方，形成有輔助電容配量53。 圖7及圖8係上述主動矩陣基板之沿圖6 D-D線及E-E線 之箭頭方向斷面圖。在具有絕緣性的玻璃基板5 1上，配 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 丨丨丨丨丨丨丨！丨丨.丨—丨丨丨—訂—丨丨丨丨丨丨丨 (請先閱讀背面之注意事項再填寫本頁) 581912 A7 '一 —-— 57__ 五、發明說明（2 ) 線有掃描線5 2 (圖6 )、#姑玲 &gt; 古# 3曰t ^ V J挪拖、、泉之支線的閘極Μ及輔助電 =線5 3。此等表面全體上，形成有由陽極氧化所形成 又虱化膜（Α0 (陽極氧化）膜）52a 53a。又，掃描線52 及輔助電容配線53上之氧化膜5 2a 53 a及未形成此膜之 坡璃基板5 1上，形成有閘絕緣膜5 4。 閘極55位置之閘絕緣膜54上，形成有由半導體區域64 及接觸層6 5所構成之作為開關元件的TFT 6〇，其係就各 晝素形成。TFT 60之源極6丨係與在閘絕緣膜5 4上和掃描 線5 2在直交方向形成之信號線5 6相接續。又，汲極6 3係 與在閘絕緣膜5 4上形成之源配線6 3 &amp;相接續。 又’其上侧形成有被覆TFT 6〇 (包含源極6 1及汲極 6 3 )、信號線5 6、汲極配線6 3 a及閘絕緣膜5 4之保護膜 5 8。其上侧又設有層間絕緣膜5 9及晝素電極5 7。晝素電 極5 7係藉由貫通層間絕緣膜5 9及保護膜5 8之接觸孔5 7 a 與汲配線5 3 a電氣接續。另，汲配線6 3 &amp;係介以閘絕緣膜 54及氧化膜53a與輔助電容配線53對向，形成輔助電容 62 ° 以下，茲就使用此種主動矩陣基板之平形面板型X射線 畫線感測器及液晶顯示裝置說明之。 平形面板型X射線畫像感測器，係以取代習用使用感光 性照片底片之X射線攝影裝置為目的之裝置，係根據入射 至畫像感測器之平板之X射線的量之二次元分布，而形成 畫線之裝置。使用此一裝置時，X射線源係另行準備，被 攝影物體係配置於X射線源與畫像感測器之間。 -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------蠍 (請先閱讀背面之注意事項再填寫本頁) 訂---------線. 經濟部智慧財產局員工消費合作社印製 581912 A7 五、發明說明（3 ) 將上述主動矩陣型基板用於平板型X射線畫像感測器之 %合’例如日本公開特許公報特開平‘212458號公報（公 開日1992年8月4日）所開示，各畫素電極5 7上設有用以將 X射線變換成電荷之光電變換層，各畫素電極5 7係作爲電 荷收集用電極使用。光電變換層係由半導體元件所構成， 此半導體元件係藉由在畫素電極57上直接成膜而形成， 或是藉由將以他途製作之元件張貼而設於基板上。 其動作方法係如下所述。其係在畫素電極5 7與設於光 私交換層上之對向電極間施加直流電壓。在讀出時以外， 係令TFT 60成關閉之狀態，將因χ射線之入射而在光電變 換層發生之電荷介以畫素電極57收集於輔助電容62。電 荷之項出’係藉由將相應之畫素以掃描線5 2選擇，再將 蓄積於輔助電容62之電荷介以TFT 6〇流出至信號線“而 達成。碩出之電荷係藉由安裝於信號線5 6端部之運算放 大器等的電路而放大。根據全畫素所讀出之電荷量的分 布，形成畫像。 另一万两，當將上述主動矩陣基板用於液晶顯示裝置之 2合，各晝素電極57上係以夾持液晶層之狀態設有對向 電極。藉由在各畫素電極57與對向電極之間施加電位 j，透過液晶層之光係遭受應於電位差之偏光面的旋轉。 猎由此光之偏光面方向，透過設於外部之偏光板的光量被 決定’而在畫素整體產生光之強弱而形成畫像。 此場口下之主動基妓，相對由掃描線5 2所選擇之晝 素，介以TFT 6〇，自各信號線56，電位寫人各畫素電極 本紙張尺度適用中國國家標準（CNS)A4規格（ χ 297公楚） -------------% (請先閱讀背面之注意事項再填寫本頁) 訂--------—線， 經濟部智慧財產局員工消費合作社印製 581912 A7581912 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, A7. V. Description of the Invention (1) Field of Invention The present invention relates to an image display device that uses liquid B county ☆ to make it apparent that the black representative is not installed, and the flat image sensing The virtues of the device and so on ▼ <Density imaging silicon device, and the active matrix substrate used in these devices and its manufacturing method. BACKGROUND OF THE INVENTION The Wangdong matrix substrate has excellent characteristics such as large area, thinness, and light weight. It can be used not only for image display devices represented by liquid crystal display devices, but also for portrait photography of flat-type X-ray image sensors. Device. The structure of a conventional active matrix substrate is described below with reference to FIGS. 6 to 8. FIG. 6 is a plan view of a conventional active matrix substrate, which shows one of many day elements formed in the active matrix substrate. Such an active matrix substrate is, for example, a liquid crystal disclosed in Japanese Patent Laid-Open Publication No. 58-172685 (published on January 11, 1983), and US Patent No. 5,953,084 (issued on September 14, 1999). The display device is used for the purpose of increasing the aperture ratio, and the purpose is as follows. On the glass substrate 51 (see FIG. 7 or FIG. 8), a plurality of scanning lines 5 2 and a plurality of signal lines 56 are arranged in a grid pattern with each other. Corresponding to each crossing portion thereof, a switching element day element electrode is arranged. 5 7. As the switching element, a thin film transistor (hereinafter referred to as TF T) 60 is used, and its gate 5 5 is connected to the scanning line 5 2, the source 6 1 is connected to the signal line 5 6, and the pole 6 3 is connected. The pixel electrode 57 is connected to the wiring electrode 6 3 a and the contact hole 5 7 a. Below the contact hole 57a, an auxiliary capacitance dosing amount 53 is formed. 7 and 8 are cross-sectional views of the active matrix substrate taken along the arrowed lines D-D and E-E of FIG. 6. On the insulating glass substrate 51, the paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm) 丨 丨 丨 丨 丨 丨!丨 丨. 丨 — 丨 丨 丨 —Order— 丨 丨 丨 丨 丨 丨 丨 (Please read the precautions on the back before filling this page) 581912 A7 '一 —- 57__ V. Description of the invention (2) The line has a scanning line 5 2 (Figure 6), # 姑 玲 &gt; 古 # 3 Said ^ VJ Norto, the gate M and the auxiliary power of the spring branch = line 53. On these surfaces, anodic oxidation films (A0 (anodic oxidation) films) 52a to 53a are formed. Further, a gate insulating film 54 is formed on the oxide film 5 2a 53 a on the scanning line 52 and the auxiliary capacitor wiring 53 and on the sloped glass substrate 51 where the film is not formed. On the gate insulating film 54 at the position of the gate electrode 55, a TFT 60 as a switching element composed of a semiconductor region 64 and a contact layer 65 is formed. The source electrode 6 of the TFT 60 is connected to a signal line 56 which is formed on the gate insulating film 54 and the scanning line 52 in the orthogonal direction. The drain electrode 6 3 is connected to the source wiring 6 3 &amp; formed on the gate insulating film 54. A protective film 5 8 is formed on its upper side to cover the TFT 60 (including the source 6 1 and the drain 6 3), the signal line 56, the drain wiring 6 3 a, and the gate insulating film 54. On the upper side, an interlayer insulating film 59 and a day element electrode 57 are provided. The day electrode 5 7 is electrically connected to the drain wiring 5 3 a through the contact hole 5 7 a penetrating the interlayer insulating film 5 9 and the protective film 5 8. In addition, the drain wiring 6 3 &amp; is opposed to the auxiliary capacitor wiring 53 through the gate insulating film 54 and the oxide film 53a to form an auxiliary capacitor of 62 ° or less, so the flat panel type X-ray drawing of such an active matrix substrate is used The sensor and the liquid crystal display device are described. The flat panel type X-ray image sensor is a device for replacing the conventional X-ray imaging device using a photosensitive photo film, and is based on the second-dimensional distribution of the amount of X-rays incident on the flat plate of the image sensor, and A device for forming lines. When using this device, the X-ray source is prepared separately, and the object system is arranged between the X-ray source and the image sensor. -5- This paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------ Scorpion (Please read the precautions on the back before filling this page) Order- -------- Line. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 581912 A7 V. Description of the invention (3) The above active matrix substrates are used in a flat X-ray image sensor. As disclosed in Japanese Patent Application Laid-Open No. '212458 (publication date August 4, 1992), each pixel electrode 57 is provided with a photoelectric conversion layer for converting X-rays into electric charges, and each pixel electrode 57 is Used as a charge collection electrode. The photoelectric conversion layer is composed of a semiconductor element, which is formed by directly forming a film on the pixel electrode 57 or is provided on a substrate by mounting an element made elsewhere. The operation method is as follows. A DC voltage is applied between the pixel electrode 57 and a counter electrode provided on the optical private switching layer. Except for reading, the TFT 60 is turned off, and the charges generated in the photoelectric conversion layer due to the incidence of x-rays are collected in the storage capacitor 62 through the pixel electrode 57. The charge output is achieved by selecting the corresponding pixel with the scanning line 52, and then flowing the charge accumulated in the auxiliary capacitor 62 to the signal line through the TFT 60. The charged charge is obtained by installing It is amplified by a circuit such as an operational amplifier at the end of the signal line 56. A picture is formed based on the distribution of the amount of charge read out in full pixels. Another is that when the above active matrix substrate is used in a liquid crystal display device 2 In contrast, a counter electrode is provided on each of the day electrode 57 in a state of sandwiching the liquid crystal layer. By applying a potential j between each pixel electrode 57 and the counter electrode, the light system passing through the liquid crystal layer is subjected to a potential difference. The rotation of the polarizing surface of the light. The direction of the polarizing surface of the light is determined by the amount of light transmitted through the external polarizing plate, and the strength of the light is generated in the entire pixel to form an image. The active prostitute under this mouth is relatively The day element selected by the scanning line 52, via the TFT 60, the potentials are written to each pixel electrode from the signal line 56, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (χ297297) --- ----------% (Please read the notes on the back first (Please fill in this page again) Order ---------- line, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 581912 A7

經濟部智慧財產局員工消費合作社印製 五、發明說明（4 ) 5 7。藉此，如上所述，各畫素電極5 7與對向電極之間產 生電壓。 上述主動基板處所設之各配線中的寄生靜電電容，對於 其主動矩陣基板之性能有大的影響。此靜電電容不只會引 起自各配線端子部輸入之信號或來自各畫素之資料的^達 延遲，同時還會引起非目的之畫素或配線等的電位變動， 或是反而使目的配線之電位易於受到其他因素影響之狀 態。由於此一靜電電容之影響，會產生藉使用主動矩陣基 板之裝置而攝影或顯示之畫像品質降低的不良現象。 平板型X射線畫像感測器中’蓄積於畫素電極5 7之電荷 係介以信號線5 6讀出，據此而形成晝像資料，因此，信 號線56在與#描線52或輔助電容配線53等之間的靜電電 谷（信號線電容）係使電荷讀出時間增大，而增加讀出電荷 之雜訊成分。如此，將使攝影畫像之品質降低。 特別是在平板型X射線畫像感測器中，由於係以微弱的 X射線形成畫像，因此有必要讀出由畫素電極57所蓄積之 少量電荷，其影響特別重大。 然而，若如習用技術般之將信號線5 6配置於閘絕緣膜 54上時’在構造上’信號線56與掃描線52之間，以及信 號線5 6與輔助電容配線5 3之間的間隔會變得狹小。因 此，信號線電容値會易於增大，以致攝影畫像之品質降 低，是爲其問題。 又’平板型X線畫像感測器中，由於晝素電極5 7係作爲 電荷收集用使用’其電位之變動較之液晶等顯示裝置之場 ------------§ (請先閲讀背面之注意事項再填寫本頁) 訂---------線 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） •—Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy V. Invention Description (4) 5 7. Thereby, as described above, a voltage is generated between each pixel electrode 57 and the counter electrode. The parasitic electrostatic capacitance in each wiring provided in the above active substrate has a great influence on the performance of the active matrix substrate. This electrostatic capacitance will not only cause the delay of the signal input from each wiring terminal or the data from each pixel, but also cause the potential change of non-purpose pixels or wiring, or make the potential of the destination wiring easy. Affected by other factors. Due to the influence of this electrostatic capacitance, a bad phenomenon occurs in which the quality of an image taken or displayed is reduced by using an active matrix substrate device. In the flat-type X-ray image sensor, the charge accumulated in the pixel electrode 57 is read out through the signal line 56, and the daytime image data is formed based on this. Therefore, the signal line 56 is connected with #Drawline 52 or an auxiliary capacitor The electrostatic valley (signal line capacitance) between the wirings 53 and the like increases the charge readout time and increases the noise component of the readout charge. In this way, the quality of photographic portraits will be reduced. In particular, in the flat-type X-ray image sensor, since an image is formed by weak X-rays, it is necessary to read out a small amount of electric charge accumulated by the pixel electrode 57 and its influence is particularly significant. However, if the signal line 56 is disposed on the gate insulating film 54 as in conventional technology, the signal line 56 is between the signal line 56 and the scanning line 52 and between the signal line 56 and the auxiliary capacitor line 53. The interval becomes narrow. Therefore, the signal line capacitance 易于 can easily increase, and the quality of the photographic image is lowered, which is a problem. In the “flat-panel X-ray image sensor, because the day element electrode 57 is used for charge collection,” the potential change is larger than that of a display device such as a liquid crystal ------------ § (Please read the precautions on the back before filling out this page) Order --------- The size of thread paper is applicable to China National Standard (CNS) A4 (21〇χ 297 mm) • —

581912 五、發明說明（5581912 V. Description of the invention (5

合易於變大。爲了不使畫素電極57之電位變動引起TFT 60 I錯誤動作，此一電位變動必須儘可能予以抑制。因 此，在畫素電極5 7上必須事先接續較液晶顯示裝置電容 値大出甚多之輔助電容62。然而，藉由將輔助電容配線 53之線寬或面積增大而增大輔助電容値有其界限，藉由 將閘、，、邑緣膜5 4或氧化膜5 3 a薄化而增大輔助電容値據信也 是一種有效的手段。 然而，在習用之構造中，將閘絕緣膜5 4或氧化膜5 3 &amp;薄 化，將伴隨有增大信I線電容値的缺點，^純予以薄化困 難。如此，根據習用之構造，將輔助電容値增大有所困 難，是爲其問題。 又，於液晶顯示裝置中，根據習用構造，信號線電容値 易於增大，與平板型X射線畫像感測器同樣有問題。液晶 顯示裝置今後相信會日益高精細化，但若高精細化，一般 而言，各配線的電容値會增加，顯示品質會降低。爲了謀 求今後之大巾田同精細化，可降低對於顯示品質有重大影響 &lt;信號線容量値之新主動矩陣基板的構造，是爲人所企盼 者。 又，在液晶顯示裝置中，冑了獲得清晰的顯示，特別重 要的是增加Pg 口率。然@，根據習用構造之主動矩陣基 板，具有遮光性之輔助電容配線53，相對畫素整體之面 積占有大的比例，因此，作爲透過型使用之場合，會成爲 開口率降低的一個原因。又，藉由將輔助電容配線53細 化，將閘絕緣膜54或氧化膜53a薄化，而在確保必要之輔 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 訂---------線· 經濟部智慧財產局員工消費合作社印製 581912 經濟部智慧財產局員工消費合作社印製 A7 B7____ 五、發明說明（6 ) 助電容値之下，提高開口率此舉雖也被考慮，但是，與上 述平板型X線畫像感測器之場合相同，若依習用之構造， 會有信號線電容値易於增大的問題。 边今爲止’針對此一問題，例如，如日本公開特許公報 「特開昭60_ 160173號公報（公開日1985年8月2 1日）」中 所開示，係形成被覆TFT 60之半導體區域6 4及玻璃基板 51之保護膜，並在其上形成源極61、汲極63、信號線 56、畫素電極57等，藉而謀求信號線電容値之降低，以 之作爲對策。 然而，根據此一構造，源極61及没極63與半導體區域 64之接觸會易於變得不安定，因此，難以增厚上述保護 膜’在信號線電容値降低此點，不夠充份。又，根據此一 構造，由於未考慮輔助電容62，爲了形成輔助電容62， 還有構造及製造過程複雜之問題。 如上所述’在平板型X線畫像感測器中，爲了降低攝影 畫像中之雜訊南k賴性’在液晶顯示裝置中爲了在高精 細化之場舍確保顯示品質及開口率，所謀求的第一是降低 #號線電容値之構造’第二是即使薄化閘絕緣膜5 4或氧 化膜5 2 a · 5 3 a (即使増大輔助電容値），也不易増加信號 線電容値之構造。 發明之概要 本發明之目的，係在提供一種信號線電容値小的主動矩 陣基板，以實現可獲得更高品質之攝影畫像或顯示畫像的 攝影裝置或顯示裝置，且對提供即使是增加輔助電容値， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------- (請先閱讀背面之注意事項再填寫本頁)It is easy to get bigger. In order to prevent the TFT 60 I from malfunctioning due to the potential variation of the pixel electrode 57, this potential variation must be suppressed as much as possible. Therefore, the pixel electrode 57 must be connected in advance with an auxiliary capacitor 62 which is much larger than the capacitance of the liquid crystal display device. However, there is a limit to increasing the auxiliary capacitor by increasing the line width or area of the auxiliary capacitor wiring 53, and increasing the auxiliary capacitor by thinning the gate, thin film 5 or oxide film 5 3 a. Capacitors are also believed to be an effective means. However, in the conventional structure, thinning the gate insulating film 54 or the oxide film 5 3 is accompanied by the disadvantage of increasing the capacitance of the I line, and it is difficult to thin it. Thus, it is difficult to increase the auxiliary capacitance 値 according to the conventional structure, which is a problem. In addition, in the liquid crystal display device, the signal line capacitance 値 is easily increased according to a conventional structure, and has the same problems as the flat-type X-ray image sensor. Liquid crystal display devices are expected to become increasingly finer in the future. However, if the fineness is increased, generally, the capacitance of each wiring will increase and the display quality will decrease. In order to achieve greater refinement in the future, the structure of a new active matrix substrate that can have a significant impact on display quality &lt; signal line capacity &gt; is expected. Moreover, in the liquid crystal display device, it is important to obtain a clear display, and it is particularly important to increase the Pg rate. However, according to the active matrix substrate with conventional structure, the auxiliary capacitor wiring 53 with light shielding occupies a large proportion of the area of the entire pixel. Therefore, it will be a cause of the decrease in the aperture ratio when it is used as a transmissive type. In addition, by thinning the auxiliary capacitor wiring 53 and reducing the thickness of the gate insulating film 54 or the oxide film 53a, it is necessary to ensure that the necessary paper size is in accordance with the Chinese National Standard (CNS) A4 standard (210 X 297 public love) ( (Please read the precautions on the back before filling this page) Order --------- Line · Printed by the Consumers 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 581912 Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7____ V. Invention Note (6) Although the increase in aperture ratio under the auxiliary capacitor 値 is also considered, it is the same as that in the case of the above-mentioned flat-type X-ray image sensor. If the conventional structure is used, the signal line capacitor 値 is easy to increase. Big question. Heretofore, in response to this problem, for example, as disclosed in Japanese Patent Application Laid-Open No. 60_160173 (publication date August 21, 1985), a semiconductor region covering the TFT 60 is formed. 6 4 And a protective film of the glass substrate 51, and a source 61, a drain 63, a signal line 56, a pixel electrode 57 and the like are formed thereon to reduce the signal line capacitance 値 as a countermeasure. However, according to this structure, the contact between the source electrode 61 and the non-electrode 63 and the semiconductor region 64 tends to become unstable. Therefore, it is difficult to increase the thickness of the protective film 'to reduce the signal line capacitance ，, which is insufficient. In addition, according to this structure, since the auxiliary capacitor 62 is not considered, in order to form the auxiliary capacitor 62, there is a problem that the structure and manufacturing process are complicated. As described above, "in order to reduce noise in photographic portraits in a flat-type X-ray image sensor", in a liquid crystal display device, it is required to ensure display quality and aperture ratio in a high-definition field. The first is the structure that reduces the capacitance of ## line. The second is that even if the gate insulation film 5 4 or oxide film 5 2 a · 5 3 a is thinned (even if the auxiliary capacitor is large), it is not easy to add signal line capacitance. structure. SUMMARY OF THE INVENTION The object of the present invention is to provide an active matrix substrate with a small signal line capacitance so as to realize a photographic device or display device capable of obtaining higher-quality photographic portraits or displaying portraits.値, this paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------- (Please read the precautions on the back before filling this page)

581912 經濟部智慧財產局員工消費合作社印製 A7 B7____ 五、發明說明（7 ) 仏號線電谷俊之增加也屬不大之主動矩陣基板。 本發明之主動矩陣基板’爲了達成上述目的，備有：根 據供給至閘極之信號而將源極與汲極間開關之開關元件， 接續於上述閘極之掃描線，接續於上述源極之信號線，及 接續於上述没極之畫素電極；又，形成上述掃描線之層， 位於形成該掃描線之層之上方，形成上述源極之層，位於 形成？茨源極之層之上方，形成上述信號線之層，形成於形 成上述源極之層與形成上述信號線之層之間的絕緣體層， 係形成於基板上；上述掃描線與信號線，係彼此介以上述 絕緣體層配置者。 根據上述構成，形成掃描線之層、位於形成掃描線之層 的上^之形成源極之層、以及位於形成源極之層的上方之 形成信號線之層，係形成於基板上。又，形成源極之層與 2成信號線之層之間，形成有絕緣體層。介以此絕緣層， &quot;U號線與掃描線例如係以彼此交又之方式配置。 習用之主動矩陣基板，係配置有掃描線，且係介以形成 於閘極上之閘絕緣膜配置掃描線及信號線。根據此一構 造，閘絕緣膜之厚度係因應開關元件之規格而決定，將由 此厚度所決定之閘絕緣膜的靜電電容値設定成較小有所困 難。因此，信號線及掃描線介以閘絕緣膜對向之部份，信 號線與掃描線之間產生之信號線電容（寄生電容）的電容値 增大，而產生上述之問題。 一相對於此’根據上述構成，係介以形成源極之層與形成 化號線之層間所形成的絕緣體層，配置信號線及掃 (請先閱讀背面之注意事項再填寫本頁) 訂---------^ -10- 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（8 ) 因此，由此絕緣體層所隔gg 、 、 ’ I L就線與掃描線之間隔，係 可設成較上述閘絕緣膜之厘♦ 子度為厚，因此，信號線與掃描 線之間所產生的信號線之雷宄精 ^ 〇人 4私备値，係可較上述習用之場合 降低。 此-絕緣體層係形成於形成源極之層與形成信號線之層 心間，與上迷閘絕緣膜等不同，與開關元件之規格獨立。 因此可將此絕緣體層形成爲使信號線電容之電容値充份 減小。 具體而言，藉由將絕緣體層之厚度充分增大，又，也可 使用介質常數小之材料形成絕緣體層，可將信號線電容之 電谷値充份地減小。 又，習狀主動矩降基板中，冑開關元件之半導體區域 與源極之間，形成有保護膜等之絕緣體層的構造。此一場 合下，如上所述，源極與半導體區域之接觸易於變得不安 定，因此，將上述絕緣體之層充分增厚此舉有所困難，以 致信號線電容之電容値降低困難。 相對於此，根據上述本發明之構成，形成源極之層與形 成信號線之層係分別形成，因此，可將源極密接於開關元 件之本體（半導體層等）形成。是以，可在不致對開關元件 之機能有不良影響的狀況下，將絕緣體層之厚度充分增 大。 ^ 又，源極與信號線例如可介以絕緣體層中所形成之接觸 孔等接續。再者，此一接續部份，可在與開關元件不同之 部份，以確保充份領域之方式形成，因此可迴避接續之不 -11 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） -----------------^--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 581912 A7 ------—__-_— _ 五、發明說明（9 ) 安定。 是以’根據上述構成，可提供開關元件之機能良好，且 #號線與掃描線之間發生的信號線電容之電容値減小的主 動矩陣基板。 又’本發明之主動基板之製造方法，係上述畫素電極與 形成上述信號線之層由同一層所形成的主動矩陣基板之製 造方法’其畫素電極與信號線係由同一層之圖案化所形 成。 根據上述方法，係將信號線及畫素電極由同一層（膜）之 圖案所形成。亦即，信號線及畫素電極係由相同材料所構 成心同一導電膜圖案化所形成，也可由相同之過程形成。 疋以’可藉由將習用主動矩陣基板製造中形成畫素電極 時所用I圖案化用罩幕的圖案作部份變更，即可製造本主 動矩陣基板。因此，在本主動基板製造中，可避免製造步 驟t複雜化或製造步驟數之增加。 又’藉由將源極及汲極由同一層（膜）圖案化所形成，再 使製造步驟簡單化。 本發明炙主動矩陣基板，爲了達成上述目的，具有接續 $關元件之仏號線、接續於上述開關元件之掃描線、以 及介在於上述信號線與掃描線之間之樹脂材料。 根據上述構成，在主動基板上，信號線與掃描線，係介 以樹脂材料例如作交叉等方式之配置。 樹脂材料與一般之無機材料等相較，介質常數較低。因 此’藉由將信號線與掃描線介以樹脂材料配置，可滅小信 -------—訂--------- (請先閱讀背面之注意事項再填寫本頁) -12-581912 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7____ V. Description of the Invention (7) The increase in the electric line Jun of Line 也 is also a small active matrix substrate. In order to achieve the above object, the active matrix substrate of the present invention includes: a switching element that switches between a source and a drain according to a signal supplied to the gate, is connected to the scanning line of the gate, and is connected to the source; The signal line, and the pixel electrode connected to the electrode; and the layer forming the scanning line is located above the layer forming the scanning line, and the layer forming the source is located? Above the source layer, a layer of the above-mentioned signal line is formed, and an insulator layer formed between the layer forming the source and the layer forming the signal line is formed on the substrate; the scanning line and the signal line are Those who arrange each other via the above-mentioned insulator layer. According to the above configuration, the scanning line forming layer, the source forming layer located above the scanning line forming layer, and the signal line forming layer above the source forming layer are formed on the substrate. An insulator layer is formed between the source-forming layer and the signal-forming layer. With this insulating layer, the "U-number line and the scanning line are arranged in such a way as to intersect each other, for example. A conventional active matrix substrate is provided with scan lines, and scan lines and signal lines are arranged through a gate insulating film formed on a gate electrode. According to this structure, the thickness of the gate insulating film is determined according to the specifications of the switching element, and it is difficult to set the capacitance 値 of the gate insulating film determined by this thickness to be small. Therefore, the signal line and the scanning line are interposed by the gate insulating film, and the capacitance 値 of the signal line capacitance (parasitic capacitance) generated between the signal line and the scanning line is increased, thereby causing the above-mentioned problem. In contrast to this, according to the above structure, the signal layer and the sweep are arranged through the insulator layer formed between the layer forming the source and the layer forming the signal line (please read the precautions on the back before filling this page). Order- -------- ^ -10- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the invention (8) Therefore, the interval between the gg,, and IL lines and the scanning lines separated by this insulator layer It can be set to be thicker than the above-mentioned gate insulation film. Therefore, the signal precision of the signal line generated between the signal line and the scanning line is ^ ○ person 4 is for personal use. Occasions decrease. This insulator layer is formed between the layer forming the source electrode and the layer forming the signal line, which is different from the upper insulating film and the like, and is independent of the specifications of the switching element. Therefore, the insulator layer can be formed so that the capacitance 値 of the signal line capacitance can be sufficiently reduced. Specifically, by sufficiently increasing the thickness of the insulator layer and forming the insulator layer using a material having a small dielectric constant, the electric valley of the signal line capacitance can be sufficiently reduced. Further, in the conventional active moment drop substrate, a structure in which an insulator layer such as a protective film is formed between a semiconductor region of a switching element and a source is formed. In this case, as mentioned above, the contact between the source and the semiconductor region tends to become unstable. Therefore, it is difficult to sufficiently thicken the above-mentioned insulator layer, so that it is difficult to reduce the capacitance of the signal line capacitance. On the other hand, according to the structure of the present invention described above, the source-forming layer and the signal line-forming layer are formed separately. Therefore, the source can be formed in close contact with the body (semiconductor layer, etc.) of the switching element. Therefore, the thickness of the insulator layer can be sufficiently increased without adversely affecting the function of the switching element. ^ The source and signal lines can be connected, for example, via contact holes formed in an insulator layer. In addition, this continuation part can be formed in a part different from the switching element in a way that ensures sufficient field, so it can avoid continuity. -11-This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 x 297 mm) ----------------- ^ --------- (Please read the notes on the back before filling out this page) Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives 581912 A7 ------—__-__ _ V. Description of Invention (9) Stability. Based on the above configuration, it is possible to provide an active matrix substrate having a good function of the switching element and a reduction in the capacitance 値 of the signal line capacitance occurring between the ## line and the scanning line. "The method of manufacturing an active substrate of the present invention is a method of manufacturing an active matrix substrate in which the pixel electrode and the layer forming the signal line are formed from the same layer", and the pixel electrode and the signal line are patterned from the same layer Formed. According to the above method, the signal line and the pixel electrode are formed by a pattern of the same layer (film). That is, the signal line and the pixel electrode are formed by patterning the same conductive film made of the same material, and can also be formed by the same process. For example, the active matrix substrate can be manufactured by partially changing the pattern of the I patterning mask used in the formation of pixel electrodes in the manufacture of conventional active matrix substrates. Therefore, in this active substrate manufacturing, it is possible to avoid complication of the manufacturing step t or increase of the number of manufacturing steps. Furthermore, the source and drain electrodes are formed by patterning the same layer (film), thereby simplifying the manufacturing steps. In order to achieve the above-mentioned object, the active matrix substrate of the present invention has a horn line connected to the element, a scanning line connected to the switching element, and a resin material interposed between the signal line and the scanning line. According to the above configuration, the signal line and the scanning line are arranged on the active substrate via a resin material, for example, in a manner such that they intersect. Compared with general inorganic materials, resin materials have a lower dielectric constant. Therefore, by disposing the signal line and the scanning line with a resin material, you can destroy the small letter -------- order --------- (Please read the precautions on the back before filling this page ) -12-

581912581912

五、發明說明（10) 經濟部智慧財產局員工消費合作社印製 號線與掃描線間所產生之靜電電容之電容值。如此， 低信號線電容之容量值。 於備有輔助電容之主動矩陣基板中，形成輔助電容 《辅助電容配線與信號線之間，宜介有樹脂材料。藉此， 可進一步降低信號電容之電容值。 本發明之主動矩陣基板，為了達成上述目的，備有：根 、供給至閘極之信號而將源極與汲極間開關之開關元件， 接、續於上述閘極之掃描線’接續於上述源極之信號線，及 接續於上述沒極之畫素電極；又，形成上述信號線之層， 位於形成該信號線之層之上方，形成上述閘極之層，位於 形成該閘極之層之上方，形成上述掃描線之層，及形成於 形成上述閘極之層與形成上述掃描線之層之間的絕緣體 層，係形成於基板上；上述掃描線與信號線，係彼此介以 上述絕緣體層配置者。 根據上述構成，形成信號線之層、位於該信號線形成層 上万 &lt; 形成閘極之層、及位於該閘極形成層上方之形成掃 描線之層，係形成於基板上。又，形成閘極之層與形成掃 描線之層之間，形成有絕緣體層。又，介以此絕緣體層， 4吕號線與掃描線例如係彼此交叉等般之配置。 上述構成’與早先所述之構成（形成掃描線之層、形成 源極之層、及形成信號線之層，依此順序在基板上形成之 構成）’同樣地係介以在閘極形成層與掃描線形成層之間 形成的絕緣體層，配置掃描線及信號線。因此，可降低掃 描線與信號線之間所產生之信號線電容的電容值。 -13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------訂---------線 (請先閲讀背面之注意事項再填寫本頁) 581912 A7 五、發明說明（Ή 又，士間極與掃描、線，例*可介以形成於絕緣體層 孔接續。再者’此-接㈣份可在與開關元件不同之 以確保充份區域之方式形成，因&amp;，可避免接續不安：刀 是以，根據上述構成，可提供開關元件之機能良 :描線與信號線之間所產生的信號線電容之電 動矩陣基板。 呵王 本發明之平板型畫像感測器’ A了達成上述目 徵係在於：由具有上述晝素電極之主動矩陣基板、及與該 =動矩陣基板中之上述畫素電極電接續之光電變換層所構 ^據上返構成’可形成畫素電極作爲電荷收集用電極發 信 測 出 電 可 揮機能之平板型畫像感測器。此外，也可形成上述具有 號線電容之電容値小的主動麵陣基板之平板型畫像感 器。因此，起因於信號線容量大之事實，以致電荷之； 所：的時間増長’或是因掃描線、輔助電容酉己線、畫素 極等（影響，以致雜訊重#於信號線之信號此 予抑制。 . 本發明之其他目的、特徵及優點，可由下述説明獲得深 經濟部智慧財產局員工消費合作社印製 圖 〈瞭解。又，本發明之利點，可由下列説明佐以附 獲得深一層之瞭解。 圖面之簡單説明 圖1係本發明第i實施形態之主動料基板的平面圖 圖2係圖1中A_A線箭頭方向的斷面圖。 圖3係圖1中β _ B線箭頭方向的斷面圖。 -14- A7 A7 經濟部智慧財產局員工消費合作社印製 *------B7__·_ 五、發明說明（12 ) 系本發明第i實施形態變形例之主動矩陣基板的平 由圖。 圖5係圖4中C_C線箭頭方向的斷面圖。 圖6係習用主動矩陣基板的平面圖。 圖7係圖6中D-D線箭頭方向的斷面圖。 圖8係圖6中Ε·Ε線箭頭方向的斷面圖。 圖9係本發明第丨實施形態又一變形例之主動矩陣基板 的平面圖。 圖10係圖9中F-F線箭頭方向的斷面圖。 圖1 1係圖9中G_ G線箭頭方向的斷面圖。 圖12係本發明第2實施形態主動矩陣基板的平面圖。 圖1 3係圖1 2中Η - Η線箭頭方向的斷面圖。 圖14係圖12中^線箭頭方向的斷面圖。. 圖1 5係本發明第3實施形態主動矩陣基板的平面圖。 圖1 6係圖1 5中J - J線箭頭方向的斷面圖。 圖1 7係圖1 5中Κ - Κ線箭頭方向的斷面圖。 圖1 8係丰發明第4實施形態平板型χ射線畫像感測器的 斷面圖。 圖1 9係本發明第5實施形態平板型X射線畫像感測器的 斷面圖。 圖2 0係本發明第6實施形態平板型X射線畫像感測器的 斷面圖。 圖2 1係本發明第7實施形態主動矩陣基板的平面圖。 圖2 2係圖2 1中L - L線箭頭方向的斷面圖。 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ' ' --------訂---------線· (請先閱讀背面之注意事項再填寫本頁) 581912V. Description of the invention (10) The capacitance value of the electrostatic capacitance generated between the number line and the scan line printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Thus, the capacitance value of the low signal line capacitance. On an active matrix substrate with an auxiliary capacitor, an auxiliary capacitor is formed. A resin material should be interposed between the auxiliary capacitor wiring and the signal line. This can further reduce the capacitance of the signal capacitor. In order to achieve the above-mentioned object, the active matrix substrate of the present invention includes: a switching element that connects a source and a drain with a signal that is supplied to the gate, and is connected to and connected to the scanning line of the gate to the above The signal line of the source electrode and the pixel electrode connected to the non-polar electrode; and the layer forming the signal line is located above the layer forming the signal line, the layer forming the gate, and the layer forming the gate. Above, a layer forming the scanning line, and an insulator layer formed between the layer forming the gate and the layer forming the scanning line are formed on the substrate; the scanning line and the signal line are interposed between the above Insulator layer arranger. According to the above configuration, the signal line forming layer, the gate line forming layer, and the scan line forming layer above the gate line forming layer are formed on the substrate. An insulator layer is formed between the gate-forming layer and the scanning line-forming layer. In addition, via the insulator layer, the 4th line and the scanning line are arranged, for example, to cross each other. The above-mentioned structure 'is the same as the structure described earlier (the structure in which the scan line is formed, the source is formed in the layer, and the signal line is formed in this order on the substrate). The insulator layer formed between the scanning line forming layer and the scanning line and the signal line are arranged. Therefore, the capacitance of the signal line capacitance generated between the scanning line and the signal line can be reduced. -13 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) -------- Order --------- Line (Please read the precautions on the back before filling (This page) 581912 A7 V. Description of the invention (Ή Also, the poles are connected to the scanning and the lines. For example, * can be formed through the hole in the insulator layer to connect. Furthermore, this-connection can be different from the switching element to ensure The area is formed in a sufficient area, which can avoid connection anxiety because of &amp;: the knife is based on the above structure, which can provide a good function of the switching element: the electric matrix substrate of the signal line capacitance generated between the trace and the signal line. The flat image sensor according to the present invention of the present invention 'A achieves the above-mentioned objective is that an active matrix substrate having the above-mentioned day electrode and a photoelectric conversion layer electrically connected to the above-mentioned pixel electrode in the moving matrix substrate According to the above structure, a flat-type image sensor capable of forming a pixel electrode as a charge-collecting electrode and measuring the electrical volatile function can be formed. In addition, the above-mentioned active capacitor with a small line capacitance can also be formed. Flat image sensor of area array substrate. This is due to the fact that the capacity of the signal line is large, resulting in the charge; So: the time is too long, or because of the scanning line, the auxiliary capacitor line, the pixel electrode, etc. (influence, so that the noise is more important than the signal on the signal line) This is inhibited.. Other objects, features, and advantages of the present invention can be obtained from the following descriptions printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs. Also, the advantages of the present invention can be obtained from the following descriptions A deeper understanding. Brief description of the drawings FIG. 1 is a plan view of an active material substrate of the i-th embodiment of the present invention. FIG. 2 is a cross-sectional view in the direction of the arrow A_A in FIG. 1. FIG. 3 is a β_B in FIG. Sectional view in the direction of the arrow. -14- A7 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * ------ B7__ · _ V. Description of the invention (12) is the initiative of the modification of the i-th embodiment of the present invention The flat substrate of the matrix substrate. Figure 5 is a cross-sectional view in the direction of the arrow C_C in Figure 4. Figure 6 is a plan view of the conventional active matrix substrate. Figure 7 is a cross-section in the direction of the arrow DD in Figure 6. Figure 8 Sectional view in the direction of the arrow of the Ε · Ε line in FIG. 6. 9 is a plan view of an active matrix substrate according to another modification of the first embodiment of the present invention. FIG. 10 is a cross-sectional view in the direction of the FF line arrow in FIG. 9. FIG. 1 is a cross-sectional view in the direction of the G_G line arrow in FIG. 9. Fig. 12 is a plan view of an active matrix substrate according to a second embodiment of the present invention. Fig. 13 is a cross-sectional view taken along the line Η-Η of the arrow in Fig. 12. Fig. 14 is a cross-sectional view taken along the line ^ of the arrow in Fig. 12. Fig. 15 is a plan view of an active matrix substrate according to a third embodiment of the present invention. Fig. 16 is a cross-sectional view taken along the direction of arrow J-J in Fig. 15. Fig. 17 is the direction of arrow KK-KK in Fig. 15 Fig. 18 is a cross-sectional view of a flat-type x-ray image sensor according to a fourth embodiment of the 8th invention. Fig. 19 is a sectional view of a flat-plate X-ray image sensor according to a fifth embodiment of the present invention. Fig. 20 is a sectional view of a flat-type X-ray image sensor according to a sixth embodiment of the present invention. FIG. 21 is a plan view of an active matrix substrate according to a seventh embodiment of the present invention. Fig. 22 is a sectional view in the direction of the arrow of the line L-L in Fig. 21. -15- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please fill in this page again)

圖23係圖21中M_M線箭頭方向的斷面圖。 圖24係圖2 1中N-N線箭頭方向的斷面圖。 圖2 5係本發明第8實施形態主動矩陣基板的平面圖。 圖26係圖25中〇-〇線箭頭方向的斷面圖。 圖2 7係圖25中P_P線箭頭方向的斷面圖。 圖2 8係圖2 5中Q - Q線箭頭方向的斷面圖。 實施例之説明 [實施形態1 ] 以下，茲將本發明的一個實施形態，佐以圖i〜圖5及圖 9〜圖11説明之。 圖1係本實施形態主動矩陣基板之平面圖，其構造係如 下所述。在玻璃基板（基板）J (請參見圖2或圖3)上，配置 有複數條掃描線2及複數條信號線6，彼此成格子狀，對 應於其各交叉部份，分別配置有開關元件及畫素電極7。 經濟部智慧財產局員工消費合作社印製 作爲開關元件’係使用具有閘極5、源極1 1及没極1 3之 薄膜電晶體（以下稱爲T F T ) 1 〇。_閘極5係與掃描線2接 續，源極U係介以源配線1 1 a及接觸孔6 a與信號線6接 續’没極1 3係介以汲配線1 3 a及接觸孔7 a與畫素電極7接 續。又，接觸孔7 a之下方形成有輔助電容配線3，與汲配 線13a之間形成有輔助電容12(請參見圖3)。 圖2及圖3係上述主動矩陣基板之A-A線及B-b線箭頭方 向之斷面圖。在具有絕緣性的玻璃基板1上，配線有閘極 5、知描線2 (圖1)及輔助容量配線3 (第1層，形成閘極$ 及掃描線2之層）。其表面整體上，形成有由陽極氧化所 -16- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 581912 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（14) 形成的氧化膜（AO (Anodic Oxidation)膜，絕緣膜）2 a · 3 a。又，閘極5、掃描線2、輔助電容配線3及未形成此等 部份之玻璃基板1上，形成有氮化矽膜（siNx)或氧化矽膜 (Si〇2)之矽系化合物所構成的閘絕緣膜（第1絕緣膜、第2 絕緣膜、絕緣膜）4。 又’氧化膜（第1絕緣膜）2 a係形成於閘極5及掃描線2 (圖1 )上，氧化膜（第2絕緣膜）3 a係形成於輔助電容配線 3上。 閘極5係以掃描線2之支線形成，閘極5位置之閘絕緣膜 4上，形成有半導體區域（非晶性矽通道層i層、半導體層） 14及接觸層（η型碎層，n+層）15。又，接觸層15上，形 成有源極11及汲極13 (第二層，形成源極11及没極13之 層）。由此等部份（閘極5、閘絕緣膜4、半導體區域i 4、 接觸層1 5、源極1 1及汲極1 3 )所形成之作爲開關元件的 TFT 10，係就各畫素配置。 TFT 10之源極1 1，係引出至閘絕緣膜4上，形成源配線 1 1 a。源配線1 1 a係與後述之信號線6接續。又，没極1 3 係引出至閘絕緣膜4上，形成汲配線1 3 a。 此一汲配線1 3 a係延伸至與輔助電容配線3對面之位 置，輔助電容配線3之上方（閘絕緣膜4上）也有形成。此 處，輔助電容配線3與汲配線1 3 a，係介以氧化膜（介電體 層）3 a及閘絕緣膜（介電體層）4部份地對向，形成輔助電 容（靜電電容）1 2。又，没配線1 3 a係與後述之畫素電極7 接續。 -17- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------------訂---------線一 (請先閱讀背面之注意事項再填寫本頁) 581912 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（15 ) 爲了被覆上述所有部份，形成有由矽系化合物所構成之 保護膜（絕緣體層）8。又，保護膜8上形成有層間絕緣膜 (絕緣體層）9。又’層間絕緣膜9上，形成有信號線6及 畫素電極7 (第三層，形成信號線6及畫素電極7之層 此一信號線6係藉由形成於層間絕緣膜9及保護膜8之接 觸孔6a，接續於源配線lla，在信號線6、源極u之間傳 達信號。同樣地，畫素電極7係藉由形成於層間絕緣膜9 及保護膜8之接觸孔7a，與汲配線13a接續，在汲極13、 畫素電極7之間傳達信號。再者，畫素電極7亦藉由接觸 孔7a與輔助電容12接觸。 又，此等接觸孔6 a · 7 a，也可在TFT 1〇以外之區域形 成，由於可以確保充份領域之方式形成上述各接續部份， 可避免接續不安定之情事發生。 其次，茲將上述構成之本實施形態主動矩陣基板之製 法，佐以圖2及圖3説明之。 首先，在具有絕緣性之玻璃基板丨上，使手濺鍍法堆積 鋁、鉬、鈕所構成之單層膜或由其重疊成之多層膜。而 後，以光刻法予以圖案化成一定之形狀，再形成掃描線2 (圖1 )作爲知描線2之支線的閘極5及輔助電容配線3之 後’將其表面整體作陽極氧化而形成氧化膜（A〇膜）2a · 3 a。此處，掃描線2與輔助電容配線3係可藉由將相同之 膜圖案化而形成，係彼此平行且交替並列配置之多數條配 線。 其次，以電漿CVD法依序堆積成爲閘絕緣膜4之氮化矽 -18 - 本紙g尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） (請先閱讀背面之注意事項再填寫本頁) ------- 訂 ----I---線一 經濟部智慧財產局員工消費合作社印製 581912 A7 ______B7 五、發明說明（16) 膜（SINX)、成爲半導體區域14之非晶矽膜、成爲接觸層 15之η型矽膜。半導體區域14係供形成TFT 10之通道， 接觸層1 5係供形成半導體區域i 4之各兩端部分別與源極 11及没極13電氣接觸之層。另，將非晶矽膜及η型矽膜同 時圖案化成供成爲TFT 10之區域。 而後，將閘絕緣膜4圖案化，而形成與主要配線（圖未示） 之接觸部’該主要配線係將對於掃描線2之信號輸入端子 (圖未示）或輔助電容配線3共通地接續。 之後，利用濺鍍法堆積ITO (氧化銦錫）膜、鈕膜、鋁膜 等，藉由予以圖案化成一定之形狀，形成源極n、源配 線11a、汲極13及汲配線i3a。此時，汲配線13a係延伸 形成至輔助電容配線3之位置。 繼之，將此處所形成之源極i 1及汲極1 3，代替光阻劑 以乾式蚀刻法作蝕刻，令n型矽膜與源極及汲極側分離， 而完成作爲開關元件之TFT 10。 繼之’在形成有TFT 10之玻璃基板1的表面整體上，堆 積作爲保讓膜8之氮化矽膜之後，將其圖案化，而後分別 將令上層處所形成之信號線6與源配線1 1 a作電氣接續之 接觸孔6 a、令畫素電極7與汲配線1 3 a作電氣接續之接觸 孔7a、以及與驅動電路或讀出電路等接續之端子部份（圖 未示）的保護膜8，分別預先除去。 又，藉由將保護膜8以上述氮化矽膜等之安定的無機材 料等形成’可將TFT 10確實地保護，避免其受損。 繼之，在保護膜8上形成層間絕緣膜9。爲了形成層間 (請先閱讀背面之注意事項再填寫本頁) 訂---------線 « -19-FIG. 23 is a sectional view in the direction of the arrow of the M_M line in FIG. 21. Fig. 24 is a sectional view taken along the arrow N-N in Fig. 21; 25 is a plan view of an active matrix substrate according to an eighth embodiment of the present invention. FIG. 26 is a cross-sectional view taken along the line O-O in FIG. 25; FIG. FIG. 7 is a sectional view in the direction of the arrow of the P_P line in FIG. 25. Fig. 28 is a sectional view in the direction of the arrow of line Q-Q in Fig. 25. Description of Embodiment [Embodiment 1] Hereinafter, an embodiment of the present invention will be described with reference to Figs. I to 5 and Figs. 9 to 11. Fig. 1 is a plan view of the active matrix substrate of this embodiment, and its structure is as follows. On the glass substrate (substrate) J (see FIG. 2 or FIG. 3), a plurality of scanning lines 2 and a plurality of signal lines 6 are arranged in a grid pattern with each other, and corresponding switching elements are respectively provided with switching elements.和 Pixel electrode 7. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. As the switching element, a thin film transistor (hereinafter referred to as T F T) 1 with gate 5, source 11 and pole 13 is used. _Gate 5 is connected to scan line 2. Source U is connected to source wiring 1 1 a and contact hole 6 a. Connected to signal line 6 'No pole 1 3 is connected to drain wiring 1 3 a and contact hole 7 a. It is connected to the pixel electrode 7. Further, an auxiliary capacitor wiring 3 is formed below the contact hole 7a, and an auxiliary capacitor 12 is formed between the auxiliary capacitor wiring 13a (see FIG. 3). Figures 2 and 3 are cross-sectional views in the direction of arrows A-A and B-b of the active matrix substrate. On the insulating glass substrate 1, there are gates 5, wiring 2 (Fig. 1), and auxiliary capacity wiring 3 (the first layer, which forms the gate $ and the scanning line 2). On its entire surface, it is formed by the Anodizing Institute-16- This paper size is applicable to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 581912 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (14) The formed oxide film (AO (Anodic Oxidation) film, insulating film) 2 a · 3 a. In addition, the gate electrode 5, the scanning line 2, the auxiliary capacitor wiring 3, and the glass substrate 1 on which these portions are not formed are formed of a silicon-based compound having a silicon nitride film (siNx) or a silicon oxide film (Si〇2). The gate insulation film (the first insulation film, the second insulation film, and the insulation film) 4 formed. An oxide film (first insulating film) 2 a is formed on the gate 5 and the scanning line 2 (FIG. 1), and an oxide film (second insulating film) 3 a is formed on the auxiliary capacitor wiring 3. The gate 5 is formed by a branch line of the scanning line 2. A semiconductor region (amorphous silicon channel layer i layer, semiconductor layer) 14 and a contact layer (n-type chip layer, n + layer) 15. On the contact layer 15, a source electrode 11 and a drain electrode 13 are formed (a second layer is a layer on which the source electrode 11 and the sink electrode 13 are formed). The TFT 10 as the switching element formed by these parts (the gate electrode 5, the gate insulating film 4, the semiconductor region i 4, the contact layer 15, the source electrode 11 and the drain electrode 1 3) is a pixel. Configuration. The source 11 of the TFT 10 is drawn out to the gate insulating film 4 to form a source wiring 1 1 a. The source wiring 1 1 a is connected to a signal line 6 described later. In addition, the electrode 1 3 is drawn onto the gate insulating film 4 to form a drain wiring 1 3 a. This drain wiring 1 3a is extended to a position opposite to the auxiliary capacitor wiring 3, and is formed above the auxiliary capacitor wiring 3 (on the gate insulating film 4). Here, the auxiliary capacitor wiring 3 and the drain wiring 1 3 a are partially opposed to each other via an oxide film (dielectric layer) 3 a and a gate insulating film (dielectric layer) 4 to form an auxiliary capacitor (electrostatic capacitor) 1. 2. The non-wiring line 1 3 a is connected to a pixel electrode 7 described later. -17- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) --------------------- Order ------ --- Line 1 (Please read the precautions on the back before filling this page) 581912 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of Invention (15) In order to cover all the above parts, a silicon-based compound is formed The formed protective film (insulator layer) 8. An interlayer insulating film (insulator layer) 9 is formed on the protective film 8. On the interlayer insulating film 9, a signal line 6 and a pixel electrode 7 are formed (the third layer is a layer forming the signal line 6 and the pixel electrode 7. This signal line 6 is formed on the interlayer insulating film 9 and protected The contact hole 6a of the film 8 is connected to the source wiring 11a and transmits a signal between the signal line 6 and the source u. Similarly, the pixel electrode 7 is formed by the contact hole 7a formed in the interlayer insulating film 9 and the protective film 8. Connected to the drain wiring 13a, a signal is transmitted between the drain electrode 13 and the pixel electrode 7. In addition, the pixel electrode 7 is also in contact with the auxiliary capacitor 12 through the contact hole 7a. These contact holes 6a · 7 a. It can also be formed in areas other than TFT 10, because the above-mentioned connection parts can be formed in a manner that ensures sufficient fields, which can avoid the occurrence of instability in connection. Second, the active matrix substrate of this embodiment with the above configuration is hereby described. The manufacturing method is described with reference to Figs. 2 and 3. First, on a glass substrate having insulation properties, a single-layer film composed of aluminum, molybdenum, or buttons is deposited by hand sputtering, or a multi-layer film formed by overlapping the layers. Then, it is patterned into a certain shape by photolithography, and then After forming scan line 2 (Fig. 1), gate 5 and auxiliary capacitor wiring 3, which are the branch lines of drawing line 2, 'the entire surface is anodized to form an oxide film (Ao film) 2a · 3a. Here, scan Line 2 and auxiliary capacitor wiring 3 can be formed by patterning the same film, and are a plurality of wirings arranged in parallel and alternately arranged side by side. Next, nitriding of gate insulating film 4 is sequentially deposited by plasma CVD method Silicon-18-The g standard of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 cm) (Please read the precautions on the back before filling this page) ------- Order ---- I- -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, Line 581912 A7 ______B7 V. Description of the invention (16) Film (SINX), amorphous silicon film that becomes semiconductor region 14, n-type silicon film that becomes contact layer 15. Semiconductor The region 14 is a channel for forming the TFT 10, and the contact layer 15 is a layer for forming both ends of the semiconductor region i 4 to be in electrical contact with the source electrode 11 and the non-electrode 13 respectively. In addition, an amorphous silicon film and an n-type are formed. The silicon film is simultaneously patterned into a region for becoming the TFT 10. Then, the gate insulating film 4 is patterned, A contact portion with a main wiring (not shown) is formed. The main wiring is connected in common to the signal input terminal (not shown) of the scanning line 2 or the auxiliary capacitor wiring 3. Then, ITO is deposited by sputtering ( Indium tin oxide) film, button film, aluminum film, etc. are patterned into a certain shape to form source n, source wiring 11a, drain 13 and drain wiring i3a. At this time, drain wiring 13a is extended to assist The position of the capacitor wiring 3. Next, the source electrode i 1 and the drain electrode 13 formed here are etched by dry etching instead of the photoresist to separate the n-type silicon film from the source and drain sides, and The TFT 10 as a switching element is completed. Following this, a silicon nitride film is deposited on the entire surface of the glass substrate 1 on which the TFT 10 is formed, and then patterned, and then the signal lines 6 and source wirings 1 formed on the upper layer are formed. a Make contact holes 6 for electrical connection a, Make pixel electrode 7 and drain wiring 1 3 a Make contact holes 7a for electrical connection, and protect terminal parts (not shown) connected to drive circuits or readout circuits, etc. The films 8 were removed in advance. In addition, by forming the protective film 8 with the above-mentioned stable inorganic material such as a silicon nitride film, the TFT 10 can be reliably protected from damage. Then, an interlayer insulating film 9 is formed on the protective film 8. In order to form the interlayer (please read the notes on the back before filling this page) Order --------- Line «-19-

五、發明說明（17) 絕緣膜9，係塗布且右咸冰、 材科），-曝光海： 脂(感光性樹脂、樹脂 與保護膜8之場合相@^&gt;狀。此時， 緣膜9分別除去而形成。 h寺&lt;層間絕 又，形成層間絕緣膜9時之樹脂的塗 塗本法签&gt; 士，卩这、 係可利用旋轉 t布法寺〈成膜万法。藉由此旋轉塗布法， 例如W…呈度之較厚的樹脂膜。依此 、:成： 層間絕緣膜9，可將形成有TFT /尸/ 坦化。 守&lt; #份的表面階差平 ’其'介質常數較小之 。特別是壓克力系樹 介質常數約小3，更 又，樹脂一般上與無機材料等比較 故’宜作爲形成層間絕緣膜9之材料 脂，與聚醯亞胺等之其他樹脂相較， 爲適宜。 而後’在此層間絕緣膜9上以濺鍍法堆積ιτ〇膜、赵 膜、銘齡’藉由將其圖案化成—定之形&amp; 號6及畫素電極7。 Π時形成仏 又，圖1.中，畫素電極7係形成爲不與 ,,,, η 1兴iFT 10重疊之形 狀’但也可配置成在TFT 10之上方重叠。 —於此-製造方法中，㈣線6與畫素電極7係藉由將同 —層圖案化形成之故，只要將迄今爲止使用之光罩變更即 可實施。是以，與習用技術相較，並未増加製造程序 此可抑制成本提高。 以上係就信號線6與畫素電極7由同—層形成之場合作 説明’但爲了降低信號線電容（寄生電容、靜電電容）=可V. Description of the invention (17) Insulating film 9 is coated and coated with ice, materials, etc.,-exposure sea: grease (photosensitive resin, resin and protective film 8 @ ^ &gt; shape. At this time, margin The film 9 is formed separately. The temples &lt; interlayer insulation, the coating of the resin when the interlayer insulation film 9 is formed, and the method can be used to rotate the Buffalo temple. By this spin coating method, for example, a thick resin film with a thickness of W. According to this, the formation of: the interlayer insulating film 9 can form the TFT / body / tanning. The surface level difference of #parts is flat. 'Its' dielectric constant is smaller. Especially the acrylic tree has a dielectric constant which is about 3 smaller. Furthermore, the resin is generally compared with inorganic materials and so on. Compared with other resins such as amine, it is more suitable. Then, ιτ〇 film, Zhao film, and Mingling were deposited by sputtering on this interlayer insulating film 9 by patterning them into a fixed shape &amp; No. 6 and drawing Element electrode 7. Π is formed at the same time. In Fig. 1, the pixel electrode 7 is formed in a shape that does not overlap with the iFT 10 However, it can also be arranged to overlap above the TFT 10. In this manufacturing method, the hafnium wire 6 and the pixel electrode 7 are formed by patterning the same layer, as long as the mask used so far is changed It can be implemented. Therefore, compared with the conventional technology, the manufacturing process is not added. This can suppress the increase in cost. Capacitance (parasitic capacitance, electrostatic capacitance) = possible

本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 581912 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（18 ) 將信號線6形成於層間絕緣膣 、 豕腰9炙上，並無限制。之所以 將化说線6與晝素電極7由同一廢 ^ U 層形成，王要是爲了製造 步驟的簡單化。 衣 是以’如透明型液晶顯示奘 &amp; 貝下表置般I畫素電極7必須爲透 明電極，且信號線6必須爲導電性較透明電極爲佳之金屬 膜之場合等等，可將渠等分別由不同之層形成。 其次，兹説明上述構成之本實施形態的主動矩陣基板， 其信號線電容値較習用主動矩陣基板大幅降低之情形。此 處，兹就占信號線電容値大部份之信號線6與掃描線2及 輔助電容配線3之間所形成的靜電電容値作考声。 作爲其典型的例子，氧化膜。〜之厚爲〇二5 [輝], 介質常數爲24，閘絕緣膜4之厚度爲〇 Μ卜瓜]，介質常 數爲6.9。保護膜8之厚度爲〇·5 ^m]，介質常數爲&amp;9, 層間絕緣膜9之厚度爲3 |&gt;m]，介質常數爲3。又，習用 之主動矩陣基板（圖6〜8 )及本實施形態，此等値係設成相 同0 根據習用之主動矩陣基板，信號線56與掃描線52或輔 助電谷配線5 3之間’僅存在有閘絕緣膜5 4及氧化膜5 2 a • 53a (請參見圖7及圖8)，而本實施形態中，信號線6與 掃描線2或輔助電容配線3之間，存在有閘絕緣膜4、氧化 膜2 a · 3 a、保護膜8及層間絕緣膜9。 與信號線6之重疊部份1 [ ju m2 ]的靜電電容之計算結果 顯示’習用之主動矩陣基板爲0.16 [fF/ju m2]，而本實施形 態則爲0.0078 [fF/a m2]。本實施形態中，藉由將信號線6 -21 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------4i!——tr------- (請先閱讀背面之注意事項再填寫本頁) 線； 581912 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（19) 配置於層間絕緣膜9上，信號線6與掃描線2或輔助電容配 線3之間隔d約大至4 [//m]。藉此，寄生於信號線6之靜電 電容則成爲習用之約1/2〇，大幅降低。 又’本實施形態中之主動矩陣基板，可使用於主動矩陣 型顯示裝置（例如液晶顯示裝置）或平板型畫像感測器（例 如平板型X射線感測器）。惟，如習用技術欄所説明，使 用於平板型畫像感測器之場合，與使用於主動型顯示裝置 比較，有必須將輔助電容配線値設定地較大之場合。 如此之場合下，可將圖1所示之主動矩陣基板作爲基 礎’而如圖9〜圖11所示，將輔助電容32之配置任意變更 即可。此處’圖9係本實施形態的一個變形例之主動矩陣 基板的平面圖。又，圖i 0及圖i i分別係沿上述主動矩陣 基板之F-F線及G-G線之箭頭方向斷面圖。又，圖9〜圖 11中，與圖1〜圖3中之構成要件具有同等機能的構成要 件，僅加註相同之符號，至於其説明在此作部份省略。 又’圖10中所示之構造，與上述圖2之場合相同。 此一主動矩陣基板，如圖9及圖所示，形成輔助電容 3 2之輔助電容配線2 3及汲配線，係配置成占有畫素中大 部份之面積。藉此而形成輔助電容32。 上述圖1中所示之主動矩陣基板中，形成有具有一定寬 度的輔助電容配線3。相對於此，圖9所示之主動矩陣基 板中所形成之輔助電容配線2 3，其信號線6之下方寬度小 (例如同於圖1之場合），而畫素電極7下方之寬度大。 又，有關汲配線3 3 a，對應於輔助電容配線2 3，其係經擴This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 581912 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the invention (18) The signal line 6 is formed in the interlayer insulation 9 Sunburn is unlimited. The reason why the chemical wires 6 and the day electrode 7 are formed from the same waste layer is to simplify the manufacturing steps. For example, if the pixel electrode 7 must be a transparent electrode, and the signal line 6 must be a metal film with better conductivity than a transparent electrode, such as a transparent LCD display, you can change the channel. Etc. are formed by different layers, respectively. Next, a description will be given of a case where the active matrix substrate of the present embodiment configured as described above has a signal line capacitance that is significantly lower than that of a conventional active matrix substrate. Here, the electrostatic capacitance formed between the signal line 6 which accounts for most of the signal line capacitance and the scanning line 2 and the auxiliary capacitor wiring 3 is considered. As its typical example, an oxide film. The thickness is 205 [glow], the dielectric constant is 24, the thickness of the gate insulating film 4 is 0 μm, and the dielectric constant is 6.9. The thickness of the protective film 8 is 0.5 μm], the dielectric constant is &amp; 9, the thickness of the interlayer insulating film 9 is 3 | &gt; m], and the dielectric constant is 3. In addition, the conventional active matrix substrate (FIGS. 6 to 8) and this embodiment are set to be the same. According to the conventional active matrix substrate, the signal line 56 is between the scanning line 52 and the scanning line 52 or the auxiliary power valley wiring 53. Only the gate insulating film 5 4 and the oxide film 5 2 a • 53 a (see FIGS. 7 and 8) exist. In this embodiment, a gate exists between the signal line 6 and the scanning line 2 or the auxiliary capacitor wiring 3. The insulating film 4, the oxide film 2 a · 3 a, the protective film 8, and the interlayer insulating film 9. The calculation result of the electrostatic capacitance of the overlapped part 1 [ju m2] with the signal line 6 shows that the conventional active matrix substrate is 0.16 [fF / ju m2], but this embodiment is 0.0078 [fF / a m2]. In this embodiment, the signal wire 6 -21 paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------- 4i! ---- tr ---- --- (Please read the precautions on the back before filling this page) line; 581912 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (19) It is arranged on the interlayer insulation film 9, the signal line 6 The interval d between the scanning lines 2 or the auxiliary capacitor lines 3 is approximately 4 [// m]. As a result, the electrostatic capacitance parasitic to the signal line 6 becomes about 1/20 of the conventional value, which is greatly reduced. Also, the active matrix substrate in this embodiment can be used in an active matrix type display device (for example, a liquid crystal display device) or a flat type image sensor (for example, a flat type X-ray sensor). However, as explained in the conventional technical column, when it is used for a flat-type image sensor, compared with an active display device, it is necessary to set the auxiliary capacitor wiring 値 larger. In this case, the active matrix substrate shown in FIG. 1 can be used as a base ', and as shown in FIGS. 9 to 11, the arrangement of the auxiliary capacitor 32 can be changed arbitrarily. Here 'FIG. 9 is a plan view of an active matrix substrate according to a modification of the present embodiment. Figs. I 0 and i i are sectional views taken along the arrows F-F and G-G of the active matrix substrate, respectively. In addition, in FIG. 9 to FIG. 11, the constituent elements having the same functions as the constituent elements in FIGS. 1 to 3 are given the same reference numerals, and descriptions thereof are omitted here. The structure shown in Fig. 10 is the same as that in the case of Fig. 2 described above. This active matrix substrate, as shown in FIG. 9 and FIG., Forms the auxiliary capacitor wiring 23 and the drain wiring of the auxiliary capacitor 32, which are arranged to occupy most of the area of the pixel. Thereby, the auxiliary capacitor 32 is formed. In the above-mentioned active matrix substrate shown in FIG. 1, an auxiliary capacitor wiring 3 having a certain width is formed. In contrast, the auxiliary capacitor wiring 23 formed in the active matrix substrate shown in FIG. 9 has a small width below the signal line 6 (for example, as in FIG. 1) and a large width below the pixel electrode 7. In addition, the drain wiring 3 3 a corresponds to the auxiliary capacitor wiring 2 3 and is expanded.

本紙張尺度適用中國國家標準（CNS)A4規格（210 X --------------------訂---------線· (請先閱讀背面之注意事項再填寫本頁) -22- 581912 A7 五、發明說明（2〇 ) 大，具有^致與輔助電容配線23相近之面積。 (請先閱讀背面之注意事項再填寫本頁) 如此’藉由將輔助電容配線2 3及汲配線3 3 a之面積擴 大，可謀求輔助電容32之電容値的增加。又，當尋求進 輔助電谷値的增大時，在TFT 1〇之開關特性可確保 的範圍内’將介在於輔助電容配線2 3與汲配線3 3 a間之氧 化膜3 a及閘絕緣膜4薄化即可。 ^ ’於本實施形態中，即使將閘絕緣膜4及氧化膜2a · 3a薄化’ d也不會成爲層間絕緣膜9及保護膜8厚度合計値 3·5 [vm]以下’因此，信號線6與掃描線2或輔助電容配 ，、泉2 3之重疊郅份所產生的電容値不會成爲〇 〇〇83 [汪“瓜2] 以上，幾乎不增加。 如此，根據本實施形態中之主動矩陣基板，信號線電容 値大幅降低，且即使閘絕緣膜4或氧化膜2 a · 3 &amp;薄化，信 號線電容値之增加量也可設地非常之小。 ,在本實施形態主動矩陣基板（請參見圖i〜圖·3)中，備有 爲了在與;及配線l3a之間形成輔助電容12之輔助電容配線 3。然而，.就本發明之實施，輔助電容配線3並非一定必 要了採利用相鄰之畫素的掃描線2形成輔助電容12之構 造。 經濟部智慧財產局員工消費合作社印製 不設此一輔助電容配線3之構造，一般爲人所知的是Cs 閘上線構造。於本實施形態中，茲就採用此（：3閘上線構 造I 一個變形例，佐以圖2、圖4及圖5作説明。又，於圖 4及圖5中，與圖i及圖3中構成要件具有同等機能之構成 要件，僅附狂相同之符號，至於其說明則在此省略。又， -23- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) 581912 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（21 ) 圖4中之Α·Α線箭頭方向斷面圖，係與圖2$Α·Α線 方向斷面圖相同，其説明在此省略。 、圖4係本變形例主動矩陣基板之平面圖。此處，與圖1 主動矩陣基板不同之點係在於，未設置輔助電容配線〕， 汲配線13a係延伸至鄰接掃描線2b之位置，汲配線13玨與 鄰接掃描線2b係介以閘絕緣膜4等配置成部份重疊。、 圖5係圖4主動矩陣基板之c_c線箭頭方向斷面圖。此 處，與圖3不同之點係在於，圖3中之輔助電容配線3在圖 4中係成爲鄰接掃描線2 b。是以，輔助電容i 2係形成於没 配線1 3 a與鄰接掃描線2 b對向之部份。 於此一場合也是，可將信號線6與掃描線2之間所產生 的靜電電容同樣地作大幅降低。又，由於毋需另行形成輔 助電容配線’與掃描線2獨立形成之輔助電容配線3所導 致之靜電電容不會產生。 本變形例之場合，與前述實施例形態相較，構造上更爲 簡單。惟若將鄰接掃描線2 b作爲輔助電容1 2使用時，特 別是如畫像感測器般，需要非常大的輔助電容値之場合， 有隨著掃描線2之時間常數的增加，由掃描線2所傳達之 信號中，延遲之問題會變得顯著，或是，鄰接掃描線2b 之電位發動、降落時，加諸畫素之雜訊成分增加，而對 S /N比帶來不良的影響等之情事。 另一方面，與掃描線2無關另行設定輔助電容配線3之 場合，加諸其上之信號直流即可，因此並無信號延遲之問 題，對於畫素也不會產生雜訊的問題。 -24- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------------- f請先閱讀背面之注意事項再填寫本頁} 581912This paper size applies to China National Standard (CNS) A4 specification (210 X -------------------- Order --------- line · (please first Read the notes on the back and fill in this page) -22- 581912 A7 V. Description of the invention (20) Large, with an area close to that of the auxiliary capacitor wiring 23. (Please read the notes on the back before filling in this page) In this way, by increasing the area of the auxiliary capacitor wiring 2 3 and the drain wiring 3 3 a, it is possible to increase the capacitance 32 of the auxiliary capacitor 32. When the increase of the auxiliary electric valley 寻求 is sought, the As long as the switching characteristics can be ensured, the thickness of the oxide film 3 a and the gate insulating film 4 between the auxiliary capacitor wiring 2 3 and the drain wiring 3 3 a can be reduced. ^ 'In this embodiment, even if the gate is insulated The thickness of the film 4 and the oxide film 2a · 3a will not become the total thickness of the interlayer insulating film 9 and the protective film 8 値 3 · 5 [vm] or less'. Therefore, the signal line 6 is matched with the scanning line 2 or the auxiliary capacitor, The capacitance generated by the overlapping component of the spring 2 3 will not be more than 0.0083 [Wang "Melon 2], which will hardly increase. In this way, according to the active matrix in this embodiment The substrate, the signal line capacitance 値 is greatly reduced, and even if the gate insulating film 4 or the oxide film 2 a · 3 &amp; is thinned, the increase amount of the signal line capacitance 可 can be set very small. In this embodiment, the active matrix substrate (Please refer to Fig. I to Fig. 3), there is an auxiliary capacitor wiring 3 for forming an auxiliary capacitor 12 between and the wiring 13a. However, for the implementation of the present invention, the auxiliary capacitor wiring 3 is not necessarily necessary Adopting the scanning line 2 of the adjacent pixels to form the structure of the auxiliary capacitor 12. The structure of the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs does not provide this auxiliary capacitor wiring 3. The structure is generally known as the Cs gate on-line structure . In this embodiment, hereby (a: 3 gate on-line structure I a modified example, described with reference to Figure 2, Figure 4 and Figure 5. Also, in Figure 4 and Figure 5, and Figure i and Figure The constituent elements in 3 have the same function as the constituent elements, and only the same symbols are attached, and the description is omitted here. Moreover, -23- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 581912 Employee Consumption of Intellectual Property Bureau, Ministry of Economic Affairs A7 printed by Sakusha Co., Ltd. 5. Description of the invention (21) The cross-sectional view in the direction of the arrow AA in FIG. 4 is the same as the cross-sectional view in the direction of the line AA in FIG. 2 and its description is omitted here. Figure 4 This is a plan view of the active matrix substrate of this modification. Here, the difference from the active matrix substrate of FIG. 1 is that no auxiliary capacitor wiring is provided], the drain wiring 13a extends to a position adjacent to the scanning line 2b, and the drain wiring 13 玨 and The adjacent scanning lines 2b are partially overlapped with each other through the gate insulating film 4 and the like. FIG. 5 is a cross-sectional view taken along the line c_c of the active matrix substrate of FIG. 4. Here, the difference from FIG. 3 lies in that the auxiliary capacitor wiring 3 in FIG. 3 becomes the adjacent scanning line 2 b in FIG. 4. Therefore, the storage capacitor i 2 is formed at a portion where the wiring 1 3 a is opposed to the adjacent scanning line 2 b. Also in this case, the electrostatic capacitance generated between the signal line 6 and the scanning line 2 can be substantially reduced similarly. In addition, since it is not necessary to separately form an auxiliary capacitor wiring 'and the auxiliary capacitor wiring 3 formed separately from the scanning line 2, no electrostatic capacitance is generated. In the case of this modification, the structure is simpler than that of the aforementioned embodiment. However, if the adjacent scanning line 2 b is used as the auxiliary capacitor 12, especially when a very large auxiliary capacitor is needed like an image sensor, there is a possibility that the scanning line 2 will increase with the time constant of the scanning line 2. In the signal conveyed by 2, the problem of delay becomes significant, or when the potential of the adjacent scanning line 2b starts and falls, the noise component added to the pixel increases, which adversely affects the S / N ratio. Waiting for love. On the other hand, when the auxiliary capacitor wiring 3 is separately set regardless of the scanning line 2, the signal DC may be added thereto, so there is no problem of signal delay, and no problem of noise is generated for pixels. -24- This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) ----------------- f Please read the notes on the back before filling in this Page} 581912

發明說明（22 ) 又，如習用般之夾著薄的閘絕緣膜4，信號線6橫斷掃 描線2及輔助電容配線3之場合，就各畫素，掃描線2及輔 助電容配線3之兩條配線會與信號線6交叉，而會有信號 電容値增加此-不良現象的疑慮。然而，根據上述實施形 悲，不會產生此一副作用，將掃描線2與輔助電容配線3 別途形成之場合，本發明之優點特別之大。 又，本發明之主動矩陣基板中，在畫素電極7上，設置 藉由X射線或光學之電磁波的入射而產生正孔及電子的構 造（光電變換層），再於其上設置對向電極，藉由在上述兩 者間施加電壓，可將在光電變換層中因χ射線或光等電磁 波的入射所生之電荷，由畫素電極7所收集。此處，作爲 光電變換層，例如可採用非晶性a_Se4CdTe、pbl2等。 此時，畫素電極7係作爲電荷收集用電極發揮機能，形 成平板型畫像感測器。於此一場合中，有讀出因微弱的光 所產生之少量電荷的場合，有必要將起因於信號線電容之 雜訊儘量減小，故而，本發明效果大。又，平板型畫像感 測器之構埠係如後述。 &quot; 如上所述，本實施形態之主動矩陣基板，如圖1〜5、圖 9〜11所示’配置於玻璃基板1之掃描線2、具有與該掃描 線接續之閘極5且配置於上述玻璃基板i上之TFT 1〇、與 該TFT 10之波極13接績之晝素電極7、以及與該tft 1 〇之 源極1 1接續之信號線6 ;上述信號線6及畫素電極7係由同 一層所構成，構成上述信號線6及畫素電極7之層與構成 上述没極1 3及源極1 1之層之間，具有絕緣體層（保護膜8 -25- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） (請先閱讀背面之注意事項再填寫本頁)Description of the invention (22) In the case where the thin gate insulating film 4 is used, the signal line 6 crosses the scanning line 2 and the auxiliary capacitor wiring 3 as usual, for each pixel, the scanning line 2 and the auxiliary capacitor wiring 3 The two wirings will cross the signal line 6, and there will be signal capacitance, which increases the concern of this undesirable phenomenon. However, according to the embodiment described above, this side effect does not occur, and when the scanning line 2 and the auxiliary capacitor wiring 3 are formed separately, the advantages of the present invention are particularly great. In the active matrix substrate of the present invention, a pixel electrode 7 is provided with a structure (photoelectric conversion layer) that generates positive holes and electrons upon the incidence of X-ray or optical electromagnetic waves, and a counter electrode is provided thereon. By applying a voltage between the two, the electric charges generated by the incidence of electromagnetic waves such as x-rays or light in the photoelectric conversion layer can be collected by the pixel electrode 7. Here, as the photoelectric conversion layer, for example, amorphous a_Se4CdTe, pbl2, or the like can be used. At this time, the pixel electrode 7 functions as a charge collection electrode to form a flat-type image sensor. In this case, in the case where a small amount of electric charge generated by weak light is read out, it is necessary to minimize noise due to the capacitance of the signal line, and therefore, the effect of the present invention is large. The structure of the flat-type image sensor is described later. &quot; As mentioned above, the active matrix substrate of this embodiment is shown in FIGS. 1 to 5 and FIGS. 9 to 11 'scanning line 2 disposed on glass substrate 1 and having gate 5 connected to the scanning line and disposed on The TFT 10 on the glass substrate i, the day element electrode 7 connected to the wave electrode 13 of the TFT 10, and the signal line 6 connected to the source 11 of the tft 10; the signal line 6 and pixels The electrode 7 is composed of the same layer, and there is an insulator layer (protective film 8 -25- this paper) between the layer constituting the signal line 6 and the pixel electrode 7 and the layer constituting the above-mentioned electrode 13 and source electrode 11. Standards are applicable to China National Standard (CNS) A4 specifications (21 × 297 mm) (Please read the precautions on the back before filling this page)

--------訂---------線I r&lt;濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 581912 A7 _ __________B7 五、發明說明（23) 或層間絕緣膜9 )，且以此爲特徵。 根據上述構成，與畫素電極7由同一層所構成之信號線 6，與形成於玻璃基板1上之TFT 10的源極1 1及構成及極 1 3之層之間，係介以絕緣體層配置。是以，配置於坡璃 基板1上之掃描線2，係與信號線6之間成爲至少介以繞緣 體層之位置關係。精此’與掃描線2之間形成之信號線電 容的電容値，可藉絕緣體層降低。 故而，起因於信號線電容之信號線6或掃描線2之時間 常數的增大，可予防止，此外，也可提高信號線6或掃描 線2所傳達之信號的傳達速度。再者，起因於信號線電容 之雜訊也可降低。 另一方面，因源極1 1及汲極1 3與信號線6之間，易言 之，ΊΤΤ 10與信號線6之間，設有絕緣體層之故，即使増 大絕緣體層之厚度降低信號線電容値，源極1 1及汲極j 3 與開關元件本體（半導體區域1 4 )仍可密接。 是以，可避免源極1 1及汲極1 3與半導體區域1 4之間的 接觸不安卑。又，藉此，還可充份增大絕緣體層之厚度， 進一步降低信號線電容値。 如此，可提供供形成信賴性高、能顯示式拍攝高品質畫 像之畫像顯示裝置或畫像攝影裝置的主動矩陣基板。 又，上述主動矩陣基板宜具有形成於上述絕緣體層與玻 璃基板1之間，而與晝素電極7串聯接續之輔助電容12或 3 2 (標彡己爲輔助電容12/3 2，以下準此）、以及該輔助電容 12/32之一側電極的輔助電容配線3/23。 -26- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -I丨丨丨丨丨•丨丨丨丨丨-丨訂-丨ί丨—丨丨-. C請先閱讀背面之注意事項再填寫本頁} A7 B7 五、發明說明（24 猎由上述構成，輔助電容配線3/23與掃描線2之場合相 同，成爲與信號線6之間至少介有絕緣體層之位置關係。 精此，與輔助電容配線3/23之間所形成的信號線電容之電 容ί，可藉絕緣體層降低。是以，起因於掃描線2或輔助 %谷配，.泉3/23 號線電容値也可降低，可大幅降低信號 線電容値。 本實施形態之主動矩陣基板，具有在玻璃基板i上成矩 陣狀配置之畫素電極7、具有與該畫素電極7接續之没極 13。且具有閘極5及源極&quot;之加1〇、與閉極#續之掃 描線2、以及與源極n接續之信號線6 ;掃描線2與信號線 6係彼此父又並在玻璃基板上分別格子狀配置，被覆掃描 線2及TFT 10之絕緣體層（保護膜8或層間絕緣膜9)係設於 玻璃基板1上，畫素電極7係設於絕緣體 係設於絕緣體層上，以此爲特徵者。 Ά泉6 藉由上述構成，掃描線2與信號線6之間，至少形成有 絕緣體層，因此，掃描線2與信號線6成對向，藉此，形 成之信號緣電容的電容値可藉絕緣體層之介在而降低。 經濟部智慧財產局員工消費合作社印製 易，藉由上述構成，掃描線2及TFT 1〇與信號線6 I間，成爲具有絕緣體層之構造。是以，可在採行半導體 區域14與TFT 10之電極密接的構造下，降低與掃描線二之 間所形成的信號線電容之電容値。如此，可提供信賴性 高、可顯示或拍攝高品質畫像之主動矩陣基板。 又，由於畫素電極7設於絕緣體層上，可將畫素電極7 露出形成。是以，使用此一主動矩陣基板形成液晶顯示裝 -27- 581912 A7 ---------— H7_ _ 五、發明說明（25 ) (請先閱讀背面之注意事項再填寫本頁) 置或畫像感測器之場合，可分別將液晶層或光電變換層與 里素電極接近形成，可使各層與畫素電極7之間，各自之 笔位或電荷的傳達圓滑地進行（迅速化）。 又，TFT 10之源1 1及汲極丨3與閘極5之間，由於與絕緣 恤層並無特別之關係，即使變更絕緣體層之厚度，也不會 對TFT 10之機能造成影響。是以，可充分地增大絕緣體層 之厚度以充分減小信號線電容之電容値。 另’上述主動矩陣基板中之信號線6及畫素電極7宜由 同一層所構成。 根據上述構成，由於可藉由將同一層圖案化形成信號線 6及2素電極7，因此，藉由變更形成習用畫素電極7時所 用之圖案化屏罩，可在避免製造過程增加下製造主動矩陣 基板。是以，可抑制構造變更所帶來之成本上昇。 再者，上述主動矩陣基板，具有自没極13延伸之汲配 ’泉13a/33a、與掃描線2係由同一層所構成且與汲配線 13a/33a部分對向形成之輔助電容配線3/23 ;較佳的是， 閘絕緣膜4.係在輔助電容配線3/23與汲配線13a/33a之間夾 設0 經濟部智慧財產局員工消費合作社印製 根據上述構成，藉由在輔助電容配線3/23與汲配線 13a/33a&lt;間夾設閘絕緣膜4，可形成輔助電容12/32。此 處，輔助電容配線3/23與掃描線2係由同一層所構成（輔助 電谷配線3/23可爲利用掃描線2之一部份（鄰接掃描線2 b 者）’且没配線13 a/3 3 a係自汲極1 3延伸，因此，絕緣膜4 之厚度，可與絕緣體層獨立決定。 -28- 本紙張尺度剌中國國家標準（CNS)A4規格（210 X 297公爱） 581912 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（26 ) 是以，可在降低^號線電容値下，增大輔助電容値。藉 此，、可抑制畫素電極7電位之變動，可作安定之晝像的顯 不或攝影。又，藉由將閘絕緣膜4薄化，可增大輔助電容 値’因此’可有化輔助電容配線3/23之線寬，提高形成透 過型顯7F裝置時之開口·率。亦即，可同時確保輔助電容値 及開口率二者。 如此，可提供信賴性高且畫像品質高之主動矩陣基板。 本實施形態中之主動矩陣基板，具有與叮丁 1〇接續之信 唬線6及掃描線2，信號線6及掃描線2係介以樹脂材料配 置，並以此爲特徵。 藉此構成，可減小信號線6與掃描線2之間所產生之靜 電電容的電容値，可降低信號線電容之電容値。 又，備有輔助電容12/32之主動矩陣基板中，形成輔助 電容12/32之輔助電容配線3/23與信號線6之間宜介在有樹 脂材料。藉此，可進一步降低信號電容之電容値。 本實施形態之主動矩陣基板之製法，其特徵在於··將掃 描線2及輔助電容配線3/23由同一膜之圖案化形成，將源 極11及汲極13由同一膜之圖案化形成，將畫素電極7與信 號線6由同一膜之圖案化形成。 根據上述方法，掃描線2與輔助電容配線3/23、源極1 1 與汲極1 3、以及信號線6與畫素電極7，分別係藉由將同 一膜圖案化而形成。是以，與具有層間絕緣膜9之習用主. 動矩陣基板的製法相較，可在避免程序之複雜化及過程數 目之下製造主動矩陣基板。 -29- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------^--------- (請先閱讀背面之注意事項再填寫本頁) 581912 經濟部智慧財產局員工消費合作社印製 A7 ______B7___ 五、發明說明（27 ) 如上所述，本實施形態之主動矩陣基板，形成掃描線2 (閘極5 )之層（第1電極層）、形成源極1 1之層（第2電極 層）、及形成信號線6之層，係在玻璃基板1上以此時序形 成，而在形成源極1 1之層與形成信號線6之層之間，備有 絕緣體層（保護膜8或層間絕緣膜9)。又，掃描線（第j配 線）之與信號線（第2配線）6，係介以絕緣體層配置。 又，較佳的是形成掃描線2之層中，形成有閘極5，没 極1 3係與形成源極1 1之層由同一層所形成，且閘極5與源 極1 1及没極1 3之間’與源極1 1及没極1 3密接形成TFT 10 之半導體區域14。 藉由此一構成，與在閘極與源極及汲極間形成絕緣體層 之習用場合不同，源極11及汲極13與半導體區域14之接 觸確實，可形成信賴性高的TFT 10。 又，較佳的是，半導體區域1 4與形成掃描線2及閘極5 之層之間，形成有第一絕緣膜（閘絕緣膜4或氧化膜2 a )， 掃描線2與信號線6係進一步介以第一絕緣膜配置。 根據此一構成，藉由此第一絕緣膜之存在，可進一步降 低仏號線6與掃描線2之間所產生之信號線電容的電容 値。 又’較佳的是，接續於汲極1 3之輔助電容12/32係形成 於上述絕緣體層與玻璃基板1之間，形成輔助電容12/32之 一側電極的輔助電容配線3/23係相對信號線6介以絕緣體 層配置。 根據此一構成，輔助電容12/32係配置於絕緣體層與破 -30- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -------訂---------線 籲 581912 五、發明說明（28 ) 埸基板1之間，將此輔助電容12/32在與汲極13間形成之 輔力私♦配、，泉3/23，係與信號線6之間介以絕緣體層配 置〇 έ用之主動矩陣基板，其構造是介以輔助電容配線上形 成 &lt; 閘絕緣膜，配置信號線及輔助電容配線。 相對於此’本發明的構成是，信號線6相對掃描線2及 輔助電容配線3/23之任一者，均是介以絕緣體層配置。是 以，就起因於掃描線2及輔助電容配線3/23之任一者的俨 號線電容，可發揮降低上述電容値的效果。如此，可大^ 降低信號線電容之電容値。 又，輔助電容配線3/23宜由與形成掃描線2之層相同的 層所形成。藉此，形成掃描線2時之圖案化過程中，藉由 變更其圖案，可形成輔助電容配線3/23。 又，較佳的是，形成汲極丨3之層與形成輔助電容配線 3/23之層之間，形成有第二絕緣膜（閘絕緣膜*或氧化膜 3 a)，輔助電容配線3/23與信號線6，進一步介以第二絕 緣膜配置。 根據此一構成，藉由第二絕緣膜之存在，信號線6與輔 助電容配線3/23間所生之信號線電容的電容値可進一步減 少0 另，較佳的是，接續於汲極13之畫素電極7，與形成信 號線6之層由同一層形成。 根據此一構成，即使是信號線6與源極i丨由不同之層形 成的上述構成中，由於信號線6與晝素電極7係由同一層 (請先閱讀背面之注意事項再填寫本頁) -1------訂---I-----線 經濟部智慧財產局員工消費合作社印製 -31 五、發明說明（29 2形成’故而製造過程中之過程數目的大幅增加可爲之避 料將電極7’藉由針對㈣材 一 子包膜作圖案化，而由相同之 f ^ 是以’耩由將習用主動矩陣基板之製造 “。 時所用的圖案化屏罩之圖案部分變更，即可製：：“極 矩陣基板。 1成此一主動 如此，可以較少之製程數製 求產率之提高及降低成本。 動矩陣基板，可謀 膜上述絕緣體層宜含有由樹脂材料所構成之層間絕緣 藉由此一構成，信號線6與掃描線2或輔助電容配緣3/23 係介以由樹脂材料所構成之層間絕緣膜9配置。樹 可藉由利用旋轉塗布法等之成膜方法容易地形成U [ 程度之較厚的膜。又’樹脂材料與一般之無機材料相較其 介質常數較小，因此可以介質常數小之材料形成層間絕緣 膜9。 是以，藉由在絕緣體層使用由樹脂材料所構成之絕緣膜 經濟部智慧財產局員工消費合作社印製 9，與只由無機材料形成絕緣體層之場合相較，可形成電 容値較小心絕緣體層。如此，可大幅降低信號線電容之電 容値。 又’藉由以旋轉塗佈法等之成膜方法將樹脂材料形成層 間絕緣膜’可將TFT 10或信號線6等形成之部份處所生的 表面階差平坦化，如此，在本主動矩陣基板上形成a_Se等 581912 五、發明說明（30 ) 之光電變換層而形成平板型畫像感測器之場合，藉由將主 動矩陣基板之表面平坦化，可防止a_Se之結晶化，從而防 止光電交換層性能之劣化。 又，絕緣體層ϋ：進一步含有保護1][71[ 1〇保護膜8。 藉由此一構成，絕緣體層，除了上述層間絕緣膜9之 外，也含有保濩TFT 10之保護膜8。作爲此一保護^^丁 1〇 I保護膜8，可以安定之無機材料等形成。藉此，可將 TFT 10確實地保護，避免订丁 1〇受損。 另，由於此保護膜8係作爲絕緣體層形成，因此，信號 線6與掃描線2或輔助電容配線3/23係成爲除了間絕緣膜4 或層間絕緣膜9等之外，又介以保護膜8之位置關係。是 以’可使k號線電容之電容値進一步降低。 又，層間絕緣膜9苴由具有感光性之樹脂材料形成。 藉由此一構成，藉由曝光、顯像等之製程，可將層間絕 緣膜9容易地圖案化。 再者，層間絕緣膜9宜由壓克力系樹脂構成。 壓克力系樹脂與聚醯亞胺等之其他樹脂材料相較，介質 常數係小至約3，可形成靜電電容値小的層間絕緣膜。是 以，可將信號線電容之電容値大幅降低。 特別是在畫素電極7重疊於信號線或掃描線2形成部份 上方之構造，藉由上述層間絕緣膜9可大幅降低畫素電極 7與信號線6或掃描線2之間所產生的靜電電容之電容値。 本實施形態之主動矩陣基板，具有接續於TFT 1〇之信號 6及掃描線2，係信號線6及掃描線2介以樹脂材料配置之 -33- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------略 (請先閱讀背面之注意事項再填寫本頁)-------- Order --------- Line I r &lt; Printed by the Employees' Cooperatives of the Ministry of Economics and Intellectual Property Bureau Printed by the Consumers ’Cooperatives of the Ministry of Economics and Intellectual Property Bureau Printed by 581912 A7 _ __________B7 V. Description of Invention (23) or the interlayer insulating film 9). According to the above configuration, the signal line 6 composed of the same layer as the pixel electrode 7 and the layer of the source electrode 11 and the structure and electrode 13 of the TFT 10 formed on the glass substrate 1 are interposed by an insulator layer. Configuration. Therefore, the scanning lines 2 arranged on the sloped glass substrate 1 are in a positional relationship with the signal lines 6 at least through the peripheral layer. The capacitance 値 of the signal line capacitor formed between this and the scanning line 2 can be reduced by the insulator layer. Therefore, an increase in the time constant of the signal line 6 or the scanning line 2 due to the capacitance of the signal line can be prevented, and the transmission speed of the signal transmitted by the signal line 6 or the scanning line 2 can be increased. Furthermore, noise due to the capacitance of the signal line can be reduced. On the other hand, since the source 11 and the drain 13 and the signal line 6 are, in other words, an insulator layer is provided between the TT 10 and the signal line 6, even if the thickness of the insulator layer is reduced, the signal line is reduced. The capacitor 値, the source 11 and the drain j 3 may still be closely connected to the switching element body (semiconductor region 1 4). Therefore, uneasy contact between the source 11 and the drain 13 and the semiconductor region 14 can be avoided. In addition, by this, the thickness of the insulator layer can be sufficiently increased, and the capacitance 信号 of the signal line can be further reduced. In this way, it is possible to provide an active matrix substrate for forming an image display device or an image photographing device that has high reliability and can display high-quality images in a display manner. In addition, the above active matrix substrate should preferably have an auxiliary capacitor 12 or 3 2 formed between the insulator layer and the glass substrate 1 and connected in series with the day electrode 7 (the standard is the auxiliary capacitor 12/3 2; ), And the auxiliary capacitor wiring 3/23 of one of the electrodes of the auxiliary capacitor 12/32. -26- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -I 丨 丨 丨 丨 丨 • 丨 丨 丨 丨 丨 丨 Order- 丨 ί 丨 — 丨 丨-. C Please first Read the precautions on the back and fill in this page again} A7 B7 V. Description of the invention (24 is composed of the above, the auxiliary capacitor wiring 3/23 is the same as the scanning line 2, and it has at least an insulator layer between the signal line 6 Positional relationship. Therefore, the capacitance of the signal line capacitance formed with the auxiliary capacitor wiring 3/23 can be reduced by the insulator layer. Therefore, it is caused by the scanning line 2 or the auxiliary% valley distribution. Spring 3/23 The capacitance of the number line can also be reduced, which can greatly reduce the capacitance 信号 of the signal line. The active matrix substrate of this embodiment has pixel electrodes 7 arranged in a matrix on the glass substrate i, and has a continuous connection with the pixel electrodes 7. Electrode 13. It has gate electrode 5 and source electrode plus 10, scan line 2 and closed electrode # 2, and signal line 6 connected to source n; scan line 2 and signal line 6 are parent and The glass substrates are arranged in a grid pattern and cover the insulator layers (protective film 8) of the scanning lines 2 and the TFT 10. The interlayer insulating film 9) is provided on the glass substrate 1, and the pixel electrode 7 is provided on the insulator layer provided in the insulating system, which is characterized by this. Xuanquan 6 With the above configuration, the scanning line 2 and the signal line 6 At least, an insulator layer is formed. Therefore, the scanning line 2 and the signal line 6 are opposite to each other, thereby the capacitance 値 of the formed signal edge capacitance can be reduced by the presence of the insulator layer. With the above-mentioned configuration, the scan line 2 and the TFT 10 and the signal line 61 have a structure having an insulator layer. The structure can be reduced under the structure in which the semiconductor region 14 and the electrode of the TFT 10 are in close contact with each other. The capacitance of the signal line capacitance formed between the scanning line 2 and the scanning line 2. In this way, it can provide an active matrix substrate with high reliability and can display or shoot high-quality images. In addition, since the pixel electrode 7 is provided on the insulator layer, it can The pixel electrode 7 is exposed and formed. Therefore, a liquid crystal display device is formed by using this active matrix substrate. -27- 581912 A7 ---------— H7_ _ V. Description of the Invention (25) (Please read the back first Please fill in this note ) When an image sensor is installed or placed, the liquid crystal layer or the photoelectric conversion layer can be formed close to the lisin electrode, respectively, so that the pen position or charge can be transferred smoothly between each layer and the pixel electrode 7 (quickly) In addition, since the source 11 and the drain 3 and the gate 5 of the TFT 10 have no special relationship with the insulation layer, even if the thickness of the insulator layer is changed, the function of the TFT 10 will not be affected. Influence. Therefore, the thickness of the insulator layer can be sufficiently increased to sufficiently reduce the capacitance of the signal line capacitance. In addition, the signal line 6 and the pixel electrode 7 in the above active matrix substrate should be composed of the same layer. According to the above The structure, because the same layer can be patterned to form the signal lines 6 and the two element electrodes 7, so by changing the patterned mask used when forming the conventional pixel electrode 7, the active matrix can be manufactured without increasing the manufacturing process. Substrate. Therefore, it is possible to suppress an increase in cost caused by a structural change. In addition, the above active matrix substrate has a sinker spring 13a / 33a extending from the electrode 13 and an auxiliary capacitor wiring 3 / formed from the same layer as the scanning line 2 and opposed to the sinker wiring 13a / 33a. 23; Preferably, the gate insulation film 4. It is interposed between the auxiliary capacitor wiring 3/23 and the drain wiring 13a / 33a. 0 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs according to the above structure, The gate insulating film 4 is sandwiched between the wiring 3/23 and the drain wiring 13a / 33a &lt; to form an auxiliary capacitor 12/32. Here, the auxiliary capacitor wiring 3/23 and the scanning line 2 are composed of the same layer (the auxiliary power valley wiring 3/23 may use a part of the scanning line 2 (those adjacent to the scanning line 2 b) 'and there is no wiring 13 a / 3 3 a is extended from the drain electrode 1 3, so the thickness of the insulating film 4 can be determined independently from the insulator layer. -28- This paper size 剌 Chinese National Standard (CNS) A4 specification (210 X 297 public love) 581912 Printed A7 by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (26) Therefore, the capacitance of the line ^ can be reduced to increase the auxiliary capacitance 値. By this, the potential of the pixel electrode 7 can be suppressed. Variations can be used to display stable daytime images or photography. In addition, by thinning the gate insulating film 4, the auxiliary capacitor can be increased. Therefore, the line width of the auxiliary capacitor wiring 3/23 can be increased, and the formation can be improved. The aperture ratio of the transmissive 7F device. That is, both the auxiliary capacitor 値 and the aperture ratio can be ensured at the same time. In this way, an active matrix substrate with high reliability and high image quality can be provided. The active matrix substrate in this embodiment , With a line 6 and a scan line that are connected to Ding Ding 10 2. The signal line 6 and the scanning line 2 are arranged with a resin material as their characteristic. With this structure, the capacitance 値 of the electrostatic capacitance generated between the signal line 6 and the scanning line 2 can be reduced, and the signal can be reduced. The capacitance of the line capacitor 値. Also, in an active matrix substrate provided with an auxiliary capacitor 12/32, a resin material should be interposed between the auxiliary capacitor wiring 3/23 forming the auxiliary capacitor 12/32 and the signal line 6. This can be used to The capacitance 信号 of the signal capacitance is further reduced. The manufacturing method of the active matrix substrate of this embodiment is characterized by: patterning the scanning line 2 and the auxiliary capacitor wiring 3/23 from the same film, and forming the source 11 and the drain 13 It is formed by patterning the same film, and the pixel electrode 7 and the signal line 6 are patterned by the same film. According to the above method, the scanning line 2 and the auxiliary capacitor wiring 3/23, the source electrode 1 1 and the drain electrode 1 3, And the signal line 6 and the pixel electrode 7 are formed by patterning the same film, respectively. Therefore, compared with the conventional method of manufacturing the active matrix substrate with the interlayer insulating film 9, the complexity of the procedure can be avoided. Active matrix -29- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------- ^ --------- (Please read the precautions on the back first Fill out this page again) 581912 Printed by A7 ______B7___, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (27) As mentioned above, the active matrix substrate of this embodiment forms the layer of scan line 2 (gate 5) (section 1 electrode layer), the layer forming the source electrode 11 (second electrode layer), and the layer forming the signal line 6 are formed on the glass substrate 1 at this timing, and the layer forming the source electrode 11 and forming the signal An insulator layer (a protective film 8 or an interlayer insulating film 9) is provided between the layers of the wire 6. The scanning line (j-th wiring) and the signal line (second wiring) 6 are arranged via an insulator layer. In addition, it is preferable that the gate 5 is formed in the layer forming the scanning line 2, and the electrode 13 is formed by the same layer as the layer forming the source 11, and the gate 5 and the source 11 are formed in the same layer. Between the electrodes 13 and 3 ', the semiconductor region 14 of the TFT 10 is formed in close contact with the source 11 and the electrode 1 3. With this configuration, unlike the conventional case where an insulator layer is formed between the gate, the source, and the drain, the source 11 and the drain 13 are in perfect contact with the semiconductor region 14, and a highly reliable TFT 10 can be formed. In addition, it is preferable that a first insulating film (gate insulating film 4 or oxide film 2 a) is formed between the semiconductor region 14 and a layer forming the scanning line 2 and the gate electrode 5, and the scanning line 2 and the signal line 6 are formed. It is further arranged via a first insulating film. According to this configuration, the presence of the first insulating film can further reduce the capacitance 电容 of the signal line capacitance generated between the 仏 -line 6 and the scanning line 2. It is also preferable that the auxiliary capacitor 12/32 series connected to the drain electrode 13 is formed between the above-mentioned insulator layer and the glass substrate 1 and the auxiliary capacitor wiring 3/23 series that forms one of the electrodes of the auxiliary capacitor 12/32 side is formed. The opposite signal line 6 is arranged via an insulator layer. According to this structure, the auxiliary capacitor 12/32 is arranged on the insulator layer and broken -30- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling in this (Page) ------- Order --------- Line appeal 581912 V. Description of the invention (28) 之间 Between the substrate 1, this auxiliary capacitor 12/32 is formed between the drain electrode 13 and the drain electrode 13 Auxiliary power distribution, spring 3/23, and the active matrix substrate configured with an insulator layer between the signal line 6 and the structure, the structure is to form a &lt; gate insulation film on the auxiliary capacitor wiring to configure the signal Line and auxiliary capacitor wiring. In contrast to this, the configuration of the present invention is such that the signal line 6 is disposed with respect to any of the scanning line 2 and the auxiliary capacitor wiring 3/23 via an insulator layer. Therefore, the effect of reducing the above-mentioned capacitance 发挥 can be exhibited by the 俨 -line capacitor caused by either of the scanning line 2 and the auxiliary capacitor wiring 3/23. In this way, the capacitance of the signal line capacitance can be greatly reduced. The storage capacitor wiring 3/23 is preferably formed of the same layer as the layer forming the scanning line 2. Thereby, during the patterning process when the scanning line 2 is formed, the auxiliary capacitor wiring 3/23 can be formed by changing its pattern. Also, it is preferable that a second insulating film (gate insulating film * or oxide film 3 a) is formed between the layer forming the drain electrode 3 and the layer forming the auxiliary capacitor wiring 3/23, and the auxiliary capacitor wiring 3 / 23 and the signal line 6 are further disposed via a second insulating film. According to this configuration, with the existence of the second insulating film, the capacitance 値 of the signal line capacitance generated between the signal line 6 and the auxiliary capacitor wiring 3/23 can be further reduced by 0. Preferably, it is connected to the drain electrode 13 The pixel electrode 7 is formed from the same layer as the layer forming the signal line 6. According to this structure, even in the above structure in which the signal line 6 and the source electrode i are formed from different layers, since the signal line 6 and the day electrode 7 are in the same layer (please read the precautions on the back before filling this page) ) -1 ------ Order --- I ----- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-31 V. Description of Invention (29 2 The formation of a large number of processes in the manufacturing process It can be avoided that the electrode 7 'can be patterned by using a sub-coating film for the sacrificial material, and the same f ^ is used to make the active matrix substrate. "The patterned mask used when If the pattern is changed, you can make: "Polar matrix substrate. If you take this initiative, you can increase the yield and reduce the cost with fewer processes. It is recommended that the insulating layer contain the moving matrix substrate. The interlayer insulation made of a resin material is thus configured, and the signal line 6 and the scanning line 2 or the auxiliary capacitor connection 3/23 are arranged through an interlayer insulation film 9 made of a resin material. The tree can be rotated by using Film formation methods such as coating methods easily form U [degree Thicker film. Also, the resin material has a smaller dielectric constant than ordinary inorganic materials, so the interlayer insulating film 9 can be formed from a material with a small dielectric constant. Therefore, by using a resin material for the insulator layer Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Insulation Film9 Compared with the case where the insulator layer is formed of only inorganic materials, the capacitor can form a smaller core insulator layer. In this way, the capacitance of the signal line capacitor can be greatly reduced. By forming a resin material to form an interlayer insulating film by a film-forming method such as a spin coating method, the surface step difference generated at a portion formed by the TFT 10 or the signal line 6 and the like can be flattened. Thus, on this active matrix substrate, Forming a_Se, etc. 581912 When the photoelectric conversion layer of the invention description (30) is used to form a flat-type image sensor, the surface of the active matrix substrate can be planarized to prevent the crystallization of a_Se and the performance of the photoelectric exchange layer. In addition, the insulator layer ϋ: further contains a protection 1] [71 [10 protection film 8. With this configuration, the insulator layer is in addition to the interlayers described above. In addition to the edge film 9, a protective film 8 for protecting the TFT 10 is also included. As this protective film 10, the protective film 8 can be formed of a stable inorganic material. By this, the TFT 10 can be reliably protected. Avoid damage to ding 10. In addition, since the protective film 8 is formed as an insulator layer, the signal line 6 and the scanning line 2 or the auxiliary capacitor wiring 3/23 become excluding the interlayer insulating film 4 or the interlayer insulating film 9 etc. In addition, the positional relationship of the protective film 8 is used. The capacitance 値 of the k-line capacitor can be further reduced by using the '. The interlayer insulating film 9 苴 is formed of a photosensitive resin material. With this structure, The interlayer insulating film 9 can be easily patterned by processes such as exposure, development, etc. Furthermore, the interlayer insulating film 9 should preferably be made of an acrylic resin. Compared with other resin materials such as polyimide, the acrylic resin has a dielectric constant as small as about 3, and can form an interlayer insulating film having a small electrostatic capacitance. Therefore, the capacitance of the signal line capacitance can be greatly reduced. In particular, the structure in which the pixel electrode 7 overlaps the signal line or the scanning line 2 formation portion, the static electricity generated between the pixel electrode 7 and the signal line 6 or the scanning line 2 can be greatly reduced by the interlayer insulating film 9 Capacitance of a capacitor. The active matrix substrate of this embodiment has a signal 6 and a scanning line 2 connected to the TFT 10, and the signal line 6 and the scanning line 2 are configured with a resin material. Specifications (210 X 297 mm) ----------- slightly (please read the precautions on the back before filling this page)

訂----------線I 經濟部智慧財產局員工消費合作社印製 581912Order ---------- Line I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 581912

五、發明說明（31) 構成。 根據此一構成，在主動矩陣基板上，信號線6與掃描線 2係介以樹脂材料例如交又狀等之配置。樹脂材料如上所 述因介質常數較低之故，可減小信號線6與掃描線2之間 所發生之靜電電容的電容値。如此，可降低信號線電容之 電容値。 [實施形態2 ] 以下，作爲第2實施形態，茲將應用實施形態i中所説 明之主動矩陣基板構造的又一主動矩陣基板' 佐以圖 12〜14説明之。又，有關與實施形態i説明之構成要件具 有同等機能之構成要件，僅加註同一符號，至於其説明則 在此省略。 圖12係本實施形態主動矩陣基板之平面圖，圖13及圖 14分別是沿圖12主動矩陣基板之H_h線及線之箭頭方 向斷面圖。 經濟部智慧財產局員工消費合作社印製 此一主動矩陣基板之基本構造，與實施形態丨中根據圖 9所説明之.主動矩陣基板構造大致相同，但在除了此構造 之外’又形成第二保護膜（信號線保護膜）8 a此點，與實 施形態1不同。又，圖12中，第2保護膜8a係以粗的二點 鏈線表示。 此弟2保遵膜8 a主要係没成將露出於層間絕緣膜9上層 之信號線6被覆。此處，第2保護膜8 a又設成除了畫素電 極7之外，又被覆全區域（第2保護膜8&amp;也被覆畫素電極7 之周邊部）。此一第2保護膜8 a係由具有絕緣性之材質所 -34- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 581912 A7V. Description of the Invention (31) Composition. According to this configuration, on the active matrix substrate, the signal lines 6 and the scanning lines 2 are arranged with a resin material such as a cross shape, or the like. The resin material can reduce the capacitance 値 of the electrostatic capacitance occurring between the signal line 6 and the scanning line 2 due to the low dielectric constant as described above. In this way, the capacitance 値 of the capacitance of the signal line can be reduced. [Embodiment 2] Hereinafter, as a second embodiment, another active matrix substrate having the active matrix substrate structure described in Embodiment i will be described with reference to Figs. 12 to 14. In addition, the constituent elements having the same functions as the constituent elements described in the embodiment i are given the same reference numerals, and the description thereof will be omitted here. Fig. 12 is a plan view of the active matrix substrate of this embodiment, and Figs. 13 and 14 are cross-sectional views taken along the line H_h and the arrow of the line of the active matrix substrate of Fig. 12, respectively. The basic structure of the active matrix substrate printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is the same as that described in the embodiment 丨 according to FIG. 9 The protective film (signal line protective film) 8 a differs from the first embodiment in this point. In Fig. 12, the second protective film 8a is indicated by a thick two-dot chain line. This brother 2 compliance film 8a is mainly covered by the signal line 6 that will be exposed on the upper layer of the interlayer insulating film 9. Here, the second protective film 8a is provided so as to cover the entire area in addition to the pixel electrode 7 (the second protective film 8 &amp; also covers the peripheral portion of the pixel electrode 7). This second protective film 8 a is made of insulating material. -34- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 581912 A7

五、發明說明（32 ) 形成。又，此處，作爲第2保護膜8 a係使用樹脂， 爲了形成此一第2保護膜8a。除了本實施形態1中所述 之製私外，加設以下製程即可。亦即，於上述製程中，係 在形成信號線6及畫素電極7之後，在主動矩陣基板上塗 布具有絕緣性及感光性之樹脂（感光性樹脂）。又，相對塗 布 &lt;樹脂，係藉由曝光、顯像而將樹脂圖案化成一定之形 狀又，有關树月曰之圖案形狀，如上所述，係被覆信號線 6，並使畫素電極7露出者。 於此，作爲第2保護膜8 a，宜藉由使用與層間絕緣膜9 相同之材料，形成1-3 〇m]厚度。 又，第2保護膜8 a不限上述者，也可爲被覆信號線6之 絕緣性保護膜。例如，第2保護膜8a可爲將信號線6本身 以陽極氧化等所獲得之氧化膜等。 如此，在信號線6上備有絕緣性第2保護膜8 a之本實施 形悲主動矩陣基板’除了實施形態1所説明之效果之外， 又具有以下之特徵。 具體言之，根據本主動矩陣基板，信號線6係由具有絕 緣性之第2保護膜8 a所被覆，因此，在形成於主動矩陣基 板上直接設置光電變換層（感測器材料）構造之平板型畫像 感測器之場合具有利點。具體而言，若使用本主動矩陣基 板，藉由第2保護膜8a，可防止信號線6與光電變換層電 氣接觸，故而，可防止吸收光或X射線之光電變換層中所 生之電荷重疊於信號線6。 再者’由於信號線6係由第2保護膜8 a所被覆，可避免 -35- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------ (請先閱讀背面之注意事項再填寫本頁) 1 I I I I I I . 線_· 經濟部智慧財產局員工消費合作社印製Fifth, the description of the invention (32) is formed. Here, a resin is used as the second protective film 8a, and this second protective film 8a is formed. In addition to the system described in the first embodiment, the following processes may be added. That is, in the above process, after the signal lines 6 and the pixel electrodes 7 are formed, a resin (photosensitive resin) having insulation and photosensitivity is coated on the active matrix substrate. The relative coating of the resin is to pattern the resin into a certain shape by exposure and development. As mentioned above, the pattern shape of the tree is covered with the signal line 6 and the pixel electrodes 7 are exposed. By. Here, as the second protective film 8 a, it is preferable to form a thickness of 1 to 3 m by using the same material as the interlayer insulating film 9. The second protective film 8a is not limited to the above, and may be an insulating protective film covering the signal line 6. For example, the second protective film 8a may be an oxide film or the like obtained by anodizing the signal line 6 itself. As described above, the second embodiment of the active matrix substrate having the insulating second protective film 8a provided on the signal line 6 has the following features in addition to the effects described in the first embodiment. Specifically, according to this active matrix substrate, the signal line 6 is covered with a second protective film 8 a having insulation properties. Therefore, a structure in which a photoelectric conversion layer (sensor material) is directly provided on the active matrix substrate is formed. The flat-type image sensor has advantages. Specifically, if the active matrix substrate is used, the second protective film 8a can prevent the signal line 6 from making electrical contact with the photoelectric conversion layer. Therefore, it is possible to prevent the charges generated in the photoelectric conversion layer from absorbing light or X-rays from overlapping.于 信号 线 6。 In the signal line 6. Furthermore, 'Because the signal line 6 is covered by the second protective film 8a, it can be avoided -35- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------- ---- (Please read the precautions on the back before filling out this page) 1 IIIIII. Line _ · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

581912 五、發明說明（33 ) L唬線6之露出，可防止信號線6之腐蝕。 又，根據本實施形態所説明《主動㈣基板，與實施形 態！所示之主動矩陣基板相同，可採利用鄰接掃描線^形 成輔助電容1 2之所謂C s閘上線構造（圖4、圖5 )。又，也 可廣泛地使用於主動矩陣型顯示裝置(例如液晶顯示裝置) 或平板型畫像感測器（例如平板型χ射線畫像感測器）等。 如上所述，本實施形態之主動矩陣基板中，較佳的是， 形成有被覆信號線6之信號線保護膜8 a。 根據此一構成，上述絕緣體層上所形成之信號線6係由 信號線保護膜8a所被覆。是以，藉由此信號線保護膜 8a，可避免信號線6之露出，故可防止信號線6之腐蝕。 又，在王動矩陣基板上直接設置光電變換層（感測器材 料）構造之平板型晝像感測器等，藉由信號線保護膜8a，. 可防止信號線6與光電變換層電氣接觸。因此，可防止因 光或X射線之吸收在光電變換層所產生之電荷，作爲雜訊 重疊於信號線6。 如此，可提供一種信號線6之信賴性高，且雜訊不易重 疊於信號線6之主動矩陣基板。 再者，在上述絕緣體層上形成信號線6所生之階差，可 由信號線保護膜8 a所掩埋。是以，可降低主動矩陣基板 之表面階差吣存在率。 如此’在本主動矩陣基板上形成a-Se等之光電變換層而 形成平板型畫像感測器之場合，可防止起因於表面階差之 a-Se的結晶化，而防止光電變換層之性能的劣化。 -36- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） ----------14 (請先閱讀背面之注意事項再填寫本頁)581912 V. Description of the invention (33) The exposure of the L6 line 6 can prevent the corrosion of the signal line 6. In addition, according to the description of this embodiment, "active substrates and implementation forms! The active matrix substrate shown is the same, and the so-called C s gate on-line structure can be formed by using adjacent scanning lines ^ to form the auxiliary capacitor 12 (Figure 4, Figure 5). It can also be widely used in active matrix display devices (for example, liquid crystal display devices) or flat-type image sensors (for example, flat-type x-ray image sensors). As described above, in the active matrix substrate of this embodiment, it is preferable that the signal line protective film 8 a covering the signal lines 6 is formed. According to this configuration, the signal line 6 formed on the insulator layer is covered with the signal line protective film 8a. Therefore, by the signal line protective film 8a, the exposure of the signal line 6 can be avoided, and the corrosion of the signal line 6 can be prevented. In addition, a flat-type day image sensor with a photoelectric conversion layer (sensor material) structure is directly provided on the Wangdong matrix substrate. The signal line protective film 8a can prevent the electrical contact between the signal line 6 and the photoelectric conversion layer. . Therefore, it is possible to prevent the electric charges generated in the photoelectric conversion layer due to absorption of light or X-rays from overlapping on the signal line 6 as noise. Thus, it is possible to provide an active matrix substrate with high reliability of the signal line 6 and noise that is not easily overlapped on the signal line 6. Furthermore, the step difference caused by forming the signal line 6 on the insulator layer can be buried by the signal line protective film 8a. Therefore, the surface step difference existence rate of the active matrix substrate can be reduced. In this way, when a flat-type image sensor is formed by forming a photoelectric conversion layer such as a-Se on the active matrix substrate, it is possible to prevent crystallization of a-Se due to a surface step, and prevent the performance of the photoelectric conversion layer Degradation. -36- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 χ 297 mm) ---------- 14 (Please read the precautions on the back before filling this page)

訂---------線I 經濟部智慧財產局員工消費合作社印製 581912 A7 -^______ B7 五、發明說明（34) [實施形態3 ] 其次，作爲第3實施形態，茲將與實施形態i所説明之 主動矩陣基板的構造不同之主動矩陣基板，以圖15〜圖 17説明之。又，有關與實施形態所説明之構成要件 具有同等機能之構成要件，僅加註相同之符號，至於其說 明則在此省略。 圖15係本實施形態主動矩陣基板之平面圖，圖16及圖 1 7分別係上述主動矩陣基板沿圖1 5中J - J線及K - K線箭頭 方向之斷面圖。 此一主動矩陣基板，相對實施形態1之依圖9所説明的 主動矩陣基板，信號線2 6之配置場所不同。 亦即，實施形態1之主動矩陣基板（參見圖9〜圖i 1 )，信 號線6係配置於層間絕緣膜9之上面，而本實施形態之主 動矩陣基板，信號線2 6則是配置於保護膜8與層間絕緣膜 9之間。故而，信號線2 6係藉由形成保護膜8之接觸孔 2 6 a接續源配線1 1 a。 又，本主動矩陣基板，係將實施例1所説明之主動矩陣 基板的製造過程之順序，係部份變更而製成。 根據本主動矩陣之製造過程，保護膜8之形成、以及相 對保護膜8之接觸孔26a (相當於實施例1之接觸孔6 a )、接 觸孔7 a之形成爲止的過程，係與實施形態i主動矩陣基板 之製造過程相同。 其次’在保護膜8上形成層間絕緣膜9之前，形成信號 線2 6。此一信號線2 6係與實施1相同，可藉由將I τ 〇膜、 -37- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 4 再填寫太Order --------- Line I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy 581912 A7-^ ______ B7 V. Description of the Invention (34) [Embodiment 3] Second, as the third embodiment, An active matrix substrate having a structure different from that of the active matrix substrate described in Embodiment i will be described with reference to FIGS. 15 to 17. In addition, constituent elements having the same functions as the constituent elements described in the embodiment are given the same reference numerals, and descriptions thereof are omitted here. FIG. 15 is a plan view of the active matrix substrate of this embodiment, and FIG. 16 and FIG. 17 are cross-sectional views of the above-mentioned active matrix substrate along the directions of arrows J-J and K-K in FIG. 15, respectively. This active matrix substrate is different from the active matrix substrate of Embodiment 1 described with reference to FIG. 9 in that the signal wires 26 are arranged in different places. That is, in the active matrix substrate of the first embodiment (see FIG. 9 to FIG. I 1), the signal line 6 is disposed on the interlayer insulating film 9, and the active matrix substrate of the present embodiment, the signal line 26 is disposed on the Between the protective film 8 and the interlayer insulating film 9. Therefore, the signal line 26 is connected to the source wiring 1 1 a through the contact hole 2 6 a forming the protective film 8. In addition, the active matrix substrate is manufactured by partially changing the order of the manufacturing process of the active matrix substrate described in the first embodiment. According to the manufacturing process of this active matrix, the formation of the protective film 8 and the formation of the contact hole 26a (corresponding to the contact hole 6a of Example 1) and the contact hole 7a with respect to the protective film 8 are related to the implementation form. The manufacturing process of i active matrix substrate is the same. Next, before the interlayer insulating film 9 is formed on the protective film 8, signal lines 26 are formed. This signal line 2 6 is the same as the implementation 1. It is possible to apply I τ 〇 film, -37- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the note on the back first Please fill in this page again) 4 Please fill in too

--------訂---------線I 經濟部智慧財產局員工消費合作社印製-------- Order --------- Line I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

經濟部智慧財產局員工消費合作社印製 581912 五、發明說明（35) 妲膜、鋁膜等以濺鍍法堆積，再將其圖案化成一定形狀而 形成。 而後，藉由在形成有保護膜8及信號線2 6之主動矩陣基 板上依同於實施形態1之方式形成層間絕緣膜9、畫素電 極7等，而完成主動矩陣基板。又，當然的是，此時也可 不相對層間絕緣膜9形成供信號線26用之接觸孔6a (參見 圖 10)。 &quot; 上述構成之本實施形態主動矩陣基板，與實施形態1及 二所說明之主動矩陣基板相同，可使得靜電電容值降低之 效果。以下茲說明與習用主動矩陣基板相較，信號線電容 值降低之事實。此處，茲就占信號線電容值大部份之信號 線2 6與掃描線2及輔助電容線2 3間所形成的靜電電容值作 考慮。 典型的例子是，氧化膜2a 3&amp;之厚度為〇.15[#111]，介 質常數為24 ;閘絕緣膜4為厚〇·35 Um]，介質常數為 6.9 ;保護膜8為厚〇·5 [#m]，介質常數為6 9。習用之主 動矩陣基板（圖6〜圖8 )及本實施形態之主動矩陣基板，此 等值係設成相同。 習用之主動矩陣基板，信號線5 6與掃描線5 2或輔助容 量配線53之間，只有閘絕緣膜54及氧化膜52a 53a存在 (圖6〜圖8 )，.而本實施形態中，信號線2 6與掃描線2或輔 助電容線2 3之間，則是有閘絕緣膜4、氧化膜2 a 3 a、 保護膜8存在。 與信號線2 6之重疊部份就1 [ # m2]之靜電電容值的計算 -38- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) I « ϋ n l i l I n 一· n 1 n ϋ 1 · 線i 581912Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 581912 V. Description of the Invention (35) The ytterbium film, aluminum film, etc. are deposited by sputtering, and then patterned into a certain shape. Then, the active matrix substrate is formed by forming an interlayer insulating film 9, a pixel electrode 7, and the like on the active matrix substrate on which the protective film 8 and the signal lines 26 are formed in the same manner as in the first embodiment. Also, of course, the contact hole 6a for the signal line 26 may not be formed with the interlayer insulating film 9 at this time (see FIG. 10). &quot; The active matrix substrate of the present embodiment configured as described above is the same as the active matrix substrate described in the first and second embodiments, and can reduce the capacitance value. In the following, the fact that the capacitance of the signal line is lower than that of the conventional active matrix substrate is explained. Here, consider the electrostatic capacitance value formed between the signal line 26, which is a large part of the capacitance value of the signal line, and the scanning line 2 and the auxiliary capacitance line 23. A typical example is that the thickness of the oxide film 2a 3 &amp; is 0.15 [# 111], the dielectric constant is 24; the gate insulating film 4 is thick 0.35 Um], the dielectric constant is 6.9, and the protective film 8 is thick 0.1 5 [#m], the dielectric constant is 6 9. The conventional active matrix substrate (Fig. 6 to Fig. 8) and the active matrix substrate of this embodiment are set to the same value. In the conventional active matrix substrate, only the gate insulating film 54 and the oxide film 52a to 53a exist between the signal line 56 and the scanning line 52 or the auxiliary capacity wiring 53 (FIG. 6 to FIG. 8). In this embodiment, the signal Between the line 26 and the scanning line 2 or the auxiliary capacitor line 23, a gate insulating film 4, an oxide film 2a3a, and a protective film 8 exist. Calculate the capacitance value of 1 [# m2] with the overlap of signal line 2 6 -38- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back first Please fill in this page again) I «ϋ nlil I n a · n 1 n ϋ 1 · line i 581912

發明說明（36 ) 〇果=丁白用的主動矩陣基板爲0·16 [fF//z m2]，而本實 施形悲（王動矩P車基板則是Q⑽师〆]。本實施形態 中，藉由將信號線26配置於保護膜8之上，可將信號線26 與掃描線2或輔助電容線23間之間隙d設成約i [請]，與 白用（场合相較’是爲增大。藉此，I生於信號線2 6之 靜包電谷値係習用之場合相較成爲約1/2 4，獲得降低。 此一靜電電容値之降低率，與實施形態i之主動矩陣基 板（降低率約1/2〇相較爲小。然而，肖習用主動矩陣基板 之場合相較，因信號線電容之電容値爲小之故，信號線 26所發生之雜訊的降低效果大。 上述主動矩陣基板，除了上述靜電電容値之降低效果之 外，尚有主動矩陣基板表面之階差（凹凸）（表面階差）的存 在率少，或是階差値小此一構造上的優點，就此，以下茲 作具體説明。 實施形態1所説明之主動矩陣基板（例如參見圖1〇及圖 1 1)的場合，係在層間絕緣膜9上露出信號線6及圖素電極 7之構造。 此處，層間絕緣膜9係如上所述藉由塗布感光性樹脂而 形成，因此，較之層間絕緣膜9，存在於下層之階差係由 層間絕緣膜9所平坦化或緩衝。是以，作爲主動矩陣基板 之表面階差，存在有相當於信號線6及畫素電極7之膜厚 的階差（膜厚階差）及接觸孔6 a · 7 a的階差。 k 5虎線6、畫素電極7及接觸孔6 a · 7 a，係設於各書 素，因此，實施形態1之主動矩陣基板中，各畫素中形成 -39· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — —---I · I------^---II--- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 581912 A7Description of the invention (36) 〇 Fruit = Ding Bai's active matrix substrate is 0 · 16 [fF // z m2], but this embodiment is sad (Wang Dong moment P car substrate is Q⑽ 师 ⑽). In this embodiment By arranging the signal line 26 on the protective film 8, the gap d between the signal line 26 and the scanning line 2 or the auxiliary capacitor line 23 can be set to about i [please], compared with white (the situation is In order to increase it, compared with the conventional case where the static-packed electric valley is born on the signal line 26, it is reduced to about 1/24, and the reduction rate of this electrostatic capacitance is the same as that of the embodiment i. Active matrix substrate (the reduction rate is about 1/20 phase is relatively small. However, compared with the case where Xiao Xi used an active matrix substrate, the noise of the signal line capacitor is small, so the noise generated by the signal line 26 is reduced. The active matrix substrate has a structure in which the existence of the step difference (concave and convexity) (surface step difference) on the surface of the active matrix substrate is small, or the step difference is small. In this respect, the following describes the advantages in detail. The active matrix substrate described in Embodiment 1 ( As shown in Fig. 10 and Fig. 1), the structure in which the signal line 6 and the pixel electrode 7 are exposed on the interlayer insulating film 9. Here, the interlayer insulating film 9 is coated with a photosensitive resin as described above. Is formed, therefore, compared with the interlayer insulating film 9, the step difference existing in the lower layer is flattened or buffered by the interlayer insulating film 9. Therefore, as the surface step difference of the active matrix substrate, there are equivalent to the signal line 6 and the drawing The film thickness step of the element electrode 7 (film thickness step) and the step of the contact hole 6 a · 7 a. K 5 tiger wire 6, the pixel electrode 7 and the contact hole 6 a · 7 a are provided in each Therefore, in the active matrix substrate of Embodiment 1, -39 · is formed in each pixel. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). — — — — — — ——— -I · I ------ ^ --- II --- (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 581912 A7

五、發明說明（37) 有與渠等對應之階差。是以，實施形態1之主動矩陣基板 中，表面階差之存在率，亦即每單位面積存在之階差的數 目較大。 另一方面’實施形態2所說明之主動矩陣基板（參見圖 1 3及1 4 )的場合，信號線6與接觸孔6 a係由第2保護膜8 a 所被覆之構造。是以，作為主動矩陣基板之表面階差，主 要只存在第2保護膜8a之膜厚階差及接觸孔7a之階差。故 而，與實施例1之主動矩陣基板相較，表面階差之存在率 降低。 然而，第2保護膜8 a係藉由如上所述般之例如塗布感光 性樹脂而形成，因此，第2保護膜8a之膜厚階差，有成為 大至千分尺之值的場合。 相對於此，本實施形態之主動矩陣基板（參見圖1 6及圖 1 7 )，信號線2 6係埋設於層間絕緣膜9之下，而層間絕緣 膜9上則只露出晝素電極7。是，作為本主動矩陣基板之 表面階差，主要只存在晝素電極7之膜厚階差及接觸孔7 a &lt;階差。因此，本實施形態之主動矩陣基板，與實施形態 1 &lt;主動矩陣基板相較，表面階差之存在率減小。 又’晝素電極7係由IT 0或金屬薄膜（例如厚〇 1〜〇 3 #m) 所形成。是以，晝素電極7之膜厚階差，遠較上述第2保 護膜8 a之膜厚階差為小。因此，根據本實施形態之主動 矩陣基板，與實施形態2之主動矩陣基板相較，可減小表 面階差之值。 ^ ’在將主動矩陣基板用於平板型晝像感測器，特別是 -40- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)5. Description of the invention (37) There is a step difference corresponding to the canal and the like. Therefore, in the active matrix substrate of the first embodiment, the existence rate of the surface step, that is, the number of step differences per unit area is large. On the other hand, in the case of the active matrix substrate described in the second embodiment (see FIGS. 13 and 14), the signal line 6 and the contact hole 6a are covered with a second protective film 8a. Therefore, as the step of the surface of the active matrix substrate, only the step of the thickness of the second protective film 8a and the step of the contact hole 7a mainly exist. Therefore, compared with the active matrix substrate of Example 1, the existence rate of the surface step difference is reduced. However, since the second protective film 8a is formed by, for example, coating a photosensitive resin as described above, the step thickness of the second protective film 8a may be as large as a micrometer. In contrast, in the active matrix substrate of this embodiment (see FIG. 16 and FIG. 17), the signal line 26 is buried under the interlayer insulating film 9, and only the day electrode 7 is exposed on the interlayer insulating film 9. However, as the surface step of the active matrix substrate, only the film thickness step of the day element electrode 7 and the contact hole 7 a &lt; step difference mainly exist. Therefore, compared with the active matrix substrate of Embodiment 1 &lt; active matrix substrate of this embodiment, the existence rate of the surface step difference is reduced. The day electrode 7 is formed of IT 0 or a metal thin film (for example, a thickness of 0 1 to 0 3 #m). Therefore, the step thickness of the day electrode 7 is much smaller than the step thickness of the second protective film 8a. Therefore, compared with the active matrix substrate of the second embodiment, the active matrix substrate according to this embodiment can reduce the value of the surface level difference. ^ 'In the use of active matrix substrates for flat day image sensors, especially -40- This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (Fill in this page)

-· I I I 訂·--------線 經濟部智慧財產局員工消費合作社印製 581912 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（38 ) 作爲光電變換層使用A表性a_Se之平极型畫像感測器之場 合，業界所I求的是將主動㈣基板之表面階差儘量減小 及減少（減少表面階差之存在率）（參見如後所述之圖 20)。 其理由是’在主動料基板上將a_Seii接歧之場合等 時，若主動矩睁基板上存有表面階差，則其表面階差部會 f爲特異點’而有成爲a_Se結晶化之引發點的可能性。如 是，當a-Se之結晶化進行，則光電變換層之時電流增加， 造成作爲光電變換層的特性顯著地惡化。 是以，如上所述之表面階差小，且表面階差存在率小的 本實施形態主動夕巨陣基板，係、纟適用於平板型畫像顯示器 之構化。又，藉由將本實施形態之主動矩陣基板使用於平 板型晝像感測器，可抑制由來自心等之光電變換層的結 晶化，防止光電變換層特性之惡化。 又，本實施形態所説明之主動矩陣基板，與實施形態1 ^示之主動矩陣基板相同，可採用將輔助電容Μ以鄰接 掃描線2b形成之所謂的Cs閘上線構造（參見圖斗及圖5)。 又，還可廣泛地應用於主動矩陣型顯示裝置（例如液晶顯 示裝置）或平板型畫像感測器（例如平板型X射線畫像咸測 器）等等。 一〜 又，根據本實施形態之主動矩陣基板，由於信號線26 與畫素電極7之間介在有層間絕緣膜9，也可爲在形成有 信號線2 6之部份的上方重疊有畫素電極7之構造。藉此， 可增大畫素電極7之面積提高開口率。 __ -41 - Λ張尺度適用中國國家^^i)A4規格⑽χ挪公爱）--- --------^---------^ (請先閱讀背面之注意事項再填寫本頁) 581912 A7 -____B7__ 五、發明說明（39 ) 如上所述，本實施形態之主動矩陣基板，較佳的是，其 上述絕緣體層係由保護TFT 10之保護膜8所構成，且形成 有被覆信號線2 6及保護膜8之層間絕緣膜9。 藉由此一構成，則成爲介以作爲絕緣體層之保護膜8， 配置有信號線2 6及掃描線2或輔助電容配線2 3之情形。 此一場合也是，保護膜8與TFT 10獨立，具有保護TFT 1〇之機能，可在無損TFT 10之機能下增厚保護膜8。又， 藉由增厚保護膜8，可降低信號線電容之電容値。 又，藉由上述構成，作爲絕緣體層之保護膜8及形成於 保護膜8上之信號線2 6，係由層間絕緣膜9所被覆。因 此，藉由此層間絕緣膜9，可將保護膜8與形成於保護膜8 上之&quot;^號線2 6的階差或起因於T F T之階差掩埋平坦化。 如此，在本主動矩陣基板上設置a_Se等之光電變換層形成 平私型畫像感測器之場合’可防止起因於信號線2 6或TFT 10之表面階差的a-Se等之結晶化，防止光電變換層性能之 劣化。 又，較隹的是，在層間絕緣膜9上，形成有與汲極i 3接 續之畫素電極7的構成。 藉由上述構成，信號線2 6與畫素電極7係成爲介以層間 絕緣膜9配置之情形。是以，可作成在形成有信號線2 6之 部份的上方，被覆有畫素電極7之構造，可増大畫素電極 7之面積提高開口率。 又’藉由層間絕緣膜9，可降低在信號線2 6與畫素電極 7之間所產生的靜電電谷之電容値，可使信號線電容之電 •42- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 581912 A7 B7 五、發明說明（4〇 容値進一步降低。 另’層間絕緣膜9宜由樹脂材料摄土 韓塗料W日^構成。樹脂材料可以旋 γ布法寺的成膜方法，容易地形成卜5㈣程度之較厚 二:ΓΠ有TFT1°或信號線26等之部份的表面 阳差千坦化。如此，在本主動矩陣基 電，而形成平板型畫像感測器之場合，可防止a-se= 結晶化而防止光電變換層性能之劣化。 較：之:脂：料、：言與無機材料等相較，介質常數 - w精由介貝$數小的材料形成層間絕緣膜9。 =而’在形成有信號線26之部份的上方，被覆有畫素 二極7:構造的場合等’可藉由該介質常數小之層間絕緣 艇9，大幅降低信號線26與畫素電極7之間所發生的靜啦 電容之電容値。 ％ [實施形態4 ] 其次，作爲第4實施形態，兹將實施形^所説明之主 動矩陣基板的平板型畫像感測器，佐以_説明如下。 又，與實施形態…説明之構成要件具有同等機能之構成 要件1附加相同符別，至於其説明則在此省略。 、作t本實施形態平板型晝像感測器的平板型X射線畫像 感測器，如圖1 8所示，係由實施形態1中圖9〜圖1 i所説 明的王動矩陣基板1 0 0與感測器基板1 1 2，介以導電接續 材108組合形成。又，此平板型χ射線畫像感測器中之^ 動矩陣基板100，係如實施形態1之圖9〜圖η中户斤示者相 ------------«敦 Γ請先閱讀背面之&gt;i意事項再填寫本頁) -1!^ ·!1_11· 線·. 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製-· Order III Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 581912 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the invention (38) Use A table as the photoelectric conversion layer In the case of a flat-type image sensor of a_Se, what the industry is looking for is to minimize and reduce the surface step difference of the active substrate (to reduce the existence rate of the surface step difference) (see Figure 20 as described later). ). The reason is that 'in the case where a_Seii is mixed on the active material substrate, if there is a surface step difference on the active moment substrate, the surface step portion f will be a singular point', which may cause a_Se crystallization. Point of possibility. If so, when the crystallization of a-Se proceeds, the current at the time of the photoelectric conversion layer increases, causing the characteristics as a photoelectric conversion layer to deteriorate significantly. Therefore, as described above, the surface step difference is small, and the existence rate of the surface step difference is small. This embodiment is an active matrix substrate, which is suitable for the construction of a flat-type image display. In addition, by using the active matrix substrate of this embodiment in a flat-type day image sensor, it is possible to suppress crystallization of the photoelectric conversion layer from the heart and the like, and prevent deterioration of the characteristics of the photoelectric conversion layer. In addition, the active matrix substrate described in this embodiment is the same as the active matrix substrate shown in the first embodiment, and a so-called Cs gate on-line structure in which the auxiliary capacitor M is formed adjacent to the scanning line 2b (see FIG. 5 and FIG. 5) ). It can also be widely used in active matrix display devices (such as liquid crystal display devices) or flat-panel image sensors (such as flat-panel X-ray image sensors) and the like. According to the active matrix substrate of this embodiment, since the interlayer insulating film 9 is interposed between the signal line 26 and the pixel electrode 7, the pixel may be overlapped on the portion where the signal line 26 is formed. Structure of the electrode 7. Thereby, the area of the pixel electrode 7 can be increased to improve the aperture ratio. __ -41-Λ Zhang scale is applicable to Chinese country ^^ i) A4 size ⑽χ Norwegiano love) ----------- ^ --------- ^ (Please read the note on the back first Please fill in this page again) 581912 A7 -____ B7__ V. Description of the Invention (39) As mentioned above, the active matrix substrate of this embodiment, preferably, the above-mentioned insulator layer is composed of the protective film 8 for protecting the TFT 10, An interlayer insulating film 9 covering the signal lines 26 and the protective film 8 is formed. With this configuration, the signal line 26 and the scanning line 2 or the auxiliary capacitor line 23 are arranged in the protective film 8 as the insulator layer. Also in this case, the protective film 8 is independent of the TFT 10 and has the function of protecting the TFT 10. The protective film 8 can be thickened without damaging the function of the TFT 10. In addition, by thickening the protective film 8, the capacitance 信号 of the capacitance of the signal line can be reduced. With the above configuration, the protective film 8 as an insulator layer and the signal lines 26 formed on the protective film 8 are covered with the interlayer insulating film 9. Therefore, with this interlayer insulating film 9, the step difference between the protective film 8 and the &quot; ^ line 26 formed on the protective film 8 or the step difference due to T F T can be buried and planarized. In this way, in the case where a photoelectric conversion layer such as a_Se is provided on the active matrix substrate to form a private image sensor, 'a-Se and the like which are caused by the surface step difference of the signal line 26 or the TFT 10 can be prevented, Prevents deterioration of the performance of the photoelectric conversion layer. In addition, it is rather complicated that a pixel electrode 7 is formed on the interlayer insulating film 9 in succession to the drain electrode i 3. With the above-mentioned configuration, the signal lines 26 and the pixel electrodes 7 are arranged through the interlayer insulating film 9. Therefore, a structure in which the pixel electrode 7 is covered above the portion where the signal line 26 is formed can be made, and the area of the pixel electrode 7 can be enlarged to increase the aperture ratio. Also, with the interlayer insulating film 9, the capacitance of the static electricity valley generated between the signal line 26 and the pixel electrode 7 can be reduced, and the electricity of the signal line capacitance can be reduced. 42- This paper size applies to Chinese national standards (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back before filling this page) Installed by the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumer Cooperatives of the Ministry of Economic Affairs. In addition, the interlayer insulating film 9 should be made of a resin material, such as Korean paint W. It is possible to form a thicker film by rotating the Buffalo ’s film forming method. The thickness is 5 °: ΓΠ has TFT1 ° or a signal line. The surface difference of parts such as 26 and so on is ten thousand. In this way, in the case where the active matrix matrix is used to form a flat-type image sensor, a-se = can be prevented from crystallizing and the performance of the photoelectric conversion layer can be prevented from being deteriorated. Compared with: Fat: Material, In comparison with inorganic materials, the dielectric constant-w is formed from a material with a small dielectric constant to form an interlayer insulating film 9. = 'Above the portion where the signal line 26 is formed, Covered with pixel dipole 7: Structure occasion, etc. ' With the interlayer insulation boat 9 having a small dielectric constant, the capacitance 静 of the static capacitance occurring between the signal line 26 and the pixel electrode 7 is greatly reduced. [Embodiment 4] Next, as a fourth embodiment, the following will be described. The flat-type image sensor of the active matrix substrate described in the embodiment ^ is described below with _. In addition, the components 1 having the same functions as the components described in the embodiment ... have the same designations. As for the description, This is omitted. As shown in FIG. 18, the flat-type X-ray image sensor of the flat-type day image sensor of this embodiment is described by the king of the movement in FIG. 9 to FIG. 1 i in Embodiment 1. The matrix substrate 1 0 0 and the sensor substrate 1 12 are formed by combining conductive conductive materials 108. In addition, the matrix substrate 100 in the flat-type x-ray image sensor is as shown in FIG. 9 of Embodiment 1. ~ In the picture of the households in the picture ------------ «Dun, please read the" I "on the back before filling in this page) -1! ^ ·! 1_11 · Line ·. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

581912 經濟部智慧財產局員工消費合作社印製 A7 B7____ 五、發明說明（41 ) 同，其説明在此省略。又，圖1 8係上述平板型X射線畫像 感測器中，與圖9之G - G線相當的部份之箭頭方向斷面 圖。 首先’茲就感測器基板1 1 2説明之。感測器基板i i 2具 有玻璃基板106，此一玻璃基板1〇6之主動矩陣基板ι〇〇 側的面（與X射線入射之面相對向的面）上，依序配置有感 測器偏壓電極1 0 4、光電變換層（感測器膜、感測器層、 感測器材料）1 0 2及電荷收集電極1 1 〇。 上述光電變換層1 0 2，係藉由X射線之入射發生正負之 電荷，此處係由CdTe所形成。 又’感測器偏壓電極1 〇 4及電荷收集電極1 1 〇，係由 ITO膜或金屬膜所形成，介以光電變換層1〇2對向。又， 感測器偏壓電極1 0 4及電荷收集電極丨][〇之間，係可施加 高電壓。 此處，若將X射線入射至光電變換層1 〇 2，因應入射之 X射線的強度’如上所述，正負之電荷係在光電變換層 102内產生。此時，若在感測器偏壓電極1〇4與電荷收集 電極1 1 0之間施加南電壓，則因產生之電場之故，正負之 各電荷會移動至感測器偏壓電極i 0 4或電荷收集電植 1 1 0 0 例如，圖1 8所示的是，相對感測器偏壓電極i 〇4，施加 有高電壓使電荷收集電極1 1 〇爲正之狀態，此時，正電荷 係移動至感測器偏壓電極1 〇 4側，負電荷係移動至電荷收 集電極1 1 0侧。 (請先閱讀背面之注意事項再填寫本頁)581912 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7____ V. Description of Invention (41) Same, the description is omitted here. Fig. 18 is a cross-sectional view in the direction of an arrow in a portion corresponding to the line G-G in Fig. 9 in the flat-panel X-ray image sensor. First, the sensor substrate 1 12 will be described. The sensor substrate ii 2 has a glass substrate 106, and the glass substrate 106 has an active matrix substrate ιOO side surface (a surface opposite to the X-ray incident surface) on which a sensor bias is sequentially arranged. Pressing electrode 104, photoelectric conversion layer (sensor film, sensor layer, sensor material) 102 and charge collecting electrode 1104. The above-mentioned photoelectric conversion layer 102 is a positive and negative charge generated by the incidence of X-rays, and here is formed of CdTe. The sensor bias electrode 104 and the charge collection electrode 1 10 are formed of an ITO film or a metal film, and are opposed to each other through a photoelectric conversion layer 102. In addition, a high voltage can be applied between the sensor bias electrode 104 and the charge collection electrode 丨] [〇. Here, when X-rays are incident on the photoelectric conversion layer 102, the positive and negative charges are generated in the photoelectric conversion layer 102 in accordance with the intensity of the incident X-rays' as described above. At this time, if a south voltage is applied between the sensor bias electrode 104 and the charge collection electrode 110, the positive and negative charges will move to the sensor bias electrode i0 due to the generated electric field. 4 or charge collection electrode 1 1 0 0 For example, as shown in FIG. 18, a high voltage is applied to the sensor bias electrode i 〇4 to make the charge collection electrode 1 1 〇 to be positive. The charge is moved to the sensor bias electrode 104 side, and the negative charge is moved to the charge collection electrode 110 side. (Please read the notes on the back before filling this page)

-44- 581912 經濟部智慧財產局員工消費合作社印製 A7 _____B7 五、發明說明（42 ) 如此，藉由將移動至電荷收集電極i i 〇側，且收集於電 荷收集電極1 1 0心電荷，利用主動矩陣基板i 〇 0作爲畫像 信號就各圖案讀出，可獲得入射至本平板型χ射線畫像感 測器之X射線的二次元畫像。 又，如上所述，爲了將收集於電荷收集電極110之電荷 就各畫素讀出’電荷收集電極1 i 0係就各晝素獨立地形 成。藉此’可避免鄰接之畫素間信號的串聯。另一方面， 有關感測器偏壓電極104及光電變換層1〇2，可在玻璃基 板106之大致全面上形成。 其次，茲就上述感測器基板i丨2與主動矩陣基板i 〇 〇之 接續，説明如下。如上所述，主動矩陣基板i 〇 〇，係將在 感測器板1 1 2中作爲收集電荷收集電極i i 〇之畫像信號的 電荷，介以設於各畫素之TFT 10 (參見圖㈧讀出。是以， 將感測器基板112之電荷收集電極u〇與主動矩陣基板 100之畫素電極7接續之導電接續材1〇8，係就各畫素設 置。 作爲此一導電接續材1 〇 8，可使用賦與導電性之感光性 樹脂、可作圖案印刷之焊料或導電接著劑等等。藉由使用 此等材料，可就各畫素電極7分別形成經圖素化之導電接 續材1 0 8。 此處，發明人等曾製作具有上述製造，且約28〇〇χ28〇〇 畫素，晝素間距爲〇· 15 mm之平板型X射線圖像感測器。 就X射線之晝像取得測試之結果確認，藉由上、述主動矩陣 基板1 0 0之仏號線電容的降低效果，可獲得$ / n非常優異 (請先閱讀背面之注意事項再填寫本頁) --------訂---------線k -45- 經濟部智慧財產局員工消費合作社印製 581912 Α7 -— ___Β7 五、發明說明（43 ) 之畫像信號，確認其可作動畫攝影。 又，具有上述構造之平板型X射線圖像感測器，可在主 動矩陣基板100與感測器基板112分別形成後，再接續該 主動矩陣基板1 〇 〇及感測器基板丨丨2進行製作。因此，感 測器基板112之形成中的光電變換層1〇2的成膜溫度，並 不受主動矩陣基板1 〇 〇耐熱溫度之限制。是以，作爲光電 變換層102，除了上述CdTe以外，例如可選擇CdZnTe等 之各種材料。 又，根據上述構造之平板型X射線畫像感測器，光電變 換層102並未直接形成於主動矩陣基板1〇〇上。因此，即 使是使用表面階差之存在率較大的主動矩陣基板丨〇 〇之場 合，也仍可防止起因於主動矩陣基板1〇〇之表面階差的光 電變換層1 0 2的成膜不良等，可抑制光電變換層1 〇 2特性 之劣化。 另，以上係就光電變換層丨〇 2受到χ射線的照射而發生 電荷之X射線畫像感測器作説明，但不限於此，也可藉由 變更光電變換層102之形成材料，而構成能獲得其他波長 區域的電磁波畫像之畫像感測器。 如上所述，較佳的是，本發明之平板型畫像感測器，光 電變換層102及畫素電極7，係介以與該晝素電極7對應而 經圖案化之導電接續材1 〇 8作電氣接續。 此一構成之平板型畫像感測器，可在分別形成主動矩陣 基板100及具有光電變換層102之基板後，將各基板介以 導電接續材108作電氣接續而製成。因此，可避免光電變 --------^---------線秦 (請先閱讀背面之注意事項再填寫本頁) -46--44- 581912 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _____B7 V. Description of the Invention (42) So, by moving to the side of the charge collection electrode ii 〇 and collected at the charge collection electrode 1 1 0 heart charges, use The active matrix substrate i 00 is read as an image signal for each pattern, and a two-dimensional image of X-rays incident on the flat-plate x-ray image sensor can be obtained. As described above, in order to read out the charges collected in the charge collecting electrode 110 for each pixel, the charge collecting electrode 1 i 0 is formed separately for each day element. In this way, the series of signals between adjacent pixels can be avoided. On the other hand, the sensor bias electrode 104 and the photoelectric conversion layer 102 can be formed on substantially the entire surface of the glass substrate 106. Next, the continuation of the above-mentioned sensor substrate i 丨 2 and the active matrix substrate i00 is described below. As described above, the active matrix substrate i 00 is the charge of the image signal that will be used to collect the charge collection electrode ii 0 in the sensor board 1 12 through the TFT 10 provided in each pixel (see FIG. Therefore, the conductive connecting material 108 connecting the charge collecting electrode u0 of the sensor substrate 112 and the pixel electrode 7 of the active matrix substrate 100 is provided for each pixel. As this conductive connecting material 1 〇8, it is possible to use a photosensitive resin that imparts conductivity, a solder that can be used for pattern printing or a conductive adhesive, etc. By using these materials, it is possible to form a pixelated conductive connection for each pixel electrode 7材 108. Here, the inventors have produced a flat-plate type X-ray image sensor having the above-mentioned manufacturing and having about 2800 × 2800 pixels and a daytime pitch of 0.15 mm. For X-rays The result of the day image acquisition test confirms that by reducing the capacitance of the No. 1 line of the active matrix substrate 100, the excellent $ / n can be obtained (please read the precautions on the back before filling this page)- ------- Order --------- line k -45- Staff of Intellectual Property Bureau, Ministry of Economic Affairs Fei Cooperative Co., Ltd. printed 581912 Α7-___ Β7 5. The portrait signal of the invention description (43) confirms that it can be used for animation photography. In addition, the flat-type X-ray image sensor with the above structure can be used on the active matrix substrate 100 and After the sensor substrates 112 are formed separately, the active matrix substrate 100 and the sensor substrates 2 and 2 are then fabricated. Therefore, the film-forming temperature of the photoelectric conversion layer 102 during the formation of the sensor substrate 112 It is not limited by the heat-resistant temperature of the active matrix substrate 1000. Therefore, as the photoelectric conversion layer 102, in addition to the above-mentioned CdTe, various materials such as CdZnTe can be selected. In addition, the flat-type X-ray image sense according to the above structure Sensor, the photoelectric conversion layer 102 is not directly formed on the active matrix substrate 100. Therefore, even when an active matrix substrate with a large surface step existence rate is used, it can still be prevented from being caused by the active matrix substrate. The poor film formation of the photoelectric conversion layer 102 on the surface difference of the matrix substrate 100 can suppress deterioration of the characteristics of the photoelectric conversion layer 102. In addition, the above is the photoelectric conversion layer 〇2 An X-ray image sensor that generates electric charges when irradiated with X-rays will be described, but it is not limited to this. The image of the electromagnetic wave image in other wavelength regions can also be formed by changing the material of the photoelectric conversion layer 102 As described above, it is preferable that the flat-type image sensor of the present invention, the photoelectric conversion layer 102 and the pixel electrode 7 are patterned conductive connections corresponding to the day element electrode 7 The material 1 08 is used for electrical connection. The flat-type image sensor with this structure can form the active matrix substrate 100 and the substrate with the photoelectric conversion layer 102 separately, and then electrically connect each substrate with a conductive connection material 108. production. Therefore, you can avoid photoelectric changes -------- ^ --------- Xin Qin (Please read the precautions on the back before filling this page) -46-

經濟部智慧財產局員工消費合作社印製 581912 A7 __B7 五、發明說明（44) 換層102之成膜溫度受到主動矩陣基板1〇〇之耐熱溫度的 限制。是以’作爲光電變換層1 〇 2，例如可選擇成膜溫度 較高之CdTe或CdZnTe等之各種材料。 再者，上述構成之平板型畫像感測器，可採用光電變換 層102未直接形成於主動矩陣基板1〇〇上之構造。是以， 即使疋使用表面階差之存在率較大的主動矩陣基板1〇〇之 場合’也仍可防止主動矩陣基板1 〇 0之表面階差所引起的 光電變換層1 0 2之成膜不良，可抑制光電變換層1 〇 2特性 之劣化。 [實施形態5 ] 其次，作爲5實施形態，茲就使用實施形態2所説明之 主動矩陣基板的平板型晝像感測器，佐以圖1 9説明如 下。又’有關與實施形態2所説明之構成要件具有同等機 •能之構件要件，僅附加相同之符號，至於其説明則在此省 略0 作爲本實施形悲之平板型畫像感測器的平板型X射線畫 像感測器：如圖1 9所示’係由實施形態2中佐以圖1 2〜圖 1 4所説明之主動矩陣基板2 〇 〇、光電變換層2 〇 2及感測器 偏壓電極2 0 4組合而成。又，此平板型X射線畫像感測器 中之主動矩陣基板2 00，係如實施形態2之圖12〜圖14所 示，其説明在此省略。又，圖1 9係上述平板型X射線晝像 感測器中’相當於圖1 2之I -1線邵份的箭頭方向斷面圖。 此一平板型X射線畫像感測器中，主動矩陣基板2 〇 〇之 大致全面上，形成有光電變換層（感測膜、感測層）2 0 2。 -47- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ------------m裝--------訂---------線· (請先閱讀背面之注意事項再填寫本頁) 581912 Α7 — Β7 五、發明說明（45 ) 又，光電變換層202上，大致全面地形成有感測器偏壓電 極 204 〇 (請先閱讀背面之注意事項再填寫本頁) 此處，光電變換層2 0 2係由a-Se等形成，感測器偏壓電 極2〇4係由Au (金）等之金屬膜等形成。 本平板型X射線畫像感測器也是，與實施形態4之平板 型X射線感測器相同，藉由將X射線入射至光電變換層 202，可將光電變換層202内所發生之正負電荷，作爲畫 像信號讀出。 此處，本平板型X射線畫像感測器與實施形態4之平板 型X射線畫像感測器之相異點係在於，光電變換層2 〇 2係 直接形成於主動矩陣基板200上。藉此，平板型X射線畫 像感測器之製造變得容易，也將製程簡單化。 又’感測器偏壓電極2 0 4與畫素電極7之間，可施加高 電壓。又，藉由施加此一高電壓，在光學變換層2〇2移動 至主動矩陣基板2 0 〇側之電荷，係由主動矩陣基板2 〇 〇之 畫素電極（電荷收集用電極）7所直接收集，並介以TFT 10 (參見圖1 2.)讀出。 經濟部智慧財產局員工消費合作社印製 例如’在圖1 9之場合中所示的是，相對感測器偏壓電 極204’以畫素電極7成爲負之方式施加高電壓時的狀 悲’此時’負電荷係朝感測器偏壓電極2 〇 4側，正電荷係 朝畫素電極7側移動。 本平板型X射線畫像感測器，係在主動矩陣基板2 〇 〇上 直接將a-Se等之光電變換層202成膜之構造。然而，作爲 王動矩陣基板2 〇 〇，係使用藉由第2保護膜8 a表面階差之 -48- 尽紙浪尺度通用中國國家標準（CNS)A4規格（21〇 χ 297公釐） A7 -----^ _g7 五、發明說明（46 ) :在率T低者’因此’可防止作爲光電變換層202之a% 寺的、、，化。是以，本平板型X射線畫像感測器，可抑制 光電變換層2 02之暗電流的增加。 此處’發明人等曾製作具有上述製造，約2_ χ Μ的畫 素，畫素間距爲〇·15 mm之平板型χ射線晝像感測器。就 其X射線之畫像取得進行測試的結果顯示，根據上述主動 矩陣基板200《信號線電容的降低效果及暗電流增加抑制 效果，確忍可獲得S/时常優異之晝像信號，可作動晝辑 影。 一 如上所述，本實施形態之平板型畫像感測器，具有在畫 素電極7上配置光電變換層2〇2，且該畫素電極7係作爲電 荷收集用電極發揮機能之構成。 %根據上述構成，可形成信號線電容小之平板型畫像感測 姦，因此，可謀求減小起因於信號線電容之電荷讀出所需 的時間之增大化，或來自掃描線2 (參見圖12)及輔助電 容配線23之影響所造成的施加於信號線6之信號的雜訊。 如此，可在特別是在醫藥用之X射線晝像感測器等中，提 仏即使疋源自微弱光之晝像’也能獲得正確晝像資料之書 像感測器。 經濟部智慧財產局員工消費合作社印製 又’在平板型X射線畫像感測器，由於係採用以第2保 護膜8Α降低表面階差存在率之主動矩陣基板2〇〇所構 成，因此，可以上述平坦化抑制主動矩陣基板2〇〇上所設 之a-Se等的光電變換層2 0 2之結晶化。藉此，可防止平板 型畫像感測器中光電變換層2 0 2的性能劣化。 -49- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐）Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 581912 A7 __B7 V. Description of the Invention (44) The film formation temperature of the layer change 102 is limited by the heat-resistant temperature of the active matrix substrate 100. As the photoelectric conversion layer 102, various materials such as CdTe or CdZnTe having a higher film forming temperature can be selected. In addition, the flat-type image sensor having the above-mentioned structure can adopt a structure in which the photoelectric conversion layer 102 is not directly formed on the active matrix substrate 100. Therefore, even in the case of using an active matrix substrate 100 having a large surface step existence rate, it is still possible to prevent the formation of the photoelectric conversion layer 102 caused by the surface step difference of the active matrix substrate 100. Defective, suppressing deterioration of the characteristics of the photoelectric conversion layer 102. [Embodiment 5] Next, as a fifth embodiment, a flat-type day image sensor using the active matrix substrate described in Embodiment 2 will be described below with reference to FIG. Also, regarding the components having the same functions and functions as the components described in the second embodiment, only the same reference numerals are added, and the description is omitted here. As a flat type of the flat image sensor of this embodiment, X-ray image sensor: As shown in FIG. 19, 'the active matrix substrate 2 00, the photoelectric conversion layer 2 02, and the sensor bias are described in Embodiment 2 with reference to FIG. 12 to FIG. 14 The electrodes 2 0 4 are combined. The active matrix substrate 2000 in this flat-type X-ray image sensor is as shown in Figs. 12 to 14 of the second embodiment, and its description is omitted here. Fig. 19 is a sectional view in the direction of the arrow corresponding to the line "I-1" in Fig. 12 of the flat-plate X-ray day image sensor. In this flat-type X-ray image sensor, the active matrix substrate 2000 has a photoelectric conversion layer (sensing film, sensing layer) 202 formed on almost all sides. -47- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) ------------ m installed -------- order ----- ---- Line · (Please read the precautions on the back before filling in this page) 581912 Α7 — Β7 V. Description of the invention (45) In addition, on the photoelectric conversion layer 202, a sensor bias electrode 204 is formed almost completely 〇 (Please read the precautions on the back before filling in this page) Here, the photoelectric conversion layer 202 is made of a-Se and so on, and the sensor bias electrode 204 is made of Au (gold) and other metal film And other formation. This flat-type X-ray image sensor is also the same as the flat-type X-ray sensor of Embodiment 4. By entering X-rays into the photoelectric conversion layer 202, the positive and negative charges generated in the photoelectric conversion layer 202 can be generated. Read out as an image signal. Here, the difference between the flat-type X-ray image sensor and the flat-type X-ray image sensor of the fourth embodiment is that the photoelectric conversion layer 202 is directly formed on the active matrix substrate 200. This makes it easier to manufacture the flat-type X-ray image sensor and simplifies the manufacturing process. A high voltage can be applied between the sensor bias electrode 204 and the pixel electrode 7. In addition, by applying this high voltage, the charges moving from the optical conversion layer 200 to the active matrix substrate 2000 side are directly caused by the pixel electrodes (charge collection electrodes) 7 of the active matrix substrate 2000. Collect and read out via TFT 10 (see Figure 1 2.). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, for example, 'as shown in the case of FIG. 19, the relative sensor bias electrode 204' is shown when a high voltage is applied in such a way that the pixel electrode 7 becomes negative. At this time, the 'negative charge' is toward the sensor bias electrode 204 side, and the positive charge is moving toward the pixel electrode 7 side. The flat-type X-ray image sensor has a structure in which a photoelectric conversion layer 202 such as a-Se is directly formed on an active matrix substrate 2000. However, as the Wang moving matrix substrate 2000, the -48- surface level difference of the second protective film 8a is used-the universal Chinese national standard (CNS) A4 specification (21〇χ 297 mm) A7 ----- ^ _g7 V. Description of the invention (46): Those who have a low rate T can therefore be prevented from being used as a% of the photoelectric conversion layer 202. Therefore, this flat-type X-ray image sensor can suppress an increase in the dark current of the photoelectric conversion layer 202. Here, the inventors and others have produced a flat-type x-ray day image sensor having the above-produced pixels of about 2 mm and a pixel pitch of 0.15 mm. The test results of the X-ray image acquisition show that according to the above-mentioned active matrix substrate 200, the effect of reducing the signal line capacitance and the effect of suppressing the increase of dark current, it is sure to obtain a daytime image signal with excellent S / often, and can be operated Shadow. As described above, the flat-type image sensor of this embodiment has a structure in which a photoelectric conversion layer 202 is arranged on the pixel electrode 7, and the pixel electrode 7 functions as a charge collection electrode. According to the above configuration, a flat-type portrait sensor with a small signal line capacitance can be formed. Therefore, it is possible to reduce the increase in the time required for the charge readout due to the signal line capacitance, or from the scanning line 2 (see FIG. 12) and the noise of the signal applied to the signal line 6 due to the influence of the auxiliary capacitor wiring 23. In this way, it is possible to improve a book image sensor that can obtain accurate day image data even if a day image derived from a weak light is used in a medical X-ray day image sensor and the like. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the flat-type X-ray image sensor is composed of an active matrix substrate 2000 that uses a second protective film 8A to reduce the surface step existence rate. The above-mentioned planarization suppresses the crystallization of the photoelectric conversion layer 202 such as a-Se provided on the active matrix substrate 2000. This can prevent the performance of the photoelectric conversion layer 202 from being deteriorated in the flat-type image sensor. -49- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm)

581912 五、發明說明（47 ) [實施形態6 ] 其次’作爲第6實施形態，茲就使用實施形態3所説明 之主動矩陣基板的平板型畫像感測器，佐以圖2 〇説明 心。又，有關與實施形態3所説明之構成要件具有相同的 構成要件，在此僅附加同一符號，至於其説明則在此省 略。 作爲本實施形態平板型畫像感測器的平板型X射線畫像 感測器，如圖2 0所示，係由實施形態3基於圖1 5〜圖i 7所 説明之主動矩陣基板3 0 0、光電變換層3 〇2及感測器偏壓 電極3 04組合而成。又，此一平板型χ射線畫像感測器中 之主動矩陣基板3 〇 〇，係實施形態3中由圖1 5〜圖i 7所示 者，其説明在此省略。又，圖2 〇係上述平板型X射線晝像 感測器中相當於圖1 5中K-K線部份之箭頭方向斷面圖。 此一平板型X射線畫像感測器，其主動矩陣基板3 〇 〇之 大致全面上，形成有光電變換層（感測膜、感測層）3 〇 2。 又’光電變換層302上，大致全面上形成有感測器偏壓電 極 3 0 4 0 此處’光電變換層3 0 2係由a-Se等所形成，感測器偏壓 電極304係由Au (金）等之金屬膜等來形成。 又，在平板型X射線畫像感測器，基本上與實施形態5 之平板型X射線畫像感測器，具有大致同等之構成、機 能。在平板型X射線畫像感測器，與實施形態5之平板型 X射線畫像感測器不同的點像在於，在主動矩陣基板3 〇 〇 中，信號線2 6係埋設於層間絕緣膜9與保護膜8之間，層 -50- 本紙張尺度適用中國國家標準（CNS)A4規格(210 X 297公釐） -----------裝·-------訂---I----- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ^1912581912 V. Description of the invention (47) [Embodiment 6] Next, as a sixth embodiment, a flat-type image sensor of the active matrix substrate described in Embodiment 3 is used, and illustrated in FIG. It should be noted that the same constituent elements as those described in the third embodiment have the same constituent elements, and only the same reference numerals are given here, and descriptions thereof will be omitted here. As shown in FIG. 20, the flat-type X-ray image sensor as the flat-type image sensor of this embodiment is the active matrix substrate 300 described in Embodiment 3 based on FIGS. 15 to i7, The photoelectric conversion layer 302 and the sensor bias electrode 304 are combined. The active matrix substrate 3 in this flat-type x-ray image sensor is shown in Fig. 15 to Fig. 7 in the third embodiment, and its description is omitted here. Fig. 20 is a cross-sectional view in the direction of the arrow corresponding to the line K-K in Fig. 15 in the flat-plate X-ray day image sensor. This flat-type X-ray image sensor has an active matrix substrate 300 substantially formed on the entire surface, and a photoelectric conversion layer (sensing film, sensing layer) 3 02 is formed. On the photoelectric conversion layer 302, a sensor bias electrode 3 0 4 is formed substantially on the entire surface. Here, the photoelectric conversion layer 3 0 2 is formed by a-Se and the like, and the sensor bias electrode 304 is formed by A metal film such as Au (gold) is formed. The flat-type X-ray image sensor basically has the same configuration and function as the flat-type X-ray image sensor of the fifth embodiment. The flat-type X-ray image sensor is different from the flat-type X-ray image sensor of the fifth embodiment in that in the active matrix substrate 300, the signal lines 26 are embedded in the interlayer insulating film 9 and Between protective film 8 and layer -50- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ----------- installation ------- order --- I ----- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 1912

五、發明說明（48 ) 間絕緣膜9上只有畫素電極7露出。是以，如上所述，除 了表面階差之存在率之外，可將表面階差之値形成爲較實 施形態5爲小。因此，可進一步抑制心&amp;等之光電變換層 3 〇 2的結晶化，可減低光電變換層3 〇2之暗電流。 又，發明人等曾製作具有上述製造，且約28〇〇 χ 晝 素，畫素間距爲0.15 mm之平板型χ射線畫像感測器。 又，嘗試X射線之畫像取得的結果確認，藉由上述主動矩 陣基板3 0 0之信號線電容降低效果及暗電流增加抑制效 果，可獲得S/N非常優異之畫像信，號，也可作動畫攝影。 此外，又確認起因於光電變換層3 〇 2之結晶化的不良之發 生率非常之低。 如上所述，本發明形態之平板型χ射線畫像感測器，由 於使用藉由層間絕緣膜9，表面階差之存在率經降低或表 面經平坦化的主動矩陣基板3 〇 〇所構成，主動矩陣基板 3 〇 〇上所設之a-Se等光電變換層3 〇 2之結晶化，可由上述 平坦化而抑制。藉此，可防止平板型畫像感測器中光電變 換層3 0 2 4性能劣化。 [實施形態7 ] 實施形態1〜3中所説明之主動矩陣基板，均是使用底閘 型（逆交錯型構造）之TFT 10 (參見圖2及圖3)。但本發明 不受此限制，當然在使用頂閘型（正交錯構造）之Τ ρ τ (開 關元件）8 0之場合也可適用。 是以，作爲第7實施形態，就使用頂閘極TFT 80之主動 矩陣基板，佐以圖2 1〜圖2 4説明如下。又，與實施形態 -51 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂---------· 經濟部智慧財產局員工消費合作社印製 581912 A7 --B7___ 五、發明說明（49 ) 1〜3所說明之構成要件具有同等機能之構成要件，在此僅 附記以同一符號，至於其說明在此省略。 圖2 1係本實施形態主動矩陣基板之平面圖，圖2 2、圖 2 3及圖2 4分別係圖2 1主動矩陣基板的L - L線、Μ - Μ線及 Ν-Ν線之前頭方向斷面圖。 與實施形態1所說明之主動矩陣基板的本質上之相異 點，係在於TFT 80之構造為頂閘極，且伴隨於此，掃描線 7 2及信號線7 6相對玻璃基板1之上下關係相異。此一主動 矩陣基板之構造係如下所述。 玻璃基板1上，複數之掃描線7 2與複數之信號線7 6，彼 此係配置成格子狀，與其各交叉部份對應，分別配置有 TFT 80及晝素電極7。 此處，頂閘型TFT 80及底閘型TFT 10 (參見圖2及圖 3 )，就玻璃基板1之上下關係係相反。亦即，有關tft 80 ’係在玻璃基板1上首先形成源極8 1及汲極8 3。又， 源極81及ί及極83之上方，依序形成有接觸層（圖未示）、 半導體區域（半導體層）8 4、閘絕緣膜7 4 (絕緣膜）及閘極 Ί 5。 此外’又形成有被覆該TFT 80或閘絕緣膜7 4之層間絕 緣膜（絕緣體層）9。此一層間絕緣膜9，可採用由壓克力 等之感光樹脂膜、SiNx等之無機膜、或此等膜之積層膜。 閘極7 5係介以形成於層間絕緣膜9之接觸孔7 2 a，接績 於形成在層間絕緣膜9上之掃描線7 2。又，源極8 1係接績 於由同層所構成之信號線7 6。又，汲極8 3係介以形成於 •52- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) — 1 I ·1 ϋι ϋ ϋ H 一-οπ i_Bi ia— a— n ϋ n 1_&gt; I · 經濟部智慧財產局員工消費合作社印製 5819125. Description of the invention (48) Only the pixel electrode 7 is exposed on the interlayer insulating film 9. Therefore, as described above, in addition to the existence rate of the surface level difference, the surface level difference can be made smaller than that in the fifth embodiment. Therefore, it is possible to further suppress the crystallization of the photoelectric conversion layer 3 2 such as the heart &amp;, and to reduce the dark current of the photoelectric conversion layer 3 2. In addition, the inventors have produced a flat-type X-ray image sensor having the above-mentioned manufacturing and having a pixel distance of about 2800 x pixels and a pixel pitch of 0.15 mm. In addition, the results obtained by trying the X-ray image confirmed that the signal line capacitance reduction effect and the dark current increase suppression effect of the active matrix substrate 300 described above can obtain the image signal with excellent S / N, which can also be used as Animation photography. In addition, it was also confirmed that the incidence of defects due to crystallization of the photoelectric conversion layer 3 2 was very low. As described above, the flat-type x-ray image sensor according to the present invention is formed by using an active matrix substrate 300 having an interlayer insulating film 9 having a reduced surface step existence rate or a flat surface. Crystallization of the photoelectric conversion layer 300 such as a-Se provided on the matrix substrate 300 can be suppressed by the above-mentioned planarization. This can prevent deterioration of the performance of the photoelectric conversion layer 3 0 2 in the flat-type image sensor. [Embodiment 7] The active matrix substrates described in Embodiments 1 to 3 are all TFTs 10 using a bottom gate type (inverse staggered structure) (see FIGS. 2 and 3). However, the present invention is not limited to this, and it is of course applicable to the case where a top gate type (positive staggered structure) of τ ρ τ (switch element) 80 is used. Therefore, as a seventh embodiment, an active matrix substrate using a top-gate TFT 80 is described below with reference to Figs. 21 to 24. And, implementation form -51-This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) (Please read the precautions on the back before filling this page) Order --------- Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 581912 A7 --B7 ___ V. The constituent elements described in the invention description (49) 1 ~ 3 have the same functional constituent elements. Only the same symbols are attached here. This is omitted. Fig. 2 is a plan view of the active matrix substrate of this embodiment, and Figs. 2, 2, 3, and 24 are the front directions of the L-L line, the M-M line, and the N-N line of the active matrix substrate of Fig. 2, respectively. Sectional view. The essential difference from the active matrix substrate described in the first embodiment lies in that the structure of the TFT 80 is a top gate electrode, and along with this, the scanning line 72 and the signal line 76 are up and down relative to the glass substrate 1. Different. The structure of this active matrix substrate is as follows. On the glass substrate 1, a plurality of scanning lines 72 and a plurality of signal lines 76 are arranged in a grid shape, corresponding to each crossing portion thereof, and a TFT 80 and a day electrode 7 are respectively arranged. Here, the top-gate TFT 80 and the bottom-gate TFT 10 (see FIG. 2 and FIG. 3) have opposite relationships with respect to the top and bottom of the glass substrate 1. That is, regarding the tft 80 ', the source 8 1 and the drain 8 3 are first formed on the glass substrate 1. A contact layer (not shown), a semiconductor region (semiconductor layer) 8 4, a gate insulating film 7 4 (insulating film), and a gate Ί 5 are sequentially formed above the source 81 and the electrode 83. In addition, an interlayer insulating film (insulator layer) 9 covering the TFT 80 or the gate insulating film 74 is formed. As this interlayer insulating film 9, a photosensitive resin film such as acrylic, an inorganic film such as SiNx, or a laminated film of these films can be used. The gate electrode 75 is a contact hole 7 2 a formed in the interlayer insulating film 9 through a scanning line 72 formed in the interlayer insulating film 9. The source 8 1 is connected to the signal line 76 composed of the same layer. In addition, the drain electrode 8 3 is formed in • 52- This paper size applies the Chinese National Standard (CNS) A4 specification (21〇χ 297 mm) (Please read the precautions on the back before filling this page) — 1 I · 1 ϋι ϋ ϋ H a-οπ i_Bi ia— a— n ϋ n 1_ &gt; I

五、發明說明（加） (請先閲讀背面之注意事項再填寫本頁) 閘絕緣膜74之接觸孔83b、閘絕緣膜74與層間絕緣膜9間 所形成之汲配線83a、以及形成於層間絕緣膜9之接觸孔 7a，與形成於層間絕緣膜9上之畫素電極7接續。 又，接觸孔7ai下方，在破璃基板i與閘絕緣膜”之 間，形成有輔助電容配線7 3，而與汲配線8 3 a之間，形成 輔助電容82 (參見圖24)。 上述構成中，玻璃基板1上，形成有：形成信號線76之 層、位於形成信號線76層之上方的形成閘極75之層、位 於形成閘極75層之上方的形成掃描線72之層。又，形成 信號線7 6之層與形成閘極75之層之間，形成有閘絕緣膜 74，形成閘極75之層與形成掃描線72之層之間，形成有 層間絕緣膜9。 又，上述構成中，信號線7 6、源極8 1、汲極8 3及輔助 電容配線7 3，可由相同之層形成。同樣地，閘極7 5與汲 配線8 3 a可由同一層形成，畫素電極7與掃描線7 2也可由 同一層形成。 又，各構成要件之材質，可與實施形態i等相同，又， 製法也可適當地變更實施形態1過程之順序而適當達成， 至於其説明在此省略。 經濟部智慧財產局員工消費合作社印製 根據習用之主動矩陣基板’在形成有頂閘型Τρτ者中也 是，掃描線與信號線主要只是介以閘絕緣膜配置。根據此 一構造，閘絕緣膜之厚度係由TFT之規格所決定，將基於 此決定之厚度的閘絕緣膜之靜電電容値設定地較小有所困 難。因此，信號線與掃描線介以閘絕緣膜對向之部份，信 -53- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） &quot; 581912V. Description of the invention (plus) (Please read the precautions on the back before filling out this page) Contact hole 83b of gate insulating film 74, drain wiring 83a formed between gate insulating film 74 and interlayer insulating film 9, and formed between layers The contact hole 7 a of the insulating film 9 is connected to the pixel electrode 7 formed on the interlayer insulating film 9. Below the contact hole 7ai, an auxiliary capacitor wiring 7 3 is formed between the broken glass substrate i and the gate insulating film ”, and an auxiliary capacitor 82 is formed between the drain wiring 8 i and the drain wiring 8 3 a (see FIG. 24). In the glass substrate 1, a layer forming a signal line 76, a layer forming a gate 75 above the layer forming the signal line 76, and a layer forming a scan line 72 above the layer forming the gate 75 are formed. Between the layer forming the signal line 76 and the layer forming the gate electrode 75, a gate insulating film 74 is formed, and between the layer forming the gate electrode 75 and the layer forming the scan line 72, an interlayer insulating film 9 is formed. In the above configuration, the signal line 76, the source 81, the drain 83, and the auxiliary capacitor wiring 73 can be formed in the same layer. Similarly, the gate 75 and the drain wiring 83a can be formed in the same layer. The element electrode 7 and the scanning line 72 may be formed in the same layer. The material of each constituent element may be the same as that of the embodiment i, and the manufacturing method may be appropriately changed to the order of the process of the embodiment 1 to achieve appropriately. The explanation is omitted here. The active matrix substrate printed according to the convention is also used in the formation of the top gate type Tρτ, and the scanning lines and signal lines are mainly configured only through a gate insulating film. According to this structure, the thickness of the gate insulating film is determined by the TFT specifications. It was difficult to set the electrostatic capacitance 値 of the gate insulating film based on the thickness determined by this decision to be small. Therefore, the part where the signal line and the scanning line are opposed to each other by the gate insulating film, letter -53- China National Standard (CNS) A4 (210 X 297 mm) &quot; 581912

五、發明說明（51 號線與掃描線之間所發生的信號線電容之電容値會增大， 是爲其問題。 相對於此，根據上述構成，介以形成閘極7 5之層與形 成掃描線72之層之間所形成的層間絕緣膜9，配置有掃描 線7 2及信號線7 6。因此，介以該層間絕緣膜9所分隔的信 號線76與掃描線72之間隔，可設定成較上述閘絕緣膜74 之厚度爲大，因此，信號線7 6與掃描線7 2之間所發生之 #號線電容的電容値，可形成爲較上述習用場合爲小。 該層間絕緣膜9係形成於閘極7 5形成層與信號線7 6形成 層之間’與上述閘絕緣膜7 4等不同，與TFT 80之规格獨 立。是以，可將此層間絕緣膜9形成爲使信號線電容之電 容値充份地小。 又，因應必要，可與實施形態2相同，形成爲該置保護 主動矩陣基板之最表面處露出的掃描線7 2之保護膜（相當 於第2保遵膜、掃描線保護膜、上述信號線保護8 a (參見 圖1 3及圖1 4))的構成。 再者’本實施形態之主動矩陣基板，可構成與實施形態 4及5中分別以圖1 8及圖1 9説明之平板型畫像感測器大致 相同的平板型畫像感測器。根據本實施形態之主動矩陣基 板所構成的平板型畫像感測器，可獲得與實施形態4及5 之平板型畫像感測器大致相同之效果。 如上所述，本實施形態之主動矩陣基板，信號線7 6 (源 極81)形成層（第1電極層）、閘極75形成層（第2電極層）、 才f描線7 2形成層’係在玻璃基板1上依此順序形成，而在 -54- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · I-----—訂-------！ 經濟部智慧財產局員工消費合作社印製 581912 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（52 ) 閘極75形成層與掃描線72形成層之間，備有絕緣體層（層 H彖膜9 )又，彳&amp;號線（弟1配線）7 6與掃描線（第2配 線）7 2，係介以絕緣體層配置。 此一構成中，介以絕緣體層，信號線76與掃描線”例 如係配置成彼此交又等等。因此，藉由絕緣體層，可減少 信號線電容之電容値。是以，可充份減小信號線電容之電 容値。 如此，根據此一構成，可提供TFT 80之機能良好，信號 線7 6與掃描線7 2之間所發生之信號線電容的電容値小之 主動矩陣基板。 又，與汲極83接續之畫素電極7，宜由與掃描線72形成 層相同之層所構成。、 此一構成中，接續於汲極8 3之晝素電極7，係由與掃描 線72形成層相同之層所形成。是以，在掃描線72與閘極 由不同層所形成之上述構成中也是，由於掃描線η與 晝素電極7係由同一層形成，可避免製造過程中過程數之 增加。 如此，可以較少之工程數目，製造上述主動矩陣基板， 了謀求產率之提南或成本之降低。 [實施形態8 ] 作爲實施形態8，係在實施形態7之主動矩陣基板的構 成中，再追加保護膜（絕緣體層）7 8之構成，就此，茲佐 以圖25〜圖28説明如下。又，就與實施形態i〜7所説明之 構成要件具有相同機能之構成要件，僅附記相同之符號， (請先閲讀背面之注意事項再填寫本頁)V. Description of the Invention (The capacitance of the signal line capacitance occurring between the 51 line and the scanning line will increase, which is a problem. In contrast, according to the above structure, the layer and formation of the gate 75 are formed. The interlayer insulating film 9 formed between the layers of the scanning lines 72 is configured with scanning lines 72 and signal lines 76. Therefore, the interval between the signal lines 76 and the scanning lines 72 separated by the interlayer insulating film 9 may be It is set to be larger than the thickness of the above-mentioned gate insulating film 74. Therefore, the capacitance # of the #line capacitor occurring between the signal line 76 and the scanning line 72 can be formed smaller than the above-mentioned conventional occasion. The film 9 is formed between the gate electrode 75 formation layer and the signal line 76 formation layer, and is different from the gate insulation film 74 above, and is independent of the specifications of the TFT 80. Therefore, the interlayer insulation film 9 can be formed as The capacitance of the signal line capacitor is sufficiently small. If necessary, it can be formed as a protective film (corresponding to the second portion) of the scanning line 72, which is exposed at the outermost surface of the active matrix substrate, as in Embodiment 2. Warranty film, scanning line protection film, signal line protection 8 a ( (See FIG. 13 and FIG. 14)). Furthermore, the active matrix substrate of this embodiment can be configured as a flat-type image sensor described in Embodiments 4 and 5 with FIGS. 18 and 19 respectively. Approximately the same flat-type image sensor. According to the flat-type image sensor composed of the active matrix substrate of this embodiment, the same effect as that of the flat-type image sensor of the fourth and fifth embodiments can be obtained. In the active matrix substrate of this embodiment, the signal line 76 (source electrode 81) forming layer (first electrode layer), the gate electrode 75 forming layer (second electrode layer), and the drawing line 7 2 forming layer are described below. The glass substrate 1 is formed in this order, and the paper size of -54- applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) · I-- ----- Order -------! Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 581912 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (52) Gate 75 formation layer and scan Lines 72 are formed between layers, and an insulator layer (layer H 彖 film 9) is provided. &amp; The number line (the first wiring) 7 6 and the scanning line (the second wiring) 7 2 are disposed via an insulator layer. In this configuration, the signal line 76 and the scanning line are interposed via the insulator layer, for example, configured as Intersect each other and so on. Therefore, the capacitance 信号 of the signal line capacitance can be reduced by the insulator layer. Therefore, the capacitance 信号 of the signal line capacitance can be sufficiently reduced. Thus, according to this configuration, the function of the TFT 80 can be provided Good, the active matrix substrate has a small capacitance of the signal line capacitance occurring between the signal line 76 and the scanning line 72. Also, the pixel electrode 7 connected to the drain electrode 83 should preferably be the same layer as the scanning line 72. Constituted by layers. In this configuration, the daylight electrode 7 connected to the drain electrode 83 is formed of the same layer as that of the scanning line 72. Therefore, even in the above-mentioned configuration in which the scanning line 72 and the gate electrode are formed by different layers, since the scanning line η and the day electrode 7 are formed in the same layer, an increase in the number of processes in the manufacturing process can be avoided. In this way, the above-mentioned active matrix substrate can be manufactured with a smaller number of projects, and the production efficiency can be improved or the cost can be reduced. [Embodiment 8] As Embodiment 8, the structure of an active matrix substrate according to Embodiment 7 is further added with a protective film (insulator layer) 78, and the following description will be given with reference to FIGS. 25 to 28. In addition, the constituent elements having the same functions as the constituent elements described in the embodiments i to 7 are only marked with the same symbols. (Please read the precautions on the back before filling in this page)

-55--55-

581912 A7 B7 五、發明說明（53 ) 至於其説明則在此省略。 圖2 5係本實施態主動矩陣基板之平面圖，圖2 6、圖2 7 及圖2 8分別係沿圖2 5主動矩陣基板之〇 _ 〇線、P _ p線及 Q · Q線箭頭方向的斷面圖。 此一主動矩陣基板中，實施形態7中之主動矩陣基板的 閑極7 5及没配線8 3 a形成層與畫素電極7形成層之間的絕 緣體層（參見圖2 6〜圖2 8 )，係成保護膜7 8及層間絕緣膜9 •^二層構造。又，保護膜7 8與層間絕緣膜9之間，形成有 掃描線7 2。 此一主動矩陣基板，與實施形態3之主動矩陣基板相 同，除了靜電電容値之降低效果之外，還具有主動矩陣基 板t表面的階差（凹凸K表面階差）之存在率少，或是階差 値小之構造上的利點。 因此，此一主動矩陣基板，也是適於平板型晝像感測器 心構造。又’藉由將此主動矩陣基板使用於平板型畫像感 測器’可抑制由a_Se等所構成之光電變換層的結晶化，防 止光電變換層特性之劣化。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 又，本實施形態之主動矩陣基板，與實施形態3主動矩 陣基板相同，掃描線7 2與晝素電極7之間介在有層間絕緣 膜9 ’因此，可形成在形成有掃描線72部份之上方，重疊 畫素電極7之構造。藉此，可增大晝素電極7之面積而提 南開口率。 又，本實施形態之主動矩陣基板，可構成與實施形態6 中以圖2 0所説明之平板型畫像感測器大致同等之平板型 -56- 581912581912 A7 B7 V. Description of the invention (53) The description of the invention is omitted here. Figure 2 5 is a plan view of the active matrix substrate of the present embodiment, and Figures 26, 27, and 28 are along the directions of the arrows __o, P_p, and Q.Q of the active matrix substrate of Figure 25, respectively. Section view. In this active matrix substrate, the insulators 7 5 and the non-wiring lines 8 3 a of the active matrix substrate in Embodiment 7 are insulator layers between the formation layer and the pixel electrode 7 formation layer (see FIGS. 2 6 to 2 8) A two-layer structure of the protective film 7 8 and the interlayer insulating film 9 is formed. Scanning lines 72 are formed between the protective film 78 and the interlayer insulating film 9. This active matrix substrate is the same as the active matrix substrate of the third embodiment. In addition to the effect of reducing the capacitance 还, it also has a small existence rate of the step (the uneven K surface step) on the surface of the active matrix substrate, or The structural advantage of small step difference. Therefore, this active matrix substrate is also suitable for a flat-type day image sensor core structure. Furthermore, by using this active matrix substrate in a flat-type image sensor, it is possible to suppress crystallization of a photoelectric conversion layer composed of a_Se and the like, and to prevent deterioration of the characteristics of the photoelectric conversion layer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The active matrix substrate of this embodiment is the same as the active matrix substrate of Embodiment 3. There is an interlayer insulating film 9 'between the scanning line 72 and the day electrode 7' A structure in which the pixel electrode 7 is superimposed on a portion where the scanning line 72 is formed may be formed. Thereby, the area of the day element electrode 7 can be increased to improve the aperture ratio. In addition, the active matrix substrate of this embodiment can be configured as a flat plate type which is approximately equivalent to the flat plate type image sensor described in FIG. 20 in Embodiment 6 -56- 581912

經濟部智慧財產局員工消費合作社印製 五、發明說明（54) 畫像感測器。另，根據本實施形態主動矩陣基板所構成之 平板型畫像感測器，可獲得與實施形態6平板型畫像感測 器大致相同之效果。 如上所述，本實施例形態之主動矩陣基板，較佳的是， 絕緣體層係由保護TFT 80之保護膜7 8所構成，而又形成 被覆掃描線7 2及保護膜7 8之層間絕緣膜9。 此一構成中，係介以作爲絕緣體層之保護膜7 8配置掃 為線7 2及仏號線7 8。此一場合也是，可在無損TFT 80之 機能下增厚保護膜7 8，可降低信號線電容之電容値。 又’根據上述構成，可藉由層間絶緣膜9將保護膜78與 保護膜7 8上所形成之掃描線7 2的階差、或起因於τρτ 之階差掩埋平坦化。如此，在本主動矩陣基板上設置心&amp; 等之光電變換層形成平板型畫像感測器之場合，可防止起 因於由掃描線7 2或ITT 80所造成之表面階差的a_Se之結 晶化，而防止光電變換層之性能劣化。 又，罝在層間絕緣膜9上，形成與汲極8 3接續之畫素電 極7。 里“私 在此一構成中，掃描線72與畫素電極7係介以層間絕緣 膜9配置。是以，可構成在形成有掃描線72之上方，重疊 有畫素電極7之構造，可增大晝素電極7之面積提高〇 率。 曰以上，發明説明項中所舉的具體實施態樣或實施例，口 是爲將本發明技術内容明確揭示，本發明並不受此等具體 例&lt;限制而作狹義解釋，在本發明之精神與下述申請專: (請先閱讀背面之注意事項再填寫本頁} · I! I I I I 訂·！ 1!!-· -57- 581912 A7 _B7_五、發明說明（55 ) 範圍之範圍内，可作各種變更實施。 [符號説明] 經濟部智慧財產局員工消費合作社印製 1 玻璃基板（基板） 2 掃描線 2a 氧化膜（第1絕緣膜） 2b 鄰接掃描線 3 輔助電容配線 3a 氧化膜（介電體膜、第2絕緣膜） 4 閉絕緣膜（介電體層；第1絕緣膜、第2絕緣膜、 絕緣膜） 5 閘極 6 信號線 6a 接觸孔 7 畫素電極 7a 接觸孔 8 保護膜（絕緣體膜） 8a 第.2保護膜（信號線保護膜） 9 層間絕緣膜 10 T F T (薄膜電晶體、開關元件） 11 源極 11a 源配線 12 輔助電容（靜電電容） 13 汲極 13a 汲配線 ------------裝— (請先閱讀背面之注意事項再填寫本頁) 3-0· ' -58· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 581912 A7 B7 五、發明說明（56) 14 半導體區域（半導體層） 15 接觸層 23 輔助電容配線 26 信號線 32 輔助電容 72 掃描線 72a 接觸孔 73 輔助電容配線 74 閘絕緣膜（絕緣膜） 75 閘極 76 信號線 78 保護膜（絕緣體層） 80 T F T (薄膜電晶體、開關元件） 81 源極 82 輔助電容（靜電電容） 83 汲極 83 a 汲配線 84 半導體區域 102 光電變換層 202 光電變換層 302 光電變換層 -59- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (54) Image sensor. In addition, according to the flat-type image sensor composed of the active matrix substrate of this embodiment, it is possible to obtain substantially the same effects as those of the flat-type image sensor of the sixth embodiment. As described above, in the active matrix substrate of this embodiment, it is preferable that the insulator layer is composed of the protective film 78 protecting the TFT 80, and an interlayer insulating film covering the scanning lines 72 and the protective film 78 is formed. 9. In this configuration, the protective film 78, which is an insulator layer, is arranged as a wire 72 and a horn line 78. Also in this case, the protective film 7 8 can be thickened without loss of the function of the TFT 80, which can reduce the capacitance 値 of the capacitance of the signal line. According to the above configuration, the step difference between the scanning lines 72 formed on the protective film 78 and the protective film 78 or the step difference due to τρτ can be buried and planarized by the interlayer insulating film 9. In this way, when a photoelectric conversion layer such as a core &amp; is provided on the active matrix substrate to form a flat-type image sensor, it is possible to prevent crystallization of a_Se due to the surface step caused by the scanning line 72 or ITT 80. , And prevent the performance of the photoelectric conversion layer from being deteriorated. Further, a pixel electrode 7 is formed on the interlayer insulating film 9 to connect to the drain electrode 8 3. In this configuration, the scanning line 72 and the pixel electrode 7 are arranged via an interlayer insulating film 9. Therefore, the scanning line 72 and the pixel electrode 7 may be formed above the scanning line 72 and the pixel electrode 7 is superimposed. Increasing the area of the daylight electrode 7 increases the rate of 0. In the above, the specific implementation modes or embodiments mentioned in the description of the invention are intended to clearly disclose the technical content of the present invention, and the present invention is not limited to these specific examples &lt; Restricted interpretation in the narrow sense, in the spirit of the invention and the following applications: (Please read the precautions on the back before filling out this page} · I! IIII Order! 1 !!-· -57- 581912 A7 _B7 _Fifth, the scope of the description of the invention (55) can be modified and implemented. [Symbol] Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy 1 Glass substrate (substrate) 2 Scan line 2a Oxide film (the first insulating film ) 2b Adjacent scanning line 3 Auxiliary capacitor wiring 3a Oxide film (dielectric film, second insulating film) 4 Closed insulating film (dielectric layer; first insulating film, second insulating film, insulating film) 5 Gate 6 signal Line 6a contact hole 7 Pixel electrode 7a is connected Contact hole 8 Protective film (insulator film) 8a No. 2 protective film (signal line protective film) 9 Interlayer insulating film 10 TFT (thin-film transistor, switching element) 11 source 11a source wiring 12 auxiliary capacitor (electrostatic capacitor) 13 drain Pole 13a Wiring ------------ Installation— (Please read the precautions on the back before filling in this page) 3-0 · '-58 · This paper size applies to China National Standard (CNS) A4 Specifications (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 581912 A7 B7 V. Description of the invention (56) 14 Semiconductor area (semiconductor layer) 15 Contact layer 23 Auxiliary capacitor wiring 26 Signal line 32 Auxiliary capacitor 72 Scan Line 72a Contact hole 73 Auxiliary capacitor wiring 74 Gate insulation film (insulation film) 75 Gate electrode 76 Signal line 78 Protective film (insulator layer) 80 TFT (thin film transistor, switching element) 81 Source electrode 82 Auxiliary capacitor (electrostatic capacitor) 83 Drain electrode 83 a Drain wiring 84 Semiconductor region 102 Photoelectric conversion layer 202 Photoelectric conversion layer 302 Photoelectric conversion layer -59- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read first (Read the notes on the back and fill out this page)

Claims (1)

581912581912 六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 L 一種主動矩陣基板，備有·· 根據供給至閘極之信號而將源極與汲極間開關之開關 元件， 接續於上述閘極之掃描線， 接續於上述源極之信號線，及 接續於上述汲極之畫素電極，又 形成上述掃描線之層， 位於形成該掃描線之層之上方，形成上述源極之層， 位於形成該源極之層之上方，形成上述信號線之層，及 形成於形成上述源極之層與形成上述信號線之層之間 的絕緣體層，係形成於基板上， 上述掃描線與信號線，係彼此介以上述絕緣體層配 者。 2·如申叫專利範圍第1項之主動矩陣基板，其中形成上 掃描線之層中，形成有上述閘極； 上述汲極係與形成上述源極之層，由同一層所形成 、上述明極與上述源極及上述汲極之間，形成有與上 源極及汲極密接之開關元件的半導體層。 3·如申請專利範圍第2項之主動矩陣基板，其中形成上 源極（層，係藉由延伸至形成有上述半導體層之區域 外部，而形成源配線； 上述絕緣體層中之形成上述源配線的位置，形成有接 觸孔； 介以該接觸孔，上述信號線係接續於上述源配線者。 置 述 述 的 ------------»!裝 (請先閱讀背面之注意事項 寫本頁) ，線· ‘紙張尺度適用中國國家標準（CNS)A4規格（210 ： -60- 581912 A8B8C8D8 經濟部智慧財產局員工消費合作社印製 '、申請專利:範圍 1申請專利範圍第2項之主動矩陣基板，其中該半導體玲〃、形成上述半導體層與掃插線之層之間，形成 絕緣膜； 上述掃描線與信號線，係又介以上述第i絕緣膜配置 者。 5.如申4專利範圍第2項之主動矩降基板，其中接續於上 述汲極之輔助容量，係形成於上述絕緣體層與基板之 間； 形成上述輔助容量之一者電極的輔助容量配線，係相 對上述仏號線介以上述絕緣體層配置者。 6·如申請專利範圍第5項之主動矩陣基板，其中該輔助 量配線，係由與形成上述掃描線之層相同之層所形 者。 y 7. 如申請專利範圍第5項之主動矩陣基板，其中該辅助 量配線’係與上述信號線成交叉地配置，在與上述信 線父叉之邵份，係形成為寬度相對變狹者。 8. 如申請專利範圍第5項之主動矩陣基板，其中該輔助 量之另一電極，係由形成上述源極之層延伸所形成者 9. 如申请專利範圍第5項之主動矩陣基板，其中形成上 沒極之層與形成上述輔助容量配線之層之間，形成有 2絕緣膜； 上述輔助容量配線與信號線，係又介以上述第2絕緣 膜配置者。 10·如申請專利範圍第4項之主動矩陣基板，其中藉由形 -61 - 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） 容 成 容 號 容 第 成 581912 A8 B8 C8 D8 六、申請專利範圍 上述汲極 &lt; 層延伸而形成汲配線，該汲配線係介以上述 第1絕緣膜與鄰於上述掃描線之其他掃描線相對向者。 11. 如申請專利範s第〗項之主動矩陣基板，其中接續於上 述汲椏之畫素電極，係由與形成上述信號線相同之層 形成者。 12. 如申凊專利範圍第j j項之主動矩陣基板，其中該畫素 電極係介以形成於上述絕緣體層之接觸孔，與上述汲極 相接續者。 13‘如申請專利範圍第i項之主動矩陣基板，其中形成有被 覆上述信號線之信號線保護膜者。 14·如申請專利範圍第！項之主動矩陣基板，其中上述絕緣 體層包含由樹脂材料所構成之層間絕緣膜者。 15·如申請專利範圍第i 4項之主動矩陣基板，其中上述絕 緣豆層又包含保護上述開關元件之保護膜者。 16.如申請專利範圍第i 4項之主動矩陣基板，其中該層間 絕緣膜係由具有感光性之樹脂材料所構成者。 17·如申請專利範圍第1 4項之主動矩陣基板，其中該層間 絶緣膜係由丙烯酸系樹脂所構成者。 18·如申請專利範圍第！項之主動矩陣基板，其中該絕緣體 層係由保護上述開關元件之保護膜所構成，且形成有保 護上述信號線及保護膜之層間絕緣膜者。 19·如申請專利範圍第1 8項之主動矩陣基板，其中該層間 絕緣膜上形成有與上述汲極接續之畫素電極者。 20·如申請專利範圍第i 8項之主動矩陣基板，其中該層間 -62 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）6. Scope of patent application: The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints an active matrix substrate equipped with a switching element that switches between the source and the drain according to the signal supplied to the gate, which is connected to the above gate The scanning line is connected to the signal line of the source and the pixel electrode connected to the drain, and a layer of the scanning line is formed, which is located above the layer forming the scanning line, and the layer forming the source is located at Above the layer on which the source is formed, the layer on which the signal line is formed, and an insulator layer formed between the layer on which the source is formed and the layer on which the signal line is formed are formed on a substrate, and the scan line and the signal line , Is a match between the above-mentioned insulator layer. 2. As claimed in the active matrix substrate of item 1 of the patent scope, wherein the gate is formed in the layer forming the upper scanning line; the drain is formed from the same layer as the layer forming the source, and the above Between the electrode and the source and the drain, a semiconductor layer of a switching element in close contact with the upper source and the drain is formed. 3. The active matrix substrate according to item 2 of the scope of patent application, in which an upper source electrode (layer) is formed to extend the source wiring by extending to the outside of the area where the semiconductor layer is formed; the source wiring is formed in the insulator layer A contact hole is formed at the position of the device; the signal line is connected to the source wiring via the contact hole. Note for writing this page), line · 'Paper size applies to Chinese National Standard (CNS) A4 specifications (210: -60-581912 A8B8C8D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs'), patent application: scope 1 The active matrix substrate of 2 items, wherein the semiconductor ridge, an insulating film is formed between the above-mentioned semiconductor layer and the layer of the scanning line; the scanning line and the signal line are arranged through the i-th insulating film. The active moment drop substrate of item 2 in the scope of claim 4, wherein the auxiliary capacity connected to the drain is formed between the insulator layer and the substrate; the electrode of one of the auxiliary capacities is formed. The auxiliary capacity wiring is arranged with the above-mentioned insulator layer relative to the above-mentioned No. 6 line. 6. As in the active matrix substrate of the scope of patent application No. 5, wherein the auxiliary quantity wiring is formed by the same layer as the layer forming the scanning line. Y 7. The active matrix substrate according to item 5 of the scope of patent application, wherein the auxiliary quantity wiring is arranged to intersect with the above signal line, and is formed in a width with the parent fork of the above-mentioned signal line. Those who are relatively narrow. 8. If the active matrix substrate of item 5 of the scope of patent application, the other electrode of the auxiliary amount is formed by the extension of the layer forming the source electrode. The active matrix substrate has two insulating films formed between the upper electrode-less layer and the layer forming the auxiliary capacity wiring; the auxiliary capacity wiring and the signal line are arranged through the second insulating film. For example, the active matrix substrate of the fourth item of the patent application, in which the shape of -61-This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × x297 mm). 581912 A8 B8 C8 D8 VI. Scope of patent application The above drain electrode &lt; layer is extended to form a drain wiring, which is opposed to the other scanning lines adjacent to the scanning line through the first insulating film. The active matrix substrate of item No. s of the patent application, in which the pixel electrodes connected to the above-mentioned pumps, are formed by the same layer as the above-mentioned signal lines. 12. The active matrix substrate of item jj of the scope of patent application The pixel electrode is connected to the drain electrode through a contact hole formed in the insulator layer. 13 'For example, the active matrix substrate of the item i in the patent application scope, wherein a signal line covering the signal line is formed. Protective film. 14 · If the scope of patent application is the first! The active matrix substrate of the above item, wherein the insulator layer includes an interlayer insulating film composed of a resin material. 15. The active matrix substrate according to item i 4 of the scope of patent application, wherein the aforementioned insulating bean layer further includes a protective film for protecting the switching element. 16. The active matrix substrate according to item i 4 of the patent application scope, wherein the interlayer insulating film is made of a photosensitive resin material. 17. The active matrix substrate according to item 14 of the patent application scope, wherein the interlayer insulating film is made of acrylic resin. 18 · If the scope of patent application is the first! In the active matrix substrate of the present invention, the insulator layer is composed of a protective film that protects the switching element, and an interlayer insulating film that protects the signal line and the protective film is formed. 19. The active matrix substrate according to item 18 of the scope of patent application, wherein the interlayer insulating film is formed with a pixel electrode connected to the above drain electrode. 20 · If the active matrix substrate of item i 8 of the scope of patent application, the interlayer -62 paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) r---^---------丨 請先閱讀背面之注意事項再填寫本頁) 六、申請專利範圍 、、愚緣膜係由樹脂材料所構成者。 21. 一種平板型畫像感測器，並 、、 八係包括申請專利範圍第1工% &lt;王動矩陣基板，及與該击 動矩陣基板中之晝素電極相 接續（光電變換層。 22·如申請專利範圍第2 i項之平拓 只〈卞扳型畫像感測器，其中該 光電變換層與晝素電極，#务 今+主 來 二 你/丨以與该畫素電極對應地圖 末化之導電接續材作電氣接績者。 23.如申請專利範圍第21項之平板型晝像感測器，其中該 光電變換層係形成於上述晝素電極上者。 24· —種主動矩陣基板，備有： 根據供給至閘極之信號而將源極與沒極間開關之 元件， 接續於上述閘極之掃描線， 接續於上述源極之信號線，及 接續於上述沒極之晝素電極，又 形成上述信號線之層， 位於形成該信號線之層之上方，形成上述閘極之層， 位於形成該閘極之層之上方，形成上述掃描線之層，及 形成於形成上述閘極之層與形成上述掃描線之^之間 的絕緣體層，係形成於基板上， 上述掃描線與信號線，係彼此介以上述絕緣體層配置 25.如申請專利範圍第2 4項之主動矩陣基板，其中該接績 於上述沒極之畫素電極，係與形成上述掃描線之層由同 -63- 581912 A8 B8 C8r --- ^ --------- 丨 Please read the notes on the back before filling out this page.) 6. Scope of patent application. The film is made of resin material. 21. A flat-type image sensor, and series of eight and eight series including the first patent of the patent application scope &lt; Wang Dong matrix substrate, and connected to the day element electrode (photoelectric conversion layer. 22) in the hit matrix substrate. · If the application of the scope of the patent application No. 2i only pin-type image sensor, in which the photoelectric conversion layer and day element electrode, # 务 今 + 主 来 二 你 / 丨 to correspond to the pixel electrode map The finalized conductive splicing material is the electrical successor. 23. For example, a flat-type day image sensor with the scope of application for patent No. 21, wherein the photoelectric conversion layer is formed on the above-mentioned day element electrode. 24 · — Kind of initiative The matrix substrate includes: an element that switches between a source and an electrode according to a signal supplied to the gate, is connected to the scanning line of the gate, is connected to the signal line of the source, and is connected to the above electrode. The day electrode forms a layer of the above-mentioned signal line, which is located above the layer forming the signal line, forms a layer of the gate, is located above the layer of forming the gate, forms a layer of the scanning line, and is formed on the layer Of the above gates The insulator layer between the formation of the scanning lines is formed on the substrate, and the scanning lines and the signal lines are arranged with the above-mentioned insulator layers between each other. 25. For example, the active matrix substrate of the 24th aspect of the patent application, where This result is the same as the above-mentioned pixel electrode, which is the same as the layer forming the scan line. -63- 581912 A8 B8 C8 經濟部智慧財產局員工消費合作社印製 一層所形成者。 26.如申請專利範圍第；4項之主動矩陣基板，其中該絕緣 體層係由保護上述開關元件之保護膜所構成，且形成有 保護上述掃描線及上述保護膜之層間絕緣膜者。 27·如_請專利範圍第2 6項之主動矩陣基板，其中該層間 絕緣膜上，形成有接績於上述汲極之晝素電極者。 28·種主動矩陣基板，具有：接續於開關元件之信號線、 接續於上述開關元件之掃描線、以及介在於上述信號線 與掃描線之間之樹脂材料。 29. —種主動矩陣基板，備有： 包含半導體層及彼此介以該半導體層配置之第1電極 層及第2電極層之開關元件； 接續於上述第1電極層之第2配線；及 介在於上述開關元件及第丨配線與上述第2配線之間之 絕緣體層。 3〇· —種主動矩陣基板之製造方法，該主動矩陣基板備有： 根據供給至閘極之信號而將源極與汲極間開關之開關 元件， 接續於上述閘極之掃描線， 接續於上述源極之信號線，及 接續於上述沒極之畫素電極，又 形成上述掃描線之層， 位於形成該掃描線之層之上方，形成上述源極之層， 位於形成該源極之層之上方’形成上述信號線之層，及 -64- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Γ%先閱讀背面之注意事項寫本頁) i· 裝 · 581912Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 26. The active matrix substrate according to the scope of patent application No. 4; wherein the insulator layer is composed of a protective film for protecting the switching element, and an interlayer insulating film for protecting the scanning line and the protective film is formed. 27. For example, please refer to the active matrix substrate of item 26 of the patent, wherein the interlayer insulating film is formed with a daylight electrode that succeeds the above-mentioned drain electrode. 28. An active matrix substrate comprising a signal line connected to a switching element, a scanning line connected to the switching element, and a resin material interposed between the signal line and the scanning line. 29. An active matrix substrate comprising: a switching element including a semiconductor layer and a first electrode layer and a second electrode layer arranged through the semiconductor layer; a second wiring connected to the first electrode layer; and a dielectric The switching element and the insulator layer between the first wiring and the second wiring. 30. A method of manufacturing an active matrix substrate, the active matrix substrate is provided with: a switching element that switches between a source and a drain according to a signal supplied to a gate, connected to a scan line of the gate, and connected to The signal line of the source and the pixel electrode connected to the non-polar electrode form the scanning line layer, which is located above the layer forming the scanning line, the layer forming the source electrode, and the layer forming the source electrode. Above the layer forming the above signal line, and -64- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Γ% Read the precautions on the back first and write this page) i. 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 -65- 其中該信號 其中該信號 其中該信號 其中該畫素Printed by the Consumer Goods Agency of the Intellectual Property Agency of the Ministry of Economic Affairs 形成於形成上述源極之層與形成上述信號線之層之間 的絕緣體層，係形成於基板上， 上述掃描線與信號線，係彼此介以上述絕緣體層配 置， 、上述源極上所接續之畫素電極，係與形成上述信號線 之層由同一層所形成；其特徵係在： 上述圖素電極與上述信號線，係由同一層之圖案所形 成者。 31.如申请專利範圍第1 3項之主動矩陣基板 線保護膜係由壓克力樹脂所構成者。 32·如申請專利範圍第1 3項之主動矩陣基板 線保護膜係具有1-3 //m之厚度者。 33·如申請專利範圍第i 3項之主動矩陣基板 線保護膜係上述信號線之氧化膜者。 34·如申請專利範圍第1 9項之主動矩陣基板 一 電極係形成爲介以上述層間絕緣膜與上述信號線重最 者。 且 35.如申請專利範圍第2 2項之平板型畫像感測器，其中該 導電接續材係烊料者。 A如申請專利範圍第2 2項之平板型畫像感測器，其中該 導電接續材係導電接著劑者。 37·如申請專利範圍第2 1項之平板型畫像感測器，其中該 光電變換層係選自包括CdTe、a-Se及CdZnTe之群組 者0 本紙張尺度適用中國國家標準（CNS)A4規格⑽χ 297An insulator layer formed between a layer forming the source and a layer forming the signal line is formed on the substrate, and the scan lines and the signal lines are configured with the insulator layer interposed therebetween. The pixel electrode is formed by the same layer as the layer forming the signal line; its characteristics are: the pixel electrode and the signal line are formed by the same layer pattern. 31. The active matrix substrate according to item 13 of the patent application. The line protective film is made of acrylic resin. 32. For active matrix substrates such as item 13 of the patent application, the line protective film has a thickness of 1-3 // m. 33. If the active matrix substrate of the patent application scope item i 3, the line protective film is the oxide film of the above signal line. 34. The active matrix substrate according to item 19 of the scope of patent application-The electrode system is formed by the weight of the interlayer insulating film and the signal line. And 35. The flat-type image sensor according to item 22 of the patent application scope, wherein the conductive splicing material is a material supplier. A The flat-type image sensor according to item 22 of the patent application scope, wherein the conductive bonding material is a conductive adhesive. 37. The flat-type image sensor according to item 21 of the patent application, wherein the photoelectric conversion layer is selected from the group consisting of CdTe, a-Se, and CdZnTe. Specifications ⑽χ 297