TW579606B

TW579606B - Manufacturing method of low-temperature polysilicon thin film transistor

Info

Publication number: TW579606B
Application number: TW92105006A
Authority: TW
Inventors: Shr-Lung Chen
Original assignee: Au Optronics Corp
Priority date: 2003-03-07
Filing date: 2003-03-07
Publication date: 2004-03-11
Also published as: TW200418188A

Abstract

A manufacturing method of low-temperature polysilicon (LTPS) thin-film transistor liquid crystal display (TFT LCD) is disclosed. Firstly, form the buffer layer, the first metal layer on the substrate sequentially. Then use the first mask to proceed photolithography/etching process onto the first metal layer, so as to define the gate structure. Next, form the insulation layer, semiconductor layer sequentially on the substrate. Proceed ion implantation process onto the semiconductor layer. Next, form the second metal layer on the semiconductor layer. Use the second mask to proceed photolithography/etching process onto the second metal layer and the semiconductor layer, so as to define the active area, source structure and drain structure. Then form a protection layer on the substrate, use the third mask to proceed photolithography/etching process onto the protection layer, so as to expose partial area of the drain structure. Finally, form a transparent electrode layer on the protection layer, and use the fourth mask to proceed photolithography/etching process onto the transparent electrode layer, so as to define the pixel electrode on the surface of the protection layer, and is electrically connected to the drain structure.

Description

579606 五、發明說明（1) 發明所屬技術領域：本發明係關於一種低溫多晶石夕（Low Temperature Poly Silicon，LTPS)薄膜電晶體液晶顯示器，特別是一種低溫多晶硬薄膜電晶體液晶顯示器之製作方法。先前技術：隨著薄膜電晶體（Thin Film Transistor, TFT)製作技術的快速進步，液晶顯示器（Liquid Crystal Display，LCD )由於具有體積小、重量輕、消耗功率低等優點丄而大量的應用於個人數位助理（pDA )、筆記型電月自二=Ϊ貝办色電視、行動電話等各式電子產品中。尤其 rt；iLiir^T^irature p〇iy siiic〇n, ltps) ^ 玻璃基板上不同功能的積體電路（ic)於之，模組接點減少工程上所使用ic的數量，換言還有載體（電子或電洞^ !提昇。此外，此顯示器的特點 si 1 icon )的3〇〇倍、低的移動度為非晶矽（amor phous 小、高品質及完装沾么耗電、鬲壳度、高解析度、輕薄短杲的糸統整合性。請參照第一圖，係— 示器之基本結構。其製’—低溫多晶矽薄膜電晶體液晶顯衝層12與第一金屬層广，=法首先於基板1 0上依序形成緩進行微影|虫刻程序，以f著使用第一道光罩對第一金屬層再於基板1 0上依庠、、又義出薄膜電晶體之閘極結構1 4。、、、、巴緣層1 6及半導體層1 8，接著使用 579606579606 V. Description of the invention (1) Technical field of the invention: The present invention relates to a low temperature polycrystalline silicon (LTPS) thin-film transistor liquid crystal display, particularly a low-temperature polycrystalline hard-film transistor liquid crystal display. Production Method. Prior technology: With the rapid advancement of thin film transistor (TFT) manufacturing technology, liquid crystal displays (LCDs) are widely used in personal applications due to their small size, light weight, and low power consumption. Digital assistants (pDA), notebook computers and other electronic products such as TV, mobile phones and other electronic products. Especially rt; iLiir ^ T ^ irature p〇iy siiic〇n, ltps) ^ Integrated circuit (ic) with different functions on the glass substrate, the module contacts reduce the number of ICs used in engineering, in other words, there is a carrier (Electron or hole ^! Upgrade. In addition, this display features si 1 icon) 300 times lower mobility than amorphous silicon (amor phous is small, high quality and complete power consumption High-resolution, high-resolution, light-thin, short-thickness system integration. Please refer to the first figure, which is the basic structure of the display. Its system '--low temperature polycrystalline silicon thin film transistor liquid crystal display layer 12 and the first metal layer, = Method First, sequentially form a gradual lithography on the substrate 10 and perform the lithography | worming process. Use the first photomask to f to the first metal layer, and then lay a thin film transistor on the substrate 10. Gate structure 1 4. ,,,, edge layer 16 and semiconductor layer 18, then use 579606

第二道光罩以定義薄膜電晶使用第三道光罩定義出光阻層。接著沉積隔絕介電層（ )20 ’並使用第四道光罩對曝露出電晶體之部分汲極區第二金屬層22，填充並覆蓋罩’對第二金屬層22進行蝕極結構。接著沉積保護層24 2 4進行蝕刻程序，以曝露出明導電層於保護層2 4上，接膜電晶體之晝素電極2 6。體之主動區（island)。然後圖案’做為離子植入之阻絕The second photomask defines the thin-film transistor. The third photomask defines the photoresist layer. Next, an insulating dielectric layer (20) is deposited and a fourth photomask is used to partially expose the drain region of the transistor. The second metal layer 22 is filled and covered with the mask 'to perform an electrode structure on the second metal layer 22. Next, a protective layer 24 2 4 is deposited and an etching process is performed to expose the bright conductive layer on the protective layer 24 and the day electrode 26 is coated with a transistor. The active area of the body (island). Then the pattern ’is used as a barrier to ion implantation.

InterLayer Dielectric, ILD 隔絕介電層2〇進行蝕刻程序以域，以定義接觸窗。隨後沉積上述接觸窗，再使用第五道光刻程序，以定義出電晶體之汲 ’並使用弟六道光罩對保護層部分汲極結構。最後，形成透著使用第七道光罩以定義出薄InterLayer Dielectric, ILD The isolation dielectric layer 20 is subjected to an etching process to define the contact window. Subsequently, the above-mentioned contact window is deposited, and then a fifth photolithography process is used to define the drain of the transistor and a sixth photomask is used to partially drain the protective layer. Finally, a transparent mask is used to define the thin

其中上述製程總共使用了七道光罩的手續，每使用一道光罩不僅增加成本，製程參數的調校更是耗費時間，而且每多增加二道手續就是增加可能產生誤差的來源。所以，若能盡量減少光罩的使用數量，對於生產者而言，不僅能同時達曰到樽節成本、縮短製程時間，對於產品的良率 (yield)提昇亦有不少助益。而藉由本發明提供之製^乍方法將町有效減少光罩的使用數量。乂The above-mentioned process uses a total of seven mask procedures. Each mask used not only increases the cost, but the adjustment of the process parameters is time-consuming, and each additional two procedures is a source of possible errors. Therefore, if the number of photomasks used can be reduced as much as possible, for producers, not only can they achieve the cost of bottles and shorten the process time at the same time, but also have a lot of benefits in improving the yield of the product. The method provided by the present invention will effectively reduce the number of photomasks used. Qe

發明内容：晶矽薄膜電晶體本發明之目的為提供一種製作低溫多液晶顯系器的方法。SUMMARY OF THE INVENTION The purpose of the present invention is to provide a method for manufacturing a low-temperature multi-liquid crystal display device.

第6頁Page 6

種減少微影製程程序，即晶顯示器的製造方法。 ^ ，本發明之再一目的為提供一可氣作低溫多晶矽薄膜電晶體液根據本發明之較佳實施例* . . ^ 低溫多晶石夕（LTPS)㈣雷二=供一種在基板上形成的制、生古土、，專膑電日日體液晶顯示器（TFT-LCD ) 上依ί沉積緩衝層、第一金屬層於該基板序，以定義出壤胺蕾光罩對第一金屬層進行微影蝕刻程緣層、非曰矽=:曰曰體之閘極結構。隨後再依序沉積絕 .；(Εΐ; )"Λ ^ ^ ^ t, 體之通道區域使用。非曰曰石夕轉為多晶石夕，以做為電晶塗佈光定義第幕，對石夕層上層上。多晶碎汲極結層進行著濺鍍極層進且電性限於多晶矽層上接著程序，以圖案為罩層於多晶第二金屬金屬層與極結構與罩對保護區域。接對透明電層表面，一光阻圖基板施以 ’並使用接著以第層進行蝕構。沉積微影I虫刻透明電極行微影蝕連接至汲案於多晶離子佈值第二光罩二光阻圖刻程序，保護層於程序，以層於保護刻程序，極結構。並對基板施矽層上。再。然後，沉定義出第二案為餘刻罩以定義出主基板上’並曝露出沒極層上，並使以定義畫素以背面曝光以第一光阻積第二金屬光阻圖案於幕，對第二動區域、源使用第三光結構之部分用第四光罩電極於保護A method for reducing the lithographic process, that is, a crystal display. ^ Another object of the present invention is to provide a liquid crystal liquid which can be used as a low-temperature polycrystalline silicon thin film transistor according to a preferred embodiment of the present invention *.. ^ Low-temperature polycrystalline stone (LTPS) ㈣雷二 = for forming a substrate on a substrate The manufacturing process, the ancient soil, and the solar cell-liquid crystal display (TFT-LCD) are designed to deposit a buffer layer and a first metal layer on the substrate sequence to define the first metal layer Lithographic etching process for edge layer, non-silicon = gate structure of the body. Subsequent deposition of .. (Εΐ;) " Λ ^ ^ ^ t, which is used in the channel area of the body. Fei Yue said that Shi Xi was transformed into polycrystalline Shi Xi, as the crystal coating, the definition of the second act, the upper layer of Shi Xi layer. The polycrystalline crushed drain junction layer is sputtered and the electrode is electrically confined to the polycrystalline silicon layer. Then, a pattern is used as a mask layer on the polycrystalline second metal metal layer and the electrode structure and the mask pair to protect the area. A photoresist substrate is applied to the surface of the transparent electrical layer, and is then etched with a second layer. Deposition lithography I etched transparent electrodes Row lithography Etched to polycrystalline Ion cloth value Second photomask Two photoresist pattern Engraving procedure, protective layer to procedure, layer to protective etching procedure, polar structure. A silicon layer is applied to the substrate. Again. Then, Shen defined the second case as a mask to define the 'on the main substrate' and exposed the electrode layer, and exposed the definition pixels on the back side with a first photoresist and a second metal photoresist pattern on the curtain. For the second moving region and the source, the part using the third light structure is protected by a fourth photomask electrode.

579606 五、發明說明（4) 實施方式：579606 V. Description of the invention (4) Implementation mode:

)薄示為一種在基板上形成低溫多晶石夕（LTPS 2膜電曰曰體液晶顯示器（TFT_L 使本發明之敘述更加詳盡與完備，可失:製:方法。為了述/至第八圖之圖式。有關本發明之詳細說明如下所 5月參照第二圖，根據本發明較 3〇上形成緩衝層（buffer lay二匕1其4百先於基板用破域、z： # ju 上述基板3 0可以使則可、耍埋，Γ 似的透明絕緣材質H緩衝層32 避# t f5物或氮化物等—般的介電材料，其作用1於第:ί質因後續的較高溫製程而擴散出來。接藉著諸如濺鑛法等物理氣相沉積程序Li:屬 /成於基板30之表面。其中，用來構成第屬岸 ΞΪ用：選擇':鈕m、鈦等金屬或合：：光罩對§亥第一金屬層進行微影蝕刻程序，6 ，電晶體之間極結構34。在較佳實施例中彳二光阻材料於第一金屬層上，並使用第一光罩佈行曝光、顯影等程序，以定義出一光阻圖帛，再 2 罩幕，對第一金屬層進行钱刻程序， = 或反應性離子㈣⑴E)的乾則，以定義薄膜H刻之閘極結構34。如同熟悉該項技藝者所知，在定曰曰― 構34的程序中，通常會同時定義基板3()表面的電容^子^) Thin is a kind of low-temperature polycrystalline stone (LTPS 2 film electric liquid crystal display (TFT_L) on the substrate to make the description of the present invention more detailed and complete, and can be lost: manufacturing: method. To describe / to the eighth figure The detailed description of the present invention is as follows. With reference to the second figure in May, according to the present invention, a buffer layer (buffer lay 2) is formed 400 times before the substrate is used to break the area. The substrate 30 can be used, and can be buried, Γ-like transparent insulating material H buffer layer 32 to avoid # t f5 or nitride and other general dielectric materials, its role 1 in the following: high quality due to the subsequent higher temperature It is diffused through the manufacturing process. By the physical vapor deposition process such as splattering method, Li: belongs to / forms on the surface of the substrate 30. Among them, it is used to form a subordinate bank. Use: Select ': button m, titanium or other metals or Closing: lithography of lithography of the first metal layer, §6, interelectrode structure 34. In a preferred embodiment, the second photoresist material is on the first metal layer, and the first The mask is exposed and developed to define a photoresist pattern, and then 2 masks. The metal layer carries out the money engraving procedure, or the principle of the reactive ion ㈣⑴E), to define the gate structure 34 of the thin film H engraving. As is known to those skilled in the art, in the process of defining the structure 34, usually Will also define the capacitance of the substrate 3 () surface ^

第8頁 579606 五、發明說明（5) 極、掃描線結構（皆未顯示於圖中）一般。 30· 凊參照第三圖’於緩衝層32、閘極結構34盘美板 3:表面上沉積絕緣層36。絕緣層 ^ s1〇2) (SlNx) 材料，並藉著低溫化學氣相沉積法（ )專適* 後，沉積半導體層38於絕緣6 來構成。隨準分子雷射回火（ELA)程序，使得为H半導體層38進行晶轉變為多晶矽（poly—Si)的紝，，、用t日日矽的結構結電晶體之通道（channel)區域^用。用以做為後續薄膜請參照第四圖，接著塗佈光阻4〇於丰遙辨猛Q0 對基板30施以背面曝光（back 、體層38上，並定義第-光阻圖案42於半導體声3: JXP〇』UJe )程序’以係以一光源自基板30底部投射二出，^二背面曝光程序擒，使得閘極結構34上方區域的光阻；的阻到自封準（s】f〗· 不又光線的照射，達光區域的光阻則心：i ”果。再經-顯影程序後，受弟先阻圖案42 (如第五圖所示）。^而疋義出 :，以第-光阻圖案42為罩幕（k )者；參照第五 :離子植入。。…lantation)申4離子進硼、鎵等三價的雜質），以P型而g ，選擇如 42 〇雜貝離子。接者即可移除此第—光阻圖案 ^79606Page 8 579606 V. Description of the invention (5) The structure of the pole and the scanning line (neither of which is shown in the figure) is general. 30 · 凊 Referring to the third figure, an insulating layer 36 is deposited on the surface of the buffer layer 32 and the gate structure 34. The insulating layer ^ s102) (SlNx) material, and is adapted by the low temperature chemical vapor deposition method (), and then a semiconductor layer 38 is deposited on the insulating layer 6 to form. Following the excimer laser tempering (ELA) procedure, the H semiconductor layer 38 is converted into polycrystalline silicon (poly-Si), and the channel region of the transistor is junctioned with the silicon structure ^ use. For the subsequent film, please refer to the fourth figure, and then apply a photoresist 40 on Fengyao Q0 to apply back exposure to the substrate 30 (back, on the body layer 38, and define the first photoresist pattern 42 on the semiconductor sound). 3: JXP〇 "UJe) The program 'uses a light source to project two out from the bottom of the substrate 30, and two rear exposure programs make the photoresistance in the area above the gate structure 34; the resistance is to the self-sealing standard (s) f. · Without light exposure, the photoresistance in the area of light reaches the heart: i ”. After the -development process, the first blocking pattern 42 (as shown in the fifth figure). ^ And the meaning is: The first photoresist pattern 42 is for the mask (k); refer to the fifth: ion implantation ... Lantation) apply 4 ions into trivalent impurities such as boron, gallium, etc., choose P type and g, choose 42 as Miscellaneous ions. You can remove this-Photoresist Pattern ^ 79606

请參照第六圖，減接著，使用第二光罩定 4 3上。在本發明的較佳二金屬層43上，接著使得第二光阻圖案44上方域。接著，以此第二光金屬層43與半導體層38 主動區域（island)。 (ashing )的程序，並第二金屬層43露出即停罩幕，對第二金屬層4 3 體之源極結構46與汲極案4 4 〇鑛第二金屬義出第二光實施例中，用 ha 1f ton 對應閘極結阻圖案44為進行餘刻程再如第七圖將動作控制止，接著以進行姓刻程結構48。隨層4 3於半阻圖案4 4 可先塗佈 e光罩或s 構34處，颠刻罩幕序，以定所示，先在去除通第二光阻序，以定後即可移彳瓶增058上。於第二金屬層光阻材料於第 1 i t光罩，使具有一開口區，分別對第二義出電晶體的經去光阻道區域上方的圖案44為蝕刻義出薄膜電晶除第二光阻圖請參 3 0上沉積影蝕刻程分及極結在較佳實構成。接第四光罩極5 2於保透明電極照第八圖保護層5 0 序’以形構4 8表面施例中，著，再於對透明電護層5 0表層的材質签扳ό u上形成，接著使用第三光成接觸孔（contact ，亦即金屬接觸區此處的保護層5 〇可保護層5 0上形成透極層進行微影蝕刻面，且電性連接至可選擇透明導電材保護層5 0。係於基罩對保護層50進行 hole)，並曝露出 (contact area ) 選擇由氮化矽材料明電極層。然後使程序，以定義晝素該沒極結構4 8。其質，如：氧化銦錫Please refer to the sixth figure. Then, use the second mask to fix the 4 3. On the preferred two metal layer 43 of the present invention, a region above the second photoresist pattern 44 is then formed. Then, the second light metal layer 43 and the semiconductor layer 38 are active regions. (ashing) procedure, and the second metal layer 43 is exposed to stop the curtain. The source metal structure 46 of the second metal layer 4 3 and the drain metal 4 4 0 second metal are defined in the second light embodiment. Use ha 1f ton to correspond to the gate junction resistance pattern 44 in order to perform the remaining process, and then control the operation as shown in the seventh figure, and then perform the last process structure 48. With the layer 4 3 on the semi-resistive pattern 4 4, the e-mask or the s-structure 34 may be coated first, and the mask sequence is engraved. As shown in the figure, the second photoresist sequence is removed first, and then it can be moved. The bottle was increased by 058. The photoresist material on the second metal layer and the first photomask are provided with an opening area, and the pattern 44 over the photoresist removal channel area of the second transistor is etched to remove the second transistor. For the photoresist pattern, please refer to the deposition process and electrode structure on 30. Connect the fourth photomask electrode 5 2 to the transparent electrode according to the eighth figure. The protective layer 5 0 is used in the embodiment of the shape 4 8 surface. Then, apply the material on the transparent electrical protective layer 50 surface. Forming, and then using a third photo-forming contact hole (contact, that is, the protective layer 50 of the metal contact area here) can form a transmissive layer on the protective layer 50 for lithographic etching, and is electrically connected to the optional transparent conductive The material protective layer 50 is attached to the base cover to hole the protective layer 50 and exposed (contact area). A bright electrode layer made of a silicon nitride material is selected. Then make a program to define the dipolar structure. Its quality, such as: indium tin oxide

579606 五、發明說明（7) __ (IT〇)或氧化銦鋅（IZ0) 加熱或電子束加熱的真空蒸鲈、i /、f膜方式有乾式的電阻或濕式的無電電鍍法等法來^成。離子化蒸鍍法和濺鍍法如下述’根據本發明之製作方法關於光罩的使用係以定義層進行微影钱刻程序，. 以定義出薄膜電晶先體罩之層及進影#刻程序， ⑺使用第三光罩對保護極=構；露出汲極結構之部分區域；9 〜〜蝕刻程序，以曝 (4)使用第四光罩對透明 — 以定義出畫素電極於保護芦表曰订镟影蝕刻程序，構。 …’且電性連一結利用本發明製作低溫多晶矽薄有相當多的優點。首先，在進行換雜區：器具統的做法是以-道光罩透過微影製程的步驟m，傳進行離子植入；而本發明的做法則是利用背面夕層序’在不須增加-道光罩的手續及成本下，即；= 的效果’更有甚者’透過背面曝光還可達到自：：至丨相同 (self-aiign)的結果，可完全避免使用光 = 的偏移（shift)因而造成關鍵尺寸（Criti /T此發生 _ 第11頁 579606 五、發明說明（8)579606 V. Description of the invention (7) __ (IT〇) or indium zinc oxide (IZ0) heating or electron beam heating vacuum steamed bass, i /, f film method have dry resistance or wet electroless plating method ^ 成. The ionization evaporation method and the sputtering method are as follows. The use of the photomask according to the manufacturing method of the present invention is a lithography process using a defined layer to define a layer and a film of a thin film transistor precursor mask # Use the third photomask to protect the electrode structure; expose a part of the drain structure; 9 ~~ etching procedure to expose (4) use the fourth photomask to be transparent—to define the pixel electrode for protection Lu Biao said that the shadow etching process was designed. ... 'and the electrical connection is quite advantageous in making the low-temperature polycrystalline silicon thin film by using the present invention. First of all, in the process of changing the clutter, the method of the apparatus is to pass-channel photomask through step m of the lithography process to carry out ion implantation; and the method of the invention is to use the back surface sequence 'without adding-channel light Under the procedure and cost of the mask, that is, the effect of "=" is even more. Through the exposure on the back, you can also achieve from :: to the same (self-aiign) result, you can completely avoid using the light = shift. This results in critical dimensions (Criti / T this happens _ page 11 579606 V. Description of the invention (8)

Dimension，CD )的誤差。此外，在本發明中藉著使用第二道光罩’可同時定義出薄膜電晶體的主動區域（island )及源極、汲極結構；相較傳統的做法，得分別使用兩道光罩的手續，根據本發明僅只一道光罩的製程，即可達到相同的結果。綜上所述，相較於傳統上製作低溫多晶石夕薄膜電晶體液晶顯示器的六至七道光罩的製程，縮減為僅需四道光罩即可達到相同的結構，所節省的成本及製程時間可說是相當巨大的。Dimension, CD). In addition, in the present invention, by using a second photomask, the active area (island) and source and drain structures of the thin film transistor can be defined at the same time. Compared with the traditional method, two photomasks have to be used separately. According to the present invention, the same result can be achieved with only one photomask manufacturing process. In summary, compared with the traditional process of manufacturing six to seven photomasks for low-temperature polycrystalline silicon thin-film transistor liquid crystal displays, the cost is reduced and the process is reduced to only four photomasks to achieve the same structure. Time can be said to be quite huge.

發明精ϊϊί以較佳實例闡明如上，然其並非用以限定離本發明體僅止於上述實施例爾。是以，在不請專ϋΐΓ與範圍内所作之修改，均應包含在下述The invention is explained in the above with a better example, but it is not intended to limit the present invention to the above embodiments. Therefore, all modifications made within the scope and scope of this article should be included in the following

579606 圖式簡單說明圖式簡單說明：藉由以下詳細之描述結合所附圖式，將可輕易的了解上述内容及此項發明之諸多優點，其中： ^ 第一圖為利用傳統技術所形成之低溫多晶矽薄膜電晶體液晶顯示器之基板截面圖；第二圖為利用本發明沉積緩衝層且定義出閘極結構之步驟的基板截面圖；第三圖為利用本發明接續沉積絕緣層、半導體層之步驟的基板截面圖；鲁第四圖為利用本發明塗佈光阻於半導體層之步驟的基板截面圖；第五圖為利用本發明以第一光阻圖案為罩幕，定義半導體層摻雜區之步驟的基板截面圖； ·. 第六圖為利用本發明接續沉積第二金屬層且定義出第。二光阻圖案之步驟的基板截面圖； ^ 第七圖為利用本發明定義出源極結構與汲極結構之步驟的基板截面圖；以及第八圖為利用本發明晝素電極於保護層上之步驟的基 _ 板截面圖。圖號對照表： 1 0、3 0 基板 1 2、3 2緩衝層579606 Brief description of the drawings Brief description of the drawings: With the following detailed description combined with the drawings, the above content and the many advantages of this invention can be easily understood, of which: ^ The first picture is formed by using traditional technology A cross-sectional view of a substrate of a low-temperature polycrystalline silicon thin-film liquid crystal display; the second view is a cross-sectional view of a substrate that uses the present invention to deposit a buffer layer and define a gate structure; Cross-sectional view of the substrate in the step; FIG. 4 is a cross-sectional view of the substrate in the step of applying the photoresist to the semiconductor layer by using the present invention; FIG. A cross-sectional view of the substrate in the step of the region; the sixth figure is a second metal layer which is successively deposited using the present invention and defines the first. A cross-sectional view of a substrate in the step of two photoresist patterns; ^ FIG. 7 is a cross-sectional view of the substrate in the step of defining a source structure and a drain structure using the present invention; and FIG. Sectional step of the base plate. Drawing number comparison table: 1 0, 3 0 substrate 1 2, 3 2 buffer layer

第13頁 579606 圖式簡單說明 1 4、3 4 閘極結構 16 18、38 半導體層 20 22、43第二金屬層 24 2 6、5 2 晝素電極 40 42 第一光阻圖案 44 46 源極結構 48 5 0 保護層 52 、3 6 絕緣層隔絕介電層、5 0保護層光阻第二光阻圖案汲極結構晝素電極Page 579606 Brief description of the diagram 1 4, 3 4 Gate structure 16 18, 38 Semiconductor layer 20 22, 43 Second metal layer 24 2 6, 5 2 Daylight electrode 40 42 First photoresist pattern 44 46 Source Structure 48 50 protection layer 52, 3 6 insulation layer insulation dielectric layer, 50 protection layer photoresist second photoresist pattern drain structure day electrode

第14頁Page 14

Claims

579606 六晶步以上申睛專利範圍 —種在基板上形成低溫多晶矽顯示器（TFT-LCD)的製造方法驟：形成一緩衝層於該基板上；形成一第一金屬層於該緩衝層 ^使用一第一光罩對該第一金屬疋義薄膜電晶體之閘極結構；形成一絕緣層於該緩衝層、該 (L X p 〇 \ ，〇 )薄膜電晶體液 Λ方法至少包含下列上运進仃微影蝕刻程序，閘極結構與該基板表面形成通道區域對該形成使用影蝕刻程以及汲極形成使用露出該汲形成使用以定義晝構0 一半使用半導一第一第序，結構一保 -第極結一透一第素電導體層於該絕緣層上做為該薄膜電晶體之體層進行離子佈值程二金屬層於該半導體一光罩對該第二金屬以定義該薄膜電晶體護層於該基板上；二光罩對該保護層進構之部分區域；明電極層於該保護層四光罩對該透明電極極於該保護層表面，序；層上；層與該半導體層進行微之主動區域與源極結構行微影蝕刻程序，以曝上；以及層進行微影蝕刻程序，且電性連接至該汲極結579606 Patent application scope above six crystal steps—A manufacturing method for forming a low temperature polycrystalline silicon display (TFT-LCD) on a substrate: forming a buffer layer on the substrate; forming a first metal layer on the buffer layer; using a The first photomask is a gate structure of the first metal thin film transistor; an insulating layer is formed on the buffer layer, and the (LX p 〇 \, 〇) thin film transistor liquid Λ method includes at least the following operations: Lithography etching procedure, the gate structure and the substrate surface form a channel area for the formation using the shadow etching process and the drain formation using the exposure formation to define the day structure 0 half use semiconductor a first order, structure a guarantee A first electrode junction through a first elementary electrical conductor layer on the insulating layer as the body layer of the thin film transistor to perform an ion distribution process; a two metal layer on the semiconductor; a photomask to the second metal to define the thin film transistor A protective layer is on the substrate; two photomasks cover a part of the protective layer; a bright electrode layer is on the protective layer; the four photomasks are on the transparent electrode; Surface protective layer sequence; layer; layer, the active region is finely of the semiconductor layer and the source structure line lithography process to the exposure; and the layer photolithography etching process, and is electrically connected to the drain junction

579606 六、申請專利範圍 2. 如申請專利範圍第1項之方法，更包含對該半導體層進行準分子雷射回火（ELA )程序，使得該半導體層之非晶矽結構轉為多晶矽結構。 3. 如申請專利範圍第1項之方法，其中上述之離子佈值程序更包含下列步驟：塗佈光阻於該半導體層上，並對該基板施以背面曝光程序，定義一光阻圖案；以該光阻圖案為罩幕’對該基板施以離子佈值；以及移除該光阻圖案。 ® 4. 如申請專利範圍第1項之方法，其中上述之第二光罩係使用half tone光罩與slit光罩其中之一種。 5. 如申請專利範圍第1項之方法，其中在對該第二金屬層. 與該半導體層進行微影蝕刻程序時，更包含一去光阻 · (ashing)的程序。 6 · —種在基板上形成低溫多晶石夕（L T P S )溥膜電晶體液 _ 晶顯示器（TFT-LCD )的製造方法，該方法至少包含下列579606 6. Scope of patent application 2. The method in the first scope of patent application further includes performing an excimer laser tempering (ELA) procedure on the semiconductor layer, so that the amorphous silicon structure of the semiconductor layer is transformed into a polycrystalline silicon structure. 3. The method according to item 1 of the patent application range, wherein the above-mentioned ion distribution procedure further includes the following steps: coating a photoresist on the semiconductor layer, and applying a back exposure procedure to the substrate to define a photoresist pattern; Using the photoresist pattern as a mask to apply an ionic cloth value to the substrate; and removing the photoresist pattern. ® 4. The method according to item 1 of the patent application range, wherein the second photomask is one of a half tone photomask and a split photomask. 5. The method according to item 1 of the patent application scope, wherein when performing a lithographic etching process on the second metal layer and the semiconductor layer, a process for removing photoresist (ashing) is further included. 6 · —A method for forming a low-temperature polycrystalline silicon (L T P S) 溥 film transistor liquid crystal _ TFT-LCD on a substrate, the method includes at least the following

層結屬極金閘一之第體該晶對電並膜 ’薄上義層定 ; 衝以上緩，板該序基於程該層刻於屬# 層金影衝一微緩第一一一第成成行 :形形進 tKax 驟步第16頁 579606 六、申請專利範圍構；上；形成—絕緣層於該緩衝層、該閘極結構與該基板表面形成—半導體層於該絕緣層上，做為薄膜電晶體之逼區域使用；塗佈光阻於該半導體層，並對該基板施以背面曝光程序，定義一第一光阻圖案；以該第一光阻圖案為罩幕，對該基板施以離子佈值；移除該第一光阻圖案；The layering belongs to the first body of the gold gate. The crystal is electrically connected to the thin film. The thin layer is fixed; the sequence is based on the process. The layer is carved in the genus. : Shape into the tKax step on page 16 579606 6. Application for patent scope structure; on; formation-insulation layer is formed on the buffer layer, the gate structure and the substrate surface are formed-semiconductor layer on the insulation layer as a thin film Use the transistor's driving area; apply a photoresist to the semiconductor layer, and apply a back exposure procedure to the substrate to define a first photoresist pattern; use the first photoresist pattern as a mask and apply the substrate Ion cloth value; removing the first photoresist pattern;

，成第二金屬層於該半導體層上，並對該第二金屬 :二。亥半&體層進行第二微影餘刻程序，以定義該薄膜電晶體之主動區域與源極結構以及汲極結構； ^ 形成一保護層於該基板上，並對該保護層進行第三微影蝕刻程序，以曝露出該汲極結構之部分區域；以及、形成一透明電極層於該保護層表面，並對該透明電極層進行第四彳政影蝕刻程序，以定義晝素電極於該保護層表面’且電性連接至該汲極結構；To form a second metal layer on the semiconductor layer, and to the second metal: two. The Haiban & body layer performs a second photolithography process to define the active region, source structure, and drain structure of the thin film transistor; ^ forming a protective layer on the substrate, and performing a third step on the protective layer A lithographic etching process to expose a portion of the drain structure; and, forming a transparent electrode layer on the surface of the protective layer, and performing a fourth etching process on the transparent electrode layer to define a day element electrode on The surface of the protective layer is electrically connected to the drain structure;

^ 其中上述之第二微影蝕刻程序係在形成該第二金屬層後’先塗佈光阻於該第二金屬層上表面，並利用ha i f 光罩與SUt光罩其中一種來定義一第二光阻圖案，使得該第二光阻圖案上方對應該閘極結構處，具有一開口，再經過一餘刻程序，以定義該薄膜電晶體之主動區域與源極結構以及汲極結構。^ Wherein the second lithographic etching procedure is to form a second photoresist on the upper surface of the second metal layer after forming the second metal layer, and use one of a ha if mask and a SUt mask to define a first The two photoresist patterns make an opening above the second photoresist pattern corresponding to the gate structure, and then go through an additional process to define the active region, the source structure, and the drain structure of the thin film transistor.

第17頁 579606 六、申請專利範圍 7·如申請專利範圍第6項之方法，承^人行準分子雷射回火（ELA)程更〜包含詩該半導體層進矽結構轉為多晶矽結構。使件该半導體層之非晶 8.如申請專利範圍第6項之方法，复由— 與該半導體層進行第二微影蝕刻^中±在對該第二金屬層 (ashing)的程序。守’更包含一去光阻 9· 一種在基板上形成低溫多晶Page 17 579606 VI. Scope of Patent Application 7. If the method in the scope of patent application No. 6 is adopted, the excimer laser tempering (ELA) process will also include the conversion of the semiconductor layer's silicon structure into a polycrystalline silicon structure. Make the semiconductor layer amorphous 8. According to the method in the scope of patent application No. 6, repeat the process of performing a second lithographic etching with the semiconductor layer ± in the second metal layer (ashing). Conservation ’also includes a photoresist removal 9 · A kind of low-temperature polycrystalline formed on the substrate

晶顯示器（m—LCD)的製造方法，(TPS =膜：土體液步驟：孩方法至少包含下列形成一緩衝層於該基板上；形成一第一金屬層於該緩衝層上；使，+第光罩對該第一金屬層進行微影餘刻裎庠以定義薄膜電晶體之閘極結構；形成一絕緣層於該缓衝層、該間極結構與該基板表上；形成-非晶石夕層於該絕緣層上，做為該薄膜電晶通道區域使用；A method for manufacturing a crystal display (m-LCD), (TPS = film: soil fluid step): The method includes at least the following forming a buffer layer on the substrate; forming a first metal layer on the buffer layer; A photomask is etched on the first metal layer to define a gate structure of the thin film transistor; an insulating layer is formed on the buffer layer, the interelectrode structure and the surface of the substrate; formation-amorphous stone The evening layer is on the insulating layer and is used as the thin film transistor area;

對該非晶矽層進行準分子雷射回火（Eu)程序，使得該非晶矽層轉為一多晶矽層；塗佈，阻於該多晶矽層上，並對該基板施以背面曝光程序，以定義一第一光阻圖案於該多晶矽層上；以該第一光阻圖案為罩幕，對該基板施以離子佈值；An excimer laser tempering (Eu) procedure is performed on the amorphous silicon layer to make the amorphous silicon layer into a polycrystalline silicon layer; coating, blocking on the polycrystalline silicon layer, and applying a back exposure procedure to the substrate to define A first photoresist pattern on the polycrystalline silicon layer; using the first photoresist pattern as a mask, applying an ion cloth value to the substrate;

579606 六、申請專利範圍移除該第光阻圖案；形使上，其開口；以多晶碎與源極移形使露出該形使以定義構。成一第用一第、金屬層於該多晶矽層上；中兮篦ί罩定義一第二光阻圖案於該第二金屬層中孩第一光阻圖案上方對應該閘極結構處，具有一該第二層進行結構以除該第成一保用一第沒極結成一透用一第晝素電光阻圖案為蝕刻罩幕，對餘刻程序，以定義該心！二金屬層與該及汲極結構；厚膜電晶體之主動區域二光阻圖案；護層於該基板上；二光罩對該保護層進旦/ 構之部分區域； *衫蝕刻程序，以曝明電極層於該保護層四光罩對該读M及極於該保護層而極層進行微影蝕刻程序， 9 ’且電性連接至該汲極結 10·如申請專利範圍第9項之方係使用ha If tone光罩盥以\ 法，其中上述之第二光罩一 1光罩其中之一種。 Π ·如申請專利範圍第9項與該多晶矽層進行蝕刻程栌，法，其中對該第二金屬層的程序。守更包含一去光阻（ashing)579606 6. Scope of patent application: Remove the first photoresist pattern; shape the opening; open the shape with polycrystalline chip and source shift to define the structure. A first and a metal layer are formed on the polycrystalline silicon layer; the mask defines a second photoresist pattern on the second metal layer above the first photoresist pattern corresponding to the gate structure, and has a The second layer is structured to remove the first guarantee, the first electrode, the first electrode, and the first electrode, and then the first photoresist pattern is used as an etching mask. For the remaining processes, define the heart! Two metal layers and the drain structure; two photoresist patterns in the active area of the thick film transistor; a protective layer on the substrate; two photomasks that cover the protective layer / structure area; * shirt etching process to The exposed electrode layer is lithographically etched on the protective layer and the four photomasks of the protective layer and the protective layer and the electrode layer is 9 ′, and is electrically connected to the drain junction. The method is to use the ha If tone mask, which is one of the above-mentioned second mask and 1 mask. Π • If the polysilicon layer is etched with the polycrystalline silicon layer according to item 9 of the application, the procedure of the second metal layer is performed. Mori includes a photoresist (ashing)