TW578272B

TW578272B - Manufacturing method of bottle shaped trench

Info

Publication number: TW578272B
Application number: TW91135852A
Authority: TW
Inventors: Tung-Wang Huang; Shian-Jyh Lin
Original assignee: Nanya Technology Corp
Priority date: 2002-12-11
Filing date: 2002-12-11
Publication date: 2004-03-01
Also published as: TW200410370A

Abstract

This invention provides a manufacturing method of bottle shaped trench, which comprises: firstly, providing a semiconductor substrate with a hardmask layer, which has a trench formed thereon; conformally forming a first liner layer, a second liner layer, a conductive layer and a third liner layer sequentially on the semiconductor substrate and the STI surface, in which the first liner layer and the second liner layer are different; then, filling up a predetermined depth of the trench with a sacrificial layer which is used as an etching hardmask to remove the third liner layer, and removing the sacrificial layer; performing oxidation step to the conductive layer to form an oxide layer which is used as an etching hardmask to sequentially remove the third liner layer, the conductive layer, the second liner layer and the first liner layer to expose the surface of the semiconductor substrate on the bottom of the trench; and using the oxide as a hardmask to etch the semiconductor substrate to form a bottle shaped trench.

Description

578272578272

發明所屬之技術領域本發明係有關於一種溝槽的製造方法，特別係有關於一種動態隨機存取記憶體（Dynamic Rand〇in Access Memory ，DRAM)之溝槽電容用的瓶型深溝槽的形成先前技術 / ° 隨著動態隨機存取記憶體的密度持續地增加，記憶w 元（memojy cell)亦朝向縮小尺寸以提高密度的方向發$展早，而隨著DRAM製程持續縮小，深溝槽之孔徑大小亦隨之限縮。當溝槽之縱寬比（aspect ratio)已超過35 :1時，作為電容儲存區之深溝槽將因此而受限；此外，由於電容曰係與電容電極板之表面積成正比，而溝槽電容之電極== 面積為溝槽之深度與溝槽圓周面積之乘積，溝槽圓周面積則又與溝槽之孔徑有關，換言之，當製程技術從0.2um縮、小至0· 1 8um時，溝槽之孔徑隨之變小，連帶使溝槽電容難以得到足夠之電容表面積以使電容量能夠維持。再者，欲形成具f較小臨界尺寸之深溝槽，便必須選擇高縱寬比= 方式進行钱刻，同時當溝槽臨界尺寸愈小，即命保持垂直輪廓。 . —為了增加因為dram的尺寸縮小而變小的溝槽儲存電容，必需發展增加儲存電容的方法，例如蝕刻半導體基底以擴大溝槽底部而形成瓶型溝槽（bottle shaped trench) 的方法。以傳統製程為例，請參考第1 a- 1 j圖，第1 a- 1 j圖係顯示習知之製造瓶型溝槽之示意圖。TECHNICAL FIELD The present invention relates to a method for manufacturing a trench, and more particularly, to the formation of a bottle-shaped deep trench for a trench capacitor of a dynamic random access memory (DRAM). Prior technology / ° As the density of dynamic random access memory continues to increase, memory cells (memojy cells) are also moving in the direction of reducing size to increase density, and as the DRAM process continues to shrink, the depth of deep trenches The size of the aperture is also reduced accordingly. When the aspect ratio of the trench has exceeded 35: 1, the deep trench as a capacitor storage area will be limited accordingly. In addition, since the capacitance is proportional to the surface area of the capacitor electrode plate, the trench capacitance The electrode == area is the product of the depth of the trench and the circumferential area of the trench, and the circumferential area of the trench is related to the aperture of the trench. In other words, when the process technology shrinks from 0.2um to as small as 0.8 μm, the trench The hole diameter of the trench becomes smaller accordingly, and it is difficult for the trench capacitor to obtain a sufficient surface area to maintain the capacitance. Furthermore, in order to form a deep trench with a smaller critical dimension of f, it is necessary to choose a method of high aspect ratio = to carry out money engraving, and at the same time, as the critical dimension of the trench is smaller, the vertical contour is maintained. -In order to increase the trench storage capacitance which is reduced due to the shrinking of the size of the dram, it is necessary to develop a method for increasing the storage capacitance, such as a method of etching a semiconductor substrate to enlarge the bottom of the trench to form a bottle shaped trench. Taking the traditional manufacturing process as an example, please refer to Figures 1a-1j. Figures 1a-1j are schematic diagrams showing the conventional manufacturing of bottle grooves.

578272 五、發明說明（2) 首先，提供一半導體基底101，於半導體基底101上依，形成有一墊層102、一硬罩幕層103及一具有開口之圖案化光阻層（未顯示），以圖案化光阻層為罩幕，蝕刻硬罩幕曰1 0 3以在硬罩幕層1 〇 3上形成一開口，接著餘刻墊層 1〇2及半導體基底101以形成溝槽1〇4。其中，半導體基底 1 〇 1例如是矽基底；墊層1 〇 2之材質例如是氮化層；硬罩幕層1〇3之材質例如是硼矽玻璃絕緣層或是氮化層與硼矽玻璃之組合，可使溝槽之品質較佳，深度等條件亦較容易控制；，半導體基底101與墊層102間更可形成一薄氧化層，可使半導體基底1 〇 1與塾層1 〇 2間之附著性更佳。請參考第lb圖，接著，在溝槽1〇4中露出表面之半導，基底101表面上順應性形成一第一襯層，第一襯層例如 ^在攝氏690至710度之溫度下，對半導體基底1〇1進行熱氧化作用之氧化層105，其厚度約為25至35 A ;並且，於半導體基底1 0 1及氧化層1 0 5的表面上順應性形成一第二櫬層第一襯層例如是在攝氏700至720度之溫度下所形成之氮化層106，其厚度約為45至55 A ;然後，在攝氏49()至 5 1 0、度之溫度下，於氮化層丨〇 6之表面上順應性形成一厚度約為75至85 A之導電層107，導電層1〇7例如是多晶矽層或蟲晶碎層。一請參考第lc圖，在導電層1〇7的表面上順應性形成一第三襯層，第三襯層例如是氧化層1 08。然後，在氧化層 =8上形成一犧牲層（未顯示），並以硫酸與雙氧水的混合溶液（SPM)作為蝕刻液來進行濕蝕刻去除部份之犧牲層至第6頁 0548-8874twf(Nl) ； 91110 ； Clairc.ptd 五、發明說明（3) 留下溝槽104底部之犧牲層，溝槽1〇4底部之光阻層109，光阻層1〇9的厚度可根據f θ 1 钱刻的時間越長則光阻層1G9的厚度越薄行疋進丁/ =間越短則光阻層109的厚度越厚，如第ld圖所丁的中，光阻層2 0 9亦可以旋塗玻璃層來取代。八睛參考第le圖，接著，以光阻層1〇9為飿層1〇1遮盍之氧化層1〇8 ’以留下溝槽104底部二匕^ 後，同、樣以硫酸與雙氧水的混合溶液乍為蝕刻液來進行濕蝕刻，將光阻層1 〇 9完全去陝。請參考第If圖，在攝W 〇〇〇至1100度之溫度下，二露出表面之導電層1 07之表面上順應性形成一氮化層丨丨〇。因為形成氮化層110時之溫度相當高，因此會導致構成導電層107之夕日日石夕層或蠢晶石夕層晶格化，而在導電声IQ?上形成空隙。曰請參考第lg圖，接著，以氮化層11()為蝕刻罩幕，依序去除位於溝槽1〇7底部未被氮化層11〇覆蓋之氧化層i〇8a 及導電層107，而留下導電層i〇7a。。月參考第1 h圖’以構酸（Hs Ρ Ο* )作為钱刻液體，對氮化層1 1 〇進行濕蝕刻，同時，位於溝槽丨〇4底部之露出表面之氮化層1 0 6亦會被去除。請參考第1 i圖，以緩衝氫氟酸（BHF)為蝕刻液，以導電層107a及其下方之氮化層i〇6a為蝕刻罩幕，對溝槽1〇4 底部之露出表面之氧化層1 〇 5進行濕蝕刻，以留下氧化層 10 5a ’同時會露出溝槽104底部之半導體基底1〇ι的表面；578272 V. Description of the invention (2) First, a semiconductor substrate 101 is provided. On the semiconductor substrate 101, a pad layer 102, a hard cover curtain layer 103, and a patterned photoresist layer (not shown) having openings are formed. The patterned photoresist layer is used as a mask, and the hard mask is etched to form an opening in the hard mask layer 103, and then the pad layer 102 and the semiconductor substrate 101 are etched to form a trench 10. 4. Among them, the semiconductor substrate 101 is, for example, a silicon substrate; the material of the cushion layer 10 is, for example, a nitride layer; and the material of the hard cover curtain layer 103 is, for example, a borosilicate glass insulation layer or a nitride layer and borosilicate glass. The combination can make the quality of the trench better and the conditions such as depth easier to control; a thin oxide layer can be formed between the semiconductor substrate 101 and the pad layer 102, which can make the semiconductor substrate 1 〇1 and the hafnium layer 1 〇2 Better adhesion. Please refer to FIG. Lb. Next, the surface of the semiconductor is exposed in the groove 104, and a first liner is conformably formed on the surface of the substrate 101. The oxide layer 105 that thermally oxidizes the semiconductor substrate 101 has a thickness of about 25 to 35 A; and conforms to form a second silicon oxide layer on the surfaces of the semiconductor substrate 101 and the oxide layer 105. A liner layer is, for example, a nitrided layer 106 formed at a temperature of 700 to 720 degrees Celsius, and has a thickness of about 45 to 55 A; then, at a temperature of 49 () to 5 10 degrees Celsius, under nitrogen, A conductive layer 107 having a thickness of about 75 to 85 A is compliantly formed on the surface of the chemical layer 〇6. The conductive layer 107 is, for example, a polycrystalline silicon layer or a worm-like fragment. First, referring to FIG. 1c, a third liner layer is conformably formed on the surface of the conductive layer 107, and the third liner layer is, for example, an oxide layer 108. Then, a sacrificial layer (not shown) is formed on the oxide layer = 8, and a mixed solution (SPM) of sulfuric acid and hydrogen peroxide is used as an etching solution to perform wet etching to remove the sacrificial layer. ); 91110; Clairc.ptd V. Description of the invention (3) Leave the sacrificial layer at the bottom of the trench 104, the photoresist layer 109 at the bottom of the trench 104, and the thickness of the photoresist layer 109 can be engraved according to fθ 1 money The longer the time is, the thinner the photoresist layer 1G9 is. The shorter the interval is, the thicker the photoresist layer 109 is. The shorter the photoresist layer 109 is, the higher the photoresist layer 109 can be. Replace with glass. Eight eyes refer to the first figure, and then, the photoresist layer 109 is used as the sacrificial layer 101 to mask the oxide layer 108 ′ to leave the bottom of the trench 104. After that, the same method is used for sulfuric acid and hydrogen peroxide. At first, the mixed solution is an etching solution to perform wet etching, and the photoresist layer 109 is completely removed. Please refer to the If diagram. At a temperature of 5000 to 1100 degrees, a nitride layer is formed on the surface of the conductive layer 107 on the exposed surface. Since the temperature at which the nitrided layer 110 is formed is quite high, it leads to the lattice formation of the conductive layer 107 or the stupid stone layer, and voids are formed in the conductive acoustic IQ ?. Please refer to FIG. 1g, and then use the nitride layer 11 () as an etching mask to sequentially remove the oxide layer 108 and the conductive layer 107 which are not covered by the nitride layer 11 at the bottom of the trench 107. The conductive layer i07a remains. . Referring to Figure 1h, using the acid (Hs P 0 *) as the etching liquid, the nitride layer 1 1 0 is wet-etched, and at the same time, the nitride layer 10 on the exposed surface at the bottom of the trench 1 0 6 will also be removed. Please refer to Figure 1i, using buffered hydrofluoric acid (BHF) as the etching solution, and using the conductive layer 107a and the nitride layer i6a below as the etching mask to oxidize the exposed surface at the bottom of the trench 104 The layer 105 is wet-etched to leave an oxide layer 105a, and at the same time, the surface of the semiconductor substrate 10m at the bottom of the trench 104 is exposed;

0548-8874twf(Nl) ； 91110 ； Claire.ptd 第7頁 578272 五、發明說明（4) 然後，以氫氧化銨（NH4 0H )作為蝕刻液，並以導電層1 〇 7a 為罩幕’對溝槽104底部露出表面之半導體基底1〇1進行濕蝕刻，以形成一瓶型溝槽丨丨工。上述之傳統製程的問題在於，進行如第1 f圖所示之氮化層11 0時，高溫會導致構成導電層丨〇 7之多晶矽層或磊晶石夕層晶格化而形成空隙，當在利用氫氧化銨（NH4〇h)作為 #刻液來對溝槽1 〇4底部露出表面之半導體基底丨〇1進行濕 #刻以形成瓶型溝槽1 1 1時，餘刻液會藉由空隙侵姓半導體基底101而產生缺口 112，導致半導體基底1〇1之品質下降’如第1 j圖所示。發明内容 ,有鑑於此，本發明之目的在於提供一種在半導體基底製造瓿型溝槽的方法，可利用將溝槽上部之導電層氧化的方法來保護半導體基底之結構不會在形成槪型溝槽的過程中產生損壞。根據上述目的，本發明提供一種瓶型溝槽的製造方二列步驟：提供一半導體基底，半導體基底上具广β、# &層，且半導體基底上形成有—溝槽；於半導體底及溝槽之表面上依序順應性形成一第一襯層、一第二0548-8874twf (Nl); 91110; Claire.ptd Page 7 578272 V. Description of the invention (4) Then, ammonium hydroxide (NH4 0H) is used as the etching solution, and the conductive layer 107a is used as a mask to face the trench. The semiconductor substrate 101 at the bottom surface of the trench 104 is wet-etched to form a bottle-shaped trench. The problem with the conventional process described above is that when the nitrided layer 110 is performed as shown in Figure 1f, the high temperature will cause the polycrystalline silicon layer or epitaxial layer that constitutes the conductive layer to be latticed to form voids. When ammonium hydroxide (NH4〇h) is used as the #etching solution to wet-etch the semiconductor substrate at the bottom of the groove 104, the surface is exposed to form a bottle-shaped groove 1 1 1. The gap 112 invades the semiconductor substrate 101 and generates a notch 112, which causes the quality of the semiconductor substrate 101 to decrease, as shown in FIG. 1j. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a method for manufacturing a pit-shaped trench on a semiconductor substrate. The method of oxidizing the conductive layer on the top of the trench can be used to protect the structure of the semiconductor substrate from forming a trench. Damage occurred during the groove. According to the above object, the present invention provides a two-step manufacturing method of a bottle-shaped trench: providing a semiconductor substrate having a wide β, # & layer on the semiconductor substrate, and a trench formed on the semiconductor substrate; A first lining layer, a second

層於：：：？及於一第三襯層’第一襯層與第二襯層相罩真入一既定深度之犧牲層；以犧牲層為姓對^表面之導電層進行氧化步驟以形成化層為餘刻罩幕，依序去除未被氧化層覆蓋之第丄襯層Layer on :::? And a third liner 'the first liner and the second liner cover the sacrificial layer of a predetermined depth; using the sacrificial layer as a surname to perform an oxidation step on the surface conductive layer to form a chemical layer as a mask Curtain, sequentially remove the third liner that is not covered by the oxide layer

578272 發明說明（5) _ 底：：襯f及第-襯層1露出位於溝槽底部之半及以氧化層…，㈣半導體基底以形根據上述目的，太名么日日田# 法，包括下列步驟：提；一月=:種瓶型溝槽的製造方序形成有-墊層、一硬罩幕=體ί;化基= 基底，以在半導體基底：：：=、；=層…^ 層；於半導體基底及第一；形成-第-襯第二襯層及一導電層1 一；士依序順應性形成- 層表面上順應性形成一第三襯；？表犧牲層’且犧牲層填滿溝ί 上: 在溝槽底邛留下一既定深度之犧牲声；曰幕，去除未被犧牲層覆蓋之第三襯^ 〔厂蝕刻罩表面；將犧牲層去除；胃露出表面‘導；層之化層覆盍之第三襯層、導電層、第- 、衣破虱【出位於溝槽底部之半導體基底表；覃以幕，姓刻半導體基底以形成一瓶型溝槽。曰為罩根據上述目的，本發明更提供一 ^ 法，包括下列步驟：提供一半導體η ί槽的製造方序形成有一第一氮化層、一及上依 ;以圖案化光阻層為蝕刻罩$ ’依序蝕刻第一氮化^且層578272 Description of the invention (5) _ Bottom: The lining f and the first lining layer 1 are exposed at the bottom half of the trench and exposed with an oxide layer ..., the semiconductor substrate is shaped according to the above purpose, the Taiming Modi Hita # method includes the following Steps: mention; January =: The manufacturing sequence of the bottle-shaped groove is formed with-a cushion layer, a hard mask = body ί; chemical base = substrate, to the semiconductor substrate :: = ,; = layer ... ^ Layer; on the semiconductor substrate and the first; forming-the first-lining second lining layer and a conductive layer 1-a; sequential compliance formation-forming a third lining on the surface compliance; The surface sacrificial layer 'and the sacrificial layer fill the trench. On the bottom of the trench, a sacrificial sound of a predetermined depth is left; the curtain is removed, and the third liner that is not covered by the sacrificial layer is removed. Removed; the exposed surface of the stomach is guided; the third layer of the chemical layer is covered with the third conductive layer, the conductive layer, the first, and the second one, the semiconductor substrate at the bottom of the trench; Qin Yimu, the semiconductor substrate is engraved to form Bottle-shaped groove. According to the above purpose, the present invention further provides a method including the following steps: providing a manufacturing sequence of a semiconductor η groove, forming a first nitride layer, a top layer, and using a patterned photoresist layer as etching Mask $ 'sequentially etch the first nitride layer

578272 五、發明說明（6) 矽玻璃層及並去除圖案半導體基底，以在化光阻層；於溝槽應性形成一第一氧化層；於半半導體基底露出之半導導體基底及表面上依序三氮化層；光阻層填滿深度之光阻蓋之第三氮去除；氧化以第二氧化化層覆蓋之化層，以露氧化層為罩槽0 順應性形成於半導體基溝槽；蝕刻層；以光阻化層以露出該多晶層以層為蝕刻罩第三氮化層出位於溝槽幕，對半導上形成一溝槽，體基底表面上川貝該第一氧化層之弟一氣化層、一多晶碎層及一第成一光阻層，且底表面光阻層層為钱部分多使該多幕，依、多晶底部之體基底上順應性形，以在溝槽刻罩幕，去晶石夕層之表面，將晶矽層形成序去除溝槽底部留下除未被既定光阻層覆該光阻層第二氧化層；矽層、第二半導體基底進行濕蝕刻底部未被第二氧氮化層及第一氧表面；及以第二以形成一瓶型溝猫旦ί使本發明之上述和其他目的、特徵、和優點能更明 ”、、，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：實施方法：第2a-2i圖係顯示本發明之製造瓶請參考第2a-2i圖型溝槽之示意圖。请參考第2a圖，首矣 Α L ^百先，提供一半導體基底201，於半導體基底201上依序形忐士〇 « ^ „ 成有一墊層202、一硬罩幕層203及一具有開口之圖案化光阪罢莖 u ^ ^ 〜1且層（未顯示），以圖案化光阻層為578272 V. Description of the invention (6) Silicon glass layer and pattern semiconductor substrate are removed to form a photoresist layer; a first oxide layer should be formed in the trench; and a semiconducting substrate and surface exposed on the semi-semiconductor substrate Sequential trinitride layer; the photoresist layer fills the depth of the third photoresist cap with the third nitrogen removed; oxidizes the chemical layer covered with the second oxide layer, and exposes the exposed oxide layer as the cover groove. 0 Compliance is formed in the semiconductor base trench Groove; etching layer; photoresistive layer to expose the polycrystalline layer; layer as an etch mask; third nitride layer; located on the trench curtain; a groove is formed on the semiconductor; The layer's brother is a gasification layer, a polycrystalline fragment layer, and a photoresist layer, and the bottom surface photoresist layer is made of money to make the multi-screen, conforming to the conformal shape of the body substrate at the bottom of the polycrystal. The trench is engraved with a mask to remove the surface of the spar layer, and the crystalline silicon layer is formed in order to remove the bottom of the trench, leaving a second oxide layer on the photoresist layer that has not been covered by a predetermined photoresist layer; a silicon layer and a second semiconductor substrate Wet etched bottom not second The nitrided layer and the first oxygen surface; and the second to form a bottle-shaped trench cat to make the above and other objects, features, and advantages of the present invention clearer. ",,, a preferred embodiment is given below. With the accompanying drawings, the detailed description is as follows: Implementation method: Figures 2a-2i show the manufacturing bottle of the present invention. Please refer to the schematic diagram of the grooves of Figure 2a-2i. Please refer to Figure 2a, first L ^ Baixian provided a semiconductor substrate 201 on which the substrates were sequentially formed. «^« Formed with a cushion layer 202, a hard cover curtain layer 203, and a patterned light-emitting stem with openings ^ ^ ~ 1 and layer (not shown), with patterned photoresist layer as

罩幕，蝕刻硬覃暮層？nQ 更皁拳層203 ’以在硬罩幕層2〇3上形成一開Mask, etch hard Tan Mu layer? nQ Gengzao Boxing Layer 203 ′ to form an opening on the hard cover curtain 203

第10頁 578272Page 10 578272

口，接著蝕刻墊層20 2及半導體基底2〇1以形成溝槽2〇4。半導體基底2 0 1例如是矽基底；墊層2 〇 2之材質例如，，化層，硬罩幕層2 〇 3之材質例如是硼矽玻璃絕緣層或 f氮化層與哪矽玻璃之組合，可使溝槽之品質較佳，深度專條件亦較谷易控制，·半導體基底2 0 1與墊層2 0 2間更可形成一薄氧化層，可使半導體基底2〇1與墊層2〇2間之附著性更佳。 5月參考第2b圖，接著，在溝槽204中露出表面之半導體基底201表面上順應性形成一第一襯層，第一襯層例如是在攝氏650至750度之溫度下，對半導體基底2〇1進行熱氧化作用之氧化層205，其厚度約為25至35A ;並且，於半導體基底2 0 1及氧化層2 0 5的表面上順應性形成一第二襯層’第二襯層例如是在攝氏7〇〇至720度之溫度下所形成之氮化層206，其厚度約為45至55A ;然後，在攝氏4 90至 51 〇度之溫度下，於氮化層2 〇 6之表面上順應性形成一厚度約為75至85A之導電層207，導電層207例如是多晶矽層或蠢晶矽層。其中，第一襯層與第二襯層之材質必須相異，以利後續製程之進行。接下來，進行本發明之一特徵步驟。請參考第2c圖，在導電層207的表面上順應性形成一第三襯層，第三襯層例如是在攝氏70 0至720度之溫度下所形成之厚度約為35至45 A之氮化層208。然後，在氮化層208上形成一犧牲層（未顯示），並以硫酸與雙氧水的混合溶液（SPM)作為蝕刻液來進行濕蝕刻Then, the pad layer 202 and the semiconductor substrate 201 are etched to form a trench 204. The semiconductor substrate 2 01 is, for example, a silicon substrate; the material of the cushion layer 2 2 is, for example, a chemical layer, and the hard cover layer 2 3 is a material such as a borosilicate glass insulating layer or a f-nitride layer and a combination of silicon glass It can make the quality of the trench better, and the depth specific conditions are easier to control than the valley. · A thin oxide layer can be formed between the semiconductor substrate 201 and the pad layer 202, which can make the semiconductor substrate 201 and the pad layer Better adhesion between 002. Referring to FIG. 2B in May, a first liner layer is conformably formed on the surface of the semiconductor substrate 201 whose surface is exposed in the trench 204. The first liner layer is, for example, a semiconductor substrate at a temperature of 650 to 750 degrees Celsius. The oxide layer 205 undergoing thermal oxidation has a thickness of about 25 to 35 A; and a second liner layer is formed on the surface of the semiconductor substrate 201 and the oxide layer 205 to conform to the second liner layer. For example, the nitrided layer 206 formed at a temperature of 700 to 720 degrees Celsius has a thickness of about 45 to 55 A; then, at a temperature of 4 90 to 5100 degrees Celsius, the nitrided layer 206 is formed. A conductive layer 207 having a thickness of about 75 to 85 A is compliantly formed on the surface. The conductive layer 207 is, for example, a polycrystalline silicon layer or a staggered silicon layer. Among them, the materials of the first lining layer and the second lining layer must be different to facilitate the subsequent processes. Next, a characteristic step of the present invention is performed. Referring to FIG. 2c, a third liner is conformably formed on the surface of the conductive layer 207. The third liner is, for example, a nitrogen layer having a thickness of about 35 to 45 A at a temperature of 70 to 720 degrees Celsius.化层 208. The layer 208. Then, a sacrificial layer (not shown) is formed on the nitride layer 208, and wet etching is performed using a mixed solution of sulfuric acid and hydrogen peroxide (SPM) as an etching solution.

0548-8874twf(Nl); 91110 ； Claire.ptd 第11頁 578272 五、發明說明（8) 部份之犧牲層至留下溝槽2〇4底部之犧牲層，溝槽2〇4 =邛之犧牲層例如是光阻層209，光阻層20 9的厚度可根據需^來決定，進行濕蝕刻的時間越長則光阻層2〇9的厚度越溥，進行濕蝕刻的時間越短則光阻層2 〇 9的厚度越厚^ ^第2d圖所示。其中，光阻層2〇9亦可以旋塗玻璃層：取代。、凊參考第2e圖，接著，以緩衝氫氟酸（BHF)作為蝕刻液並以光阻層2〇9為蝕刻罩幕，去除未被光阻層2〇9遮蓋之氮化層208，以留下溝槽204底部之氮化層2〇8& ;狹後，同樣以硫酸與雙氧水的混合溶液（s p M)作為蝕刻液來進行濕敍刻，將光阻層2 〇 9完全去除。接下來，進行本發明之另一特徵步驟。請參考第2f圖，以氮化層208&為罩幕， 91〇度之溫度下，對露出表面之導電層2〇7進行氧=作用，以使導電層207形成一厚度約為145至155人之氧化層以^。請參考第2g圖’以氧化層21〇為蝕刻罩幕，在二氏16〇至170友度的溫度下，以麟酸（H3p〇4)作為敍刻液，對露出表面之氮化層208a進行濕敍刻，以完全去除氮化層2〇8a。接著，以氫氧化銨（NH4〇H)作為蝕刻液，對露出表面之導電層207進行濕㈣’以去除未被氧化層⑽覆蓋之導電層而留下導電層2G7a。錢，在攝氏16()至17()度的溫度下以碗酸（Η3Ρ04)作為餘刻液，對露出表面之氮化蝕刻，以留下氮化層2〇6a。 …、請參考第2h圖’以緩衝氫氟酸⑽F)為蝕刻液，以氧第12頁 0548-8874twf(Nl) ί 91110 » Claire.ptd 578272 五、發明說明（9) =層了為餘刻罩幕，對露出表面之氧化層2〇5進娜體美底2(1 H化層2〇5& ’同時會露出溝槽204底部之半導 if: MO 因為氧化層210下方形成有氮化層2〇6a J二匕層210之厚度較氧化層2〇5之厚度要來的厚，因此化層2〇5的過程中’氧化層210及氮化層，可保產溝槽2 0 4之側壁不會損壞。 :參，第21圖’然後，以氫氧化銨(NH4QH)作為餘刻美二:化層210為罩幕，對溝槽204底部露出表面之半導體基底2G1進行濕#刻’以形成—瓶型溝槽川。开4 ί Ϊ Γ所Ϊ供的方法’主要是讓導電層進行氧化作用 :卞化層’來徹底防止構成導電層之多晶石夕層或蠢晶石夕 = 境下晶格化’所以不會有蝕刻液經由空隙來 ::ί ί底的情況發生，保持半導體基底之完整性，進而知：咼產品之可靠度。 W 一 ί、、;、本發明已以較佳實施例揭露如上，然其並非用以發明：任何熟習此技藝者，在不脫離本發明之精神 ^内，§可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。0548-8874twf (Nl); 91110; Claire.ptd Page 11 578272 V. Description of the invention (8) part of the sacrificial layer to the sacrificial layer leaving the bottom of the trench 204, trench 204 = sacrificial layer of 邛For example, the photoresist layer 209, the thickness of the photoresist layer 209 can be determined according to requirements. The longer the wet etching time is, the thicker the photoresist layer 209 is, and the shorter the wet etching time is, the photoresist is. The thicker the thickness of the layer 209 is shown in Figure 2d. Among them, the photoresist layer 209 can also be spin-coated with a glass layer: instead. Refer to Figure 2e, and then use buffered hydrofluoric acid (BHF) as the etching solution and the photoresist layer 209 as the etching mask to remove the nitride layer 208 that is not covered by the photoresist layer 209. After the nitride layer 208 at the bottom of the trench 204 is left narrow, wet engraving is also performed using a mixed solution (sp M) of sulfuric acid and hydrogen peroxide as an etching solution, and the photoresist layer 009 is completely removed. Next, another characteristic step of the present invention is performed. Please refer to FIG. 2f. With the nitrided layer 208 & as a mask, the conductive layer 207 exposed at the surface is subjected to oxygen action at a temperature of 91 ° C, so that the conductive layer 207 forms a thickness of about 145 to 155. The human oxide layer is ^. Please refer to Fig. 2g, with the oxide layer 21 as the etching mask, at a temperature of 160 to 170 degrees Celsius, and using linoleic acid (H3p〇4) as the etch liquid, the nitrided layer 208a on the exposed surface A wet engraving is performed to completely remove the nitride layer 208a. Next, using the ammonium hydroxide (NH4OH) as an etching solution, the conductive layer 207 exposed on the surface is wet-etched 'to remove the conductive layer not covered by the oxide layer and leave the conductive layer 2G7a. Qian, using a bowl of acid (Η3Ρ04) as a post-etching solution at a temperature of 16 () to 17 () degrees Celsius, etched the exposed surface by nitriding to leave a nitrided layer 206a. …, Please refer to Figure 2h 'Using buffered hydrofluoric acid (F) as the etching solution and oxygen Page 12 0548-8874twf (Nl) ί 91110 »Claire.ptd 578272 5. Description of the invention (9) = layer is for the time left The mask, the exposed surface of the oxide layer 205 into the body beautiful bottom 2 (1 Hization layer 205 & 'At the same time, the semiconductor at the bottom of the trench 204 will be exposed if: MO because nitride formed under the oxide layer 210 The thickness of the layer 206a and the second layer 210 is thicker than the thickness of the oxide layer 205. Therefore, in the process of forming the layer 205, the oxidized layer 210 and the nitrided layer can guarantee the production of the trench 2 0 4 The side walls will not be damaged .: See, Figure 21 'Then, use ammonium hydroxide (NH4QH) as a finish. Second: The chemical layer 210 is used as a mask, and the semiconductor substrate 2G1 exposed at the bottom of the trench 204 is wet-etched. 'To form-bottle-shaped trenches. The method provided by Kai 4 ί Ϊ Γ' is mainly to allow the conductive layer to oxidize: tritium layer 'to completely prevent the polycrystalline stone layer or stupid stone that constitutes the conductive layer. Xi = Lattice in the environment 'so no etching solution will come through the gap :: ί the bottom will happen, maintaining the integrity of the semiconductor substrate, and then knowing: The reliability of the invention W. The invention has been disclosed above in a preferred embodiment, but it is not intended to invent: Any person skilled in the art can make changes and modifications without departing from the spirit of the invention ^. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.

578272 圖式簡單說明第1 a- 1 j圖係顯示習知之製造瓶型溝槽之示意圖。第2a-2i圖係顯示本發明之製造瓶型溝槽之示意圖。符號說明： 101、 201〜半導體基底； 102、 20 2〜墊層； 1 0 3、2 0 3〜硬罩幕層； 1 0 4、2 0 4〜溝槽； 105、 105a、205、205a〜氧化層； 106、 106a、20 6、20 6a〜氮化層； 107、 107a、20 7、20 7a〜導電層； 108、 108a〜氧化層； 109、 209〜光阻層； 11 0〜氮化層； 111、2 11〜瓶型溝槽； 11 2〜缺口； 208、208a〜氮化層； 2 1 0〜氧化層。578272 Brief description of the drawings Figures 1 a to 1 j are schematic diagrams showing the conventional manufacturing of bottle grooves. Figures 2a-2i are schematic views showing the manufacturing of a bottle groove according to the present invention. Explanation of symbols: 101, 201 ~ semiconductor substrate; 102, 20 2 ~ underlayer; 1 0 3, 2 0 3 ~ hard cover curtain layer; 104, 2 0 4 ~ groove; 105, 105a, 205, 205a ~ Oxidation layer; 106, 106a, 20 6, 20 6a ~ nitride layer; 107, 107a, 20 7, 20 7a ~ conductive layer; 108, 108a ~ oxide layer; 109, 209 ~ photoresist layer; 11 0 ~ nitride 111, 2 11 ~ bottle-shaped groove; 11 2 ~ notch; 208, 208a ~ nitride layer; 2 1 0 ~ oxide layer.

0548-8874twf(Nl) ； 91110 ； Claire.ptd 第14頁0548-8874twf (Nl); 91110; Claire.ptd page 14

Claims

578272 六、申請專利範圍 1 · 一種提供一層，且該半於該半第一襯層、一襯層與該於該溝以該犧第三襯層，對露出層；以該氧之該第三襯露出位於該以該氧溝槽。 2. 如申，其中該硬層。 3. 如申，其中該第 4 ·如申，其中該第 5·如申瓶型溝槽的製造方法，包括下列步驟·· 半導體基底，該半導體基底上具有一硬罩幕導體基底上形成有一溝槽；導體基底及該溝槽之表面上依序順應性形成一一第二襯層、一導電層及於一第三襯層，該第第二襯層相異；槽底部填入一既定深度之犧牲層；牲層為钱刻罩幕，去除未被該犧牲層覆蓋之該並去除該犧牲層；表面之該導電層進行氧化步驟以形成一氧化化層為餘刻罩幕，依序去除未被該氧化層覆蓋層、該導電層、該第二襯層及該第一襯層，以溝槽底部之該半導體基底表面；及化層為罩幕，蝕刻該半導體基底以形成一瓶型請專利範圍第1項所述之瓶型溝槽的製造方法罩幕層為氮化矽層或氮化矽/珊矽玻璃組合 "青專利範圍第1項所述之瓶型溝槽的製造方法 :概層之厚度為25至35 A。請專利範圍第1項所述之瓶型溝槽的製造方法二襯層為氧化層。請專利範圍第1項所述之瓶型溝槽的製造方法578272 VI. Scope of patent application1. A layer is provided, and the half of the first liner, a liner and the trench are sacrificed to the third liner, and the exposed layer is the third layer of the oxygen. The liner is exposed at the oxygen trench. 2. If applied, the hard layer. 3. Ruoshen, where the 4th Rushen, wherein the 5th Rushen bottle-shaped trench manufacturing method, includes the following steps: a semiconductor substrate having a hard cover conductor substrate formed on the semiconductor substrate A trench; a conductor substrate and a surface of the trench are sequentially compliantly formed with a second liner, a conductive layer, and a third liner, the second liner is different; the bottom of the trench is filled with a predetermined The sacrificial layer of depth; the animal layer is a mask of money, remove the one that is not covered by the sacrificial layer and remove the sacrificial layer; the conductive layer on the surface is subjected to an oxidation step to form an oxide layer as a mask of remaining etching, in order Removing the cover layer that is not the oxide layer, the conductive layer, the second liner layer, and the first liner layer, using the surface of the semiconductor substrate at the bottom of the trench; and a chemical layer as a mask, etching the semiconductor substrate to form a bottle The manufacturing method of the bottle-shaped groove described in item 1 of the patent scope is a silicon nitride layer or a silicon nitride / silicon glass combination " Manufacturing method: The thickness of the rough layer is 25 to 35 A. The manufacturing method of the bottle groove as described in the first item of the patent scope is that the second liner is an oxide layer. Method for manufacturing bottle groove according to item 1 of patent scope

0548-8874twf(Nl) ； 91110 ； Claire.ptd 第15頁 578272 六、申請專利範圍 ’其中該第二襯層之厚度為45至55A。 6·如申請專利範圍第丨項所述之瓶型溝槽，其中該第二襯層為氮化層。造方法 7 ·如申請專利範圍第1項所述之瓶型溝，其中該導電層之厚度為75至85A。曰的I造方 Λ: ΐ ϊ專利範圍第1項所述之瓶型溝槽的製、q ，其中該導電層為多晶矽層或磊晶矽層。W I造方 9.如申請專利範圍第丨項所述之瓶型溝样其中該第三襯層之厚度為35至45人。9、，造方 1〇.如申請專利範圍第！項所述之其中該第三襯層為氮化層。戽槽的製造方 U·如申請專利範圍第丨項所述之瓶 :中該犧牲層為光阻層或旋塗式破璃槽的製造方 i，Λ'請專利範圍第1項所述之瓶型i 其中該氧化層之厚度為145至155入。槽的製造方 1 3.如申請專利範圍第】項所述之其中該敍刻方法為以 f槽的製造方其中該勉刻液為氫氧化録貝所述之瓶型溝槽的製造方 15. —種瓿型溝槽的製造方法，提供一半導體基底，該半導體括下列步驟： 7硬罩幕層及-圖案化光阻層上依序形成有硬罩幕層及該半導^ 蝕刻罩幕，依序蝕刻該墊層體基底’以在該半導體基底上形成法法法法法法法法層塾 0548-8874twf(Nl) ； 91110 ； Claire.ptd 第16頁 ’去除未被該犧牲層覆蓋之層之表面；進行氧化步驟以形成一氧化 578272 六、申請專利範圍槽，並去除該圖案化光阻層；於該溝槽露出之該半導體基一襯層；上項應性形成- 於。亥半導體基底及該第一襯層之表成一第二襯層及一導依序順應伯異；导電盾w亥第一襯層與該第二襯層相於該導電層表面上順應性形成一第三襯声；於該半導體基底表面上順應性形成—1屉牲層填滿該溝槽； ^犧牲層’且该餘刻該犧牲層，以在該溝槽底邱牲層；你唸/再價履邛遠下一既定深度之以該犧牲層為蝕刻罩幕第三襯層以露出部分該導電將該犧牲層去除；對露出表面之該導電層層； ▲以該氧化層為蝕刻罩幕，依序去除未被該氧化層覆之该第二襯層、該導電層、該第二襯層及該第一襯層，露出位於該溝槽底部之該半導體基底表面；及以該氧化層為罩幕，蝕刻該半導體基底以形成一瓶溝槽。 1 6 ·如申請專利範圍第1 5項所述之瓶型溝槽的製造法’其中該硬罩幕層為氮化矽層或氮化矽/硼矽玻璃組層。 •第 •形犧犧該蓋以型0548-8874twf (Nl); 91110; Claire.ptd page 15 578272 6. Application for patent scope 'wherein the thickness of the second liner is 45 to 55A. 6. The bottle-shaped groove according to item 丨 of the patent application scope, wherein the second liner layer is a nitride layer. Manufacturing method 7 · The bottle-shaped groove according to item 1 of the scope of patent application, wherein the thickness of the conductive layer is 75 to 85A. The manufacturing method of I: Λ: ΐ ϊ The manufacturing method and bottle shape of the bottle-shaped groove described in item 1 of the patent scope, wherein the conductive layer is a polycrystalline silicon layer or an epitaxial silicon layer. W I Fabrication 9. The bottle-shaped groove sample as described in item 丨 of the patent application scope, wherein the thickness of the third liner is 35 to 45 people. 9, the manufacturer 10. If the scope of patent application is the first! In the above item, the third underlayer is a nitrided layer. The manufacturer of the trough U. As described in the bottle of the scope of the patent application: The sacrificial layer is the manufacturer of the photoresist layer or the spin-coating glass-breaking trough. Bottle type i wherein the thickness of the oxide layer is 145 to 155 in. The manufacturer of the groove 1 3. As described in item 1 of the scope of the patent application, where the method of engraving is the manufacture of f groove, where the etching solution is the manufacturer of the bottle groove described in Hydrochloric Acid 15 — A method for manufacturing a ampule-type trench, providing a semiconductor substrate, the semiconductor including the following steps: 7 a hard mask curtain layer and a patterned photoresist layer are sequentially formed with a hard mask curtain layer and the semiconductor etch mask Screen, sequentially etch the pad body substrate 'to form a law method law method law method law 0548-8874twf (Nl); 91110; Claire.ptd page 16' remove the layer not sacrificed Cover the surface of the layer; perform an oxidation step to form an oxide 578272 6. Apply for a patent range groove and remove the patterned photoresist layer; The semiconductor-based liner layer exposed at the trench; The above-mentioned response is formed-at . The surface of the semiconductor substrate and the first lining layer is formed into a second lining layer and a guide in accordance with the order; the conductive shield and the second lining layer are compliantly formed on the surface of the conductive layer. A third contrasting sound; compliantly formed on the surface of the semiconductor substrate-a drawer layer fills the trench; ^ sacrifice layer 'and the sacrificial layer is left at the bottom of the trench; you read / The price is far from the next predetermined depth. The sacrificial layer is used as the third lining of the etching mask to expose a part of the conductive layer and the sacrificial layer is removed. The conductive layer layer on the exposed surface is used. ▲ The oxide layer is used as the etching layer. The mask sequentially removes the second underlayer, the conductive layer, the second underlayer, and the first underlayer that are not covered by the oxide layer, exposing the surface of the semiconductor substrate at the bottom of the trench; and The oxide layer is a mask, and the semiconductor substrate is etched to form a bottle trench. [16] The method for manufacturing a bottle groove according to item 15 of the scope of the patent application ', wherein the hard mask layer is a silicon nitride layer or a silicon nitride / borosilicate glass layer. • 第 • shaped sacrifice the cover with type

578272 六、〗 _請專利範圍 17, .如申晴專利範圍第1 5項戶斤述之瓶型溝槽的製造方法，其中該第一襯層之厚度為25奚35A。 18· ，如申請專利範圍第丨5項所述之瓶型溝槽的製造方法，其中該第一襯層為氧化層。 19. .如申請專利範圍第丨5項所述之瓶型溝槽的製造方法，其中该第二襯層之厚度為45至55A。 20, •如申請專利範圍第1 5項所述之瓶型溝槽的製造方法，其中該第二襯層為氮化層。 21, .如申請專利範圍第1 5項所述之瓶型溝槽的製造方法，其中該導電層之厚度為75至85 A。 22 .如申請專利範圍第1 5項所述之瓶型溝槽的製造方法，其中該導電層為多晶矽層或磊晶矽層< 23 •如申請專利範圍第1 5項所述之瓶型溝槽的製造方法，其中該第三襯層之厚度為35至45 A。 24 .如申請專利範圍第1 5項所述之瓶型溝槽的製造方法，其中該第三襯層為氮化層。 2 5, .如申請專利範圍第1 5項所述之瓶型溝槽的製造方法，其中該犧牲層為光阻層或旋塗式玻璃層。 26, .如申請專利範圍第1 5項所述之瓶型溝槽的製造方法，其中該氧化層之厚度為145至155A。法 27. .如申請專利範圍第1 5項所述之瓶型溝槽的製造方，其中该餘刻方法為以蝕刻液進行濕蝕刻。法 28. 如申請專利範圍第27項所述之瓶型溝槽的製造方，其中該钱刻液為氫氧化銨。 ^78272 六、申請專利範圍槎供種^瓶型溝槽的製造方法’包括下列步驟一氮化>、基底，該半導體基底上依序形成爛石夕玻場層及-圖案化光阻層；層、該二二二=光阻層為餘刻罩幕，依序姓刻該第 ;成二溝ί =及該半導體基底，以在該半導體於去除該圖案化光阻層； -氧化層露出之該半導體基底表面上順應性形於該半導體基底形成一第二氮化厚_ f第一軋化層之表面上依序於今層、—多晶矽層及一第三氮化層；阻層填滿該^ 面上順應性形成—光阻層，阻層；“亥光阻層’以在該溝槽底部留下-既定深第=氮蝕刻罩幕’去除未被該光阻層覆【7 露出部分該…層之表面，將該光軋化該多晶層以使該多晶矽層形成一第 j该第二氧化層為蝕被該第二氧化層覆蓋一：：斤去除忒溝槽二氮化声及兮笛^ w第一虱化層、該多晶矽層虱化層及忒第一氧化層，導體基底表面；及路®位於4溝槽底部 X4第一氧化層為罩幕，對該以形成一瓶型溝槽。守瓶丞底進仃有一第一氮化基底上成一第順應性且該光度之光蓋之該阻層去層；底部未、該第之該半濕餘刻578272 VI. _Please patent scope 17, such as the manufacturing method of the bottle-shaped groove described in item 15 of the patent scope of Shenqing, in which the thickness of the first liner is 25 奚 35A. 18. · The method for manufacturing a bottle-shaped groove as described in item 5 of the patent application, wherein the first lining layer is an oxide layer. 19. The method for manufacturing a bottle groove according to item 5 of the patent application scope, wherein the thickness of the second liner is 45 to 55A. 20, • The method for manufacturing a bottle-shaped groove as described in item 15 of the scope of patent application, wherein the second liner is a nitrided layer. 21. The method for manufacturing a bottle-shaped groove as described in item 15 of the scope of patent application, wherein the thickness of the conductive layer is 75 to 85 A. 22. The method for manufacturing a bottle-shaped groove as described in item 15 of the scope of patent application, wherein the conductive layer is a polycrystalline silicon layer or an epitaxial silicon layer < 23 • The bottle-type as described in item 15 of the scope of patent application The trench manufacturing method, wherein the thickness of the third liner is 35 to 45 A. 24. The method for manufacturing a bottle groove according to item 15 of the scope of the patent application, wherein the third liner is a nitrided layer. 25. The method for manufacturing a bottle groove as described in item 15 of the scope of patent application, wherein the sacrificial layer is a photoresist layer or a spin-on glass layer. 26. The method for manufacturing a bottle-shaped groove according to item 15 of the scope of patent application, wherein the thickness of the oxide layer is 145 to 155A. Method 27. The method for manufacturing a bottle-shaped groove as described in item 15 of the scope of patent application, wherein the remaining method is wet etching with an etching solution. Method 28. The manufacturer of the bottle-shaped groove as described in the scope of patent application No. 27, wherein the coin solution is ammonium hydroxide. ^ 78272 VI. Patent application scope 槎 For seeding ^ Bottle-shaped trench manufacturing method 'includes the following steps: nitriding>, a substrate on which a rotten stone glass field layer and a patterned photoresist layer are sequentially formed on the semiconductor substrate Layer, the two-two-two = photoresist layer is a mask with an engraving, and the first and last names are engraved; Cheng Ergou = and the semiconductor substrate to remove the patterned photoresist layer on the semiconductor;-an oxide layer The exposed surface of the semiconductor substrate is conformally shaped on the surface of the semiconductor substrate to form a second nitrided layer. The first rolled layer is sequentially formed on this layer, a polycrystalline silicon layer, and a third nitrided layer. The photoresist layer is formed on the surface ^-a photoresist layer, a resist layer; "The photoresist layer 'remains at the bottom of the trench-a predetermined depth = nitrogen etch mask' and is not covered by the photoresist layer [7 A part of the surface of the ... layer is exposed, and the light is used to roll the polycrystalline layer so that the polycrystalline silicon layer forms a jth second oxide layer which is covered by the second oxide layer. Acoustic and acoustic sound ^ w first lice formation layer, the polycrystalline silicon layer lice formation layer and the first oxide layer , The surface of the conductor substrate; and the first oxide layer at the bottom of the 4 trench X4 is a mask, which forms a bottle-shaped trench. The bottom of the bottle is placed on a first nitride substrate to form a first compliance and Delamination of the resist layer of the luminosity light cover;

578272 六、申請專利範圍 3 0.如申請專利範圍第2 9項所述之瓶型溝槽的製造方法，其中該第一氧化層之厚度為25至35A。 3 1.如申請專利範圍第2 9項所述之瓶型溝槽的製造方法，其中該第二氮化層之厚度為45至55A。 3 2.如申請專利範圍第29項所述之瓶型溝槽的製造方法，其中該導電層之厚度為75至85A。 3 3.如申請專利範圍第29項所述之瓶型溝槽的製造方法，其中該第三襯層之厚度為35至45A。 34.如申請專利範圍第29項所述之瓶型溝槽的製造方法，其中該第三襯層為氮化層。 3 5.如申請專利範圍第29項所述之瓶型溝槽的製造方法，其中該氧化層之厚度為145至155A。 3 6.如申請專利範圍第2 9項所述之瓶型溝槽的製造方法，其中該蝕刻液為氫氧化銨。578272 6. Scope of patent application 30. The method for manufacturing a bottle groove according to item 29 of the scope of patent application, wherein the thickness of the first oxide layer is 25 to 35A. 3 1. The method for manufacturing a bottle-shaped groove according to item 29 of the scope of patent application, wherein the thickness of the second nitride layer is 45 to 55A. 3 2. The method for manufacturing a bottle-shaped groove according to item 29 of the scope of patent application, wherein the thickness of the conductive layer is 75 to 85A. 3 3. The method for manufacturing a bottle groove according to item 29 of the scope of patent application, wherein the thickness of the third liner is 35 to 45A. 34. The method for manufacturing a bottle-shaped groove according to item 29 of the application, wherein the third liner is a nitrided layer. 3 5. The method for manufacturing a bottle-shaped groove according to item 29 of the patent application, wherein the thickness of the oxide layer is 145 to 155A. 3 6. The method for manufacturing a bottle groove according to item 29 of the scope of the patent application, wherein the etching solution is ammonium hydroxide.

0548-8874twf(Nl) ； 91110 ； Clairc.ptd 第20頁0548-8874twf (Nl); 91110; Clairc.ptd page 20