TW576997B - Method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design - Google Patents

Abstract

A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given the clock tree netlist, inserted buffers locations information, wires electrical parameters and buffers timing library, the components delay (buffer delay and wire delay) of the clock tree can be calculated first. Then, for each I/O pin, the path delay, clock delay and clock skew can be obtained. Finally using the proposed method, a modified clock tree netlist which satisfying the timing specifications can be constructed.

Description

576997 五、發明說明（l) 本發明之技術領域 本發明係有關高速超大型積體電路中時鐘樹（clock Tree) 電路合成之電腦辅助設計，尤其與在給定的緩衝器時序資 料庫中，適當選擇時鐘樹上各緩衝器種類之技術有關。 本發明之技術背景 現今的高速數位超大型積體電路設計大部分皆以時鐘頻率 (Clock Frequency)作為資料處理速度的指標。時鐘頻 是指時鐘訊號在邏輯〇與丨之間切換的頻率。在數位電路 中，-個時鐘網路必須負責將時鐘訊號由發送端傳 電路中任—個同步“的接收端，使這些系統能在: 計規範内上同步運作。 (L 〇Ce⑴已Ά 部結構圖。晶片中各區塊 !:二 1 佈局(Floorplaning)，區塊中各 早兀電路（Cel丨）亦已完成初步的放置（p 訊號透過一接墊（pad)1〇由曰 Πΐ； 卞知 用時鐘樹網路1 2將時鐘m _曰曰# # ° 至晶片内部，再利 塊14中，時鐘樹網路會繼續 、妾腳在區 K、1甲主于冋步糸統各部分。 在訊號傳送的過程中， (Signal Integrity)， 必須盡可能維持訊號之完整性 亦即必須滿足以下時序設計規範：576997 V. Description of the Invention (l) Technical Field of the Invention The present invention relates to computer-aided design of clock tree circuit synthesis in high-speed ultra-large integrated circuits, especially in a given buffer timing database, The technique of properly selecting each buffer type on the clock tree is related. Technical background of the present invention Most of today's high-speed digital ultra-large integrated circuit designs use a clock frequency as an indicator of data processing speed. Clock frequency refers to the frequency at which the clock signal switches between logic 0 and 丨. In digital circuits, a clock network must be responsible for transferring the clock signal from the transmitting end to any of the synchronous “receiving ends,” so that these systems can operate synchronously within the design specifications. (L 〇Ce⑴ 已 Ά 部Structure diagram. Each block in the chip !: 2 1 Floorplaning, the early circuit (Cel 丨) in the block has also completed the initial placement (p signal through a pad (pad) 10 by Πΐ; I do n’t know how to use the clock tree network 1 2 to move the clock m _ Yue # # # to the inside of the chip, and then in block 14, the clock tree network will continue, stumbling in the area K, 1 A master in the pacing system. In the process of signal transmission, (Signal Integrity) must maintain the signal integrity as much as possible, that is, it must meet the following timing design specifications:

第5頁 576997 五、發明說明（2) 盡可能減小時鐘延遲（Clock Delay)與時鐘歪曲率（cl〇ck Skew)。時鐘延遲意指由時鐘訊號發送端傳送到各同步系 統接收端所花費的最長時間。縮短時鐘延遲有助於加速時 鐘訊號的傳遞。換言之，可提升電路的操作頻率。'時鐘^ 曲率則為時鐘訊號發送端到時鐘樹中任兩接收端之間的路 徑時間差，其值若過大，各同步系統接收端接收到的時鐘 訊號便不同步，可能造成訊號失真與邏輯誤動作。Page 5 576997 V. Description of the invention (2) Minimize the Clock Delay and the Clock Skew as much as possible. Clock delay means the longest time it takes for the clock signal sender to transmit to the receivers of each synchronization system. Shortening the clock delay can help speed up the transmission of the clock signal. In other words, the operating frequency of the circuit can be increased. 'Clock ^ curvature is the path time difference between the clock signal sender and any two receivers in the clock tree. If the value is too large, the clock signals received by the receivers of the synchronization systems will not be synchronized, which may cause signal distortion and logical malfunction. .

隨著超大型積體電路深次微米製程技術的突飛猛進，訊载 在互連線路（Interc〇nnect)上的延遲已遠大於在各元^ 的延遲。對時鐘樹合成設計而言，為減小 知技術中，第一插执呌古斗、*办1 逆 在白 f種汉汁方式為盡可能縮短時鐘樹線路的長 二、 、又愈長’則在線路上的時間延遲愈大。一妒s I在超大型積體電路佈局設計中，短 優先被考慮來減小時間延遲。 长h吊取 上適當之位置***緩衝器1With the rapid advancement of deep sub-micron process technology for ultra-large integrated circuits, the delay on the interconnection line (Interconnect) has been far greater than the delay in each element ^. In terms of clock tree synthesis design, in order to reduce the knowledge, the first method is to intervene in the ancient fighting, * to do 1 inverse, and to reduce the length of the clock tree line as much as possible. The greater the time delay on the line. In the layout design of very large integrated circuits, short priority is considered to reduce time delay. Long h lift and insert buffer 1 at appropriate position

容，可減少各段載e且解㈣ 上升時間，遠至，丨纩丨：載1 n虎快速充電^ 的時鐘樹網路二：線？延遲的目的。圖-⑻為圖-(κ〇〇〇，正ί％鐘訊號的輸入接墊10稱為樹才I 接墊1〇(樹根）二私ρ時鐘訊號接收端稱為樹葉（Leaf) < 葉），包含沿途^的°線俺正。。反器16的時鐘訊號接收端β1.Κ 、、、衝杰與連接線路，構成一條完整路It can reduce the load of each section and solve the rise time, as far as, 丨 纩 丨: Clock tree network 2 with 1n tiger fast charge ^: line? The purpose of the delay. Figure-⑻ is a picture-(κ〇〇〇, the input signal 10 of the clock signal is called a tree I I pad 10 (root) two private ρ clock signal receiving end is called a leaf (Leaf) < Ye), including the ° line along the way ^ Zheng. . The clock signal receiving end β1.KK of the inverter 16 and the connection line constitute a complete circuit.

第6頁 五、發明說明（3) (Path)，所累積的镑输您&Page 6 V. Description of the Invention (3) (Path), the accumulated pound loses you &

Delay)。因此時鐘樹中為路徑延遲(Path 數。至於圖中兩條分別 反/數即荨於時鐘樹中的路徑 延遲差便是-組Si;曲細·：與Fl.3崎，其路徑 置***緩衝器1 8，除可減±在日^'鐘樹網路1 2上的適當位 缓衝器種類而改變卜，•過選擇不同的 小時鐘樹中各路徑的時鐘歪曲率。 0方式☆了減 圖二為習知技術（美國專利5,564,022、5,638,29 1盘 5^ 974’245等）之1C設計佈局流程圖。傳統的佈局設計通 常僅進行放置21與繞線25。使用邏輯合成（L〇gic Synthesis)工具產生一組描述邏輯閘及其連線的電網排線 表列（Net list)，接著放置21將電網排線表列中代表各種 類邏輯閘的標準單元（Standard Ce 11)放在晶片中所選定 的位置，通常位置之間的距離與電網排線表列中各元件的 連結關係有關’其目的是為了減少稍後繞線的長度。繞線 2 5則依放置的結果作貫際連線。Delay). Therefore, the clock tree is the path delay (Path number. As for the two inverse numbers in the figure, the path delay difference between the two in the clock tree is-group Si; the curve is fine: and Fl.3 Saki, the path is inserted Buffer 18 can be changed by subtracting the appropriate type of buffer on the clock tree network 12, and by changing the clock skew rate by selecting different paths in different small clock trees. 0 Method ☆ The minus figure 2 is the 1C design layout flow chart of the conventional technology (US patents 5,564,022, 5,638,29 1 plate 5 ^ 974'245, etc.). Traditional layout design usually only places 21 and winding 25. Use logic synthesis ( L0gic Synthesis) tool generates a set of grid lists describing the logic gates and their connections, and then places 21 standard cells (Standard Ce 11) in the grid layout lists that represent various types of logic gates. It is placed at the selected position in the chip, and the distance between the positions is usually related to the connection relationship of the components in the grid wiring table. The purpose is to reduce the length of the later winding. The winding 2 5 is based on the placement result. Make continuous connections.

現今的設計則將日守鐘樹合成步驟2 2、2 3與2 4加入佈局設計 中。步驟2 2進行最佳化時鐘樹網路的合成與繞線，因此修 改部分邏輯合成電網排線表列的内容。此外步驟2 2尚包含 一分析硬體描述處理器（Hardware Description P r o c e s s o r)，根據給定的時序設計規範，分析邏輯合成電 網排線表列中最佳化緩衝器***方式，其緩衝器加入電網In today's design, steps 2 2, 2 3, and 2 4 are added to the layout design. Step 2 2 Optimize the synthesis and winding of the clock tree network. Therefore, modify the content of the logic synthesis grid routing table. In addition, step 22 also includes an analysis hardware description processor (Hardware Description P r c e s s r r). According to a given timing design specification, the logic is synthesized to optimize the buffer insertion method in the grid routing table. The buffer is added to the power grid.

第7頁 ^^6997 五、發明說明（4) 排線表列中與其他元件的相關位置可作為下一步驟的緩_ 器***之實體設計（Physical Design)的參考依據。 由於描述各元件連線關係的 於步驟21時放置妥當，*** 它元件，因此步驟2 3必須重 外’因緩衝器的***分段了 枚端的連線，因此必須修改 芦、體繞線。一般而言，為了 、、爰衝為位置並不能離其原先 衝器會較其它元件擁有較優 一由時鐘訊號輸入端至正反 建立的時鐘樹網路有無違反 乾’則可進行步驟2 5各元件 =步驟23重新調整包括緩衝 知樹網路實體繞線。 原始邏 緩衝器 新調整 原先由 步驟22 維持最 選定的 先的放 器接收 時序設 的實體 器在内 輯合成 後將會 各元件 時鐘訊 已完成 小時鐘 最佳位 置權利 端的路 計規範 繞線； 各元件 電網排線 影響已放 的放置位 號發送端 之時鐘樹 延遲，調 置太遠， 。步驟24 徑延遲， 。若符合 反之，則 的放置位 表列已 置的其 i。另 至各接 網路的 整後的 因此緩 計算每 判斷所 時序規 必須回 置與時 均 衝 器 彈 鐘 因 而 僅 器 類 性 樹 調 ，如圖 使用同 時序資 型以供 以滿足 上各緩 整各路 料 選 時 衝 徑 的時鐘樹網路人★、六種缓衝器類型虔：η的緩衝器 庫⑴niing Lib :有：：：計中’緩擇，因而盔法有多種不同的缓衝序設計規範，為;；的時序控制更具 器的類型，可处击 點。若適當選擇時 的延遲值而能H:步減小時鐘延遲，並 “文善時鐘歪曲率使其符合時序 576997 五、發明說明（5) =汁規範。通常標準單元式設計資料庫中不同類型的緩衝 ^ f面積的大小可能互異，於是驅動下一級電路的能力 也不同、一般面積較大的緩衝器能比面積較小的能驅動較 大的負載’加速負載的訊號上升時間。然而較大的緩衝器 本身也/、有較大的延遲，反而可能增加路徑延遲。 供選擇 個緩衝 必須判 鐘延遲 衝器插 建立會 階層模 的1C設 單元式 合成階 庫中， ，並維 在時鐘 的緩衝器類型有 為。右採取地毯 斷所有mn種緩衝 並符合時鐘歪曲 入與緩衝器類型 依時序限制判斷 擬（C i r c u i t 計流程中將會花 超大型積體電路 段’***緩衝器 决速找出一組適 持最小時鐘延遲 樹電路合成工具 於選擇緩衝器類型時，假設考慮可 n種’同時時鐘樹網路上需要***m 式搜尋法（Exaustive Search)，則 為組合方式中，何者能求得最小時 率限制。一般而言，在同時考慮緩 選擇的問題上，由於時鐘樹網路的 的結果反覆進行多次的放置與電路Page 7 ^^ 6997 V. Description of the invention (4) The relative positions of other components in the wiring list can be used as a reference for the physical design of the retarder inserted in the next step. Since the connection relationship of each component is properly placed in step 21 and the component is inserted, step 2 3 must be repeated. Because the buffer is inserted to segment the connection of the end, the reed and body windings must be modified. Generally speaking, in order to avoid the impact of the original punch, the original punch will have better performance than other components. From the clock signal input to the clock tree network established in front and back, if there is any violation, you can perform steps 2 and 5 Element = Step 23 readjustment includes buffering the physical tree network winding. The original logic buffer is newly adjusted. The entity device that maintains the most selected first receiver receiving timing set in step 22 is internally synthesized, and the clock signals of each component have been completed. The grid wiring of each component affects the clock tree delay of the placed end number sending end, which is adjusted too far. Step 24 Path delay,. If the opposite is true, the placement table of is listed i. In addition, the overall calculation of the timing of each connection network must be reset and the time-averaged clock must be reset. Therefore, only the tree type is adjusted. As shown in the figure, the simultaneous sequence type is used to meet the above requirements. The clock tree network person who chooses the path when the whole material is selected ★, six types of buffers: η buffer library η niing Lib: Yes ::: plan, slow selection, so the helmet method has a variety of different buffers The sequence design specification is:; The sequence control is more of a type, which can be hit. If the delay value is properly selected, the clock delay can be reduced by H: steps, and "Wenshan clock distortion rate makes it conform to the timing 576997. V. Description of the invention (5) = juice specification. Usually different types in standard unit design database The size of the buffer area may be different from each other, so the ability to drive the next stage circuit is also different. Generally, a buffer with a larger area can drive a larger load than a smaller area can drive a larger load. The large buffer itself also has a large delay, but may increase the path delay. To choose a buffer, you must determine the clock delay. The puncher must be inserted to create a 1C unit-level synthesis library that is hierarchical, and maintained in the clock. The buffer type is promising. Right take the carpet to break all the mn types of buffers and meet the clock distortion. The buffer type is judged according to the timing constraints. (Circuit calculation process will take a very large integrated circuit segment to insert the buffer speed. Find a set of suitable minimum clock delay tree circuit synthesis tools. When choosing a buffer type, suppose that n kinds of 'simultaneous clock tree' networks are needed. Insert m-type search method (Exaustive Search), which is the combination method, which one can get the minimum time limit. Generally speaking, when considering the slow selection at the same time, the results of the clock tree network are repeated many times. Placement and circuit

Level Simulations)，因此在圖二 費大量的計算時間。因此對於標準 設計工具而言，如何在時鐘樹電路 後’由給定的緩衝器時序設計資料 當的緩衝器類型，以減少模擬時間 且符合時鐘歪曲率時序設計規範， 中佔有相當重要的地位。 本發明的概要說明 本舍明的目的在於提出一種快速決定高速史 型積體電路Level Simulations), so it takes a lot of calculation time in Figure 2. Therefore, for the standard design tools, how to design the buffer type with the given buffer timing information after the clock tree circuit, in order to reduce the simulation time and meet the clock skew timing design specifications, occupies a very important position. SUMMARY OF THE INVENTION The object of this invention is to propose a fast-determining high-speed history integrated circuit.

五、發明說明（6) 時鐘樹上各緩衝器種 合成设計流程，迅速 延遲維持最小且時鐘 樹合成設計流程中， 計流程中時鐘樹之實 行。此時輸入的資訊 各段線路的電性參數 5十异時鐘樹的線路延 與時鐘延遲的運算架 本模組。透過本發明 合成工具，最後輸出 鐘歪曲率設計規範的 類的方法 決定適合 歪曲率可 緩衝器種 體繞線與 包括時鐘 與各種類 遲與緩衝 構，作為 所提出的 更新後能 時鐘樹電 ’不僅 之緩衝 以符合 類的選 緩衝器 樹電網 緩衝器 器延遲 本發明 快速決 維持最 網排線 可配合 器種類 時序設 擇，將 ***兩 排線表 的時序 。接著 決定緩 定緩衝 小時鐘 表歹U 。 現有的 ，以保 計規範 於傳統 步驟之 列、時 資料庫 建立路 衝器種 器種類 延遲並 時鐘樹 證時鐘 。時鐘 晶片設 後執 鐘樹中 ，以供 徑延遲 類的基 之電路 符合時V. Description of the invention (6) The design process of each buffer in the clock tree is synthesized quickly, and the delay is kept to a minimum, and the clock tree is synthesized during the design process of the clock tree. Information entered at this time Electrical parameters of each section of the line 50 The calculation of the line delay and clock delay of different clock trees This module. Through the synthesizing tool of the present invention, the method of finally outputting the clock distortion rate design specification class is determined to be suitable for the distortion rate bufferable seed winding and including the clock and various types of late and buffer structures, as the proposed updated clock tree can be powered. Not only does the buffering match the class selection buffer tree, the grid buffer delays the invention, the present invention quickly maintains the most network cable, which can be matched with the timing setting of the device type, and the timing of the two-row cable table will be inserted. It is then decided to buffer the small clock table U. Existing, to ensure the standard in the traditional steps and time database to establish the type of the router type delay and clock tree to verify the clock. The clock chip is set in the bell tree to provide the basic circuit of the path delay class.

本發明之選擇時鐘樹上各緩衝器種類的方法之所以可以達 J述的目的，快速地決定出緩衝器種類，其特點在於： 本發明所設計的延遲計算器（Delay Calculator)，在 每/一 ί最佳化運算過程中，僅計算部分種類或負載改變的 緩衝器資訊’不必計算時鐘樹中其它未受影響的部分，可 1 ^減少運算量。運用等效模型化簡的概念，可有效減少 ^麵樹路徑數，因此減少排序各路徑延遲的時間；（2)可 快速判斷一時鐘樹是否具有符合時序設計規範的可行解 (Feasible Solution)。如果沒有，則不再進行最佳化運 异’將判斷的結果輸出作為參考；（3)應用啟發式 (Heuristic)的觀念作最佳化運算，而不採用地毯式搜尋The reason why the method for selecting each buffer type on the clock tree according to the present invention can achieve the purpose described in J and quickly determine the buffer type is characterized by: The delay calculator (Delay Calculator) designed by the present invention is -During the optimization operation, only buffer information of some types or load changes is calculated. 'It is not necessary to calculate other unaffected parts of the clock tree, and the amount of calculation can be reduced. Using the concept of equivalent model simplification can effectively reduce the number of face tree paths, thus reducing the delay time of sorting each path; (2) It can quickly determine whether a clock tree has a feasible solution that meets the timing design specifications (Feasible Solution). If not, the optimization operation will not be performed anymore, and the result of the judgment is used as a reference; (3) Heuristic concepts are used for optimization operations instead of carpet search

第10頁 576997Page 10 576997

576997 五、發明說明（8) ' 提供選擇的緩衝器種類有限，最簡單使用來求解上 化問題的方式即為地毯式搜尋：逐一置換時鐘樹中每一緩 衝器的種類並比較各組之時鐘延遲與時鐘歪曲率，直到最 後挑出其中擁有最小時鐘延遲並符合時鐘歪曲率時序設^ 規範的最佳緩衝器類型組合。然而此方法最主要m =:(ι)浪費運算時間；（2)若某一特定實施例根本不; 1合^序設計規範的可行解，該方法仍必須檢查過所有組 合，最後才能發現沒有可行解，無法迅速反應錯誤訊息。 基於上述理由，並針對此最佳化問題的特性，本發明發展 一快速決定時鐘樹中緩衝器種類的方法，希望達到：（工） 能快1判斷某一特定實施例是否具有符合時序設計規範的 可行解；（2)快速有效地決定時鐘延遲最小且符合時鐘歪 曲率設計規範的最佳緩衝器種類組合。圖三顯示依據本發 明施行特定實施例的系統方塊圖。輸入特定實施例的時^ 樹合ΐ電網排線表列27、時鐘歪曲率設計規範上限值28與 緩彳f器時序資料庫29，經由本發明之快速決定時鐘樹中緩 衝器種類演，工具3〇做最佳化運算：若有可行解，即輸出 更新後具有最佳緩衝器種類組合之時鐘樹電網排線表列3工 與此時時鐘樹的時鐘延遲與時鐘歪曲率；反之， 法符合時序設計規範之錯誤訊息。 圖四為本發明之快速決定時鐘樹中緩衝器種類演算工具3 〇 的方塊圖，包括以下各模組：初始狀態設定38、、二速&斷576997 V. Description of the invention (8) 'The types of buffers provided are limited. The easiest way to solve the problem is to perform carpet search: replace the types of each buffer in the clock tree one by one and compare the clocks of each group. Delay and clock skew, until the best buffer type combination is selected that has the smallest clock delay and meets the clock skew timing specifications. However, the most important method of this method is m =: (ι) wasted computing time; (2) if a particular embodiment is not at all; a feasible solution of the 1st order design specification, the method must still check all combinations before finally finding no Feasible solution, unable to respond quickly to error messages. Based on the above reasons, and in view of the characteristics of this optimization problem, the present invention develops a method for quickly determining the type of buffers in the clock tree. It is hoped that: (work) can quickly determine whether a particular embodiment has a timing design specification. Feasible solution; (2) quickly and efficiently determine the best combination of buffer types with the smallest clock delay and the design specifications of clock skew. FIG. 3 shows a block diagram of a system according to a specific embodiment of the present invention. Enter the time ^ tree combination grid list 27, clock distortion rate design specification upper limit value 28, and buffer timing database 29 of the specific embodiment, and quickly determine the type of buffer in the clock tree through the present invention. Tool 30 performs optimization calculations: if there is a feasible solution, that is, output the updated clock tree grid routing table with the best combination of buffer types after the update, and the clock delay and clock distortion rate of the clock tree at this time; otherwise, The error message conforms to the timing design specification. Fig. 4 is a block diagram of a buffer type calculation tool 3 0 in the fast-determined clock tree of the present invention, including the following modules: initial state setting 38, two-speed &

576997 五、發明說明（9) __ 有無可行解39、快速調整緩衝器 類型41與時鐘延遲微調42。由 ^ ^王辍衝器 遲計算，因此各模組：需要用模組皆必須進行路徑延 詳細過程閣述於下。 用到延遲計算器36。各模組之 各步驟中常用的代表符號首先說 曲率上限；（2 ) P ··時鐘榭φ播+ · 以⑽：時鐘歪 該路，延遲即為時鐘延遲；(3)Pmin:時鐘樹中擁：：：路 徑延遲的路徑；（4) AD :時鐘歪曲率’即卩 取小路 減去Pm i η的路徑延遲；（5 ) b ·為彳 max 虹延遲 ^ Λ /η、 ρ ·為任一路徑Ρ中所有绥彻哭 集合；⑷Bp，。:為任兩路徑…之共有的緩衝器集合衝- I先是延遲計算器36，有兩項觀察重點··（1)置換時鐘 置的緩衝器種類’除了導致該緩衝器的延遲改變 之卜士由於輸出訊號斜率會傳送至負載，因此可能使得時 = 衝器的延遲改變；(2)在決定緩衝 :=二; 的過程中，可能必須重複地置 換不同位置或同一位置緩衝器的種類。因此哭576997 V. Description of the invention (9) __ Is there any feasible solution 39? Quick adjustment of buffer type 41 and fine adjustment of clock delay 42. Since ^ ^ Wang Chuan puncher is late to calculate, so each module: need to use the module must carry out path delay. The detailed process is described below. A delay calculator 36 is used. The representative symbols commonly used in each step of each module first say the upper limit of curvature; (2) P ·· clock clock φ broadcast + · ⑽: the clock skews the path, the delay is the clock delay; (3) Pmin: the clock tree C ::: path with path delay; (4) AD: clock skew rate 'i.e., the path delay taken by subtracting Pm i η; (5) b · bmax rainbow delay ^ Λ / η, ρ · is any The set of all Sui crying in a path P; ⑷Bp ,. : For the buffer set shared by any two paths ... I first is the delay calculator 36, and there are two observation points ... (1) Replace the type of buffer set by the clock 'except for the buffer that causes the delay of the buffer to change Because the output signal slope will be transmitted to the load, it may make the time = delay of the punch change; (2) In the process of determining the buffer: = 2 ;, it may be necessary to repeatedly replace different types of buffers at the same location or the same location. So cry

將成為本發明中最常被使用的模所 ^ OD 執行的時間’計算延遲時必須盡可能；二效減少程式 本發明所考慮的時序設計規範都與計首 出端的路徑延遲有關，即累積一條由。：：輸入端至輸 徑的緩衝器延遲與線路延遲總和。歸i i樹茱之完整路 W其計算原則有··第It will become the most commonly used mode in the present invention. ^ The execution time of OD must be as much as possible when calculating the delay. The two-effect reduction program. The timing design specifications considered by the present invention are all related to the path delay of the head and end. by. :: Sum of buffer delay and line delay from input to path. The complete way to return to i

第13頁 576997 五、發明說明（ίο) 一、為達快速計算路徑延遲的目的，線路電 uced Standard ParasiUc ―⑷格 ::日巧換綾衝器Λ種類僅影響緩衝器延遲，與線路延遲i I。圖五（a)表不緩衝器46與緩衝器5〇 …、 "n^r;P"f"Y(s)〇wi(b)^Rs-^ -电性茶數，其中PI模型（R1，C1，C2)為Y(s)的前三階夫 開5近似’可視為緩衝器46的等效線路負載，其線ς 、 載，為C1+C2。該線路的接腳對接腳（pin_t〇__pin)延遲^可、 以簡早的RC模型表示，線路延遲為咖㈡。因為各段 的電性簽數由輸入資料給定，線路延遲 :影響。缓衝器延遲值與輪出訊號斜率可由：、二 ;L〇〇k_UP)得知，其示意圖如圖六，利 ^知：輸入訊號斜率值舆負•電容值查出則固角落的緩 广延遲值，再利用分段線性内插法⑺⑽ nte 了 UtlQn)等方法計算内插值可求近 值，求取輸出訊號斜率值的方式亦 $ ^二 的種類1對改變該緩衝器的=容二置換緩衝器Page 13 576997 V. Description of invention (ίο) 1. To achieve the purpose of calculating the path delay quickly, the line voltage Uced Standard ParasiUc ― Grid :: The day-to-day change of the punch Λ type only affects the buffer delay, and the line delay i I. Figure 5 (a) shows the buffer 46 and the buffer 50... &Quot; n ^ r; P " f " Y (s) 〇wi (b) ^ Rs- ^-the electrical tea number, where the PI model ( R1, C1, C2) are the first three orders of Y (s), and can be regarded as the equivalent line load of the buffer 46. The line load and load are C1 + C2. The delay of the pin butt pin (pin_t0__pin) of this line can be expressed by a simple RC model, and the line delay is caffeine. Because the number of electrical signatures of each segment is given by the input data, the line delay is affected. The buffer delay value and the round signal slope can be known from: (2; LOOk_UP), the schematic diagram is shown in Figure 6, and it is easy to know: the slope of the input signal is negative. • The capacitance value is detected to slow down the corner. Delay value, then use piecewise linear interpolation method (nte has UtlQn) and other methods to calculate the interpolation value can be approximated, and the way to obtain the output signal slope value is also $ ^ 二 的 类 1 Pair changes the buffer = Rongji Replacement buffer

CaP=tance]二如由其前一級緩衝器輸出觀察， 負載$ ’而緩衝器延遲亦會隨之改變。 ：工 緩衝器50的類型，則改變緩衝哭 右改、殳 器46與5。都必須重新查表計以的^負二CaP = tance] As observed by the buffer output of the previous stage, the load $ 'and the buffer delay will change accordingly. : The type of the buffer 50, then change the buffer, right, and 46 and 5. Must check the table again

器為最後一級緩衝器的負載，通當ί ^ V i;多換句洁…體正反器的數量比最後-級緩衝器的The device is the load of the last-stage buffer, which means that the number of body flip-flops is larger than that of the last-stage buffer.

第14頁 576997 五、發明說明（π) 綜合以上各點，本發明之延遲計算器的作法以圖七為例， 概分為兩階段：（a )缓衝器延遲計算，與（b)正反器線路延 遲計算，各自負責時鐘樹結構中不同區域的路徑延遲計 异。圖七的緩衝為、54與58為緩衝器52的負載，緩衝器56為 緩衝為5 4的負載’正反器組6 0與6 2分別為緩衝器5 6與5 8的 負載。詳細步驟說明如下。 要考慮時鐘樹中因為 致部分緩衝器其時間 若改變緩衝器5 6的類 查表计鼻，然而若改 必須重新查表計算。 ，否則不會計算整個 。為了使父級 新過後的路徑延遲能 明結合深度優先搜尋 佇列（Queue)先進先 ’其流程如圖八。以 步驟，假設改變緩衝 入緩衝器5 8的父級緩 庫重新計算緩衝器5 2 更新緩衝器54與58的 驟70將兩者依序寫入 變，而導 如圖八， 必須重新 緩衝器皆 載值改變 運算時間 斜率與更 器，本發 的概念與 特性達成 合圖八的 ’首先輸 時序資料 時步驟6 8 ’然後步Page 14 576997 V. Description of the invention (π) To sum up the above points, the method of the delay calculator of the present invention is shown in Figure 7 as an example, which is divided into two stages: (a) buffer delay calculation, and (b) positive The inverter line delay calculation is responsible for calculating the path delay of different areas in the clock tree structure. The buffers in Fig. 7 are 54 and 58 are the loads of the buffer 52, and the buffer 56 is the load of the buffer 54. The flip-flop groups 60 and 62 are the loads of the buffers 5 6 and 5 8 respectively. The detailed steps are explained below. It is necessary to consider the time in the clock tree because part of the buffer is changed. If the type of the buffer 56 is changed, the table lookup counts, but if it is changed, the table lookup calculation must be performed again. , Otherwise the entire will not be calculated. In order to make the path delay of the parent after the new path clear and the depth-first search queue first, the process is shown in Figure 8. In steps, suppose that the parent buffer of buffer 5 8 is changed and the buffer 5 2 is recalculated. Step 70 of updating buffers 54 and 58 writes the two in order. As shown in Figure 8, the buffer must be re-buffered. The all-load value changes the calculation time slope and changer. The concept and characteristics of the present invention are as shown in Figure 8. 'First input timing data step 6 8' and then step

緩衝器延遲計算：本7X ^… 緩衝器種類改變或負載量改 延遲隨之改變的更新計算。 型’則緩衝器5 4與5 6的延遲 變緩衝器58的類型，則所有 除非樹基緩衝器的類型或負 時鐘樹的延遲，因此可減少 (Parent)緩衝器的輪出訊號 傳給各子級（Children)緩衝 二Breadth_flrst Search) 出（F irst-in-f irst ‘、从 闽， rst—out)的 =的時鐘樹電路為例，配 :5二的類型’由步驟64開始 的：步驟66查表緩衝器 的延遲與輸出訊號斜率，同 緩衝器延遲與輸入訊號斜率Buffer delay calculation: This 7X ^ ... Update calculation when the buffer type changes or the load amount changes. Type 'means the types of buffers 5 4 and 5 6 are variable delay buffers 58, then all types except tree-based buffers or the delay of the negative clock tree can reduce the round-trip signal of the (Parent) buffer to each For example, the clock tree circuit of the children buffer (Breadth_flrst Search) out of (F irst-in-f irst ', from Fujian, rst — out) =, with the type of "5 two" from step 64: Step 66: Look up the delay of the table buffer and the slope of the output signal, the same as the delay of the buffer and the slope of the input signal.

576997 五、發明說明（12) 件列中。此時步驟72判斷出佇列 74讀出緩衝器54進行步驟66杳表衝：緩衝器，步驟 重複以上步驟，直到步驟72以=以料庫。接著 止。 研丁列中再無缓衝器為 ^ ^有數個正反器當作同一緩衝 正反器線路延遲計算： 器的負載，如此這此正反哭便擁i久益畜作问一緩衝 器的緩衝器延•，:i… 路延遲而已。以圖七為例，丘古 廷二正反态的線 有相同由^為/ /、有五條路徑。正反器組62擁 令祁IJ由緩衝益52至58的緩衝器 62弋不-定有相同的正反器線路；遲： 器的時鐘訊號接收端為時鐘樹的樹葉遲正反二 根啟始至正反器時鐘訊號接 .^ σ 置換演算法中，需|蚪&女叻 么數。因為在緩衝器 徑數愈多丄；”作…如果路 一缓衝器所有正反器錄Τ ΐ規乾，本發明僅考慮接到同 則不考慮。本發明：正5魂：最大與最小者’其餘路徑576997 V. Description of Invention (12). At this time, Step 72 judges the queue 74, reads out the buffer 54, and performs step 66: Buffering: buffer. Step Repeat the above steps until Step 72 uses the stock. Then stop. There are no buffers in the research column. ^ ^ There are several flip-flops as the same buffer. The line delay calculation of the flip-flops: the load of the device, so if you cry, you will have a buffer.器 延 •,: i ... The road is delayed. Taking Figure VII as an example, the lines of Qiu Guting's two normal states have the same path from ^ to // and there are five paths. The flip-flop group 62 holds the Qi IJ from the buffer 62 of the buffer 52 to 58. It may not have the same flip-flop circuit; the clock signal receiving end of the device is the leaves of the clock tree. From the clock signal to the flip-flop, the ^ σ replacement algorithm requires | & Because the more the number of buffers in the buffer; "Work ... If all the flip-flops in the buffer of a road are regulated, the present invention only considers receiving the same but does not consider it. The present invention: positive 5 soul: maximum and minimum The 'remaining path

Array)FF盥FF的建办^；線路延遲指標陣列（Pointer _ ” Hmin的建立方式如圖九。 兩組正反器組60與62，經過+驟以姚皮么囷*為例，/、有 延遲60.1>60.2>60·3且62 2則牛ί ，若正反器線路 指標陣礼會指 此兩指標陣脾盘'、+. _私向6 0. 3與6 2. 2。 遲=陣列將與刖迷之緩衝器延遲計算結合為完整的延Array) FF and FF construction ^; Line delay indicator array (Pointer _ ”Hmin is set up as shown in Figure 9. Two sets of flip-flop groups 60 and 62, take + Pips to take Yao Pi Mo 囷 * as an example, /, There is a delay of 60.1 > 60.2 > 60 · 3 and 62 2 bulls. If the flip-flop line indicator array ceremony will refer to these two indicators as the spleen disk ', +. _Private direction 6 0. 3 and 6 2.2 Lateness = The array will combine with the delay calculation of the buffer to complete the latency

576997576997

現舉例說明本發明之延遲計算哭 ^ 有η個最下級緩衝器…"管：土：。右某-時鐘樹擁 各η個最大與最小的正個累加的緩衝器延遲與 ;遲=亡所i的緩衝器延遲，因此產生2*η個；：ΓNow, the delay calculation of the present invention will be described as an example. ^ There are n lowest-level buffers ... " Right-Clock tree has n maximum and minimum positive accumulated buffer delays and; delay = buffer delay of death i, so 2 * η are generated; Γ

遲。/、中联大者即為時鍾延遲匕，最大p盥芒丨D 即為時間歪曲△ D。由；^正及# _ /、小匕U的差 ^ , 由於正反線路延遲不會隨緩衝哭罟 新=艾因此每次置換緩衝器僅需計算緩衝器延遲， 3 /延、，再對其中Μ11個路徑延遲作排序。因此真正 排序的數目比正反器數少，可以減少運算量。 〃 接著討論圖四中本發明之快速決定緩衝器種類演算工 =v私首先疋初始狀態設定3 8。本發明的目的為最小化 時鐘延遲，假設先不考慮時鐘歪曲率的限制，此問題即形 成所。月的非限制型敢佳化（Unc〇nstrainecj 問，，局部最佳解會接近給定的初始狀態。因此，本發明 將日守鐘樹中所有緩衝器的初始狀態皆設定為延遲最小的緩 衝器種類’會使得時鐘延遲接近局部最小值。late. /, The United Nations University is the clock delay dagger, and the maximum p is the time distortion Δ D. From the difference of ^ positive and # _ /, small dagger U ^, because the forward and reverse line delay will not cry with the buffer 罟 new = Ai, so each time you replace the buffer, you only need to calculate the buffer delay, Among them, M11 path delays are sorted. Therefore, the number of true sorts is less than the number of flip-flops, which can reduce the amount of calculation. 〃 Next, the fast-calculating buffer type operator of the present invention in FIG. 4 is discussed. First, the initial state setting is 38. The object of the present invention is to minimize the clock delay. Assuming that the limitation of clock skew is not considered, this problem is caused. The unrestricted dare to optimize the month (Uncoonstrainecj asks, the local optimal solution will be close to a given initial state. Therefore, the present invention sets the initial state of all buffers in the horological clock tree to the buffer type with the least delay 'Will cause the clock delay to approach a local minimum.

$二’快速判斷有無符合時序設計規範的可行解3 9。考慮 知歪曲率限制時，因為必須判斷是否存在可行解，問題 會變得較複雜。如前所述，如果使用地毯式搜尋方式找最 佳解’會浪費太多時間，甚至搜尋到最後依然沒有可行 角午。因此’為及早發現某一時鐘樹是否根本就不存在符合$ 二 ’Quickly determine if there is a feasible solution that meets the timing design specifications 3 9. When considering the distortion limit, the problem becomes more complicated because it is necessary to determine whether there is a feasible solution. As mentioned earlier, if we use the carpet search method to find the best solution ’, it will waste too much time, and even the search is not feasible in the end. So ‘to find out early if a clock tree does n’t exist at all

第17頁Page 17

d 丨 \>7y I 五、發明說明（14) 規範的可行解，本發明建立一、 示。快速判斷有無可行解的:判斷機制，步驟如圖十所 兩條路#的延遲差是否可點在於—僅比較Lx與卩_ 時不管其它路徑。幻乍法招/合時鐘歪曲率限制，而暫 …—#，P Fu i根據以下原則：（1 )因為初妒狀 態設定时，pmax上的緩衝器仍鈇給杜田t ^ π初始狀 1 ο 〇每次依序由樹葉往樹根的方内延’藉由步驟 衝写成最大延遲類型，可mf換路上的—個緩 的缓衝類型改變不影響P :二的路控延遲增大。若p-上 曲率。（2 )由於緩衝器時序庫非 t楚正 與輸出戒J斜率對愈大的輸入訊號斜率愈敏感，而且延遲 愈大的，故衝益類型愈明顯。因此步驟m 徑中共有之緩衝器集合Β_ιη緩衝器尺寸變二雖；： 延遲增加現U:: ，緩衝器集合u，—的輸出訊號斜 率增加。現以圖七為例說明共有之緩衝器集合Β 52奚 緩衡 、^ 叫〜a仗呵莕rt〇吕，具共有$ 器集a _，心為緩衝器52。因為上緩衝器類型已 延遲，如^將有機會使匕⑺的路徑延遲增加的幅度較 P一的為大，換言之，時鐘歪曲率可能因而減小。 前戶斤述，^的時鐘樹可等效為兩條路徑，分;;：緩衝器 <緩衝态56與緩衝器58。因此對後兩者而言，其共: 合 丄為 Μ 输哭 R 9 . m α η ..... " T=7 取Λ max 本發明利用分支約束演算法的精神，快速調整緩衝 相較地毯式搜尋，分枝約束演算法更具彈性 第彡 器類塑4〇 ” 〜开仏人六坪，Γ 部 藉由建立刀支約束樹（Branch-and-bound Tree)、固定 分的變數且不考慮其餘變數的機制，可以提早剔除部分d 丨 \ > 7y I V. Description of the invention (14) The feasible solution of the specification. Quickly determine whether there is a feasible solution: The judgment mechanism, the steps are shown in Figure 10. Whether the delay difference between the two paths # is significant-only comparing Lx and 卩 _ regardless of other paths. The magic trick / combined clock distortion rate limit, and temporarily ... — #, P Fu i according to the following principles: (1) Because the initial jealous state is set, the buffer on pmax still gives Du Tian t ^ π initial state 1 ο 〇Sequentially from the leaves to the root of the tree each time, by writing the maximum delay type by steps, mf can be changed on the road—a gentle buffer type change does not affect P: 2's increase in road control delay. If p- on curvature. (2) Since the buffer timing library is not positive and the output or J slope is more sensitive to the larger input signal slope, and the larger the delay, the more obvious the type of benefit. Therefore, the size of the buffer set B_ιη shared by the path m becomes two. Although the delay increases, the output signal slope of the buffer set u, — increases. Now take Figure 7 as an example to illustrate the shared buffer set B 52 奚, the balance is called aa 荇 呵 荇 rt〇 吕, with a total of $ set a _, and the heart is the buffer 52. Because the type of the upper buffer has been delayed, for example, there will be a chance that the path delay of the dagger will increase by a larger amount than that of P-1. In other words, the clock skew rate may be reduced accordingly. As mentioned before, the clock tree of ^ can be equivalent to two paths, which are divided into:; buffer < buffer state 56 and buffer 58. Therefore, for the latter two, they are: Μ 哭 R 9. M α η ..... " T = 7 Take Λ max The present invention uses the spirit of the branch constraint algorithm to quickly adjust the buffer phase Compared with carpet-type search, the branch and constraint algorithm is more flexible. The first device class is 4 ″ ~ Kaiping Renliuping. The Γ part establishes a branch-and-bound tree and fixed-point variables. Regardless of the mechanism of the remaining variables, some can be eliminated early

第18頁 五、發明說明（15) 不合理的解甚至解分古姓 . 變數放在八# 變數依重要性排序，重要的Page 18 V. Description of the invention (15) Unreasonable solution or even ancient surnames. Variables are placed in eight # Variables are sorted by importance, important

夂歎敌在分支約束樹上声 > 主文W 效率。 3 μ 可以k咼求得最佳解的 ，進入快 行解的狀 緩衝器在 明於選擇 ，其緩衝 徑延遲） 級緩衝器 響的範圍 而非其它 ，在選擇 大延遲類 首先，在前述中已得知 的如'^為已確定存在可 中，變數的優先順序與 種類有關。此外，本發 (1)路徑延遲最小的p min k先考慮（為了增加路 後，子級緩衝器應較父 緩衝器較父級緩衝器影 延遲加在選定的路徑上 路徑與緩衝器位置之後 最小延遲類型置換成最 種類的次數）。 速調整緩衝器類型演算法 態下。其次，在此問題 時鐘樹中的位置及緩衝器 置換種類考慮以下原則： 器應比其它路徑的緩衝哭 。（2)當選定某一路徑 優先選定種類（因為子級 小’因而較容易將緩衝器 無關的路徑）。（3)選定σ 1衝器的種類時，直接由 型（可以減少置換緩衝器 圖十一 程圖。 是最小 意謂此 取最佳 的種類 有路徑 所示為本發明之快速調整緩 步驟112為恢復初始狀態，讓痛型演算法40的流 延遲。當步驟114判斷初始狀能器的種類都 時的解已接近最佳解，即可進二士付合條件限制， 解，加速求解時間。反之，仃時鐘延遲微調4 2求 。在步驟116中，維持pmax不變二周整部分緩衝器 中最大者。每次排序挑出P 一路徑延遲為所 出k路傻’並置換路徑上 576997 五、發明說明（16) 一個緩衝裔類型為最大延遲類型的方式，Lament the enemy on the branch-constrained tree > Subject W efficiency. 3 μ can get the best solution. The state of the buffer entering the fast-moving solution is clear in the selection, and its buffer path is delayed.) The range of the buffer response is not other than that in the selection of the large delay class. First, in the foregoing, It has been known that if '^' has been determined to exist, the priority of the variables depends on the type. In addition, (1) the minimum path delay p min k is considered first (in order to increase the path, the child buffer should be delayed from the parent buffer to the parent buffer shadow after adding the path and the buffer position on the selected path The minimum delay type is replaced with the most kind number). Speed adjustment buffer type algorithm. Secondly, in this question, the position in the clock tree and the type of buffer replacement consider the following principles: The device should cry than the buffers of other paths. (2) When a certain path is selected, the type is preferentially selected (because the child level is small, it is easier to buffer unrelated paths). (3) When the type of σ 1 punch is selected, it is directly made by type (it can reduce the eleven-pass map of the replacement buffer. It is the minimum meaning that this is the best type. The path is shown as the rapid adjustment of the present invention. Step 112 In order to restore the initial state, the flow of the pain algorithm 40 is delayed. When it is determined in step 114 that the types of initial energy sensors are close to the optimal solution, the conditions of the two conditions can be limited, and the solution can be accelerated. Conversely, the clock delay is fine-tuned 4 2 to find. In step 116, pmax is maintained at the largest of the whole part of the buffer for two weeks. Each time the P is selected, the path delay is k for the path k and it is replaced on the path. 576997 V. Description of the invention (16) A buffering type is the maximum delay type.

大’因此可以減小時鐘歪曲率。步驟n8用來、:上延遲增 生的P_路徑延遲超過ρ_路徑延遲的情況。 1 X 便逐步減小適才增大路徑延遲的p ^步驟120 大於或等於路徑延遲，而、於〇_路：：遲仍然 116與120一旦調整緩衝器類型，則必須Γ新路v j、ife 序並找H，計算。“須更新路-延遲，排 =之步驟122判斷路徑匕X是否改變，主要是防止一種 寺殊以.饭设存在任一路徑P與目前最小路徑延遲？‘除 了树根之外，兩路徑尚有共有之緩衝器集合_存在，且 p的路徑延遲可能很接近Lx。接著按照演算法步驟增加 P^in的路徑延遲，假設改變到pmin與？兩路徑共有之缓衝器 集，Bp，min，而造成P的路徑延遲超過匕衫。此時雖然可以試 圖。周iPmin與P非共有之緩衝器集合的部分，希望可以使p 的路杈延遲減小，但由於可能會造成其它路徑上缓衝器的 一連串變化，可能導致演算法產生無窮迴圈的最壞情形。 因此對於此種狀況，便不再繼續進行快速調整缓衝器演算 法40，於是進入完整調整緩衝器演算法41。另外，步驟 114與122的判斷式可合併成為圖三中的步驟4〇 2，作為進 入置換緩衝器演算其它步驟的判斷條件。 第:，本發明之完整調整緩衝器演算法41。圖四的置換緩 衝為廣异法步驟3 9與4 0所提到的—些特殊案例，雖然它們Large 'can therefore reduce clock skew. Step n8 is used for the case where the P_path delay increased by the delay exceeds the ρ_path delay. 1 X will gradually decrease the path p to increase the path delay. ^ Step 120 is greater than or equal to the path delay, and in the __ road :: the delay is still 116 and 120. Once the buffer type is adjusted, the new path vj, ife must be sequenced. And find H, calculate. "It is necessary to update the path-delay, row = step 122 to determine whether the path X is changed. It is mainly to prevent a kind of temple. There is any path P and the current minimum path delay? ' A shared buffer set _ exists, and the path delay of p may be very close to Lx. Then follow the algorithm steps to increase the path delay of P ^ in, assuming a change to the buffer set shared by pmin and?, Bp, min , And the path delay of P exceeds the dagger. At this time, although you can try. Part of the buffer set that iPmin and P do not share, I hope to reduce the delay of p, but it may cause slowness on other paths. A series of changes in the buffer may cause the worst case of the infinite loop of the algorithm. Therefore, in this case, the fast adjustment buffer algorithm 40 is not continued, so the full adjustment buffer algorithm 41 is entered. In addition, The judgment formulas of steps 114 and 122 can be combined into step 402 in FIG. 3 as the judgment conditions for entering other steps of the replacement buffer calculation. Second: The complete adjustment buffer of the present invention Algorithm 41. The permutation buffer in Figure 4 is mentioned in steps 3 9 and 40 of the wide disparity method—some special cases, although they

576997 是無法應用 能與本發明 曲率限制有 做法，希望 困難，本發 最小化時鐘 實際的時鐘 ，便不強求 入啟發式觀 五、發明說明（17) 可能具有可行解，但 解。探究其原因，可 不變以致違反時鐘歪 明將應用較一般化的 為解決步驟39與4〇的 時鐘延遲」修改為r 束後再考慮是否符合 於問題的困難度增加 最佳化計算過程中加 延遲。 或不適用步驟40求最佳 所堅持pmax維持初始狀態 關。面對這些情形，本^發 依然能求得的合適的解。 明將原先欲求取「最小化 歪曲率」，直到演算法結 正曲率没计規範。並且由 最小的時鐘延遲，但仍於 念’還是盡可能減小路經 完整調整緩衝_开』、由1、+ μ 頰型凟异法41的步驟如圖十二。首春止 =為2,接著每往下'級階層數再加1:: 層數為L。接著衣^優先搜哥法計算階層數，求得最大的階 型30由第1階層開始設定緩衝器的類 第i階声最小’並挑選出？_ ’此時的路徑僅由 數大/ 、去衝态到第L階層的緩衝器。因每條路徑的階層 整緩衡Ϊ = ί目=，當步驟132由階層數大的往小的方向調 ^然合Ϊ埋^時，路徑較短的（即意謂路徑延遲小）後來 碎維^ 4· 乂大延遲的緩衝器，而路徑較長的便有可能繼 α、准持原先較大尺寸的緩衝器。 ^ 守釦延遲微調4 2。此演算法的主要功用乃是藉由微576997 can not be applied. It can have a method with the curvature limitation of the present invention, and it is difficult to hope. The present invention minimizes the actual clock, so it is not forced to enter the heuristic view. 5. Invention description (17) may have a feasible solution, but the solution. Investigate the reason, it may not change so that it violates the clock distortion. The more general application is to solve the clock delay of steps 39 and 40. Modify it to r beam and then consider whether it meets the difficulty of the problem. Increase the optimization calculation process. delay. Or not applicable Step 40 to find the best pmax insisted to maintain the initial state off. In the face of these situations, this paper can still find the appropriate solution. Ming Jiang originally wanted to "minimize distortion" until the algorithm concluded that the positive curvature was not standardized. And with the minimum clock delay, but still thinking about the path is still as small as possible. Completely adjust the buffer_on ”, the steps from 1, + μ buccal type method 41 are shown in Figure 12. The first spring stop = 2 and then the number of levels plus 1 :: is L. Next, search the brother method first to calculate the number of levels, and find the largest level 30. Set the buffer type from the first level. The i-th level sound is the smallest ”and selected? _ ”At this time, the path only consists of a large number /, and a flushing state to the L-th level buffer. Because the hierarchy of each path is slowly balanced = 目 目 =, when step 132 is adjusted from a large number of layers to a small one, the path is shorter (meaning that the path delay is small) and then broken. Dimensions 4 4 · 乂 large delay buffers, and long paths may follow α, quasi-hold the original larger buffer size. ^ Defer delay fine adjustment 4 2. The main function of this algorithm is

第21頁 五、發明說明（18) ----- 遲計^二緩衝态的種類，讓時鐘延遲更小。其概念源自延 徑延ί1當緩衝器的負載量變小後，其緩衝器延遲與路 ρ 都^ ^減小。因此為了讓時鐘延遲更小，在不改變 max的緩衝态及不增加時鐘歪曲率的條件下，試圖調整 "3Χ I斤有緩衝器的負載（即鄰近路徑的緩衝器）為最小尺 :的=衝器的等效輸入電容值減小，如此L上缓衝 口口曰]貞载1便會減輕。 利用圖三的你、土 生 & 實施例的相關資。：：：出提供作為測試本發明之五個 歪曲率上限14〇、皆設^、為^。在此假設五個實施例的時鐘 提供四種緩衝哭m ，緩衝器時序資料庫142共 線表列皆不同r由本，、選擇，各個實施例的時鐘樹電網排 符合時鐘歪曲率上^ 了:發現，因為實施例一與五皆無法 出結果。其餘三個^1此無時鐘延遲與時鐘歪曲率的輸 電網排線表列的輸二比較其輸入與更新後之時鐘樹 率確實已有改善。出…果，可發現其時鐘延遲與時鐘歪曲Page 21 V. Description of the invention (18) ----- Late counting ^ The two types of buffer states make the clock delay smaller. The concept is derived from the delay path. When the buffer load becomes smaller, both the buffer delay and the path ρ are reduced. Therefore, in order to make the clock delay smaller, without changing the buffer state of max and increasing the clock skew rate, try to adjust the load of the buffer with 3 × 1 kg (that is, the buffer of the adjacent path) to the minimum scale: = The equivalent input capacitance of the punch is reduced, so that the buffer port on L] will be reduced by 1. Use the relevant information for your, native & embodiment in Figure 3. ::: The upper limit of the five distortion rates provided for testing the present invention is 14 °, all of which are set to ^. It is assumed here that the clocks of the five embodiments provide four kinds of buffers. The collinear list of the buffer timing database 142 is different. The routing table of each embodiment conforms to the clock skew rate. It was found that the results could not be obtained because of Examples 1 and 5. The remaining three ^ 1 comparison of the input and the updated clock tree rate of the transmission grid layout table without clock delay and clock skew has indeed improved. Out of the results, you can find its clock delay and clock skew

第22頁 576997 五、發明說明（19) 簡言之，本發明提出一種快速選擇 的方法，可以配合已設定之時鐘樹 決定出緩衝器種類，使得時鐘延遲 率可以符合條件限制。本發明之快 種類演算工具，包括：輸入待處理 線路的資訊與緩衝器***的位置； 電路結構是否具有符合時鐘歪曲率 行解，進行快速或完整調整緩衝器 延遲求取最佳解；若無可行解，則 僅將判斷的結果輸出作為參考。 時鐘樹上 合成設計 可以最小 速決定時 的時鐘樹 初始狀態 限制的可 類型演算 不再進行 各緩衝 流程， 而且時 鐘樹中 結構， 設定； 行解； 法與微 最佳化 器種類 迅速地 鐘歪曲 緩衝器 包含各 判斷此 若有可 調時鐘 運算， 最後，上述所列的討論僅用以說明本發明的工作原理。許 多不同的實施例可由具一般技藝之人士修改而得，然其皆 不脫離本發明的精神與所申請的專利範圍。Page 22 576997 V. Description of the invention (19) In short, the present invention proposes a fast selection method, which can be used with the set clock tree to determine the type of buffer, so that the clock delay rate can meet the conditions. The fast-type calculation tool of the present invention includes: inputting the information of the line to be processed and the position where the buffer is inserted; whether the circuit structure has a solution that conforms to the clock distortion rate, and quickly or completely adjust the buffer delay to obtain the best solution; if not For a feasible solution, only the result of the judgment is used as a reference. Clock tree synthesis design can determine the minimum speed of the clock tree initial state when the type of calculation is no longer performed in each buffering process, and the clock tree structure, setting; solution; method and micro-optimizer types quickly clock distortion The buffer contains various judgments if there is an adjustable clock operation. Finally, the discussion above is only used to illustrate the working principle of the present invention. Many different embodiments can be modified by those skilled in the art without departing from the spirit of the invention and the scope of the applied patent.

第23頁 576997 圖式簡單說明 圖一 ：（a)為一簡單的1C晶片内部結構圖，（b)為（a)的時 鐘樹網路展開圖。 圖二：為一基本之I C設計佈局流程圖。 圖三：為特定實施例施行本發明之演算工具的輸入輸出方 塊圖。 圖四：為本發明之緩衝器置換演算法的方塊圖。 圖五：（a)表示連線的寄生RC電路，（b)為其RSPF格式線路 電性參數。 圖六：為緩衝器延遲值與輸出訊號斜率的資料庫查表計算 示意圖。 圖七：為本發明之延遲計算器的作法。 圖八：為本發明之緩衝器延遲計算器步驟流程圖。 圖九··為本發明之正反器線路延遲計算器步驟流程圖。 圖十：為本發明之快速判斷有無可行解演算法步驟流程 圖。 圖十一：為本發明之快速調整緩衝器類型演算法步驟流程 圖。 圖十二：為本發明之完整調整緩衝器類型演算法步驟流程 圖。Page 23 576997 Brief description of the diagram Figure 1: (a) is a simple internal structure diagram of a 1C chip, and (b) is an expanded view of the clock tree network of (a). Figure 2: Flow chart of a basic IC design layout. FIG. 3 is an input-output block diagram of a calculation tool for implementing the present invention for a specific embodiment. FIG. 4 is a block diagram of a buffer replacement algorithm according to the present invention. Figure 5: (a) shows the parasitic RC circuit of the connection, and (b) its electrical parameters of the RSPF format line. Figure 6: Schematic diagram of database lookup table calculation for buffer delay value and output signal slope. Figure 7: The method of the delay calculator of the present invention. FIG. 8 is a flowchart of steps of a buffer delay calculator according to the present invention. Figure IX is a flowchart of the steps of the flip-flop line delay calculator of the present invention. Figure 10: This is a flowchart of the steps of the rapid determination of the feasible algorithm of the present invention. FIG. 11 is a flowchart of the steps of the fast adjusting buffer type algorithm of the present invention. FIG. 12 is a flowchart of the steps of a complete adjustment buffer type algorithm according to the present invention.

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Claims (1)

〇^97 a 1請專利範圍 1 ·〜種快速決定拉於也L (:電路合成工，：其里步驟=器種類並滿足時序設計規範 的電\^數\理訊的成;^網排線表列，包含各線路 (b) ^ λ ^ ，、、後^ ^ ^序資料庫資訊· (〇::ϊ = ί的時序規範上限值’ 及 口异杰’計算時鐘樹網路各路徑的延遲；以 (2) ~套快速決定緩衝器類型演管 化並符合時鐘歪曲率設計;^"法，輸出時鐘延遲最小 列咬3於Φ 、執的最佳化時鐘樹雷锢iit綠主 1 疋輸出無法符合時鐘歪曲率限制的電網排線表 主如申請專利範圍第丨項所述之快 ，類並滿足時序設計規範的電路;疋時鐘樹上緩衝器 异器的組成包含： σ成工具，其路徑延遲計 (a) 一個緩衝器延遲計算器，計嘗 延遲與置換緩衝器類型後更新的政-為之間連線的線路 (b) —個正反器線路延遲計算器t延—遲；以及 接至正反器之間連線的最大與最。、彔母一由同一緩衝器 鐘延遲與時鐘歪曲率使用。搭配楱，延遲，提供計算時 小置換緩衝器後排序路徑延遲的計瞀:延遲計算器，以減 3 ·如申請專利範圍第1項所述之他、*、二 種類並滿足時序設計規範的電路合、’、疋枯鐘樹上緩衝器 衝器類型演算法的步驟包含： 工具’其快速決定緩〇 ^ 97 a 1 Please patent scope 1 ~~ Quick decision to pull the L (: circuit synthesis engineering, where the step = device type and meet the timing design specifications of the electrical \ ^ 数 \ 理 成 成; ^ network row Line table column, including each line (b) ^ λ ^,,, ^ ^ ^ ^ sequence database information · (〇 :: ϊ = ί timing specification upper limit value 'and Kou Yijie' calculation clock tree network each Path delay; (2) ~ Set to quickly determine the buffer type and manage it and meet the clock skew design; ^ " method, the minimum output clock delay is 3 to Φ, and the optimized clock tree is optimized. 锢 iit Green main 1 疋 The power grid wiring table whose output cannot meet the clock distortion rate limit. The main circuit is as fast as described in item 丨 of the scope of patent application, and it meets the timing design specifications. 缓冲器 The components of the buffer on the clock tree include: σ-forming tool, its path delay meter (a) a buffer delay calculator, which measures the updated political-to-connected line after delay and replacement of the buffer type (b) a flip-flop line delay calculator t delay—late; and the maximum and maximum of the connection to the flip-flop. The same buffer clock delay and clock skew rate are used. With 楱, delay, provides a calculation of the sequencing path delay after the small replacement buffer when calculating: delay calculator, minus 3 · Others as described in item 1 of the scope of patent application , *, Two types of circuits that meet the timing design specification, and the steps of the buffer punch type algorithm on the dead clock tree include: The tool 'its rapid decision delay