TW575911B - Method of rendering good material property and reducing resistivity of titanium nitride - Google Patents

Abstract

A method of rendering good material property and reducing resistivity of titanium nitride is disclosed. Firstly, a titanium nitride film is formed on a semiconductor substrate, which is followed by performing an ammonium treatment on the titanium nitride film to remove chlorine residue within. Then, a nitrogen plasma treatment process is performed on the titanium nitride to further remove impurities therein and thus reduce resistivity and stress thereof.

Description

575911 五、發明說明（1) 發明所屬之技術領域： . 本發明與一種使氮化鈦膜具有良好材料特性之方法有 關，特別是一種在化學氣相沈積法後，對其施以氮氣電漿處 理程序，以進一步移除位於其中之雜質，而降低其電阻值與 結構應力之相關方法。 先前技術： 隨著半導體工業持續的進展，在超大型積體電路（ULSI) 的開發與設計中，為了符合高密度積體電路之設計趨勢，各 式元件之尺寸皆降至次微米以下。由於元件不斷的縮小，也 導致在進行相關半導體製程時，其複雜程度亦不斷提高。因 此，積體電路的性能，除了依靠所含元件之性能及可靠度 外，更需要無數精密細微的金屬内連線，以便能有效傳遞元 件間的電子訊號。當前，積體電路設計，已朝著多重金屬内 連線發展。 在多重金屬内連線的相關製程中，鑲嵌製程 (d a m a s c e n e p r 〇 c e s s)的相關技術，受到廣泛的發展與運 用。 請參閱第一圖至第二圖，此兩圖揭露了傳統之鑲嵌製 程。首先沈積介電層1 2於半導體底材1 0上，接著利用微影蝕 刻程序，以形成鑲嵌開口 1 4於介電層1 2中。其中，此介電層 12之材料可選擇Si02、SiN4、SiON、PSG、以及BPSG，此外亦 可選擇具有低介電係數的材料。隨後，填充金屬於鑲嵌開口 1 4中，而形成内連線結構1 6 (如第四圖所示）。575911 V. Description of the invention (1) The technical field to which the invention belongs:. The invention relates to a method for making titanium nitride films with good material properties, especially after applying chemical vapor deposition to nitrogen plasma. A process to further remove impurities located therein while reducing its resistance and structural stress. Prior technology: With the continuous progress of the semiconductor industry, in the development and design of ultra large integrated circuits (ULSI), in order to meet the design trend of high density integrated circuits, the size of various components has been reduced to sub-micron. Due to the continuous shrinking of components, the complexity has also increased during the related semiconductor processes. Therefore, in addition to the performance and reliability of the contained components, the performance of integrated circuits also requires countless precision and fine metal interconnections in order to effectively transfer electronic signals between the components. Currently, integrated circuit designs have evolved toward multi-metal interconnects. Among the related processes of multi-metal interconnections, the related technology of the damascene process (d a m a s c e n e p r 0 c e s s) has been widely developed and used. Please refer to the first picture to the second picture. These two pictures reveal the traditional mosaic process. First, a dielectric layer 12 is deposited on the semiconductor substrate 10, and then a lithographic etching process is used to form a damascene opening 14 in the dielectric layer 12. Among them, Si02, SiN4, SiON, PSG, and BPSG can be selected as the material of the dielectric layer 12, and materials having a low dielectric constant can also be selected. Subsequently, filling metal is inserted into the openings 14 to form interconnect structures 16 (as shown in the fourth figure).

575911 五、發明說明（2) 然而，由於矽對填充的金屬有一定的固.態溶解度 (solid solubility)，使得含矽材料（如介電層與半導體 底材）與金屬的接觸接面（j u n c t i ο η)，容易發生擴散現象 而產生尖峰效應（spiking effect)，進一步導致半導體元 件的短路及失敗。因此，在半導體製程上通常會先形成一層 阻障層（b a r r i e r 1 a y e r)於含石夕材料與金屬層的接面，以 提高金屬對其他材質的附著能力。 請參閱第三圖，在填充金屬於鑲嵌開口 1 4之前，先形成 一層阻障層1 8於介電層1 2上，且沿著鑲嵌開口 1 4的表面覆 蓋，接著移除位於介電層1 2上表面之部分阻障層1 8，其中所 製作之阻障層1 8其較佳厚度約在1 0 0至5 0 0埃。之後，再填充 金屬於鑲嵌開口 1 4中以形成内連線結構2 0。 氬化鈦（Titanium nitride; TiN)，是現在 VLSI製程 裡使用最頻繁的一種阻障層材料。傳統上製作氱化鈦的方式 最主要分成物理氣相沈積法（p h y s 1 c a 1 v a p〇r d e p〇s i t l ο η ; P V D)以及化學氣相沈積法（c h e m i c a 1 v a p〇r deposition; CVD)兩種。在較先進的半導體製程中，由於 鑲嵌圖案開口的尺寸越做越小，導致鑲嵌圖案開口之高寬比 (a s p e c t r a t 1 〇)變大，在這樣的情況之下，阻障層的階梯 覆蓋能力就顯得相當重要。根據上述理由，利用氣化鈦 (T 1 C 1 4)與氨氣（N Η 在加熱環境下進行化學氣相沈積法 以形成氮化鈦的方式，於是被業界普遍採用。上述之化學氣 相沈積法包括主要沈積（main deposition)與氨氣處理程 序兩個步驟。575911 V. Description of the invention (2) However, because silicon has a certain solid solubility in the filled metal, the contact interface between silicon-containing materials (such as dielectric layers and semiconductor substrates) and metals (juncti ο η), it is prone to diffusion and spiking effect, which further causes short circuit and failure of semiconductor elements. Therefore, a barrier layer (b a r r e r 1 a y e r) is usually formed first on the semiconductor manufacturing process at the interface between the stone-containing material and the metal layer to improve the metal's adhesion to other materials. Referring to the third figure, before filling the metal with the damascene opening 14, a barrier layer 18 is formed on the dielectric layer 12 and covered along the surface of the damascene opening 14, and then the dielectric layer is removed. A part of the barrier layer 18 on the upper surface of the substrate 12 has a preferred thickness of about 100 to 500 angstroms. Thereafter, metal is filled in the inlaid openings 14 to form the interconnect structure 20. Titanium nitride (TiN) is one of the most frequently used barrier layer materials in the VLSI manufacturing process. Traditionally, the methods for making titanium hafnium are mainly divided into two types: physical vapor deposition (p h y s 1 c a 1 v a p0r d e p0s i t l ο η; P V D) and chemical vapor deposition (c h e m i c a 1 v a p0r deposition; CVD). In more advanced semiconductor processes, the size of the mosaic pattern openings becomes smaller and smaller, resulting in a larger aspect ratio (aspectrat 1 0) of the mosaic pattern openings. In this case, the step coverage of the barrier layer is reduced. It seems quite important. Based on the above reasons, the chemical vapor deposition method using titanium gas (T 1 C 1 4) and ammonia gas (N Η under a heating environment to form titanium nitride) is widely used in the industry. The above chemical vapor phase The deposition method includes two steps, a main deposition and an ammonia treatment process.

575911 五、發明說明（3) 主要沈積程序是利用氯化鈦（T 1 C 1 Ο與氨氣在加熱的 狀況下形成氮化鈦，其反應式如下： 6TiC14 (g) + 8NH3 (g) - 6T1N (s) + 24HC1 (g) + N2 (g) 氮化鈦形成之後，對其施以氨氣處理程序以移除位於其 中之氯殘留（Cl residues)。 内容： 本發明之主要目的為提供一種使氮化鈦膜具有良好之材 料特性，以降低其電阻值之方法。 本發明之另一目的為提供一種移除氮化鈦膜中之雜質， 以降低其結構應力之方法。 本發明之再一目的為提供一種在化學氣相沈積法後，對 氮化鈦膜施以氮氣電漿處理程序，以移除位於氮化鈦膜中雜 質之方法。 一種移除位於氮化鈦膜中之雜質以使其具有良好材料特 性之方法。首先，在半導體底材上之介電層中形成鑲嵌開 口 ，接著形成氮化鈦膜於介電層上，並沿著該鑲嵌開口之表 面均勻覆蓋。隨後，對氮化鈦膜施以氨氣處理程序，以移除 位於氮化鈦膜中的氯殘留。最後，對此氮化鈦膜施行氮氣電 漿處理程序，以進一步移除位於其中之雜質，並降低其電阻575911 V. Description of the invention (3) The main deposition procedure is to use titanium chloride (T 1 C 10 and ammonia gas to form titanium nitride under heating. The reaction formula is as follows: 6TiC14 (g) + 8NH3 (g)- After 6T1N (s) + 24HC1 (g) + N2 (g) titanium nitride is formed, it is subjected to an ammonia gas treatment procedure to remove Cl residues therein. Content: The main purpose of the present invention is to provide A method for making titanium nitride film with good material characteristics to reduce its resistance value. Another object of the present invention is to provide a method for removing impurities in titanium nitride film to reduce its structural stress. Yet another object is to provide a method for removing the impurities in the titanium nitride film by applying a nitrogen plasma treatment process to the titanium nitride film after the chemical vapor deposition method. Method for making impurities have good material characteristics. First, a damascene opening is formed in a dielectric layer on a semiconductor substrate, then a titanium nitride film is formed on the dielectric layer, and the surface is uniformly covered along the damascene opening. Subsequently, ammonia was applied to the titanium nitride film. Handler positioned to remove the residual chlorine in the titanium nitride film. Finally, this implementation of the titanium nitride film is electrically nitrogen plasma treatment process to further remove the impurities therein, and to lower its electric resistance

575911 五、發明說明（4) 值及結構應力。 . 實施方式： 本發明揭露了一種移除氣化鈦膜中之雜質以使氣化鈦膜 具有良好材料特性之方法。其中於利用化學氣相沈積法以形 成氮化鈦膜後，對其施以氮氣電漿處理程序以進一步移除位 於其中之雜質，而降低其電阻值與結構應力。有關本發明的 詳細製程與實施例如下所述。 首先請參照第五圖，沈積介電層5 2於半導體底材5 0上。 其中此半導體底材5 0可為一 < 1 0 0 >或< 1 1 1 >晶向之單晶矽或是 位於絕緣層上之石夕基底（silicon on insulator， SOI) 等，且在形成介電層5 2以前，半導體底材5 0上已製作了積體 電路所需之各式主動元件、被動元件、與週圍電路等等（未 標示於圖中）。換言之，在此半導體底材5 0的表面上，已具 有各式所需之功能層與材料層。至於介電層5 2之製作，則可 由氧化矽或氮化矽來形成。例如，利用化學氣相沈積法以四 乙基矽酸鹽（TE0S)可形成氧化矽，或者在大約4 0 0至4 5 0° C的爐中通入反應氣體SiH4，N2〇及N Η 3，而形成氮化石夕。另 外，亦可以低壓化學氣相沉積法（LPCVD)形成氣碎玻璃 (FSG)或未摻雜矽玻璃（USG)，來構成上述之介電層52。 一般說來，此介電層5 2除了可由上述這些材料構成，亦可選 擇具有低介電係數的材料。 接著仍請參照第五圖，對介電層5 2施以微影蝕刻程序， 在介電層52中形成鑲嵌開口 54，且曝露出半導體底材50之部575911 V. Description of the invention (4) Value and structural stress. Embodiments: The present invention discloses a method for removing impurities in a vaporized titanium film so that the vaporized titanium film has good material characteristics. After the chemical vapor deposition method is used to form a titanium nitride film, a nitrogen plasma treatment process is performed on the titanium nitride film to further remove impurities therein, thereby reducing its resistance value and structural stress. The detailed processes and examples of the present invention are described below. First, referring to the fifth figure, a dielectric layer 52 is deposited on the semiconductor substrate 50. The semiconductor substrate 50 may be a < 1 0 0 > or < 1 1 1 > crystal-oriented single crystal silicon or a silicon on insulator (SOI) on an insulating layer, etc., Before the dielectric layer 52 is formed, various active components, passive components, and surrounding circuits required for integrated circuits have been fabricated on the semiconductor substrate 50 (not shown in the figure). In other words, on the surface of this semiconductor substrate 50, there are already various functional layers and material layers required. As for the fabrication of the dielectric layer 52, it can be formed of silicon oxide or silicon nitride. For example, chemical vapor deposition can be used to form silicon oxide with tetraethyl silicate (TE0S), or the reaction gases SiH4, N2O, and NΗ3 can be passed into a furnace at about 400 to 450 ° C. And form nitride nitride. In addition, a low-pressure chemical vapor deposition (LPCVD) method can be used to form a gas-ground glass (FSG) or an undoped silica glass (USG) to form the above-mentioned dielectric layer 52. Generally speaking, in addition to the above-mentioned materials, the dielectric layer 52 may be made of a material having a low dielectric constant. Next, referring to the fifth figure, a lithography etching process is performed on the dielectric layer 52 to form a damascene opening 54 in the dielectric layer 52, and a portion of the semiconductor substrate 50 is exposed.

575911 五、發明說明（5) 分上表面。一般而言，在定義上述鑲欲開口.5 4日夺，可先在介 電層5 2上先形成光阻層（未顯示於圖中），繼而轉移光罩上 之鑲喪開口圖案至光阻層中。接著，利用此光阻層作為I虫刻 罩冪，對介電層5 2進行蝕刻程序，而定義鑲嵌開口 5 4於其 中 。 請參閱第六圖，當鑲嵌開口 5 4定義完成後，接著形成氮 化鈦膜5 6於介電層5 2上，且沿著鑲嵌開口 5 4的表面覆蓋。其 中，此氮化鈦膜5 6是作為一阻障層使用，防止後續填充於鑲 嵌開口 54中之金屬，與介電層52及半導體底材50間產生尖峰 效應。在本發明之實施例中，形成氮化鈦膜的方式為化學氣 相沈積法，且其較佳厚度約介於5 0至1 0 0 0埃，其中，此方法 包含了下列步驟： 首先，藉由主要沈積步驟，利用氯化鈦（T 1 C 1 4)與氨 氣在加熱的狀況下形成氮化鈦，其反應式如下： 6 T 1 C 1 4 ( g ) + 8 N Η 3 ( g ) - 6 T 1 N ( s ) + 2 4 H C 1 ( g ) + N 2 (g ) 由上式可知，此步驟會沈積固態的氮化鈦在介電層5 2之 上表面，且沿著鑲嵌開口 5 4的表面覆蓋。之後，對此氮化鈦 膜5 6施以氨氣處理步驟，以移除位於其中之氣殘留。 在氨氣處理步驟後，接續施行氮氣電漿處理程序，以進一步 去除位於氮化鈦膜.5 6中之雜質。其中，施行此程序的相關條 件為：時間介於3 0至9 0秒，壓力為1至1 0 t 〇 r r，射頻功率 (radio frequency power)為 400至 1000瓦特，溫度言支在 4 0 0至7 0 0°C ，且氮氣的流速（f 1 〇 w r a t e)為5 0 0至2 0 0 0575911 Fifth, the description of the invention (5) points on the upper surface. Generally speaking, in the definition of the above-mentioned inlay opening. 5 4th, you can first form a photoresist layer (not shown) on the dielectric layer 52, and then transfer the inlay opening pattern on the photomask to light Barrier layer. Then, the photoresist layer is used as a lithography mask to perform an etching process on the dielectric layer 5 2 to define a mosaic opening 54 in it. Referring to the sixth figure, after the definition of the mosaic openings 5 4 is completed, a titanium nitride film 56 is formed on the dielectric layer 52 and covered along the surface of the mosaic openings 5 4. Among them, the titanium nitride film 56 is used as a barrier layer to prevent the subsequent filling of the metal in the embedded opening 54 with a spike effect between the dielectric layer 52 and the semiconductor substrate 50. In the embodiment of the present invention, the method for forming the titanium nitride film is a chemical vapor deposition method, and its preferred thickness is between 50 and 100 angstroms. The method includes the following steps: First, The main deposition step uses titanium chloride (T 1 C 1 4) and ammonia to form titanium nitride under heating. The reaction formula is as follows: 6 T 1 C 1 4 (g) + 8 N Η 3 ( g)-6 T 1 N (s) + 2 4 HC 1 (g) + N 2 (g) As can be seen from the above formula, this step will deposit solid titanium nitride on the surface of the dielectric layer 5 2 and The surface of the mosaic opening 5 4 is covered. Thereafter, an ammonia gas treatment step is performed on the titanium nitride film 56 to remove the gas residues located therein. After the ammonia gas treatment step, a nitrogen plasma treatment process is successively performed to further remove impurities located in the titanium nitride film .56. The relevant conditions for implementing this procedure are: time is between 30 and 90 seconds, pressure is between 1 and 10 t 〇rr, radio frequency power is between 400 and 1000 watts, and temperature is between 40 and 0 To 7 0 ° C and the flow rate of nitrogen (f 1 〇wrate) is 5 0 0 to 2 0 0 0

第8頁 575911 五、發明說明（6) s c c hi。在一較佳實施例中，可將施行此程序.的條件設定成： 時間為6 0秒，壓力為4 . 8 t 〇 r r，射頻功率為8 0 0瓦特，溫度 為6 5 0°C ，且氮氣流速定在1 0 0 0 s c c πι。 接著如第七圖所示，沈積金屬層5 8於氮化鈦膜5 6上表面 且填充於鑲嵌開口 5 4中，隨後依序移除位於介電層5 2上表面 之部分金屬層5 8與部分氮化鈦膜5 6，以形成内連線結構。 利用本發明具有下列優點： (1) 降低氮化鈦膜之電阻值與結構應力。請參閱表 一，由表中可以很明顯的看出在傳統的化學氣相沈積法形成 氮化鈦膜之後，再接續對其施以氮氣電漿處理程序，可明顯 使氮化鈦膜層之電阻值減少4 8 %，且結構應力亦減少4 5 % ; (2) 所形成之氮化鈦膜即使置於空氣中長達4 8小時， 其電阻值依舊未提高。由表二中可以發現，單獨利用化學氣 相沈積法所形成之氮化鈦膜，置於空氣中4 8小時後，其電阻 值會提高5 . 2 %，然而，利用本發明之方法所形成之氮化鈦 膜，放置於空氣中不同時間，其電阻值幾乎無任何改變； (3) 增加氮化鈦膜之抵抗氧化能力（ο X 1 d a t i〇η resistance capacity)。如表三所示，單獨使用化學氣相 沈積法所形成之氮化鈦膜，在進行氧化反應4分鐘之後，其 電阻值增加至原來的1 1 . 5倍左右；而使用本發明之方法所形 成之氮化鈦膜，在進行氧化反應4分鐘之後，其電阻值增加 至原來的3倍。這樣的結果顯示利用本發明所形成之氮化鈦 膜其抵抗氧化的能力提高；以及Page 8 575911 V. Description of the invention (6) s c c hi. In a preferred embodiment, the conditions for performing this procedure can be set as follows: time is 60 seconds, pressure is 4.8 t rr, RF power is 800 watts, temperature is 6 50 ° C, And the nitrogen flow rate is set at 100 scc πm. Next, as shown in the seventh figure, a metal layer 5 8 is deposited on the upper surface of the titanium nitride film 56 and filled in the mosaic opening 54, and then a part of the metal layer 5 8 on the upper surface of the dielectric layer 52 is sequentially removed. And a portion of the titanium nitride film 56 to form an interconnect structure. Utilizing the present invention has the following advantages: (1) Reduce the resistance value and structural stress of the titanium nitride film. Please refer to Table 1. It can be clearly seen from the table that after the conventional chemical vapor deposition method is used to form a titanium nitride film, and then applying a nitrogen plasma treatment program to it, the titanium nitride film layer can be significantly changed. The resistance value is reduced by 48%, and the structural stress is also reduced by 45%; (2) Even if the titanium nitride film formed is left in the air for 48 hours, its resistance value has not improved. From Table 2, it can be found that the resistance value of the titanium nitride film formed by using the chemical vapor deposition method alone is increased by 5.2% after being left in the air for 48 hours. However, the method formed by the method of the present invention The titanium nitride film has almost no change in resistance value when placed in air for different times; (3) Increase the oxidation resistance of titanium nitride film (ο X 1 dati〇η resistance capacity). As shown in Table III, the resistance value of the titanium nitride film formed by using the chemical vapor deposition method alone is increased to about 1 1.5 times after the oxidation reaction is performed for 4 minutes; and the method of the present invention is used. After the formed titanium nitride film was subjected to an oxidation reaction for 4 minutes, its resistance value increased to three times the original value. Such results show that the titanium nitride film formed using the present invention has improved resistance to oxidation; and

第9頁 575911 五、發明說明（7) (4)利用本發明之方式形成氮化鈦膜·，以作為金屬-介 電層-金屬（metal-insulator-metal; MIM)電容器之底部 電極時’可降低電流漏）¾ ( 1 e a k a g e)之情形。 本發明雖以一較佳實例闡明如上，然其並非用以限定本 發明精神與發明實體，僅止於此一實施例爾。是以，在不脫 離本發明之精神與範圍内所作之修改，均應包含在下述之申 請專利範圍内。Page 9 575911 V. Description of the invention (7) (4) When using the method of the present invention to form a titanium nitride film as the bottom electrode of a metal-insulator-metal (MIM) capacitor ' Can reduce current leakage) ¾ (1 eakage). Although the present invention is explained above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. Therefore, all modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below.

第10頁 575911 圖式簡單說明 圖式簡單說明： 將可輕易的了解上 藉由以下詳細之描述結合所附圖示 述内容及此項發明之諸多優點，其中： 顯不根據目前業界技術 顯不根據目前業界技術 顯不根據目前業界技術 顯不根據目前業界技術 顯示根據本發明形成鑲 顯示根據本發明形成氮 第 形成鑲 第 製作内 第 形成阻 第 製作内 第 嵌開口 第 化鈦膜 第 屬層於 一圖為半導體晶圓之戴面圖 嵌開口於介電層中之步驟； 二圖為半導體晶圓之截面圖 連線結構之步驟； 三圖為半導體晶圓之截面圖 障層於鑲嵌開口表面之步驟 四圖為半導體晶圓之截面圖 連線結構之步驟； 五圖為半導體晶圓之截面圖 於介電層中之步驟； 六圖為半導體晶圓之截面圖 於鑲嵌開口表面之步驟；以及 七圖為半導體晶圓之截面圖，顯示根據本發明形成金 氮化鈦膜上表面之步驟。 圖號對照表： 半導體底材1 鑲嵌開口 1 4 阻障層1 8 介電層1 2 内連線結構1 6 内連線結構2 0Page 575911 Simple illustration of the diagram Simple illustration of the diagram: It will be easy to understand the following detailed description combined with the attached diagram and the many advantages of this invention, of which: According to the current industry technology, the display is based on the current industry technology. The display is formed according to the present invention. The display is formed according to the present invention. The nitrogen is formed according to the present invention. The first figure shows the steps of embedding the semiconductor wafer with the opening in the dielectric layer; the second figure shows the steps of the semiconductor wafer cross-section wiring structure; the third figure shows the cross section of the semiconductor wafer. The fourth step of the surface is the step of the wiring structure of the cross section of the semiconductor wafer. The fifth step is the step of the cross section of the semiconductor wafer in the dielectric layer. The sixth step is the step of the cross section of the semiconductor wafer on the opening surface And FIG. 7 is a cross-sectional view of a semiconductor wafer, showing a step of forming an upper surface of a gold titanium nitride film according to the present invention. Drawing number comparison table: semiconductor substrate 1 inlay opening 1 4 barrier layer 1 8 dielectric layer 1 2 interconnect structure 1 6 interconnect structure 2 0

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Claims (1)

575911 六、申請專利範圍 1. 一種使氮化鈦膜具有良好之材料特性且降.低其電阻值之方 法，首先形成氮化鈦膜於半導體底材上，接著對該氮化鈦膜 進行氨氣處理程序，以移除位於其中之氯殘留，其特徵在 於： 於該氨氣處理程序後，對該氮化鈦膜施以氮氣電漿處理 程序，以進一步移除位於其中之雜質，而降低其電阻值與結 構應力。 2 .如申請專利範圍第1項之方法，其中上述之氮氣電漿處理 程序，其處理時間約為3 0至9 0秒。 3.如申請專利範圍第1項之方法，其中上述之氮氣電漿處理 程序，其壓力約為1至10 to rr。 4 .如申請專利範圍第1項之方法，其中上述之氮氣電漿處理 程序，其射頻功率約為4 0 0至1 0 0 0瓦特。 5 .如申請專利範圍第1項之方法，其中上述之氪氣電漿處理 程序，其溫度約為4 0 0至7 0 0°C。 6 .如申請專利範圍第1項之方法，其中上述之氮氣電漿處理 程序，其氮氣的流速約為5 0 0至2 0 0 0 s c c hi。 7. —種形成阻障層之方法，其中在半導體底材上已具有鑲嵌575911 VI. Application Patent Scope 1. A method to make titanium nitride film have good material properties and reduce its resistance value. First, a titanium nitride film is formed on a semiconductor substrate, and then the titanium nitride film is subjected to ammonia. A gas treatment program to remove chlorine residues located therein is characterized in that: after the ammonia gas treatment program, a nitrogen plasma treatment program is applied to the titanium nitride film to further remove impurities located therein and reduce Its resistance value and structural stress. 2. The method according to item 1 of the patent application range, wherein the above-mentioned nitrogen plasma processing procedure has a processing time of about 30 to 90 seconds. 3. The method according to item 1 of the patent application range, wherein the pressure of the above-mentioned nitrogen plasma treatment procedure is about 1 to 10 to rr. 4. The method according to item 1 of the patent application range, wherein the above-mentioned nitrogen plasma treatment procedure has a radio frequency power of about 400 to 100 watts. 5. The method according to item 1 of the scope of patent application, wherein the temperature of the above radon plasma treatment procedure is about 400 to 700 ° C. 6. The method according to item 1 of the scope of patent application, wherein the nitrogen plasma treatment procedure described above has a nitrogen flow rate of about 500 to 2 0 0 0 c c hi. 7. —A method for forming a barrier layer, wherein a semiconductor substrate has a damascene 575911 六、申請專利範圍 開口 ，該方法至少包含下列步驟： . 形成阻障層於該半導體底材上，並沿著該鑲嵌開口之表 面均勻覆蓋； 對該阻障層施以氨氣處理程序，以移除位於該阻障層中 的氣殘留，以及 於該氨氣處理程序後，對該阻障層施行氮氣電漿處理程 序，以進一步移除位於其中之雜質，並降低其電阻值及結構 應力。 8 .如申請專利範圍第7項之方法，其中上述之氮氣電漿處理 程序，其處理時間約為3 0至9 0秒。 9 .如申請專利範圍第7項之方法，其中上述之氤氣電漿處理 程序，其壓力約為1至1 0 t 〇 r r。 1 0 .如申請專利範圍第7項之方法，其中上述之氮氣電漿處理 程序，其射頻功率約為4 0 0至1 0 0 0瓦特。 1 1 .如申請專利範圍第7項之方法，其中上述之氮氣電漿處理 程序，其溫度約為4 0 0至7 0 0°C。 1 2 .如申請專利範圍第7項之方法，其中上述之氮氣電漿處理 程序，其氮氣的流速約為5 0 0至2 0 0 0 s c c m。575911 VI. Patent application opening, the method includes at least the following steps: forming a barrier layer on the semiconductor substrate and covering it uniformly along the surface of the mosaic opening; applying an ammonia treatment process to the barrier layer, In order to remove the gas residues in the barrier layer, and after the ammonia gas treatment process, a nitrogen plasma treatment process is performed on the barrier layer to further remove impurities located therein and reduce its resistance value and structure stress. 8. The method according to item 7 of the patent application range, wherein the nitrogen plasma processing procedure described above has a processing time of about 30 to 90 seconds. 9. The method according to item 7 of the scope of patent application, wherein the pressure of the above-mentioned radon gas plasma treatment procedure is about 1 to 10 ton. 10. The method according to item 7 of the scope of patent application, wherein the above-mentioned nitrogen plasma treatment procedure has a radio frequency power of about 400 to 100 watts. 11. The method according to item 7 of the scope of patent application, wherein the temperature of the above-mentioned nitrogen plasma treatment procedure is about 400 to 700 ° C. 12. The method according to item 7 of the scope of patent application, wherein the nitrogen plasma treatment procedure described above has a nitrogen flow rate of about 500 to 2000 c s m.