TW573358B - Flash memory device structure and manufacturing method thereof - Google Patents
Flash memory device structure and manufacturing method thereof Download PDFInfo
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573358 五、發明說明（1) 發之技術 本發明是有關於一種 二573358 V. Description of the invention (1) Technology of the invention
Memory，NVM)元伴，〇 & 务性 έ己憶體（non-Volatile i特別《古μ 之結構及其製造方法。 疋有關於一種快閃記憶體元件 先前技避 快閃記憶體元件由於具 取、抹除等動作，且存入之I =夕：人進行資料之存入、讀 點’所以已成為個人電腦* 2在斷電後也不會消失之優 揮發性記憶體元件。 电子設備所廣泛採用的一種非 典型的快閃記憶體元件係 極（Float ing Gate)與控制η朽彳/的夕晶矽袅作浮置閘 控制閘極係直接設置在浮置閘 * 而且 夕門以μ八帝g 4 1上/于置閘極與控制閘極 之間以閘間介電層相隔，而淫罟 MTnnnd η ^ , 置閘極與基底間以穿隧氧化 層（Τ二0xlde)相隔（亦即所謂堆疊閘極快閃記憶體）。 *對快閃記憶體進行資料寫入之操作時，係藉由於控 制閘極與源極/汲極區施加偏壓，以使電子注入浮置開極 中。在讀取快閃記憶體中的資料時，係於控制閘極上^施1加 一工作電壓，此時浮置閘極的帶電狀態會影響其下通道 (Channe 1 )的開/關，而此通道之開/關即為判讀資料值 「0」或「1」之依據。當快閃記憶體在進行資料之抹除 時，係將基底、汲（源）極區或控制閘極的相對電位提高， 並利用穿隧效應使電子由浮置閘極穿過穿隨氧化I ^ (Tunneling Oxide)而排至基底或沒（源）極中（即Memory (NVM) element companion, 0 & service-oriented memory (non-Volatile i special "the structure of ancient μ and its manufacturing method. 疋 There is a flash memory device, the previous technology to avoid flash memory devices due to It has actions such as taking and erasing, and the stored value is I = evening: people carry on the data storage and reading point, so it has become a personal computer * 2 a superior volatile memory element that will not disappear even after power failure. Electronics An atypical flash memory element system (Float ing Gate) widely used in the equipment and a silicon gate that controls η / 彳 is used as a floating gate. The control gate is directly installed on the floating gate * and the gate It is separated by a gate dielectric layer between the gate and the control gate by μ eight emperors g 4 1, and MTnnnd η ^, and a tunnel oxide layer between the gate and the substrate (T2 0xlde) Separated (also known as stacked gate flash memory). * When writing data to the flash memory, the control gate and source / drain regions are biased so that electrons are injected into the floating Set in the open pole. When reading the data in the flash memory, it is tied to the control gate ^ 1 plus A working voltage, at this time, the charged state of the floating gate will affect the opening / closing of its lower channel (Channe 1), and the opening / closing of this channel is the basis for judging the data value "0" or "1". When When erasing data, the flash memory increases the relative potential of the substrate, the drain (source) region, or the control gate, and uses the tunneling effect to pass electrons from the floating gate through the penetrating oxide I ^ (Tunneling Oxide) and into the base or the (source) (ie
Substrate Erase 或 Drain (Source) Side Erase)，戈Substrate Erase or Drain (Source) Side Erase), Go
573358573358
是穿過閘間介電層而排至控制閘極中。 請參照第1圖所繪示之習知堆疊閘極式快閃記憶體 (Stack Gate Flash memory)之結構示意圖（美國專利 U S 6 2 1 4 6 6 8 )。此快閃記憶體是由位於p型基底丨〇 〇中之深n 型井區102、位於P型基底丨00上之堆疊閘極結構1〇6、位於 堆疊閘極結構1 〇 6兩側之P型基底1 〇 0中之源極區丨〇 8與汲極 區1 1 0、位於堆疊閘極結構1 〇 6之側壁上之間隙壁丨丨2、位 於深N型井區1 〇 2中，且從汲極區1 1 〇延伸至堆疊閘極結構 1 0 6 (穿隨氧化層1 2 0、浮置閘極1 2 2、閘極介電層1 2 4、控 制閘極126與閘極頂蓋層128)下方之P型井區丨04、位於p型 基底100上之内層介電層114、穿過内層介電層114與P型基 底100使汲極區110與p型井區1〇4短路連接在一起之接觸窗 116、位於内層介電層114上，並與接觸窗lie電性連接之 導線1 18所構成。 然而，隨著積體電路正以更高的集積度朝向小型化的 元件發展，上述快閃記憶體結構會產生下述之問題點。舉 例來說’為了增加記憶體元件之集積度，而需要縮小快閃 記憶體元件之記憶胞尺寸。其中，縮小記憶胞之尺寸可藉 由減小§己憶胞的閘極長度與資料線的間隔等方式來達成。 但是，閘極長度變小會縮短了穿隧氧化層丨2〇下方的通道 長度（Channel Length)，容易造成汲極區與源極區jog 之間發生不正常的電性貫通（punch Through)，如此將嚴 重影響此記憶胞的電性表現。而且，在快閃記憶體的製造 過程中’微影製程也會有所謂關鍵尺寸之問題，而限制記It passes through the inter-gate dielectric layer and is discharged into the control gate. Please refer to the structure diagram of the conventional stack gate flash memory shown in FIG. 1 (U.S. patent US 6 2 1 4 6 6 8). The flash memory is composed of a deep n-type well region 102 located on a p-type substrate, 00, a stacked gate structure 10 on the p-type substrate, 00, and two sides of the stacked gate structure 106. Source region in the P-type substrate 100 and the drain region 1 10, a spacer located on the side wall of the stacked gate structure 1 06, 2 and a deep N-type well region 1 2 And extend from the drain region 1 10 to the stacked gate structure 106 (through the oxide layer 12 20, the floating gate 1 2 2, the gate dielectric layer 1 2 4, the control gate 126 and the gate The P-type well region below the polar cap layer 128) 04, the inner dielectric layer 114 on the p-type substrate 100, the drain region 110 and the p-type well region 1 through the inner dielectric layer 114 and the P-type substrate 100 〇4 is formed by a short-circuited contact window 116, which is located on the inner dielectric layer 114, and is electrically connected to the contact window lie. However, as integrated circuits are being developed toward miniaturized components with a higher degree of integration, the above-mentioned flash memory structure may cause the following problems. For example, in order to increase the integration degree of the memory elements, it is necessary to reduce the memory cell size of the flash memory elements. Among them, reducing the size of the memory cell can be achieved by reducing the gate length of the memory cell and the interval between the data lines. However, a smaller gate length shortens the channel length below the tunneling oxide layer 20, which easily causes abnormal electrical penetration between the drain region and the source region jog. This will seriously affect the electrical performance of this memory cell. Moreover, in the flash memory manufacturing process, the lithography process also has the problem of the so-called critical size, which limits the
10326twf.ptd 第7頁 ^/3358 五、發明說明（3) ::::的，小。此外，由於汲極區11〇 :。構106下方’因此當記憶胞尺寸縮小時食文間 在侧向方向可能句拉、、芬扛Pt井區1 〇 4 b匕住，及極& (N +型摻雜）不夠多，卷 ==二：源極區為6伏特左☆，則汲極區為化 曰=朋潰而影響相鄰快閃記憶胞的正常操作。因' ，習知之快閃記憶胞結構會有集積度受限 發明内客 研點。 1 =於此，本發明之目的在於提供一種快 與汲極區(〇ν; = Ϊ/ρ可：避免在程式化時源極區(6V) 高記憶體元件之積ί 讣一)現象’並能夠提 有鑑於此，太就 此快閃記憶體元件提供一種快閃記憶體元件之結構， 基底、設置於第—遂、、告構，是由具有一開口之第一導電型 設置於開口底部與：電型基底十之第二導電变第-井區、 壁之穿隧介電戶上 > 壁之穿随介電層、分別設置於開口側 於第一浮置閘i盘第第一浮置開極與第二浮置間極、設置 第一導電型美底Ϊ二浮置間極上之問間介電層、設置於 -控制間極；伸覆Ϊ第一控制開極與第二控制閘極，且第 延伸覆蓋第二浮置^-浮置閑極之側；，第二控制間極 二控制間極之間的；之侧壁、㉝置：第：控：開極與第 ^ _ u刃間隙之絕緣層、設置於第一控制閘極與 ΐ :A閘極之側髮上之間隙壁、設置於開口底部之第-V私型土底中之源极區、設置於間隙壁下方的第一導電型10326twf.ptd Page 7 ^ / 3358 V. Description of the invention (3) ::::, small. In addition, due to the drain region 110 :. Below the structure 106, therefore, when the size of the memory cell is reduced, the food may be pulled in the lateral direction, and the Pt well area is held by 104 d, and the poles & (N + type doping) are not enough. == 2: The source region is 6 volts left ☆, then the drain region is changed, which affects the normal operation of adjacent flash memory cells. Because of this, the conventional flash memory cell structure will have a limited integration degree. 1 = Here, the purpose of the present invention is to provide a fast and drain region (〇ν; = Ϊ / ρ can: avoid the product of the source region (6V) high memory element during programming). In view of this, it is possible to provide a flash memory device structure for the flash memory device. The base, the first, the first, and the second structure are provided at the bottom of the opening by a first conductive type having an opening. And: The second conductive transformation of the electric substrate 10-well area, the wall of the tunnel dielectric user > The wall through the dielectric layer is located on the opening side and the first floating gate i disk first The floating open electrode and the second floating intermediate electrode, the first conductive type bottom layer, the interlayer dielectric layer on the second floating intermediate electrode, and the control electrode are arranged; the first control open electrode and the second conductive electrode are extended and covered. The control gate, and the first extension covers the side of the second floating ^ -floating idle pole; between the second control intermediate pole and the second control intermediate pole; the side wall and the arrangement: the first: the control: the open pole and the second ^ _ u Insulation layer of the blade gap, the first control gate and the ΐ: the gap wall on the side of the A gate, the -V private soil at the bottom of the opening A source region in the bottom, a first conductivity type disposed below the gap wall
10326twf.ptd 第8頁 573358 五、發明說明（4) 基底中之汲極區、設置 電型第二井區，且第一 井區之接面高於開口底 導電型基底 口袋摻雜區 在上述 電性短路連 中之一第 連接第一 結構中， 導 汲 區與第一導 括設置該第 電層上，並 在本發 隧介電層、 第一導電型 別設置於開 道區是設置 此可以藉由 免元件尺寸 度。 本發明 方法係先提 接一起。其 電型第二井 一導電型基 與接觸窗電 明之快閃記 浮置閘極、 基底内之開 口頂部周圍 於開口側壁 控制開口之 縮小時所產 於第二 導電型 部以及 導電型 電型第 極區與 中，電 區間之 底上之 性連接 憶體元 閘間介 口側壁 與底部 導電型 第二井 設置於 口袋摻 二井區 第一導 性短路 接面。 内層介 之導線 件之結 電層、 上，且 之第一 之P型基底中（ 深度準確的控 生的問題，並 第一井區中之第一導 區與第二導電型第一 該開口側壁之該第一 雜區，且第一導電型 與源極區。 電型第二井區係以一 係以接觸窗貫穿汲極 而且，上述結構更包 電層與設置於内層介 〇 構中，閘極結構（穿 控制閘極）係設置於 >及極區、源極區係分 導電型基底中，其通 垂直式通道區），因 制通道長度，而能避 可以增加元件集積 另外提供一種快閃記憶體元件之製造方法，此 供第一導電型之基底，且此基底内已形成第二 井區。接著，於基底上依序形成襯層與罩幕層 後，圖案化罩幕層、襯層與基底，以於基底中形成一開 口。於開口中形成穿隧介電層後，於開口側壁之基底中形 成第一導電型口袋摻雜區。然後，於開口之側壁形成第一 導電型第10326twf.ptd Page 8 573358 V. Description of the invention (4) The drain region in the substrate, the second well region of the electric type is set, and the interface of the first well region is higher than the open bottom conductive type substrate pocket doped region in the above One of the electrical short circuits is connected to the first structure, and the drain region and the first channel are disposed on the first electrical layer, and the dielectric layer and the first conductivity type of the tunnel are set in the open area. With no component size. The method of the present invention is first mentioned together. The second conductive type base of the electrical type has a flash type floating gate electrode with a conductive type base and a contact window, and is formed in the second conductive type portion and the conductive type electrical component when the opening side wall around the top of the opening in the substrate controls the shrinkage of the opening. The sexual connection on the bottom of the polar region, the middle and the electrical region is connected to the side wall of the interface between the memory element gate and the second conductive bottom well of the conductive type. In the inner layer of the lead wire, the junction layer, the upper, and the first P-type substrate (the problem of accurate depth control), and the first conductive region in the first well region and the second conductive type first the opening The first miscellaneous region of the side wall, and the first conductivity type and the source region. The electrical type second well region is a series of through the drain electrode with a contact window. Moreover, the above structure further includes an electrical layer and is disposed in the inner layer structure. The gate structure (through the control gate) is arranged in the conductive substrates of the polar region and the source region, which pass through the vertical channel region). Due to the length of the channel, it can be avoided to increase the component accumulation. A method for manufacturing a flash memory device is provided, which is for a substrate of a first conductivity type, and a second well region has been formed in the substrate. Then, after the liner layer and the cover layer are sequentially formed on the substrate, the cover layer, the liner layer and the substrate are patterned to form an opening in the substrate. After the tunneling dielectric layer is formed in the opening, a first conductive type pocket doped region is formed in the substrate on the side wall of the opening. Then, a first conductive type first is formed on the side wall of the opening.
10326twf.ptd 第9頁 573358 五、發明說明（5) 浮置閘極與第二浮置閘極，並於開口底部形成源極區。於 開口中形成閘間介電層後，於開口之側壁形成第一控制閘 極與第二控制閘極，且第一控制閘極延伸覆蓋第一浮置閘 極之侧壁，第二控制閘極延伸覆蓋第二浮置閘極之側壁。 接著，移除罩幕層與襯層，並於基底中形成汲極區後，於 第二導電型第一井區中形成第一導電型第二井區，且第一 導電型第二井區與第二導電型第一井區之接面高於開口底 部。於第一控制閘極與第二控制閘極之間的間隙形成絕緣 層，並於第一控制閘極與第二控制閘極之側壁形成第一間 隙壁。接著，於基底上形成内層介電層後，於内層介電層 中形成接觸窗，此接觸窗使汲極區與第一導電型第二井區 形成一短路連接。之後，於内層介電層上形成與接觸窗電 性連接之導線。 在上述快閃記憶體元件之製造方法中，於開口之側壁 形成第一浮置閘極與第二浮置閘極之步驟係先於基底上形 成填滿開口之第一導體層，然後移除部分第一導體層，使 第一導體層之表面約略低於基底表面，並於罩幕層之側壁 形成第二間隙壁。之後，以罩幕層與間隙壁為罩幕，移除 部分第一導體層，以形成第一浮置閘極與第二浮置閘極。 然後，再移除第二間隙壁。 在上述快閃記憶體元件之製造方法中，於開口之側壁 形成第一控制閘極與第二控制閘極之步驟係先於基底上形 成填滿開口之第二導體層。然後，移除部分第二導體層， 使第二導體層之表面低於罩幕層表面且高於浮置閘極。於10326twf.ptd Page 9 573358 V. Description of the invention (5) The floating gate and the second floating gate form a source region at the bottom of the opening. After the inter-gate dielectric layer is formed in the opening, a first control gate and a second control gate are formed on the side wall of the opening, and the first control gate extends to cover the side wall of the first floating gate, and the second control gate The electrode extension covers a side wall of the second floating gate. Next, after removing the mask layer and the liner layer, and forming a drain region in the substrate, a first conductive type second well region is formed in the second conductive type first well region, and the first conductive type second well region is formed. The interface with the first well region of the second conductivity type is higher than the bottom of the opening. An insulating layer is formed in a gap between the first control gate and the second control gate, and a first gap wall is formed on a side wall of the first control gate and the second control gate. Then, after an inner dielectric layer is formed on the substrate, a contact window is formed in the inner dielectric layer, and the contact window forms a short-circuit connection between the drain region and the first conductive type second well region. Thereafter, a conductive line electrically connected to the contact window is formed on the inner dielectric layer. In the above-mentioned method for manufacturing a flash memory device, the step of forming the first floating gate and the second floating gate on the side wall of the opening is to first form a first conductor layer on the substrate to fill the opening, and then remove it. Part of the first conductor layer makes the surface of the first conductor layer approximately lower than the surface of the substrate, and forms a second gap wall on the side wall of the cover layer. After that, a part of the first conductor layer is removed by using the cover layer and the partition wall as a cover to form a first floating gate and a second floating gate. Then, the second spacer is removed. In the flash memory device manufacturing method described above, the step of forming the first control gate and the second control gate on the side wall of the opening is performed by forming a second conductor layer on the substrate to fill the opening. Then, a part of the second conductor layer is removed, so that the surface of the second conductor layer is lower than the surface of the cover layer and higher than the floating gate. to
10326twf.ptd 第10頁 573358 五 、發明說明（6) 罩幕層之側壁形成第三間隙壁後，以罩幕層盥 為罩幕’移除部分第二導體層，以形成第—控制 二控制閘極。然後，再移除第三間隙壁。 ，》 本發明之閘極結構（穿隧介電層、浮置閘極、 電層、控制問極）係形成於基底内之開口側壁上，且、及極 區、源極區係分別形成於開口頂部周圍與底部的其且/極， 其通道區是設置於開口側壁之基底中（垂直式通道"區1，因 此可以藉由控制開口之深度準確的控制通道長⑽ /T — . , I _ L 兩7 月匕 免疋件尺寸細小時所產生的問題，並可以増加元件 ^ ° 八、 而且，本發明在形成浮置閘極與控制閘極時，10326twf.ptd Page 10 573358 V. Description of the invention (6) After the third gap is formed on the side wall of the cover layer, the cover layer is used as the cover to remove a portion of the second conductor layer to form the first-control-two control. Gate. Then, the third spacer is removed. The gate structure (tunneling dielectric layer, floating gate, electrical layer, and control gate) of the present invention is formed on the side wall of the opening in the substrate, and the electrode region and the source region are respectively formed on The channel area of the top and bottom of the opening is located in the base of the side wall of the opening (vertical channel " area 1), so the channel length can be accurately controlled by controlling the depth of the opening ⑽ / T —., I_L In July, the problem caused by the small size of the parts can be avoided, and the components can be added ^ 8. Moreover, when the floating gate and the control gate are formed by the present invention,
於罩幕層上形成間隙壁，然後再以間隙壁與罩幕么= 罩幕，蝕刻導體層而形成之，由於沒有使用到二姑X 口此可以私力衣程裕度，並可以節省製程成本與製程時 間。 由於閘極結構為垂直方向，因此在形成P型井區時， 並不會產生所謂側向NPN崩潰之問題，而且不像習Z的雜 反或閘式記憶胞因為需要形成良好的NPN隔離，二必 型井區進行側向趨入（Lateral Dri ve—ln)以增加ΝΜ /之範 二'為2、熱Λ程而影響到間間介電層（氧化石"氮化 夕/乳化矽，ΟΝΟ)和穿隧氧化層之界面品質。 為讓本發明之上述目 懂，下文牿兴一 ^社奋的特徵、和優點能更明顯易 明如下：’ 只施例，並配合所附圖 <，作詳細說The gap wall is formed on the mask layer, and then the gap wall and mask are used to form the mask layer, which is formed by etching the conductor layer. Since the second-gut X port is not used, this allows a personal clothing margin and can save process costs and Process time. Because the gate structure is vertical, the so-called lateral NPN collapse problem does not occur when forming a P-type well area, and unlike Xi Z ’s hybrid or gated memory cells, because of the need to form good NPN isolation, Lateral inclination (Lateral Dri ve-ln) of the bismuth type well area is added to increase the NM / Range 2 'to 2. The thermal Δ range affects the interlayer dielectric layer (oxides " nitriding evening / emulsified silicon , ΝΟΟ) and the quality of the interface of the tunneling oxide layer. In order to make the above-mentioned object of the present invention understandable, the following features and advantages of the present invention can be more clearly and easily explained as follows: ′ Only examples, and in conjunction with the accompanying drawings <
五、發明說明（7) 實施方式： 第2圖所繪示為本發明之快閃記憶體之結構剖面圖。 請參照第2圖，本發明快閃記憶體 深N型井區2〇2、P型井區204、口袋掺雜區 2 0 6a、閘極結構2 0 6b、源極區20 8、汲極區21〇、間隙壁 212、絶緣層214、接觸窗216、内層介電層218與導線220 所構成。其中，閘極結構20 6a是由穿隧介電層、'浮置 閘極2 24a、閘間介電層226與控制閘極228a所構成；閘極 結構2 0 6b是由穿隧介電層222、浮置閘極224b、閘間介電 層226與控制閘極228b所構成。 电 P型基底20 0具有一開口 230。深N型井區202設置於P型 基底20 0中。閘極結構2〇6a與閘極結構2〇6b分別設置於開 口 230側壁。其中，穿隧介電層222設置於開口23〇底部與 側壁。浮置閘極224a與浮置閘極224b分別設置於開口 23^ 側壁之穿隧介電層222上。閘間介電層226設置於浮置閘極 2 2 4 a與浮置閘極2 2 4 b上。控制閘極2 2 8 a與控制閘極2 2 8 b設 置於P型基底2 0 0上’且控制閘極2 2 8 a延伸覆蓋浮置間極 2 26a之側壁，控制閘極228b延伸覆蓋浮置閘極226b之側 壁。絕緣層2 1 4設置於閘極結構2 〇 6 a與閘極結構2 〇 6 b之間 的間隙。間隙壁212設置於控制閘極226a與控制閘極226b 之侧壁。源極區208設置於開口 230底部之P型基底2〇〇中。 汲極區210設置於間隙壁212下方的P型基底2〇〇中。p型井 區204設置於深N型井區202中，且P型井區204與深N型井區 之接面咼於開口 230底部。P型口袋摻雜區2〇4a設置於開口V. Description of the invention (7) Implementation mode: Fig. 2 is a sectional view showing the structure of the flash memory of the present invention. Referring to FIG. 2, the flash memory of the present invention has a deep N-type well region 202, a P-type well region 204, a pocket doped region 206a, a gate structure 206b, a source region 208, and a drain electrode. The region 21 is formed by the partition wall 212, the insulating layer 214, the contact window 216, the inner dielectric layer 218, and the conductive wire 220. Among them, the gate structure 20 6a is composed of a tunneling dielectric layer, a 'floating gate 2 24a, an inter-gate dielectric layer 226, and a control gate 228a. The gate structure 20 6b is composed of a tunneling dielectric layer. 222, a floating gate 224b, an inter-gate dielectric layer 226, and a control gate 228b. The electric P-type substrate 200 has an opening 230. The deep N-type well area 202 is disposed in a P-type substrate 200. The gate structure 206a and the gate structure 206b are respectively disposed on the side wall of the opening 230. The tunneling dielectric layer 222 is disposed on the bottom and the sidewall of the opening 23. The floating gate 224a and the floating gate 224b are respectively disposed on the tunneling dielectric layer 222 on the sidewall of the opening 23 ^. The inter-gate dielectric layer 226 is disposed on the floating gate 2 2 4 a and the floating gate 2 2 4 b. The control gate 2 2 a and the control gate 2 2 8 b are disposed on the P-shaped substrate 2 0 0 ′, and the control gate 2 2 8 a extends to cover the side wall of the floating intermediate electrode 2 26a, and the control gate 228b extends to cover A side wall of the floating gate electrode 226b. The insulating layer 2 1 4 is provided in a gap between the gate structure 2 06 a and the gate structure 2 06 b. The partition wall 212 is provided on a side wall of the control gate 226a and the control gate 226b. The source region 208 is disposed in a P-type substrate 200 at the bottom of the opening 230. The drain region 210 is disposed in a P-type substrate 2000 under the spacer 212. The p-type well region 204 is disposed in the deep N-type well region 202, and the interface between the P-type well region 204 and the deep N-type well region lies at the bottom of the opening 230. P-type pocket doped region 204a is provided in the opening
10326twf.ptd 第12頁 573358 五、發明說明（8) 230側壁之P型基底2 0 0中，且P型口袋摻雜區2 04a之兩側分 別連接P型井區2〇4與源極區208。内層介電層218設置於P 型基底200上。接觸窗216設置於内層介電層218中，且接 觸窗2 1 6貫穿汲極區2丨0與？型井區2 〇4間之接面使兩者電性 短路連接在一起。導線2 20設置於内層介電層218上，並與 接觸窗2 1 6電性連接。 在本發明之上述實施例中，閘極結構2〇6a、2 0 6b係設 置於P型基底20 0内之開口 230側壁上，且汲極區21〇、源極 區2 0 8係設置於開口 2 3 〇頂部與底部，因此其通道區2 3 2 a、10326twf.ptd Page 12 573358 V. Description of the invention (8) In the P-type substrate 2 0 0 of the 230 side wall, both sides of the P-type pocket doped region 2 04a are connected to the P-type well region 204 and the source region, respectively. 208. The inner dielectric layer 218 is disposed on the P-type substrate 200. The contact window 216 is disposed in the inner dielectric layer 218, and the contact window 2 1 6 penetrates the drain region 2 丨 0 and? The interface between the wells in the well area 204 makes them electrically short-circuited together. The wires 2 20 are disposed on the inner dielectric layer 218 and are electrically connected to the contact windows 2 1 6. In the above embodiment of the present invention, the gate structures 206a and 206b are disposed on the side wall of the opening 230 in the P-type substrate 200, and the drain region 208 and the source region 208 are disposed on The opening 2 3 〇 top and bottom, so its channel area 2 3 2 a,
2 3 2b是設置於開口 23 0外側之p型基底中（垂直式通道區）， 因此可以藉由控制開口之深度準確的控制通道長度，而能 避免元件尺寸縮小時所產生的問題，並可以增加元件集積 度。 八、 接著，請參照第3 A圖至第3 I圖所繪示之本發明較佳實 施例之一種快閃記憶體的製造流程剖面圖，其係用以說明 本發明之快閃記憶體的製造方法。2 3 2b is located in the p-type substrate (vertical channel area) outside the opening 23 0. Therefore, the length of the channel can be accurately controlled by controlling the depth of the opening, which can avoid problems caused when the size of the component is reduced. Increase component integration. 8. Next, please refer to FIG. 3A to FIG. 3I for a flash memory manufacturing process cross-sectional view of a preferred embodiment of the present invention, which is used to explain the flash memory of the present invention. Production method.
首先请參照第3 A圖’提供一基底3 〇 〇，此基底3 〇 〇例如 是P型基底，此基底300已形成元件隔離結構（未圖示），此 元件隔離結構成條狀的佈局，並用以定義出主動區。元件 隔離結構之形成方法例如是區域氧化法（L〇calFirst, please refer to FIG. 3A 'to provide a substrate 300. The substrate 300 is, for example, a P-type substrate. The substrate 300 has formed an element isolation structure (not shown), and the element isolation structure is arranged in a strip shape. And used to define the active area. The formation method of the element isolation structure is, for example, a regional oxidation method (Local
Oxidation ’LOCOS)或淺溝渠隔離法（Shall〇w Trench Isolation，ST I)。接著，在基底300中形成深!^型井區 3 02。之後，於P型基底3〇〇表面形成一層襯層3〇4，此襯層 3〇4之材質例如是氧化矽，襯層3〇4之形成方法例如是熱氧Oxidation 'LOCOS' or Shallow Trench Isolation (ST I). Next, a deep well region 302 is formed in the substrate 300. After that, a liner 300 is formed on the surface of the P-shaped substrate 300. The material of the liner 300 is, for example, silicon oxide, and the method of forming the liner 300 is, for example, thermal oxygen.
第13頁 573358Page 13 573358
化法（Thermal Oxidation)，其厚度例如是100埃至i5〇埃 左右。然後，於襯層304上形成一層罩幕層306，此罩幕層 3 0 6之材質例如是氮化矽，其形成方法例如是化學氣相沈 積法（Chemical Vapor Deposition ，CVD)。然後，圖案化 罩幕層306、襯層304與基底300，已於基底300中形成開口 3 08 ° 接著’請參照第3 B圖，於開口 3 〇 8之側壁與底部形成 一層穿隧介電層310，穿隧介電層31〇之材質例如是氧化 石夕。穿隧介電層310之形成方法例如是熱氧化法（Thermal Oxidation)，其厚度例如是9〇埃至1〇〇埃左右。然後，進 行離子植入步驟，於開口 3 〇 8側壁之基底3 〇 〇植入摻質，以 形成口袋摻雜區3 1 2。植入之摻質例如是p型離子，植入能 量為3 0至50仟電子伏特左右，植入劑量為丨χ 1〇12原子/平 方公分左右。其中，植入摻質之方法包括傾斜角離子植入 法，例如是以15度〜30度之傾斜角植入摻質。然後，於基 底300上形成填滿開口 308之一層導體層（未圖示），其材質 例如是推雜的多晶石夕’此導體層之形成方法例如是利用化 ::相沈ΐ法形成：層未摻雜多晶矽層後，進行離子植入 步騄以形成之。接著，移除部分導 U ^ ^ ^ ^ Γ- ο Λ A -I, 1刀导體層，使其上表面約略 低於基底30 0表面，而形成導體層314。苴 表面約略低於基底30 0表面之方、去 /、 使導 曰上 於罩幕層3 0 6之側壁形成間隙 壁316，間隙壁316之材質例 刻選擇性者，#包括氧化矽二二體f 314具有不同餘 γ間隙壁316之形成方法例如The thermal oxidation method has a thickness of, for example, about 100 angstroms to about 50 angstroms. Then, a mask layer 306 is formed on the liner layer 304. The material of the mask layer 306 is, for example, silicon nitride, and the formation method thereof is, for example, Chemical Vapor Deposition (CVD). Then, the patterned mask layer 306, the liner layer 304, and the substrate 300 have formed an opening 3 08 ° in the substrate 300. Then, 'refer to FIG. 3B, a layer of tunnel dielectric is formed on the sidewall and the bottom of the opening 308. The material of the layer 310 and the tunneling dielectric layer 310 is, for example, stone oxide. A method for forming the tunneling dielectric layer 310 is, for example, a thermal oxidation method, and a thickness thereof is, for example, about 90 angstroms to 100 angstroms. Then, an ion implantation step is performed, and a dopant is implanted in the substrate 300 on the side wall of the opening 308 to form a pocket doped region 3 1 2. The implanted dopants are, for example, p-type ions, the implantation energy is about 30 to 50 仟 electron volts, and the implantation dose is about χ 1012 atoms / cm 2. Among them, the method of implanting the dopant includes a tilt angle ion implantation method, for example, implanting the dopant at a tilt angle of 15 to 30 degrees. Then, a conductive layer (not shown) that fills the opening 308 is formed on the substrate 300, and the material is, for example, doped polycrystalline stone. The method of forming the conductive layer is, for example, by using a chemical deposition method: : After an undoped polycrystalline silicon layer is formed, an ion implantation step is performed to form it. Next, a part of the conductive layer U ^ ^ ^ ^ Γ- ο A-I, 1-kn conductor layer is formed, so that the upper surface is slightly lower than the surface of the substrate 300, and the conductive layer 314 is formed. The surface of the concrete is slightly lower than the surface of the substrate 300, so that the guide wall is formed on the side wall of the cover layer 306 to form a spacer 316. The material of the spacer 316 is engraved with selectivity, including # SiO2 The formation method of the two-body f 314 with different residual gamma spacers 316 such as
10326twf.ptd10326twf.ptd
第14頁 573358 發明說明（10) :=形成一層絕緣材料層（未圖示），然後利用非等向性蝕 除部分絕緣材料層’以於罩幕層30 6之側壁形成間 雕二1 6。然後，以罩幕層3 0 6與間隙壁3 1 6為罩幕蝕刻導 ^二旺4，而形成位於基底300側壁之導體層314a、314b。 、肢曰3 Ua、3丨4b即作為快閃記憶體之浮置閘極。 %接著’睛參照第3D圖，移除間隙壁3 1 6後，進行一摻 =% ^製程，於開口 3 0 8底部之基底3 0 0中植入摻質，以形 X 1 圣區3丨8。植入之摻質例如是N型離子，植入劑量為4 η η ^原^子/平方公分左右。然後，於基底30〇上形成一層 ，此閘間介電層320之材質例如是氧化矽/ ς 虱化矽等，且其厚度例如是6〇埃/7Q埃/6Q埃左 —:間’丨電層3 2 〇之形成方法例如是先以熱氧化法形成 声：：2’再利用低壓化學氣相沈積法形成氮化矽 二：Μ ::乳化石夕。當然，此問間介電層32 0也可以是氧 滿π二^Q氣化矽/氮化矽層等。然後，於基底30〇上形成填 矽，μ道之一層導體層3 2 2，其材質例如是摻雜的多晶 形成一 ί Ϊ層322之形成方法例如是利用化學氣相沈積法 ^。 未摻雜多晶矽層後，進行離子植入步驟以形成 表面：^贸研參照第3Ε圖，移除部分導體層322，使其上 324。盆\罩幕層3〇6且高於基底300表面，而形成導體層 底3 /矣，使導體層322上表面低於罩幕層306且高於基 側壁开二面：方法例如是回蝕刻法。然*，於罩幕層30 6之 -成間隙壁326，間隙壁326之材質例如是與導體層Page 14 573358 Description of the invention (10): = form a layer of insulating material (not shown), and then use anisotropic etching to partially remove the layer of insulating material 'to form a cross-cut 2 on the side wall of the cover layer 30 6 . Then, the mask layer 3 06 and the spacer 3 16 are used as the mask etching guide 2 to form the conductor layers 314a and 314b on the side wall of the substrate 300. The limbs 3 Ua and 3 丨 4b serve as the floating gates of the flash memory. % Next, referring to the 3D image, after removing the spacer 3 1 6, a doping process is performed. A dopant is implanted in the substrate 3 0 0 at the bottom of the opening 3 0 8 to form the X 1 sacred area 3丨 8. The implanted dopant is, for example, an N-type ion, and the implantation dose is about 4 η η ^ ^^^^^ / cm 2. Then, a layer is formed on the substrate 30. The material of the inter-gate dielectric layer 320 is, for example, silicon oxide / silicon silicon, and the thickness is, for example, 60 angstroms / 7Q angstroms / 6 angstrom angstroms: The method for forming the electric layer 3 2 0 is, for example, first to form a sound: 2 ′ by a thermal oxidation method, and then use a low-pressure chemical vapor deposition method to form silicon nitride II: M :: emulsified stone. Of course, the interlayer dielectric layer 32 0 may also be an oxygen-filled π 2 ^ Q gasified silicon / silicon nitride layer. Then, a silicon-filled, micro-conductor layer 3 2 2 is formed on the substrate 30. The material is, for example, a doped polycrystal to form a fluorene layer 322. For example, a chemical vapor deposition method is used. After the undoped polycrystalline silicon layer, an ion implantation step is performed to form a surface: Referring to FIG. 3E, the trade researcher removes a part of the conductor layer 322 and places it on top of 324. The basin \ cover curtain layer is 306 higher than the surface of the substrate 300, and the conductor layer bottom is formed 3 / 矣, so that the upper surface of the conductor layer 322 is lower than the cover curtain layer 306 and higher than the base side wall, and the method is: etch back law. However, a gap wall 326 is formed in the cover layer 306. The material of the gap wall 326 is, for example, a conductive layer
573358 五、發明說明（11) 324、具有不同蝕刻選擇性者，#包括氧化矽。間隙壁3 26之 ^ Ϊ例如疋先形成一層絕緣材料層（未圖示），然後利 寺σ陘蝕刻法移除部分絕緣材料層，以於罩幕層3 Ο Θ 之侧壁形成間隙壁3 2 6。 接著’請參照第3F圖，以罩幕層3〇6與間隙壁326為罩 柚Ϊ 5 Ϊ 2層3 24，而形成位於基底3 0 0上，且-端分別延 復孤V _層314a、314b側壁之導體層324a、324b。導體 層3 24a、324b即作為快閃記憶體之控 苴 層3 24a、閘間介電層“ο、溪鲈^ T V ^ ^ 私層32〇 V體層314a、穿隧介電層31〇構 成閘極、、、.構325a ;導體層324b、閘間介電層32〇、導體層 314b、穿隨介電層31〇構成間極結構32 5b 隙壁326、罩幕層306與襯層3〇4。 移= 與襯層3。4之移除方法例如是濕式餘刻法。之後進層:一 ;質植1程，於開口 308頂部周圍之基底300中植入掺 質，以形成…328。植入之 ：直 劑量為4 X 1 015原子/平方公分左右。 I雕千植入 接著，請參照第3G圖，在深N型井區3〇 區330。形成p型井區330之方法例如是離子植入法 ： 入劑量為1X1013原子/平方公分左右。然後’導Ϊ声植 324a、324b之間的間隙形成絕緣層332，並於 ^ 324a、f之側壁形成間隙壁叫。間隙壁334之形日成方法 例如是=基底_上形成—層絕緣材 :成方法 後利用非等向性…移除部分絕緣 ：)體展 324a、324b m彡 μ_334，並且 、—體層573358 V. Description of the invention (11) 324. Those with different etching selectivity, #including silicon oxide. Partition wall 3 26 of ^ Ϊ For example, first form a layer of insulating material (not shown), and then remove part of the layer of insulating material using the Li Si σ etch method to form the partition wall 3 on the side wall of the cover layer 3 Ο Θ 2 6. Next, please refer to FIG. 3F, using the cover layer 3 06 and the partition wall 326 as the cover pomelo 5 Ϊ 2 layers 3 24, and formed on the base 3 0, and the-end respectively extend the solitary V_ layer 314a The conductor layers 324a, 324b of the side walls of 314b. The conductor layers 3 24a and 324b serve as the flash memory control layer 3 24a, the inter-gate dielectric layer "ο", the channel ^ TV ^ ^ the private layer 320V bulk layer 314a, and the tunneling dielectric layer 310 constitute the gate. The electrode structure 325a; the conductor layer 324b, the inter-gate dielectric layer 32o, the conductor layer 314b, and the through dielectric layer 31o constitute the interelectrode structure 32 5b, the barrier wall 326, the cover layer 306, and the liner layer 30. 4. Shift = The method of removing the liner 3.4 is, for example, a wet-etching method. Afterwards, the layer is advanced: one; quality implantation, implanting dopants in the substrate 300 around the top of the opening 308 to form ... 328. Implantation: The direct dose is about 4 X 1 015 atoms / cm 2. I implantation. Next, please refer to Figure 3G, in the deep N-type well area 30 area 330. The p-type well area 330 is formed. The method is, for example, the ion implantation method: the dose is about 1 × 1013 atoms / cm 2. Then, the gap between the “conductive sound implants 324a and 324b” forms an insulating layer 332, and a gap wall is formed on the side wall of “324a, f.” The forming method of the wall 334 is, for example, = base_formed on-a layer of insulating material: using the anisotropy after the forming method ... remove part of the insulation :) body extensions 324a, 324b m μ_334, and, - layer
I0326twf.ptd 第16頁 573358 五、發明說明（12) 導體層324a、324b之間的間隙而形成絕緣層332。 接著，請參照第3H圖，於基底3 0 0上形成一層内層介 電層3 3 6，此内層介電層3 3 6之材質例如是硼磷矽玻璃 (BPSG)或磷矽玻璃（PSG)，形成内層介電層33 6之方法例如 疋化學氣相沈積法。然後進行一化學機械研磨製程，使内 層介電層340之表面平坦化。接著，於内層介電層中形 成與接觸窗338，接觸窗33 8之材質例如是鎢金屬。其中， 接觸窗338貫穿汲極區328與P型井區33 0間之接面，而使汲 極區328與P型井區330短路連接在一起。之後，於内層介 電層336上形成與接觸窗338電性連接之導線。導線 =形成方法例如是於基底3〇〇上形成導體層（未圖示）後， ;己：f Γ驟而形成條狀之導線340。後續完成快問 5”呈為習知技藝者所周知，在此不再贅述。 開口壁之上間極且1構=283咖 頂部周圍與底中源係形成於開口 開口 308外侧 < 基底3。"（中因此其通道區是設置於 元件集積度，❿且可以藉式通道區)’因此可以增加 道長度，㊆而能避免元件尺；：：之深度準確的控制通 而且，本發明在开彡点…^吩所產生的問題。 時，係分別採用於極（導體層 間隙壁316與罩幕層3()6為# t成間隙壁316，然後再以 成之，由於没有使用到微影技術，因=導：層314而形 度’並可以節省製程成本與 °以增加製程裕 衣私蛉間。同樣的，本發明在I0326twf.ptd Page 16 573358 V. Description of the Invention (12) The gap between the conductor layers 324a and 324b forms the insulating layer 332. Next, referring to FIG. 3H, an inner dielectric layer 3 3 6 is formed on the substrate 300. The material of the inner dielectric layer 3 3 6 is, for example, borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG). A method of forming the inner dielectric layer 336 is, for example, a rhenium chemical vapor deposition method. Then, a chemical mechanical polishing process is performed to planarize the surface of the inner dielectric layer 340. Next, a contact window 338 is formed in the inner dielectric layer. The material of the contact window 338 is, for example, tungsten metal. Wherein, the contact window 338 penetrates the junction between the drain region 328 and the P-type well region 330, so that the drain region 328 and the P-type well region 330 are short-circuited together. Thereafter, a conductive line electrically connected to the contact window 338 is formed on the inner dielectric layer 336. The conductive wire = forming method is, for example, forming a conductive layer (not shown) on the substrate 300, and then: f Γ to form a strip-shaped conductive wire 340. Subsequent completion of the quick question 5 "is well known to those skilled in the art, and will not be repeated here. The upper pole of the opening wall and the structure = 283 around the top and bottom of the opening are formed outside the opening 308 < substrate 3 "(The channel area is therefore set at the component integration degree, and the borrowable channel area can be used.) 'Therefore, the channel length can be increased, and the component rule can be avoided. ::: The depth can be accurately controlled and the invention At the opening point ... the problem caused by 吩 is used at the pole (conductor layer gap wall 316 and cover layer 3 () 6 is #t to form the gap wall 316, and then it is completed, because it is not used In the lithography technology, the shape of the guide layer 314 can reduce the manufacturing cost and ° to increase the manufacturing process. Similarly, the present invention provides
10326twf.ptd $ 17頁 573358 五、發明說明（13) ' 形成控制問極（導體層324a、324b)時，係分別採用於罩幕 層3 0 6上形成間隙壁3 2 6，然後再以間隙壁3 2 6與罩幕層3 0 6 ，^虫刻罩幕飿刻導體層3 2 4而形成之，由於沒有使用到 被影技術，因此可以增加製程裕度，並可以節省製程成本 與製程時間。 此外β +由於本發明之閘極結構為垂直方向，因此在形 τ里井區日才’並不會產生所謂側向NpN崩潰之 不像習知的錐G ^ 離，而必須；Λ間Λ記憶胞因為需要形成良好的崎 以增加ΝΡΝ之範^井 側向趨入（Lateral Drive —in) 層（量彳卜切/ ^圍，並因為此道熱製程而影響到閘間介電 ^ 虱化矽/氧化矽，ΟΝΟ)和穿隧氧化層之界面品 、雖然本發明已以一較佳實施例揭露如上，然其並非 =限定本發明，#何熟f此技藝者，在不脫離本發明之 :::範㈣，當可作各種之更動與潤飾，因此本發明之： a靶圍當視後附之申請專利範圍所界定者為準。 ’、10326twf.ptd $ 17, page 573358 V. Description of the invention (13) 'When forming the control interrogator (conductor layers 324a, 324b), the barrier layer 3 2 6 is formed on the cover layer 3 0 6 and then the gap The wall 3 2 6 and the mask layer 3 0 6 are formed by engraving the conductor layer 3 2 4 with the mask. Since no shadowing technology is used, the process margin can be increased, and the process cost and process can be saved. time. In addition, β +, because the gate structure of the present invention is vertical, the genius in the well area in the shape τ will not produce the so-called cone G ^ away from the so-called lateral NpN collapse, but must; Λ 间 Λ The memory cells need to form a good ridge to increase the range of NPN. Lateral Drive —in layer (quantitative cutting / circumference, and affect the inter-gate dielectric due to this thermal process ^ lice Interfacial products of siliconized silicon / silicon oxide) and tunneling oxide layers. Although the present invention has been disclosed as above with a preferred embodiment, it does not limit the present invention. # 何 熟 fThis artist does not depart from the present invention. Invention ::: Fan Ye, when various modifications and retouching can be done, so the present invention: a target range shall be determined by the scope of the attached patent application. ’,
1〇326^f.ptd 第18頁 573358 圖式簡單說明 第1圖所繪示為習知之快閃記憶體的結構剖面圖。 第2圖所繪示為本發明一較佳實施例之快閃記憶體之 結構剖面圖。 第3A圖至第3H圖所示為根據本發明一較佳實施例之一 種快閃記憶體的製造流程立體圖。 圖式標示說明： 1 00、2 0 0、3 0 0 : p 型基底 1 02、2 0 2、3 0 2 :深η 型井區 1 04、2 04、33 0 : ρ 型井區 1 0 6 :堆疊閘極結構 1 0 8、2 0 8、3 1 8 :源極區 110、210、328 :汲極區 1 12、212、316、326、334 :間隙壁 1 14、218、33 6 :内層介電層 116、216、338 :接觸窗 1 18、22 0、340 :導線 120、222、310 :穿隧介電層 122、224a、224b :浮置閘極 124、226、3 20 :閘間介電層 126、228a、228b :控制閘極 1 2 8、2 3 2、3 1 6 :閘極頂蓋層 20 6a、2 0 6b、325a、32 5b ：閘極結構 2 1 4、3 3 2 :絕緣層 2 3 0、3 0 8 :開口1〇326 ^ f.ptd Page 18 573358 Brief Description of Drawings Figure 1 shows a cross-sectional view of the structure of a conventional flash memory. FIG. 2 is a sectional view showing the structure of a flash memory according to a preferred embodiment of the present invention. 3A to 3H are perspective views showing a manufacturing process of a flash memory according to a preferred embodiment of the present invention. Description of the drawing: 1 00, 2 0 0, 3 0 0: p-type base 1 02, 2 0 2, 3 0 2: deep η-type well area 1 04, 2 04, 33 0: ρ-type well area 1 0 6: stacked gate structure 1 0 8, 2 0 8, 3 1 8: source region 110, 210, 328: drain region 1 12, 212, 316, 326, 334: gap wall 1 14, 218, 33 6 : Inner dielectric layers 116, 216, 338: Contact windows 1 18, 22 0, 340: Wires 120, 222, 310: Tunneling dielectric layers 122, 224a, 224b: Floating gates 124, 226, 3 20: Inter-gate dielectric layers 126, 228a, 228b: Control gates 1 2 8, 2 3 2, 3 1 6: Gate top caps 20 6a, 2 6b, 325a, 32 5b: Gate structure 2 1 4, 3 3 2: Insulating layer 2 3 0, 3 0 8: Open
10326twf.ptd 第19頁 573358 圖式簡單說明 232a 、2 32b :通道區 3 04 ·· 概層 3 0 6 ： 罩幕層 312 > 2 0 4a ： 口袋摻雜區 314、 314a 、 314b、32 2、324a、324b :導體層10326twf.ptd Page 19 573358 Brief description of the drawings 232a, 2 32b: Channel area 3 04 · · Profile 3 0 6: Mask layer 312 > 2 0 4a: Pocket doped areas 314, 314a, 314b, 32 2 , 324a, 324b: conductor layer
10326twf.ptd 第20頁10326twf.ptd Page 20
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