TW571516B

TW571516B - Phase-locked loop and its control method

Info

Publication number: TW571516B
Application number: TW91134570A
Authority: TW
Inventors: Sterling Smith
Original assignee: Mstar Semiconductor Inc
Priority date: 2002-11-28
Filing date: 2002-11-28
Publication date: 2004-01-11
Also published as: TW200409469A

Abstract

A PLL architecture with fast phase acquisition, a stable freerun output frequency, and post-freerun fast phase recovery. The invention is particularly well suited for use in a video graphics a/d conversion circuit. An intelligent phase lock loop is optimized to determine the time difference between the closest rising edge of an PLL output signal and the rising edge of an input signal. The time difference in combination with the current PLL lock state determine an operational code used in a digital signal processing loop filter used to control a digitally controlled oscillator. The PLL also provides a stable output frequency during freerun periods, and a phase booster circuit for post-freerun fast phase recovery.

Description

571516571516

五、發明說明（1) —、【發明所屬之技術領域】本發明係有關於鎖相迴路技術，特別是有關於具有可决速獲取相位、穩定的自由運轉（free run)輸出頻率、以及自由運轉後可快速回復相位等優點之鎖相迴路裝覃。二、【先前技術】鎖相迴路裝置（Phase Lock Loop)係廣泛應用在電子弘路内，做為頻率合成、提升工作週期（duty-cycle)、時脈去偏斜（clock de-skewing)等之用。以往大部分的個人電腦係採用顯示卡將數位信號轉換為rGB類比信號，供予陰極射線管（C R T )做圖像顯示。但是，就現今平板顯示器（flat panel display)而言，就必須考慮與既有之視訊圖像（video graphics)系統相容。第一圖係顯示具有平板顯示器之習知視訊圖像系統方塊圖，平板顯示器具備有一類比介面30，得將RAMDAC 20輸出之類比RGB信號轉換為數位信號後，供予圖像控制器40。RAMDAC 20係根據螢幕的解析度，將PC圖像顯示卡内之圖像處理器丨〇所產生之數位L號轉換為類比2 5 6階之脈衝振幅調變（p u 1 s e amplitude modulated)信號，再根據時序传號傳送至平板顯示器之類比介面30處。類比介面30接收^比^圖像資料後，利用類比/數位轉換裝置（ADC)轉換為數位模式。'因此，類比介面3 0需具備一時脈再生器（c 1 〇 c & 、 regenerator)以正確地回復原始像素時脈頻率和相位，此時脈再生器係以倍頻鎖相迴路裝置為之，利用hsyN(>^ 號做為參考頻率。時脈再生器之輸出信號及 ^V. Description of the invention (1) — [Technical field to which the invention belongs] The present invention relates to a phase locked loop technology, and more particularly, to a free running output frequency with stable speed acquisition phase, and free Phase-locked loop equipment with advantages such as quick recovery of phase after operation. 2. [Previous Technology] Phase Lock Loop device is widely used in electronic circuits, as frequency synthesis, duty-cycle, clock de-skewing, etc. Use. In the past, most personal computer systems used display cards to convert digital signals into rGB analog signals for cathode ray tubes (CRT) for image display. However, as far as flat panel displays are concerned today, compatibility with existing video graphics systems must be considered. The first diagram is a block diagram of a conventional video image system with a flat panel display. The flat panel display is provided with an analog interface 30. The analog RGB signals output from the RAMDAC 20 are converted to digital signals and supplied to the image controller 40. The RAMDAC 20 converts the digital L number generated by the image processor in the PC image display card into an analog 2-6th-order pulse amplitude modulated (pu 1 se amplitude modulated) signal according to the resolution of the screen. The signal is then transmitted to the analog interface 30 of the flat panel display according to the timing sequence. After the analog interface 30 receives the image data, the analog interface 30 uses an analog / digital converter (ADC) to convert the image data into a digital mode. 'Therefore, the analog interface 30 needs to have a clock regenerator (c 1 0c & regenerator) to correctly restore the original pixel clock frequency and phase. At this time, the pulse regenerator is based on a frequency doubling phase-locked loop device. , Use hsyN (> ^ as the reference frequency. The output signal of the clock regenerator and ^

第5頁五、發明說明（2) 轉換裝置和圖像控制器40處，知電路係採用具 contr〇lled 〇scUlat〇兒續控制震蘯器、（voltage-類比RGB信號和供单.Γ_之類比鎖相迴路裝置，然就擷取知的電路設計7在千示數位化處理等… 回復時之來考卢ΐ„田夕的限制。諸如：做為像素時脈 f ree)的信號，y號上號並^是完全無抖動（]丨tter 圖像顯示卡而定。°大Α八里之多寡，端視電腦所採用之路頻寬（loop bandwi^^%比式鎖相迴路裝置係以縮小迴解決長期的抖動效庫來解決抖動的問題，但是很難 VSYNC信號係内喪於混成式HSYNC格式之信號，致HSYNC變動現象，、號内，為補償VSYNC信號所導震盈器之控制電壓伴鎖捭相^路裳置會試圖將供予電壓控制之故，類比鎖相迴路定的準位；'然而，園於漏電生在顯示器左i角之f ”電壓易於漂_多，導致常發技处；、门μ⑯ 撕扯效應（tearing effect)。為能維持，，，路裝置穩定度之最佳化，許多習知設計是採用大里曰曰片外迴路遽、波電容，但是是項零件卻易遭致外部雜訊干擾。再者’ g知大部分鎖相迴路裝置内之相位偵測器是二進制early/late數位式、抑或是叫/d0wn脈衝寬度類比式系統。當相位獲取時，二進制鎖相迴路裝置會導致一時脈信號的不明確。若以第三圖為例，當rEF__clk之上升邊緣發生在DC0一CLK信號CLOCK 0和CLOCK 1的上升邊緣之間，系統將無法決定出那個Dc〇 CLK^开邊緣最接近REF_CLK之Page 5 V. Description of the invention (2) At the conversion device and the image controller 40, it is known that the circuit adopts controlled 〇scUlat〇 to continuously control the vibrator, (voltage-analog RGB signal and supply slip. Γ_ Analogy is a phase-locked loop device, and then the known circuit design 7 is digitized in thousands of indications, etc ... When I reply, I come to test the limits of Tian Xi. For example, as the pixel clock f ree), No. y and ^ are completely jitter-free (] 丨 tter depending on the graphics display card. ° As large as eight miles, depending on the road bandwidth used by the computer (loop bandwi ^^% ratio phase-locked loop device system The problem of jitter is solved by reducing the long-term jitter effect library, but it is difficult for the VSYNC signal to be lost in the hybrid HSYNC format signal, which causes the HSYNC to fluctuate. Controlling the voltage with phase-locking ^ Lu Changzhi will try to control the supply voltage by analogy with the phase-locked loop level; 'however, the leakage voltage f in the left corner of the display is easy to drift. Lead to the common technical office; door μ⑯ tearing effect. To maintain, and optimize the stability of the road device, many conventional designs use external circuit chips and wave capacitors, but these components are susceptible to external noise interference. The phase detector in the phase-locked loop device is a binary early / late digital or an analog system called / d0wn pulse width. When the phase is acquired, the binary phase-locked loop device will cause the ambiguous clock signal. The third picture is an example. When the rising edge of rEF__clk occurs between the rising edge of DC0-CLK signal CLOCK 0 and CLOCK 1, the system will not be able to determine which Dc0CLK ^ opening edge is closest to REF_CLK.

571516 五、發明說明（3) 上升邊緣，因此，系統可能會選擇Ex. 1和Ex. 2所示信號中之一者。然而，第三圖所示為Tl < TO，故Ex. 2應屬較佳的時序信號。此一不明確現象會減慢相位獲取，甚或在某些情狀下導致鎖相暫時喪失。複雜的類比式鎖相迴路裝置另一項限制，在於以低成本CMOS製程實現的困難度。因此，此業界之人士對於具有可快速獲取相位、穩定的自由運轉（f r e e r u η )輸出頻率、以及自由運轉後可快速回復相位等優點之鎖相迴路裝置，需求甚殷。三、【發明内容】因此，本發明之一目的，在於提供一種具有智慧型相位偵測與校正功能之鎖相迴路裝置，使得相位獲取過程更為快速精碟。本發明之另一目的，在於提供一種鎖相迴路裝置，當於參考信號變動不明期間，尚能提供穩定輸出頻率，並於自由運轉後可快速回復相位。本發明之再一目的，在於提供一種可免於時脈抖動影響之鎖相迴路裝置，不論此時脈抖動是參考信號抖動、抑或是系統雜訊。本發明之又一目的，在於提供一種鎖相迴路裝置，易於以低成本之CMOS製程實現之。為能獲致上述目地，本發明可藉由提供一種鎖相迴路裝置來完成。此鎖相迴路裝置包括：一數位控制震盪器、一相位偵測器、一迴路濾波器。數位控制震盪器係用以產571516 V. Description of the invention (3) Rising edge, therefore, the system may choose one of the signals shown in Ex. 1 and Ex. 2. However, the third figure shows Tl < TO, so Ex. 2 should be a better timing signal. This ambiguity can slow down phase acquisition and, in some cases, lead to temporary loss of phase lock. Another limitation of complex analog phase-locked loop devices is the difficulty of implementing them in low-cost CMOS processes. Therefore, people in this industry have a great need for a phase-locked loop device that has the advantages of fast phase acquisition, stable free-running (f r e r u η) output frequency, and fast phase recovery after free-running. III. [Summary of the Invention] Therefore, an object of the present invention is to provide a phase-locked loop device with intelligent phase detection and correction functions, so that the phase acquisition process is faster and more accurate. Another object of the present invention is to provide a phase-locked loop device that can provide a stable output frequency during a period when the reference signal is unknown, and can quickly recover the phase after free running. Yet another object of the present invention is to provide a phase-locked loop device that can be free from the influence of clock jitter, regardless of whether the clock jitter is a reference signal jitter or a system noise at this time. Another object of the present invention is to provide a phase-locked loop device, which can be easily implemented by a low-cost CMOS process. To achieve the above object, the present invention can be accomplished by providing a phase locked loop device. The phase-locked loop device includes a digitally controlled oscillator, a phase detector, and a loop filter. Digitally controlled oscillators are used to produce

571516 五、發明說明（4) 生一輸出時脈信號，相位偵測器則接收一參考信號與輸出時脈信號，係針對參考信號之上升邊緣與輸出時脈信號之下降邊緣暨上升邊緣做一比較，獲知輸出時脈信號之若干上升邊緣中最靠近參考信號之上升邊緣間之一相位差，並據以產生一操作碼。而迴路濾波器係根據操作碼輸出控制信號予數位控制震盪器，據以調整輸出信號之若干上升邊緣中最靠近參考信號之上升邊緣者，而與參考信號之上升邊緣成一既定關係。為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉若干較佳實施例，並配合所附圖示，做詳細說明如下：四、【實施方式】第二圖係顯示根據本發明一較佳實施例之鎖相迴路裝置之示意圖。一相位偵測器5 0接收一參考信號和數位控制震盈器1 0 0之輸出信號D C 0 _ C L K做為輸入，並與數位鎖指示器6 0耦接；此外，相位偵測器5 0尚接收計數器7 0之輸出信號CNT。一慣性運作輸入COAST至相位偵測器50和一相位推進器8 0處。相位債測器5 0輸出操作碼（〇 p - c 〇 d e s )予一數位信號處理迴路遽波器9 0。此迴路濾、波器9 0具有可規劃係數，假如迴路濾.波器9 0可以是若干電容器與電阻器之組合，因此，可規劃係數即便是該等電容器與電阻器所對應之電容值和電阻值，而迴路濾波器9 0根據相位偵測器5 0、相位推進器8 0或外部使用者控制所傳送之操作碼（opcodes) ，對可規劃係數做動態調整。迴路濾波器90尚接收571516 V. Description of the invention (4) Generate an output clock signal, and the phase detector receives a reference signal and an output clock signal. It is based on the rising edge of the reference signal and the falling edge and rising edge of the output clock signal. By comparison, a phase difference between the rising edges closest to the reference signal among the several rising edges of the output clock signal is obtained, and an operation code is generated accordingly. The loop filter outputs the control signal to the digitally controlled oscillator according to the operation code, and adjusts the rising edge of the output signal closest to the rising edge of the reference signal to form a predetermined relationship with the rising edge of the reference signal. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, several preferred embodiments are described below, and the accompanying drawings are described in detail as follows: 4. [Embodiment] The second figure It is a schematic diagram showing a phase locked loop device according to a preferred embodiment of the present invention. A phase detector 50 receives a reference signal and an output signal DC 0 _ CLK of the digital control vibrator 1 0 0 as an input, and is coupled to a digital lock indicator 6 0. In addition, the phase detector 50 0 Still receiving the output signal CNT of the counter 70. A coasting input COAST to the phase detector 50 and a phase advancer 80. The phase debt detector 50 outputs an operation code (〇 p-c 〇 de e s) to a digital signal processing loop oscilloscope 90. This loop filter and wave filter 90 have a programmable coefficient. If the loop filter. Wave filter 90 can be a combination of several capacitors and resistors, therefore, the programmable coefficient is the sum of the capacitance values of these capacitors and resistors. Resistance value, and the loop filter 90 dynamically adjusts the programmable coefficients according to the operation codes (opcodes) transmitted by the phase detector 50, the phase booster 80, or an external user control. Loop filter 90 is still receiving

第8頁 571516 五、發明說明（5) 計數器7 0之輸出信號C N T、數位控制震盪器1 0 0之輸出信號 DCO_CLK、以及一外部輸入信號，迴路濾波器90則輸出控制信號予數位控制震盪器1 0 0，令數位控制震盪器1 0 0根據控制信號產生輸出時脈信號DCO_CLK。此輸出時脈信號 DCO_CLK除了提供予迴路濾波器90和相位偵測器50之外，亦提供予計數器7 0做為輸入信號。關於數位控制震盪器 1 0 0之詳細電路可參照與本發明同時申請中華民國專利申請案，標題為「頻率合成裝置」中之第三〜五圖。數位控制震盪器1 0 0係由迴路濾波器9 0提供高解析度輸入，其具有一量化器（未繪示）將任何誤差移至高頻率區段，後續在經過一濾波器移除高頻誤差，然而此一誤差原本是位於相位轉換之震盪器頻率範圍内。然後，一低解析度輸入控制數位控制震盪器1 0 0，使得數位控制震盪器1 0 0如同相位濾波器般運作。是項設計可將輸出頻率中不需要的抖動和雜訊予以移除。鎖相迴路裝置之操作將詳如下述。參考信號輸入至相位偵測器50後，與數位控制震盪器1 00之輸出信號DC0_CLK 做一比較，然後以傳送操作碼（o p e r a t i ο n a 1 c o d e s )的方式控制迴路濾波器9 0。由相位偵測器5 0傳送之操作碼係依據參考信號與數位控制震盪器1 00之輸出信號DC0_CLK的第 N個時脈邊緣間之時間差而得，此時間差係當相位偵測器 5 0偵測到輸入參考信號之時脈邊緣時，由計數器7 0測量而得。計數器7 0根據輸入之除頻信號内部地或外部地調整 C N T數值，並配合數位控制震盪器1 0 0之輸出信號Page 8 571516 V. Description of the invention (5) Output signal CNT of counter 70, output signal DCO_CLK of digital control oscillator 100, and an external input signal. Loop filter 90 outputs control signal to digital control oscillator 1 0 0, the digital control oscillator 1 0 0 generates an output clock signal DCO_CLK according to the control signal. This output clock signal DCO_CLK is not only provided to the loop filter 90 and the phase detector 50, but also to the counter 70 as an input signal. For the detailed circuit of the digitally controlled oscillator 100, please refer to the third to fifth drawings in the "Frequency Synthesis Device" application filed with the Republic of China patent application at the same time as the present invention. The digitally controlled oscillator 1 0 0 is provided with a high-resolution input by a loop filter 90. It has a quantizer (not shown) to move any errors to the high-frequency section, and subsequently removes the high-frequency errors through a filter. However, this error was originally within the frequency range of the phase-converted oscillator. Then, a low-resolution input controls the digitally controlled oscillator 100, so that the digitally controlled oscillator 100 operates like a phase filter. This design removes unwanted jitter and noise from the output frequency. The operation of the phase locked loop device will be detailed as follows. After the reference signal is input to the phase detector 50, it is compared with the output signal DC0_CLK of the digital control oscillator 1 00, and then the control loop filter 9 0 is transmitted by transmitting an operation code (o p e r a t i ο n a 1 c o d e s). The operation code transmitted by the phase detector 50 is based on the time difference between the reference signal and the Nth clock edge of the output signal DC0_CLK of the digitally controlled oscillator 100. This time difference is detected by the phase detector 50 When the clock edge of the input reference signal is detected, it is measured by the counter 70. Counter 70 adjusts the C N T value internally or externally according to the input frequency division signal, and cooperates with the digitally controlled oscillator 1 0 0 output signal

571516 五、發明說明（6) DC0_CLK，計數參考信號之時脈週期。根據本發明，判斷出REF_CLK信號之上升邊緣位置相對於DCO_CLK信號上升邊緣者，係利用DCO_CLK信號之下降邊緣為之。請參照第三圖，既然REF —CLK信號之上升邊緣發生DCO_CLK信號之下降邊緣F0之後，本發明之鎖相迴路裝置可判知REF__CLK信號之上升邊緣較靠近DCO —CLK信號之DCO_CLK信號之上升邊緣 R 1，故可避免時脈不明確的問題，而得以快速地獲取相位資訊。另外，操作碼尚根據鎖相迴路裝置之鎖狀態（1 〇 c k s t a t e )而定，此鎖狀態係由鎖指示器β 0決定之。鎖狀態可區分為三者：LOCK、WARN、UNLOCKED等等。當既定週期數期間内，無錯誤之發生，則會出現LOCK狀態；當鎖相迴路裝置已處於LOCK狀態，卻有錯誤發生，則會出現WARN狀態；當鎖相迴路裝置已處於W A R N狀態，卻有錯誤發生，則會出現UNLOCKED狀態。錯誤之發生經定義為：相位偵測器 5 0所測得之時間差超過一個時脈週期。此等鎖狀態配合參考h號與輸出信號DC0一CLK間之時間差，會決定相位偵測為5 0輸出予迴路濾波器9 〇之操作碼。例如，相位偵測器5 0 所傳送之操作碼包括UP、DN、FREQH、FREQL、HOLD等 4。U P#作碼會對頻率做些許調整，當於下一個參考信號邊緣發生時增加CNT值；然而，DN操作碼亦對頻率做些許调整’當於下一個參考信號邊緣發生時減少CNT值。當相位僧測器5 0偵測出輸入與輸出時脈之間存在相當大的差異’並表示數位控制震盪器1 0 0的頻率過高，則會產生571516 V. Description of the invention (6) DC0_CLK, counting the clock cycle of the reference signal. According to the present invention, it is determined that the position of the rising edge of the REF_CLK signal relative to the rising edge of the DCO_CLK signal is the falling edge of the DCO_CLK signal. Please refer to the third figure. Since the rising edge of the REF-CLK signal occurs after the falling edge F0 of the DCO_CLK signal, the phase-locked loop device of the present invention can determine that the rising edge of the REF__CLK signal is closer to the rising edge of the DCO_CLK signal of the DCO_CLK signal. R 1, so it can avoid the problem of unclear clock, and can obtain phase information quickly. In addition, the operation code is also determined according to the lock state of the phase-locked loop device (10 c k s t a t e). The lock state is determined by the lock indicator β 0. Lock status can be divided into three: LOCK, WARN, UNLOCKED, and so on. When no error occurs within a predetermined number of cycles, the LOCK state will occur; when the phase-locked loop device is already in the LOCK state, but an error occurs, the WARN state will appear; when the phase-locked loop device is already in the WARN state, If an error occurs, the UNLOCKED status will appear. The occurrence of an error is defined as: the time difference measured by the phase detector 50 is more than one clock cycle. These lock states, in conjunction with the time difference between the reference number h and the output signal DC0-CLK, will determine the phase detection to be 50 and output to the operation code of the loop filter 9 0. For example, the operation codes transmitted by the phase detector 50 include UP, DN, FREQH, FREQL, HOLD, etc. 4. U P # makes some adjustments to the frequency and increases the CNT value when the next reference signal edge occurs; however, the DN operation code also makes some adjustments to the frequency ’decreases the CNT value when the next reference signal edge occurs. When the phase detector 50 detects a considerable difference between the input and output clocks' and indicates that the frequency of the digital control oscillator 1 0 0 is too high, it will produce

第10頁 571516 五、發明說明（7) ------ FREQf桑作馬，將與CNT數值相關之頻率變更為較低的數值’當相位偵測器5 0偵測出輸入與輸出時脈之間存在相當大的差異’並表示數位控制震盪器1 0 0的頻率過低，故會^ 產生FREQL#作碼，將與CNT數值相關之頻率變更為較高曰的數值。而Η 0 L D操作碼之產生，會將迴路濾波器9 〇和數位控制展盛為1 0 0鎖在目前的頻率暨相位。因此，請來照第四圖，有下列.數種狀況可供判斷： …、狀況Α在LOCK狀態期間：DCO一CLK信號相值落後，傳出送UP操作碼；、狀況B在LOCK狀態期間：DCO —CLK信號相位超前，傳出送DN操作碼；、狀況C-J在LOCK狀態期間：重置CNT值至再對準（real ign) ，保持原頻率；狀況C或D在WARN狀態期間：DCO CLK信號相位落德，重置CNT值至再對準（re-allgn)，傳出送UP操灸狀況Ε或F在WARN狀態期間：DCO —CLK信號相位超前，重置C N T值至再對準（r e - a 1 i g η )，傳出送d N操作碼；狀況Α或Β在UNLOCKED狀態期間：傳出送吓或Μ操作碼；以及狀況C - J在U N L 0 C K E D狀悲期間：重置c n T值至再對準 (r e - a 1 i g η )，以F R E Q Η和F R E Q L#作碼正比例調整頻率。對於電腦圖像顯示晶片輸出之組合（c ◦ m Ρ 〇 s i t e ) HSYN〇i§號而言’ VSYNCh號會週期性地出現，以表示新圖框的開始。因此’ VSYNC&號妨礙HSYNC信號做為鎖相迴路Page 10 571516 V. Description of the invention (7) ------ FREQf Sang Zuoma, change the frequency related to the CNT value to a lower value 'When the phase detector 50 0 detects the input and output There is a considerable difference between the pulses' and it means that the frequency of the digitally controlled oscillator 100 is too low, so FREQL # will be generated as a code, and the frequency related to the CNT value will be changed to a higher value. The generation of the Η 0 L D opcode will lock the loop filter 90 and the digital control to 100 to lock the current frequency and phase. Therefore, please come to the fourth picture, there are the following. Several conditions can be judged:…, condition A is in the LOCK state: the phase value of the DCO-CLK signal is backward, and the UP operation code is transmitted; and, condition B is in the LOCK state. ： DCO —The phase of CLK signal is advanced, and the DN operation code is sent out; 、 The state CJ is in the LOCK state: reset the CNT value to the real ign to maintain the original frequency; the state C or D is in the WARN state: DCO The phase of the CLK signal is degraded, reset the CNT value to re-allgn, and send out the UP operation condition E or F during the WARN state: DCO —The phase of the CLK signal is advanced, reset the CNT value to re-alignment (Re-a 1 ig η), sending d N opcode; status A or B during UNLOCKED state: sending frightening or M opcode; and status C-J during UNL 0 CKED state: reset The cn T value is realigned (re-a 1 ig η), and the frequency is proportionally adjusted with FREQ Η and FREQL # as codes. For the combination of computer image display chip output (c ◦ m 〇〇 s i t e) HSYN〇i§ number ’VSYNCh will appear periodically to indicate the beginning of a new frame. So ‘VSYNC & prevents the HSYNC signal from acting as a phase locked loop

第11頁 571516 五、發明說明（8) 裝置之參考信號，使得鎖相迴路裝置會跟隨著參考信號的偏差（deviation)現象。第五圖係顯示根據本發明方法的流程圖。步驟n 〇開始進行鎖相迴路的控制方法後，當 HSYNC信號錯過一或更多週期、抑或是一些系統暫時的變更（例如：在VSYNC週期内），則會經由内部或外部裝置去，立（assert)慣性運作c〇AST信號，第五圖所示步驟1 20即疋偵測C 0 A s τ信號是否已確立；若否，仍回復至步驟1 2 0做 C〇AST信號之偵測。若於步驟1 20，進行步驟偵測得知 C〇AST已確立’則進行步驟1 30令相位偵測器50產生HOLD操作碼予迴路濾波器90，在LOCK或WARN狀態下，只要HOLD操 1乍碼，確立（asserted)的話，輸出信號DC0 — CLK的時脈頻 f便得^以維持不為根據參考信號變更頻率與相位，直至 SYNC信號回復為止。假若c〇AST信號與h〇ld操作碼確立過 ^ ’數位控制震盪器100内微小頻率誤差會導致DC0_CLK信 =4目對於HSYNC參考信號做漂移（drif t)，故於步驟14〇偵 7 信號是否仍確立；若是，則回復至步驟140做 st#、號之偵剛。當於步驟H〇得知c〇AST信號已移除 ^、回便進行=驟1 5 〇令相位推進器8 0致使迴路濾波器9 0改 ^迴路渡波器係數，暫時地增加up/M操作碼的影響，人 nt與/考信號HSY’對準（reallgn)，此“ # Ι^ϋ — CLK^歲相位所需時間仍後屬正確。然後，Page 11 571516 V. Description of the invention (8) The reference signal of the device makes the phase-locked loop device follow the deviation of the reference signal. The fifth figure is a flowchart showing the method according to the invention. Step n 〇 After starting the phase-locked loop control method, when the HSYNC signal misses one or more cycles, or some system is temporarily changed (for example, within the VSYNC cycle), it will go through an internal or external device, and immediately ( assert) The inertia operation of the COAST signal. Step 1 20 shown in the fifth figure is to detect whether the C 0 A s τ signal has been established; if not, return to step 120 to detect the COAST signal. If in step 1 20, perform step detection and learn that COAST has been established, then proceed to step 1 30 so that the phase detector 50 generates a HOLD operation code to the loop filter 90. In the LOCK or WARN state, as long as HOLD operates 1 At first glance, if asserted, the clock frequency f of the output signal DC0-CLK will be ^ to maintain the frequency and phase without changing according to the reference signal until the SYNC signal is restored. If the c〇AST signal and the h〇ld opcode have been established ^ 'a small frequency error in the digitally controlled oscillator 100 will cause DC0_CLK signal = 4 mesh to drift (drif t) for the HSYNC reference signal, so detect the 7 signal in step 14 Whether it is still established; if it is, then return to step 140 to do st # 、号之探刚. When it is learned at step H0 that the c0AST signal has been removed ^, then go back to step = 150. Order the phase booster 80 to cause the loop filter 90 to change the loop wavelet coefficient and temporarily increase the up / M operation. The effect of the code is that the human nt is aligned with the test signal HSY '(reallgn). This "# Ι ^ ϋ — The time required for the CLK ^ phase is still correct. Then,

=驟1 60獲取信號相位，再進行步驟1 70將UP/DN操作碼J <束至一般狀悲。此鎖相迴路裝置控制方法於步驟1 8 0處、== Step 1 60 Get the signal phase, then go to Step 1 70 to bundle the UP / DN opcode J < to a general state. This phase-locked loop device control method is at step 180, =

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571516 圖式簡單說明第一圖係顯示具有平面顯示器之習知視訊圖像系統方塊圖；第二圖係顯示根據本發明一較佳實施例之鎖相迴路裝置之示意圖；第三圖係顯示根據本發明之鎖相迴路裝置操作之時序圖，第四圖係顯示本發明之鎖相迴路裝置另一例之時序圖；以及第五圖係顯示本發明方法之流程圖。571516 Brief description of the diagram The first diagram is a block diagram showing a conventional video image system with a flat display; the second diagram is a schematic diagram of a phase-locked loop device according to a preferred embodiment of the present invention; the third diagram is based on A timing diagram of the operation of the phase-locked loop device of the present invention, the fourth diagram is a timing diagram showing another example of the phase-locked loop device of the present invention, and the fifth diagram is a flowchart showing the method of the present invention.

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Claims

571516 六、申請專利範圍 1. 一種鎖相迴路裝置，包括：一數位控制震盪器，用以產一相位偵測器，接收一參考對該參考信號之上升邊緣與上升邊緣做一比較，獲知該中最靠近該參考信號之上升生一操作碼；以及一迴路濾波器，根據該操作震盪器，據以調整該輸出信參考信號之上升邊緣者，而既定關係。 2. 如申請專利範圍第1項所一計數器，係根據一除頻信除頻後，提供予相位偵測器與該其中，該相位偵測器會根據號間之頻率差，產生另一操作碼整該輸出時脈信號之頻率與該參 3. 如申請專利範圍第2項所括： _ _年一:斤_ α 一修通補係針緣暨邊緣以產控制近該成一括：生一輸出時脈信號；信號與該輸出時脈信號，該輸出時脈信號之下降邊輸出時脈信號之若干上升邊緣間之一相位差，並據碼輸出控制信號予該數位號之若干上升邊緣中最靠與該參考信號之上升邊緣述之鎖相迴路裝置，尚包號對該輸出時脈信號進行參考信號做一比較；該除頻後信號與該參考信予迴路濾波器，並據以調考信號呈另一既定關係。述之鎖相迴路裝置，尚包該頻生一鎖指示器，根據該參考信率差，用以決定該時間差是狀態信號。 4.如申請專利範圍第3項所述之鎖相迴路裝置，尚包號與該輸出時脈信號間之否超過一個時脈週期，產571516 6. Scope of patent application 1. A phase-locked loop device, comprising: a digitally controlled oscillator for producing a phase detector, receiving a reference to compare a rising edge of the reference signal with a rising edge, and knowing that An operation code is generated closest to the rising of the reference signal, and a loop filter is used to adjust the rising edge of the output signal reference signal according to the operating oscillator, and the predetermined relationship is established. 2. For example, a counter in item 1 of the scope of patent application is provided to a phase detector after the frequency division by a frequency division signal, and the phase detector generates another operation according to the frequency difference between the numbers. Code the frequency of the output clock signal and the parameter 3. As included in item 2 of the scope of the patent application: _ _ year one: catty _ α repairing the needle edge and edge to produce control is nearly included: An output clock signal; a phase difference between the signal and the output clock signal, the falling edge of the output clock signal outputting several rising edges of the clock signal, and outputting a control signal to the rising edges of the digital number according to the code The phase-locked loop device described in the rising edge of the reference signal is used to compare the reference signal of the output clock signal with the reference signal; the frequency-divided signal and the reference signal are sent to the loop filter, and The test signal has another established relationship. The phase-locked loop device described above still includes a frequency-lock indicator, which is used to determine that the time difference is a status signal according to the reference signal difference. 4. If the phase-locked loop device described in item 3 of the scope of patent application, whether the interval between the package number and the output clock signal exceeds one clock cycle,

第15頁 571516 六、申請專利範圍括：一相位推進器，耦接至該迴路濾波器，根據該等操作碼決定是否有加速調整縮減該頻率差之需求。 5. 如申請專利範圍第1項所述之鎖相迴路裝置，其中，該參考信號是HSYNC信號。 6. 如申請專利範圍第1項所述之鎖相迴路裝置，其中，該參考信號是混合式（c 〇 m ρ 〇 s i t e ) H S Y N C信號。 7. 如申請專利範圍第1項所述之鎖相迴路裝置，其中，該迴路濾波器輸出之該控制信號具有較該輸出時脈信號為高的解析度。、 8. —種控制方法，應用於一鎖相迴路中，該方法包括下列步驟：提供一輸出時脈信號；將該參考信號之上升邊緣與該輸出信號之下降邊緣與上升邊緣做一比較；以及調整該輸出信號之若干上升邊緣中最靠近該參考信號之上升邊緣者，而與該參考信號之上升邊緣成一既定關係。 9. 如申請專利範圍第8項所述之方法，當該參考信號變動時尚具有維持該輸出信號之步驟，包括：當該參考信號變動發生時，產生一第一控制信號；藉由一第二控制信號將該輸出信號維持於目前狀態；在該參考信號停止變動後，移除該第一控制信號與該第二控制信號；以及Page 15 571516 6. Scope of patent application Including: a phase booster, coupled to the loop filter, determines whether there is a need to accelerate adjustment and reduce the frequency difference according to these operation codes. 5. The phase-locked loop device according to item 1 of the patent application scope, wherein the reference signal is an HSYNC signal. 6. The phase-locked loop device according to item 1 of the scope of patent application, wherein the reference signal is a hybrid (c 0 m ρ 0 s i t e) H S Y N C signal. 7. The phase-locked loop device according to item 1 of the scope of patent application, wherein the control signal output by the loop filter has a higher resolution than the output clock signal. 8. A control method applied to a phase-locked loop, the method includes the following steps: providing an output clock signal; comparing a rising edge of the reference signal with a falling edge and a rising edge of the output signal; And adjusting the rising edge of the output signal that is closest to the rising edge of the reference signal to have a predetermined relationship with the rising edge of the reference signal. 9. According to the method described in item 8 of the scope of patent application, when the reference signal changes, there is a step of maintaining the output signal, including: when the reference signal changes, generating a first control signal; by a second The control signal maintains the output signal at the current state; after the reference signal stops changing, removing the first control signal and the second control signal; and

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