TW569461B

TW569461B - A fabrication method for a ferroelectric capacitor applied in a low driving voltage

Info

Publication number: TW569461B
Application number: TW91134379A
Authority: TW
Inventors: Yuan-Chieh Tseng; Chao-Hsiung Wang; Tai-Bor Wu
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2002-11-26
Filing date: 2002-11-26
Publication date: 2004-01-01
Also published as: TW200409369A

Abstract

This present invention provides a fabrication method for a ferroelectric capacitor applied in a low driving voltage. This method first forms an LNO layer as a buffer layer over the down plate. Then, a PZT-Pt ferroelectric thin film is formed over the LNO layer by a sputter deposition method. Finally, an upper plate is formed over the ferroelectric thin film.

Description

569461569461

發明所屬之技術領域：本發明係有關於一低驅動電壓之鐵電先前技術：種鐵電電容，更特別是有關於一種可降電容結構。Technical field to which the invention belongs: The present invention relates to a ferroelectric with a low driving voltage. The prior art: a ferroelectric capacitor, and more particularly to a structure with a reduced capacitance.

曰^，的結構中，隨機存取記憶胞〆般是由一個場效電 =體（FET)和一個電容器所構成。資料的儲存是藉由電容為中存在於兩個電極之間的介電層極化而造成的電荷累積所達成。然而，儲存在兩個電極之間的電荷會因為介電層的物理特性而自動放電，使得隨機存取記憶體必須週期性也充電與更新才能維持其正常操作。也就是說，_旦電源切斷’電容器内的電荷會放電，且資料會流失。因此，一般記憶體中所使用的電容器為揮發性的（volati le)。過去曾提出一種使用鐵電電容器之記憶體，係利用鐵電材料作為介電材質以避免資料流失。通常，使用鐵電電容器作為儲存媒介，可以有效地儲存資料，不需要更新，主要是因為鐵電材質的特性，電荷藉由鐵電材質極化而累積，較不容易因為放電而流失。請參照第一圖為傳統的鐵電電容記憶體。以一電晶體/一電容器（1T/1C)之結構為例’其形成方法一般是先在半導體基底10上形成電晶體的閘極12、閘極介電層1 4以及源極/汲極區1 6之後，再覆蓋上一層介電層2 0，然後在介電In the structure, the random access memory cell is generally composed of a field effect transistor (FET) and a capacitor. The storage of the data is achieved by the accumulation of charge caused by the polarization of the dielectric layer existing between the two electrodes in the capacitor. However, the charge stored between the two electrodes is automatically discharged due to the physical characteristics of the dielectric layer, so that the random access memory must be periodically charged and updated to maintain its normal operation. In other words, the charge in the capacitor will be discharged and the data will be lost. Therefore, capacitors used in general memory are volati le. In the past, a memory using a ferroelectric capacitor has been proposed, which uses a ferroelectric material as a dielectric material to avoid data loss. Generally, using a ferroelectric capacitor as a storage medium can effectively store data and does not need to be updated, mainly because of the characteristics of the ferroelectric material. Charge is accumulated by polarization of the ferroelectric material, and it is less likely to be lost due to discharge. Please refer to the first figure for the traditional ferroelectric capacitor memory. Take the structure of a transistor / capacitor (1T / 1C) as an example. Its formation method is generally to first form a gate 12, a gate dielectric layer 14 and a source / drain region of a transistor on a semiconductor substrate 10. After 16, cover another layer of dielectric layer 20, and then

569461 五、發明說明（2) 極/;及極區1 6之一，最。而傳統的鐵電電容係鐵電層薄膜26，並且在此鐵電電容係以一絕緣材質比如是鈦酸船錯態，並如熟習存取快速地可以長展簡且，傳鐵電材因為幸畐酸錯錯電壓，低之操鐵電結定或切換留其極化傳統在動電容器，鐵電電容電材質提體的可能的照射而其極化狀鐵電層材化時所需右，對於必要發展極化狀狀態。態隨機其可以器依然供了發性。而損壞，態不會料’欽之操作要於更出新的層2 0中形成接觸窗插塞2 2連接到源 i # $觸窗插塞2 2上形成鐵電電容由下向^堆疊，在下電極24上形成層薄犋26上形成上電極28，而層30所包胃覆，一般鐵電層26的構成 (PZT)或是鈦酸鳃鉍（SBT)等。鐵電材質是藉由施加外部電場來選且在移除外部電場之後，依然能保此技藝者所知，鐵電電容器可取代 (DRAM)δ己憶體中所使用的二氧化矽儲存電荷，並且在電力移除之後，時間地維持其極化狀態。因此，鐵單、低價、高密度、非揮發性記憶統的dram記憶體容易受到游離輻射質對輻射損壞具有很高的阻抗性，射而改變。然而，傳統上所使用之 (PZT)或是鈦酸銷叙（ςβτ)等，其極通常最低僅能到達1 · 5伏至2伏特左作電壓下進行編寫及讀取時，實有構以應付未來所需。發明内容：在傳統鐵電電容記憶體讀取寫回中，均會牵涉鐵電電容569461 V. Description of the invention (2) Pole /; The traditional ferroelectric capacitor is a ferroelectric layer film 26, and here the ferroelectric capacitor is made of an insulating material such as a titanate boat, and can be extended and shortened quickly as it is familiar with access. The voltage of the acid is wrong, the ferroelectricity is set or switched to keep its polarization low. Traditionally, the possible irradiation of the moving capacitor and the ferroelectric capacitor electric material is necessary, and the polarization of the ferroelectric layer is required. For the necessary development of a polarization-like state. The state is random and its processor is still available for development. But the damage is not expected. The operation of Qin is to form a contact window plug 2 in the new layer 20. Connect to the source i # $ Touch window plug 2 2 to form a ferroelectric capacitor stacked from bottom to top ^ An upper electrode 28 is formed on the lower electrode 24 with a thin layer 26, and the layer 30 is covered by the general structure of the ferroelectric layer 26 (PZT) or bismuth titanate (SBT). The ferroelectric material is selected by applying an external electric field and after removing the external electric field, it can still ensure that the skilled person knows that the ferroelectric capacitor can replace the silicon dioxide used in (DRAM) delta memory to store the charge. And after the power is removed, it maintains its polarization state in time. Therefore, iron, low-cost, high-density, non-volatile memory RAM memory is susceptible to free radiation, which has high resistance to radiation damage and changes. However, the traditionally used (PZT) or titanium titanate (ς βτ), etc., usually can only reach a minimum of 1.5 volts to 2 volts for programming and reading. Meet future needs. Summary of the Invention: In the read and write back of traditional ferroelectric capacitor memory, ferroelectric capacitors are involved

之Of

晒 Η 第5頁 569461 五、發明說明（3) 極化狀態被切換至另一個完全相反之極化狀態，此時通常需要施加一大於強制電壓之外加電壓來進行切換。一般使用來構成鐵電層的材質通常為鈦酸鉛锆（PZT)或是鈦酸鳃祕（SBT)等，其切換極化狀態所需之外加電壓最低僅能低至1 · 2伏特左右’因此對於一些僅能操作在小於1 · 2伏特電壓下之7L件’將不能使用傳統之鐵電電容記憶體。本發明主要目的即是提供一種解決上述問題之鐵電電容製造方法’本發明提供一種鐵電材料製造方法，以降低整個讀取與寫回時所需外加之電壓大小。Sun exposure Page 5 569461 V. Description of the invention (3) The polarization state is switched to another completely opposite polarization state. At this time, it is usually necessary to apply a voltage greater than the forced voltage to switch. The materials used to form the ferroelectric layer are generally lead zirconate titanate (PZT) or titanate gill (SBT). The minimum applied voltage required to switch the polarization state can only be as low as about 1.2 volts. Therefore, for some 7L pieces that can only operate at voltages less than 1.2 volts, traditional ferroelectric capacitor memories cannot be used. The main object of the present invention is to provide a method for manufacturing a ferroelectric capacitor that solves the above-mentioned problem. The present invention provides a method for manufacturing a ferroelectric material, so as to reduce the voltage required during the entire reading and writing back.

本發明之另一目的即是提供一種能在低驅動電壓之情況下’即能提供大極化狀態之鐵電材料製造方法。本發明提供一種使用於低驅動電壓之鐵電電容製造方法。此鐵電電容之製程首先於下電極上形成一層鎳—爛氧化。 (LaNi03，LNO)層做為一層緩衝層，接著於其上成長〜屉由鈦酸鉛鍅（Pb(Zr卜xTix)03，PZT)與鉑（Pt)共同組成曰鐵電層，根據本發明之較佳實施例，其係使用濺擊沈積<Another object of the present invention is to provide a method for manufacturing a ferroelectric material which can provide a large polarization state at a low driving voltage. The invention provides a method for manufacturing a ferroelectric capacitor for low driving voltage. The process of this ferroelectric capacitor first forms a layer of nickel-rotten oxide on the lower electrode. (LaNi03, LNO) layer is used as a buffer layer, and then grown thereon. The drawer is composed of lead titanate (Pb (ZrbxTix) 03, PZT) and platinum (Pt). According to the present invention, A preferred embodiment uses sputtering deposition <

(sputter deposition)之方法來沈積上述之鐵電層，種由鈦酸鉛銼與鉑共同組成之鐵電層結構中，鈦酸錯參此屬於多數載子，而鉑為少數載子，因此本發明會利用=係施加於鈦酸鉛锆與鉑耙背面之射頻能量，來調整彼此&制度大小。最後在於鐵電層上成長一層上電極，即完 $濃明之鐵電電容。 ^ 發實施方法：(sputter deposition) method to deposit the above ferroelectric layer. In a ferroelectric layer structure composed of a lead titanate file and platinum, titanate is a majority carrier, and platinum is a minority carrier. The invention will use the RF energy applied to the back of lead zirconate titanate and platinum rake to adjust the size of each other's system. Finally, a layer of upper electrode is grown on the ferroelectric layer, which is the complete ferroelectric capacitor. ^ Send Implementation method:

569461 五、發明說明（4)569461 V. Description of Invention (4)

在不限制本發明之精神及應用範圍之下，以下即以一鐵電材料製造實施例，介紹本發明之實施；熟悉此領域技藝者’在瞭解本發明之精神後，當可應用此製造方法於各種不同之鐵電記憶體電路中，藉由本發明之鐵電材料製造方法’來降低鐵電電容於讀取與寫回週期時所需外加之驅動電壓大小，消除傳統上由於用來構成鐵電層的材質，其切換極化狀態時所需之外加電壓需大於i · 2伏特，造成傳統之鐵電電容不能使用於操作電壓小於1 · 2伏特下之電路元件’本發明之應用當不僅限於以下所述之實施例。Without limiting the spirit and application scope of the present invention, the following is an example of manufacturing a ferroelectric material to introduce the implementation of the present invention; those skilled in the art will be able to apply this manufacturing method after understanding the spirit of the present invention In various ferroelectric memory circuits, the ferroelectric material manufacturing method of the present invention is used to reduce the size of the driving voltage required for the ferroelectric capacitor during the read and write-back cycles, eliminating traditionally used to form iron The material of the electrical layer requires an applied voltage greater than i · 2 volts when switching the polarization state, so that traditional ferroelectric capacitors cannot be used for circuit elements with operating voltages less than 1.2 volts. It is limited to the embodiment described below.

參閱第二圖，為鐵電材料磁滯曲線，其中橫座標代表施加於鐵電材料上之電場強度，縱座標代表鐵電材料之極化狀態。假如使用鐵電材料填充於電容兩極板間，由磁滞曲線可看出’流經電容之電流大小是根據先前施加於鐵電電容之電壓所造成之極化狀態，也就是說，假如最初施加於鐵電電容之電壓為〇伏特，鐵電電容之極化狀態可能在A點或 D點’假設極化狀態是在a點，當於鐵電電容之兩極板間施加一南於強制電壓（Coercive Voltage)(即第一圖中B 點）之轉換電壓，會轉換鐵電電容之極化狀態，在此情形下’鐵電電容將會釋放所儲存之電荷並轉換到另一種極化狀態（即第一圖中C點），當移除施加於鐵電電容之電壓’鐵電電容會維持在相同極化狀態並轉移至以點，而不會回到A點之極化狀態，若此時施加正電壓於鐵電電容上’鐵電電容極化狀態僅會造成微小之改變，若施加負電See the second figure for the hysteresis curve of the ferroelectric material, where the horizontal coordinate represents the electric field strength applied to the ferroelectric material, and the vertical coordinate represents the polarization state of the ferroelectric material. If a ferroelectric material is used to fill the two plates of the capacitor, the hysteresis curve shows that the magnitude of the current flowing through the capacitor is based on the polarization state caused by the voltage previously applied to the ferroelectric capacitor. That is, if initially applied When the voltage of the ferroelectric capacitor is 0 volts, the polarization state of the ferroelectric capacitor may be at point A or D. Assume that the polarization state is at point a. When a south-force voltage is applied between the two plates of the ferroelectric capacitor ( Coercive Voltage) (ie point B in the first picture) will change the polarization state of the ferroelectric capacitor. In this case, the 'ferroelectric capacitor will release the stored charge and switch to another polarization state ( (Point C in the first figure), when the voltage applied to the ferroelectric capacitor is removed, the ferroelectric capacitor will maintain the same polarization state and transfer to the point, instead of returning to the point A polarization state. When applying a positive voltage to a ferroelectric capacitor, the polarization state of the ferroelectric capacitor will only cause a small change.

第7頁 569461 五、發明說明（5) 壓於鐵電電容上，此時鐵電電Page 7 569461 V. Description of the invention (5) Press on the ferroelectric capacitor.

點，當移除施加於鎧電雷六夕♦極狀& 9從D點轉移至E 刀口於鐵電電4之電壓，鎩雷雷交同極化狀態並從E點轉移至A點， ς $持在相施加於鐵電電衮t# Α #因此人點和D點可代表當能，0^ #之電^為〇伏特時’兩種不同之邏輯狀 :大（ΐρ信：兩點相距越遠，亦即兩者之極化狀態值差距 1由；^ π越大），代表儲存之效能越好。鐵電材質即疋，由施力:外部電場來選定或切換其極化狀態，並且在除外部電场之後’依然能保留其極化狀態。然而，由於在切換極化狀態時，需於兩極板間施加一高於強制電壓^即第一圖中Β點）之轉換電壓，來轉換鐵電電容之極化狀態，因此，若可降低所需強制電壓之大小，將可使得鐵電電谷亦可應用於低驅動電壓之各種電路元件中。首先對本發明較佳實施例之使用低驅動電壓之鐵電電容結構進行說明，然值得注意的是，本發明並非僅限定用於其下所述之較佳實施例結構。請參照第三圖，其繪示本發明之較佳實施例的結構剖面示意圖。首先提供一半導體基底 I 0 0，例如是具有< 1 0 0 >結構之ρ型矽基底。在基底1 〇〇上已完成部分之半導體元件之製作，在基底100之主動區域上製作出電晶體’通常包括閘極1 〇 2，在閘極1 〇 2與基底1 〇〇之間的閘極氧化層1 0 4，然後比如以離子植入法在閘極1 〇 2 雨側形成源極/汲極區1 0 6。接著於電晶體上覆蓋層絕緣層 110，比如是二氧化矽、旋塗式玻璃（SOG)、低介電（Low-k)材質或是其組合。並在絕緣層110中形成一接觸窗插塞 II 2耦接至源極/汲極區1 0 6，接觸窗插塞11 2所使用之材質Point, when removing the voltage applied to the armored electric thunderstorm ♦ pole shape & 9 transferred from point D to E blade at ferroelectric 4 voltage, the thunder and lightning crossed the same polarization state and transferred from point E to point A, $ 持在相 Applied to the ferroelectric electricity 衮 t # Α # Therefore, the human point and the D point can represent when the energy, 0 ^ # 的电 ^ is 0 volts' two different logical states: large (ΐρ letter: two points apart The farther away, that is, the difference in polarization state values between the two (by ^ π the greater), the better the storage performance. The ferroelectric material is 疋, and its polarization state is selected or switched by the force: external electric field, and its polarization state can be retained after the external electric field. However, when switching the polarization state, a conversion voltage higher than the forced voltage (ie point B in the first figure) needs to be applied between the two plates to switch the polarization state of the ferroelectric capacitor. The magnitude of the forced voltage will enable the ferroelectric valley to be applied to various circuit components with low driving voltage. First, a ferroelectric capacitor structure using a low driving voltage according to a preferred embodiment of the present invention will be described. However, it should be noted that the present invention is not limited to the structure of the preferred embodiment described below. Please refer to the third figure, which is a schematic structural cross-sectional view of a preferred embodiment of the present invention. First, a semiconductor substrate I 0 0 is provided, for example, a p-type silicon substrate having a < 1 0 0 > structure. The fabrication of a part of the semiconductor element has been completed on the substrate 100, and the transistor is usually formed on the active area of the substrate 100. The gate generally includes a gate electrode 102, and a gate between the gate electrode 102 and the substrate 100. An electrode oxide layer 104 is formed, and then a source / drain region 106 is formed on the rain side of the gate electrode 102 by an ion implantation method. Then, an insulating layer 110 is coated on the transistor, such as silicon dioxide, spin-on-glass (SOG), low-k material, or a combination thereof. A contact window plug II 2 is formed in the insulating layer 110 and is coupled to the source / drain region 106. The material used for the contact window plug 11 2

第8頁 569461 五、發明說明（6) 比如是鎢（W)、複晶矽（P〇ly-Si)或是摻雜複晶矽（D〇ped poly-Si)等’以本最佳實施例而言為鎢。其製造方法一般是利用微影及蝕刻技術，首先在絕緣層u 〇上形成一層圖案化光阻層（未顯示）’接著以此圖案化光阻層為罩幕，姓刻絕緣層11 0，以在絕緣層11 〇中形成接觸窗開口，之後去除圖案化光阻層。由於此結構之製程多為熟習此技藝者所熟知之技術’所以僅作簡單的說明，但並不因此限制本發明結構之製造方法。接者於絕緣層11 〇上形成本發明之具低驅動電壓之鐵電電容’其包括由下向上之下電極134、緩衝層140、鐵電薄膜層142與上電極138。其中，下電極134的構成材質比如是鉑（Pt)、銥（Ir)或是氧化銥（ΐΓ〇2)等，上電極ι38的構成材質則對應於下電極1 3 4，比如是鉑（p t)、銥（I r)或是氧化銥（Ir02)等’除了上述舉例的材質外，其他適用之材質亦可。至於鐵電薄膜層14 2的製造方法，請參閱第四圖為本發明鐵電電容之放大圖，本發明之鐵電電容，首先於下電極 13 4上形成一層鎳-鑭氧化物（1^“03，1^0)層140，其中此鎳-鋼氧化物（LaNi03，LN0)層140，主要是做為一層緩衝層，由於鎳-爛氧化物（LaNi 03，LN0)層140為一種鈣鈦礦形式（perovskite-type)之金屬氧化物電極，其晶格常數（lattice constant)約為〇·383ηιη，且其晶格方向為 (100)，此鎳-綱氧化物（LaNi03, LN0)層140可幫助鐵電材料在低溫狀況下較容易形成晶體，因為在形成鐵電薄膜層Page 8 569461 V. Description of the invention (6) For example, tungsten (W), polycrystalline silicon (Poly-Si) or doped poly-Si, etc. An example is tungsten. Its manufacturing method generally uses lithography and etching technology. First, a patterned photoresist layer (not shown) is formed on the insulating layer u 〇, and then the patterned photoresist layer is used as a mask. To form a contact window opening in the insulating layer 110, and then remove the patterned photoresist layer. Since the manufacturing process of this structure is mostly a technique familiar to those skilled in the art, it will only be described briefly, but it does not limit the manufacturing method of the structure of the present invention. A ferroelectric capacitor with a low driving voltage according to the present invention is formed on the insulating layer 110. The ferroelectric capacitor includes a bottom electrode 134, a buffer layer 140, a ferroelectric thin film layer 142, and an upper electrode 138. The constituent material of the lower electrode 134 is, for example, platinum (Pt), iridium (Ir), or iridium oxide (ΐΓ〇2), and the constituent material of the upper electrode ι38 corresponds to the lower electrode 134, such as platinum (pt ), Iridium (Ir) or iridium oxide (Ir02), etc. 'In addition to the materials exemplified above, other suitable materials may also be used. As for the manufacturing method of the ferroelectric thin film layer 14 2, please refer to the fourth figure for an enlarged view of the ferroelectric capacitor of the present invention. In the ferroelectric capacitor of the present invention, a layer of nickel-lanthanum oxide (1 ^ "03,1 ^ 0) layer 140, wherein the nickel-steel oxide (LaNi03, LN0) layer 140 is mainly used as a buffer layer, because the nickel-rotten oxide (LaNi 03, LN0) layer 140 is a kind of calcium The perovskite-type metal oxide electrode has a lattice constant of about 0.383 ηη and a lattice direction of (100). This nickel-gang oxide (LaNi03, LN0) layer 140 can help ferroelectric materials to form crystals more easily at low temperatures, because in the formation of ferroelectric thin film layers

第9頁 569461 五、發明說明（7) 1 4 2之過程中，製程溫度約為5 〇〇至7 〇〇°c，鐵電薄膜層1 4 2 與下電極134間所形成界面反應將會影響鐵電薄膜層142之特性’因此本發明於鐵電薄膜層1 4 2與下電極1 3 4間，成長一層鎳~鑭氧化物（LaNi03，LNO)層140作為緩衝層，可降低鐵電薄膜層1 4 2所需之結晶溫度至5 0 (TC，以本較佳實施例而言，此層之厚度約為；[5 0埃（A n g s t r 〇 m)。當完成此鎳-鑭氧化物（LaNi 03，LN0)層1 40後，.本發明會於其上成長一層由鈦酸鉛錘（Pb(Zr卜xTix)03，PZT)與鉑 (Pt)共同組成之鐵電薄膜層142，根據本發明之較佳實施例’其係使用錢擊沈積（s p u 11 e r d e ρ 〇 s i t i ο η)之方法來沈積上述之鐵電薄膜層142，但是化學氣相沈積方式 (CVD) 、ΜΒΕ或電鍍之方式亦可被使用。請參閱第五圖為本發明使用來進行鈦酸鉛锆（ΡΖΤ)與鉑（Pt)鐵電層沈積之濺鍍設備概略圖，其中濺鍍是以離子加速，通常是用 Ar+，經過一電位梯度，以離子去轟擊靶，而靶材背面會施加一射頻（RF)，以吸引Ar+離子使濺擊發生，把乾材表面之原子揮發，而以蒸汽之形式鍍到晶圓上。就本發明之較佳實施例而言，本發明之結晶層1 4 2，其係使用鈦酸鉛锆150 (PZT)與鉑152 (Pt)當作靶，當進行沈積時’一元成上述製程且其上表面具有錄-綱氧化物 (LaNi 03，LNO)層14 0之基板154被放置於機座156上，其中此機座1 5 6會以一角速度ω進行旋轉，此旋轉目的係為獲得均勻之沈積。讓基板1 5 4輪流位於鈦酸船鍅1 5 〇與始1 5 2 靶之下方，以交替沈積鈦酸鉛鍅1 5 0與鉑1 5 2。當沈積開始Page 9 569461 V. Description of the invention (7) During the process of 1 42, the process temperature is about 5000 to 700 ° C, and the interface reaction between the ferroelectric thin film layer 14 2 and the lower electrode 134 will be formed. Affects the characteristics of the ferroelectric thin film layer 142. Therefore, the present invention grows a layer of nickel-lanthanum oxide (LaNi03, LNO) 140 as a buffer layer between the ferroelectric thin film layer 142 and the lower electrode 134, which can reduce ferroelectricity. The required crystallization temperature of the thin film layer 1 4 2 is 50 ° C (in the present preferred embodiment, the thickness of this layer is approximately; [50 angstrom (A ngstr om). When this nickel-lanthanum oxidation is completed, After the material (LaNi 03, LN0) layer 1 40, the present invention will grow a ferroelectric thin film layer 142 composed of a lead titanate hammer (Pb (ZrbxTix) 03, PZT) and platinum (Pt). According to a preferred embodiment of the present invention, it is a method of depositing the above-mentioned ferroelectric thin film layer 142 using a method of coin deposit (spu 11 erde ρ siti ο η), but chemical vapor deposition (CVD), MBE or The electroplating method can also be used. Please refer to the fifth figure for the lead zirconate titanate (PZT) and platinum (Pt) ferroelectric layer deposition used in the present invention. Schematic diagram of sputtering equipment. Sputtering is accelerated by ions, usually Ar +. After a potential gradient, the target is bombarded with ions. A radio frequency (RF) is applied to the back of the target to attract Ar + ions to cause sputtering. The atoms on the surface of the dry material are volatilized and plated on the wafer in the form of steam. In the preferred embodiment of the present invention, the crystalline layer 1 4 2 of the present invention uses lead zirconate titanate 150 (PZT ) And platinum 152 (Pt) as targets. When the deposition is performed, the substrate 154 having the above-mentioned process and having a recording-order oxide (LaNi 03, LNO) layer 140 on the upper surface is placed on the base 156. Among them, the base 1 56 will rotate at an angular velocity ω, and the purpose of this rotation is to obtain uniform deposition. Let the substrate 15 4 alternately be located below the titanate boat bow 1 50 and the target 1 2 5 to alternate Deposit lead titanate 鍅 15 0 and platinum 1 5 2. When the deposition begins

第10頁 569461 五、發明說明（8) 時，首先一 Ar+離子會轟擊鈦酸鉛錯1 5 〇之靶及鉑工5 2靶，鈥酸錯鍅15〇表面及始152表面之原子會揮發，並以原子之形式鍍到基板154之鎳-鑭氧化物（LaNi〇3, LN〇)層14〇上，以本較佳實施例而言，此層之厚度約為15〇〇埃 (Angstrom)，且所成長之厚度必須不改變LN〇層之結構方向。以本較佳實施例而言，此鈦酸鉛锆15〇與鉑152之沈積會持續進行至總沈積厚度約為9〇〇埃。以本發明之較佳實施例而言，此種由鈦酸鉛鍅與鉑共同組成之鐵電薄膜層1 4 2之結構中，鈦酸鉛錐係屬於多數載子，而鉑為少數載子，因此本發明會利用控制施加於鈦酸鉛鍅150與鉑152靶背面之射頻能量，來調整彼此之濃度大小。以本較佳實施例而言，於鈦酸鉛锆與鉑共同組成之鐵電層結構中，而鉑之含量比小於1 〇%，且其於其中之密度約小於5x 1013ea/cm2，其中鉑之大小為1〇至7〇奈米 (nm)。接著一回火（anneal ing)製程被施加於此完成鈦酸鉛锆 1 5 0與始1 5 2沈積之基板1 5 4上，此回火溫度約為5 5 0°C，而回火時間約為1至1 〇分鐘，用來將形成本發明鈦酸鉛锆（pb (Zrl - xTix)03，PZT)與鉑（Pt)形成結晶，由於本發明之鈦酸船錘（Pb(Zr卜xTix)03，PZT)與鉑（Pt)之結晶層係成長於鎳-鋼氧化物（LaNi 03，LN0)緩衝層140之上，因此於進行Θ火結晶時之溫度可降低至550°C。最後上電極138成長於此結晶層上即完成本發明之鐵電電容。值得注意的是，上述鈦酸鉛锆（Pb(Zrl-xTix)03, PZT)與Page 10 569461 5. In the description of the invention (8), first, an Ar + ion will bombard the target of lead titanate 1 50 and the target 5 2 of platinum, and the atoms on the surface of the acid 1150 and the surface of the first 152 will volatilize. And is atomically plated on the nickel-lanthanum oxide (LaNi〇3, LN〇) layer 14 of the substrate 154. In the preferred embodiment, the thickness of this layer is about 1 500 Angstroms (Angstrom ), And the grown thickness must not change the structural direction of the LN0 layer. In the preferred embodiment, the deposition of lead zirconium titanate 15 and platinum 152 will continue until the total deposition thickness is about 900 angstroms. According to a preferred embodiment of the present invention, in the structure of the ferroelectric thin film layer 14 composed of lead titanate and platinum, the lead titanate cone belongs to the majority carrier, and platinum is the minority carrier. Therefore, the present invention will adjust the concentration of each other by controlling the radio frequency energy applied to the back surface of the lead titanate 150 and platinum 152 targets. In this preferred embodiment, in a ferroelectric layer structure composed of lead zirconate titanate and platinum, the content ratio of platinum is less than 10%, and its density therein is less than about 5x 1013ea / cm2, of which platinum The size is between 10 and 70 nanometers (nm). Then an annealing process is applied to the substrate 1150 which has been deposited with lead zirconate titanate 1550 and starting 1524. The tempering temperature is about 550 ° C, and the tempering time About 1 to 10 minutes, used to crystallize the lead zirconium titanate (pb (Zrl-xTix) 03, PZT) forming the present invention with platinum (Pt), because the titanate boat hammer (Pb (Zr The crystal layer of xTix) 03, PZT) and platinum (Pt) is grown on the nickel-steel oxide (LaNi 03, LN0) buffer layer 140, so the temperature during Θ fire crystallization can be reduced to 550 ° C. Finally, the upper electrode 138 is grown on the crystalline layer to complete the ferroelectric capacitor of the present invention. It is worth noting that the above-mentioned lead zirconium titanate (Pb (Zrl-xTix) 03, PZT) and

569461 五、發明說明（9) 鉑（Pt)之結晶層並非僅限於僅成長一層，於另一實施例中，亦可於鈦酸鉛鍅（Pb(Zrl-xTix)03，PZT)與鉑（Pt)之結晶層上另行成長一層鈦酸鉛鍅（PZT)層，接著在於其上形成鈦酸錯錯（P b ( Z r 1 - X T i X ) 0 3，P Z T )與鉑（P t )之結晶層，而共同組成鐵電薄膜。換句話說，就本發明而言，其中之鐵電薄膜層係至少由一層鈦酸鉛锆（Pb(Zr卜xTix)03, PZT)與鉑（Pt)之結晶層所組成，但並不僅限於一層。請參閱第六圖，為本發明由鈦酸鉛锆與鉑共同形成之鐵電薄膜層，與僅由鈦酸鉛锆所形成之鐵電薄膜層兩者間於相同驅動電壓下之極化狀態值差距大小，即圖中2Pr值，由圖中可明顯看出於驅動電壓僅1伏特之情況下，僅由鈦酸鉛锆所形成之鐵電薄膜層其極化狀態值差距幾乎為〇 (// C/cm2)，換句話說，其幾乎沒有健存能力。而相反的，藉由本發明之較優具體實施例之鈹酸錯錯與始共同形成之鐵電薄膜層，其於3 · 4 %與4 %之鉑比率下，其極化狀態值差距約為7 (# C / c m 2 )左右’仍具有相當之儲存能力，因此很明顯的，利用本發明之方法所形成之鐵電薄膜層其在1伏特之驅動電壓下，仍可正常動作。綜合以上所述’本發明揭露一種鐵電層薄膜，可以使鐵電電容應用於低驅動電壓中，以降低整個讀取與寫回時所需外加之電壓大小。且能在低驅動電壓之情況下，即提供大極化狀態。如熟悉此技術之人員所暸解的，以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡569461 V. Description of the invention (9) The crystalline layer of platinum (Pt) is not limited to growing only one layer. In another embodiment, it can also be used in lead titanate (Pb (Zrl-xTix) 03, PZT) and platinum ( On the crystalline layer of Pt), another layer of lead titanate (PZT) was grown, and then titanate faults (P b (Z r 1-XT i X) 0 3, PZT) and platinum (P t) were formed thereon. The crystalline layers together form a ferroelectric thin film. In other words, as far as the present invention is concerned, the ferroelectric thin film layer is composed of at least one crystalline layer of lead zirconium titanate (Pb (ZrbxTix) 03, PZT) and platinum (Pt), but it is not limited to layer. Please refer to the sixth figure, which shows the polarization state of the ferroelectric thin film layer formed by lead zirconate titanate and platinum together with the ferroelectric thin film layer formed only by lead zirconate titanate at the same driving voltage. The value gap, that is, the value of 2Pr in the figure, can be clearly seen from the figure that when the driving voltage is only 1 volt, the difference in polarization state value of the ferroelectric thin film layer formed only by lead zirconate titanate is almost 0 ( // C / cm2), in other words, it has almost no ability to survive. On the contrary, the ferroelectric thin film layer formed by the beryllium acid fault and the co-formation of the more preferred embodiment of the present invention has a polarization state value difference of about 3.4% and 4% platinum. About 7 (# C / cm 2) still has considerable storage capacity, so it is obvious that the ferroelectric thin film layer formed by the method of the present invention can still operate normally at a driving voltage of 1 volt. To sum up, the present invention discloses a ferroelectric layer film, which can enable ferroelectric capacitors to be used in low driving voltages, so as to reduce the overall voltage required during reading and writing back. And can provide a large polarization state at low driving voltage. As will be understood by those familiar with this technology, the above are only preferred embodiments of the present invention and are not intended to limit the scope of patent application for the present invention;

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569461 圖式簡單說明本發明的較佳實施例將於往後之說明文字中輔以下列圖形做更詳細的闞述，其中為說明方便起見，各圖所示之相同數字代表相同的裝置，其中：第一圖所示為習知一般1 T -1 C鐵電記憶胞之結構示意圖；第二圖所示為鐵電材料磁滯曲線；第三圖繪示本發明之較佳實施例的鐵電電容元件結構剖面不意圖，第四圖所示為本發明之較佳實施例的鐵電電容放大圖；第五圖所示為用來進行鈦酸鉛锆（PZT)與鉑（Pt)鐵電層沈積之濺鍍設備概略圖；以及第六圖所示為本發明由鈦酸鉛#與鉑共同形成之鐵電薄膜層，與僅由鈦酸船錯所形成之鐵電薄膜層兩者間於相同驅動電壓下之極化狀態值差距大小。圖號對照說明： 10和100半導體基底 1 2和1 0 2閘極 1 4和1 0 4閘極介電層 1 6和1 0 6源極/汲極區 20介電層 2 2和11 2接觸窗插塞 2 4和1 3 4下電極569461 Schematic illustration of the preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, where for the sake of convenience, the same numbers shown in the figures represent the same device, Among them: the first diagram shows the structure of a conventional 1 T -1 C ferroelectric memory cell; the second diagram shows the hysteresis curve of a ferroelectric material; the third diagram shows a preferred embodiment of the present invention The structure section of the ferroelectric capacitor element is not intended. The fourth figure shows an enlarged view of the ferroelectric capacitor in the preferred embodiment of the present invention. The fifth figure shows the use of lead zirconate titanate (PZT) and platinum (Pt). The schematic diagram of the sputtering equipment for the ferroelectric layer deposition; and the sixth figure shows the ferroelectric thin film layer formed by the lead titanate # and platinum together with the ferroelectric thin film layer formed by the titanate only The difference between the polarization state values at the same driving voltage. Drawing number comparison description: 10 and 100 semiconductor substrates 1 2 and 1 0 2 gates 1 4 and 1 0 4 gate dielectric layers 16 and 10 6 source / drain regions 20 dielectric layers 2 2 and 11 2 Contact window plugs 2 4 and 1 3 4 lower electrodes

569461 圖式簡單說明 2 6鐵電層薄膜 2 8和1 3 8上電極 3 0和11 0絕緣層 1 4 0緩衝層 1 4 2鐵電層 1 5 0鈦酸鉛锆 15 2鉑 1 5 4基板 1 5 6機座569461 Schematic illustration 2 6 Ferroelectric layer film 2 8 and 1 3 8 Upper electrode 3 0 and 11 0 Insulating layer 1 4 0 Buffer layer 1 4 2 Ferroelectric layer 1 50 0 Lead zirconate titanate 15 2 Platinum 1 5 4 Base 1 5 6 base

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Claims

569461 六、申請專利範圍 1. 一種可使用於低驅動電壓下之鐵電電容製造方法，該方法至少包括：形成一下電極；形成一緩衝層於該下電極上；形成一由鈦酸鉛锆與鉑共同組成之鐵電層於該鎳-爛氧化物緩衝層之上；執行一回火製程，結晶化該鈦酸鉛錘與鉑共同組成之鐵電層成為一結晶層，以及形成一上電極於該結晶層上。569461 6. Application patent scope 1. A method for manufacturing a ferroelectric capacitor which can be used at a low driving voltage, the method at least comprises: forming a lower electrode; forming a buffer layer on the lower electrode; forming a lead zirconate titanate and A ferroelectric layer composed of platinum on the nickel-rotten oxide buffer layer; a tempering process is performed to crystallize the ferroelectric layer composed of the lead titanate hammer and platinum into a crystalline layer, and form an upper electrode On the crystal layer.

2. 如申請專利範圍第1項所述之方法，其中上述之緩衝層係由鎳-鑭氧化物所構成。 3. 如申請專利範圍第1項所述之方法，其中上述之緩衝層厚度約為3 5 0至1 5 0 0埃。 4. 如申請專利範圍第1項所述之方法，其中上述之於鈦酸鉛锆與鉑共同組成之鐵電層係以濺鍍之方式沈積於緩衝層上。2. The method according to item 1 of the scope of patent application, wherein the above buffer layer is composed of nickel-lanthanum oxide. 3. The method according to item 1 of the scope of the patent application, wherein the thickness of the buffer layer is about 350 to 1500 angstroms. 4. The method according to item 1 of the scope of the patent application, wherein the above ferroelectric layer composed of lead zirconate titanate and platinum is deposited on the buffer layer by sputtering.

5. 如申請專利範圍第1項所述之方法，其中上述之鈦酸鉛锆與鉑共同組成之鐵電層厚度約為50 0至200 0埃。 6. 如申請專利範圍第1項所述之方法，其中上述之鈦酸鉛5. The method according to item 1 of the scope of patent application, wherein the thickness of the ferroelectric layer composed of the above-mentioned lead zirconate zirconate and platinum is about 50 to 200 angstroms. 6. The method according to item 1 of the scope of patent application, wherein the above-mentioned lead titanate

第16頁 569461 六、申請專利範圍锆與鉑共同組成之鐵電層結構中，其中鉑之大小為1 0至7 0 奈米（nm)。 7. 如申請專利範圍第1項所述之方法，其中上述之於鈦酸鉛锆與鉑共同組成之鐵電層結構中，鉑之含量比約為2. 5% 至 8 · 5 % 〇 8. 如申請專利範圍第1項所述之方法，其中上述之於鈦酸鉛锆與鉑共同組成之鐵電層結構中，鉑之密度約為5Page 16 569461 6. Scope of patent application In the ferroelectric layer structure composed of zirconium and platinum, the size of platinum is 10 to 70 nanometers (nm). 7. The method according to item 1 of the scope of patent application, wherein in the above ferroelectric layer structure composed of lead zirconate titanate and platinum, the content ratio of platinum is about 2.5% to 8.5% 〇8 The method according to item 1 of the scope of patent application, wherein in the above ferroelectric layer structure composed of lead zirconate titanate and platinum, the density of platinum is about 5

011至 5 013ea/cm2。 9. 如申請專利範圍第1項所述之方法，其中上述之回火製程溫度約為2 5 0至7 5 0°C。 1 0.如申請專利範圍第1項所述之方法，其中上述之回火製程溫度時間約為1至1 0分鐘。 11. 如申請專利範圍第1項所述之方法，其中形成上述之上電極和下電極材料係選自鉑（Pt)、銥（Ir)或是氧化銥011 to 5 013ea / cm2. 9. The method according to item 1 of the scope of patent application, wherein the temperature of the above-mentioned tempering process is about 250 to 750 ° C. 10. The method according to item 1 of the scope of patent application, wherein the temperature time of the above-mentioned tempering process is about 1 to 10 minutes. 11. The method according to item 1 of the scope of patent application, wherein the material for forming the upper electrode and the lower electrode is selected from platinum (Pt), iridium (Ir), or iridium oxide

(Ir02)其中之一。 12. —種可使用於低驅動電壓下之鐵電電容製造方法，該方法至少包括：形成一下電極；(Ir02) One of them. 12. A method for manufacturing a ferroelectric capacitor which can be used at a low driving voltage, the method at least comprises: forming a lower electrode;

第17頁 569461 六、申請專利範圍形成一緩衝層於該下電極上；形成一由鈦酸鉛锆與鉑共同組成之鐵電層於該鎳-鑭氧化物緩衝層之上；執行一回火製程，結晶化該鈦酸鉛鍅與鉑共同組成之鐵電層成為^一結晶層；形成一緩衝層於該結晶化之鈦酸鉛錯與鉑共同組成之鐵電層上；以及形成一上電極於該結晶層上。 1 3.如申請專利範圍第1 2項所述之方法，其中上述之緩衝層係由鎳-鋼氧化物所構成。 14. 如申請專利範圍第12項所述之方法，其中上述之緩衝層厚度約為3 5 0至1 5 0 0埃。 15. 如申請專利範圍第12項所述之方法，其中上述之於鈦酸鉛锆與鉑共同組成之鐵電層係以濺鍍之方式沈積於緩衝層上。 16. 如申請專利範圍第12項所述之方法，其中上述之鈦酸鉛锆與鉑共同組成之鐵電層厚度約為3 5 0至2 0 0 0埃。 1 7.如申請專利範圍第1 2項所述之方法，其中上述之鈦酸鉛锆與鉑共同組成之鐵電層結構中，其中鉑之大小為1 〇至Page 17 569461 6. The scope of the patent application forms a buffer layer on the lower electrode; forms a ferroelectric layer composed of lead zirconate titanate and platinum on the nickel-lanthanum oxide buffer layer; performs a tempering In the manufacturing process, the ferroelectric layer composed of the lead titanate and platinum is crystallized to form a crystal layer; a buffer layer is formed on the ferroelectric layer composed of the crystallized lead titanate and platinum; and an upper layer is formed. An electrode is on the crystalline layer. 1 3. The method according to item 12 of the scope of patent application, wherein the buffer layer is composed of nickel-steel oxide. 14. The method according to item 12 of the scope of patent application, wherein the thickness of the buffer layer mentioned above is about 350 to 1500 angstroms. 15. The method according to item 12 of the scope of the patent application, wherein the above ferroelectric layer composed of lead zirconate titanate and platinum is deposited on the buffer layer by sputtering. 16. The method according to item 12 of the scope of patent application, wherein the thickness of the ferroelectric layer composed of the above-mentioned lead zirconate titanate and platinum is about 350 to 2000 angstroms. 17. The method as described in item 12 of the scope of the patent application, wherein in the above ferroelectric layer structure composed of lead zirconate titanate and platinum, the size of platinum is 10 to

第18頁 569461 六、申請專利範圍 7 0奈米（nm)。 18. 如申請專利範圍第12項所述之方法，其中上述之於鈦酸鉛锆與鉑共同組成之鐵電層結構中，鉑之含量比約為2. 5%至 8·5%〇 19. 如申請專利範圍第12項所述之方法，其中上述之於鈦酸鉛锆與鉑共同組成之鐵電層結構中，鉑之密度約為5 0 11至 5 013ea/cm2 〇Page 18 569461 6. Application scope of patent 70 nanometers (nm). 18. The method as described in item 12 of the scope of patent application, wherein in the above ferroelectric layer structure composed of lead zirconate titanate and platinum, the content ratio of platinum is about 2.5% to 8.5%. The method according to item 12 of the scope of patent application, wherein in the above ferroelectric layer structure composed of lead zirconate titanate and platinum, the density of platinum is about 5 0 11 to 5 013ea / cm2.

20. 如申請專利範圍第12項所述之方法，其中上述之回火製程溫度約為2 5 0至7 5 0°C。 2 1.如申請專利範圍第1 2項所述之方法，其中上述之回火製程溫度時間約為1至1 0分鐘。 2 2.如申請專利範圍第1 2項所述之方法，其中形成上述之上電極和下電極材料係選自鉑（P t )、銥（I r)或是氧化銥 (Ir02)其中之一。20. The method according to item 12 of the scope of patent application, wherein the tempering process temperature is about 250 to 750 ° C. 2 1. The method as described in item 12 of the scope of patent application, wherein the tempering process temperature time is about 1 to 10 minutes. 2 2. The method according to item 12 of the scope of patent application, wherein the material for forming the upper electrode and the lower electrode is selected from one of platinum (P t), iridium (I r), or iridium oxide (Ir02). .

23. —種可使用於低驅動電壓下之鐵電電容結構，其中該鐵電電容係架構在一半導體基底上，該半導體基底中具有一電晶體，以及連接該電晶體源極或汲極之接觸窗插塞，該結構至少包括：23. A ferroelectric capacitor structure which can be used at a low driving voltage, wherein the ferroelectric capacitor is structured on a semiconductor substrate having a transistor in the semiconductor substrate and a source or drain connected to the transistor. The contact window plug, the structure includes at least:

第19頁 569461 六、申請專利範圍第一導體層，位於該半導體基底上，且與該接觸窗插塞連接，作為該鐵電電容之下電極；一緩衝層，位於該第一導體層上；一由鈦酸鉛鍅與鉑共同組成之鐵電材料層，位於該緩衝層上；以及第二導體層，位於該鐵電材料層上，作為該鐵電電容之下電極。Page 19 569461 6. The scope of patent application The first conductor layer is located on the semiconductor substrate and is connected to the contact window plug as the lower electrode of the ferroelectric capacitor; a buffer layer is located on the first conductor layer; A ferroelectric material layer composed of lead titanate and platinum is located on the buffer layer; and a second conductor layer is located on the ferroelectric material layer as the lower electrode of the ferroelectric capacitor.

2 4.如申請專利範圍第23項所述之結構，其中上述之緩衝層係由鎳-爛氧化物所構成。 2 5.如申請專利範圍第2 3項所述之結構，其中上述之緩衝層厚度約為350至1 5 0 0埃。 2 6.如申請專利範圍第2 3項所述之結構，其中上述之於鈦酸鉛锆與鉑共同組成之鐵電層係以濺鍍之方式沈積於緩衝層上。2 4. The structure according to item 23 of the scope of patent application, wherein the buffer layer is made of nickel-rotten oxide. 25. The structure according to item 23 of the scope of patent application, wherein the thickness of the buffer layer is about 350 to 1500 angstroms. 2 6. The structure as described in item 23 of the scope of the patent application, wherein the above ferroelectric layer composed of lead zirconate titanate and platinum is deposited on the buffer layer by sputtering.

2 7.如申請專利範圍第23項所述之結構，其中上述之鈦酸鉛锆與鉑共同組成之鐵電層厚度約為3 5 0至2 0 0 0埃。 2 8.如申請專利範圍第23項所述之結構，其中上述之於鈦酸鉛锆與鉑共同組成之鐵電層結構中，鉑之含量比約為2. 5%至 8· 5% 〇2 7. The structure according to item 23 of the scope of the patent application, wherein the thickness of the ferroelectric layer composed of the above-mentioned lead zirconate titanate and platinum is about 350 to 2000 angstroms. 2 8. The structure described in item 23 of the scope of patent application, wherein in the above ferroelectric layer structure composed of lead zirconate titanate and platinum, the content ratio of platinum is about 2.5% to 8.5%.

第20頁 569461 六、申請專利範圍 29·如申請專利範圍第23項所述之結構，其中上述之於鈦酸錯錘與鉑共同組成之鐵電層結構中，鉑之密度約為5 〇11至 5 013ea/cm2 ° 30·如申請專利範圍第2 3項所述之結構，其中上述之第一導體層和第二導體層材料係選自銘（Pt)、銥（lr)或是氧化銥（Ir02)其中之一。 31· —種可使用於低驅動電壓下之鐵電電容製造方法，其中該鐵電電容係架構在一半導體基底上，該半導體基底中具有一電晶體，以及連接該電晶體源極或汲極之接觸窗插塞，該方法至少包括：形成第一導體層於該半導體基底上，且與該接觸窗插塞連接，作為該鐵電電容之下電極；形成一由鎳-鑭氧化物所構成緩衝層，位於該第一導體層上；形成一由鈦酸鉛锆與鉑共同組成之鐵電材料層於該緩衝層上，其中鉑於該鐵電材料層中為少數成分；執行一回火製程使該鐵電材料層結晶；以及和 r 形成第二導體層於該鐵電材料層上，作為該鐵電電令之電極。，其中上述之錄 32·如申請專利範圍第31項所述之方法 * TPage 20 569461 6. Application scope 29. The structure described in item 23 of the scope of patent application, in which the density of platinum in the ferroelectric layer structure composed of platinum titanate and platinum is about 5 011. To 5 013ea / cm2 ° 30. The structure described in item 23 of the scope of patent application, wherein the material of the first conductor layer and the second conductor layer is selected from the group consisting of Pt, iridium, or iridium oxide. (Ir02) One of them. 31 · A method for manufacturing a ferroelectric capacitor which can be used at a low driving voltage, wherein the ferroelectric capacitor is structured on a semiconductor substrate having a transistor in the semiconductor substrate, and a source or a drain connected to the transistor A contact window plug, the method at least comprises: forming a first conductor layer on the semiconductor substrate and connecting with the contact window plug as the lower electrode of the ferroelectric capacitor; forming a nickel-lanthanum oxide A buffer layer on the first conductor layer; forming a ferroelectric material layer consisting of lead zirconate titanate and platinum on the buffer layer, wherein platinum is a minority component in the ferroelectric material layer; performing a tempering The manufacturing process crystallizes the ferroelectric material layer; and forms a second conductor layer on the ferroelectric material layer with r as an electrode of the ferroelectric order. Of which mentioned above 32 · The method described in item 31 of the scope of patent application * T

569461 六、申請專利範圍鋼氧化物緩衝層之厚度約為3 5 0至1 5 0 0埃。 33·如申請專利範圍第31項所述之方法，其中上述之於鈦酸鉛锆與鉑共同組成之鐵電層係以濺鍍之方式沈積於鎳-爛氧化物緩衝層上。 34·如申請專利範圍第31項所述之方法’其中上述之鈦酸鉛錘與鉑共同組成之鐵電層厚度約為5 0 0至2 0 0 0埃。 35· 如中請專利範圍第 31項所述之方法 5 其中上述之於鈦酸截「锆與翻共同組成之鐵電層詰構中之含量比約為 2· 5 %至 • 8· 50/0〇 3 6· 如中請專利範圍第 31項所遂之方法 J 其中上述之於鈦酸叙 f鍅與鉑共同組成之鐵電層結構中 > 鉑之密度約為 5 〇11至[ 013ea/cm2c 37. 如中請專利範圍第 31項所述之方法其中上述之回火製卷 L溫度約為 250至 750〇C。 38. 如中請專利範圍第 31項所述之方法 J 其中上述之回火製程溫度時間約為 1至10分鐘0 39· 如中請專利範圍第 31項所述之方法 5 其中形成上述之569461 6. Scope of patent application The thickness of the steel oxide buffer layer is about 350 to 1500 angstroms. 33. The method as described in claim 31, wherein the ferroelectric layer composed of lead zirconate titanate and platinum is deposited on the nickel-rotten oxide buffer layer by sputtering. 34. The method according to item 31 of the scope of the patent application, wherein the thickness of the ferroelectric layer composed of the above-mentioned lead titanate hammer and platinum is about 500 to 2000 angstroms. 35 · Method 5 as described in item 31 of the patent scope, wherein the content ratio of the above-mentioned ferrite layer structure composed of zirconium and zirconium is about 2.5% to • 8.50 / 〇3 6 · The method J as described in item 31 of the patent scope, wherein the above-mentioned in the ferroelectric layer structure composed of titanium titanate and platinum together> the density of platinum is about 501 to [013ea / cm2c 37. The method described in item 31 of the patent application, wherein the temperature of the tempered coil L described above is about 250 to 7500C. 38. The method described in item 31 of the patent application, J The tempering process temperature time is about 1 to 10 minutes. 0 39 · Method 5 as described in item 31 of the patent scope, wherein the above-mentioned

569461 六、申請專利範圍第一導體層和第二導體層材料係選自鉑（Pt)、銥（Ir)或是氧化銥（Ir02)其中之一。569461 6. Scope of patent application The material of the first conductor layer and the second conductor layer is selected from one of platinum (Pt), iridium (Ir) or iridium oxide (Ir02).

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